risc0_circuit_rv32im/zirgen/poly_ext.rs
1// Copyright 2025 RISC Zero, Inc.
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15// This code is automatically generated
16
17use risc0_zkp::{
18 adapter::{MixState, PolyExt, PolyExtStep, PolyExtStepDef},
19 field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem},
20};
21
22use super::CircuitImpl;
23
24#[allow(missing_docs)]
25#[rustfmt::skip]
26pub const DEF: PolyExtStepDef = PolyExtStepDef {
27 block: &[PolyExtStep::Const(0), // loc(unknown)
28PolyExtStep::Const(1), // loc(unknown)
29PolyExtStep::Const(7), // loc(unknown)
30PolyExtStep::Const(6), // loc(unknown)
31PolyExtStep::Const(5), // loc(unknown)
32PolyExtStep::Const(4), // loc(unknown)
33PolyExtStep::Const(3), // loc(unknown)
34PolyExtStep::Const(2), // loc(unknown)
35PolyExtStep::Const(12), // loc(unknown)
36PolyExtStep::Const(11), // loc(unknown)
37PolyExtStep::Const(10), // loc(unknown)
38PolyExtStep::Const(9), // loc(unknown)
39PolyExtStep::Const(8), // loc(unknown)
40PolyExtStep::Const(48), // loc(unknown)
41PolyExtStep::Const(16384), // loc(unknown)
42PolyExtStep::Const(49151), // loc(unknown)
43PolyExtStep::Const(65535), // loc(unknown)
44PolyExtStep::Const(2013265920), // loc(unknown)
45PolyExtStep::Const(61440), // loc(unknown)
46PolyExtStep::Const(64), // loc(unknown)
47PolyExtStep::Const(256), // loc(unknown)
48PolyExtStep::Const(1024), // loc(unknown)
49PolyExtStep::Const(4096), // loc(unknown)
50PolyExtStep::Const(16), // loc(unknown)
51PolyExtStep::Const(32), // loc(unknown)
52PolyExtStep::Const(128), // loc(unknown)
53PolyExtStep::Const(512), // loc(unknown)
54PolyExtStep::Const(2048), // loc(unknown)
55PolyExtStep::Const(8192), // loc(unknown)
56PolyExtStep::Const(32768), // loc(unknown)
57PolyExtStep::Const(1073725440), // loc(unknown)
58PolyExtStep::Const(1073725472), // loc(unknown)
59PolyExtStep::Const(51), // loc(unknown)
60PolyExtStep::Const(65536), // loc(unknown)
61PolyExtStep::Const(13), // loc(unknown)
62PolyExtStep::Const(14), // loc(unknown)
63PolyExtStep::Const(15), // loc(unknown)
64PolyExtStep::Const(1006632961), // loc(unknown)
65PolyExtStep::Const(19), // loc(unknown)
66PolyExtStep::Const(99), // loc(unknown)
67PolyExtStep::Const(65520), // loc(unknown)
68PolyExtStep::Const(111), // loc(unknown)
69PolyExtStep::Const(103), // loc(unknown)
70PolyExtStep::Const(55), // loc(unknown)
71PolyExtStep::Const(23), // loc(unknown)
72PolyExtStep::Const(115), // loc(unknown)
73PolyExtStep::Const(131070), // loc(unknown)
74PolyExtStep::Const(131072), // loc(unknown)
75PolyExtStep::Const(16777216), // loc(unknown)
76PolyExtStep::Const(2013235201), // loc(unknown)
77PolyExtStep::Const(65280), // loc(unknown)
78PolyExtStep::Const(35), // loc(unknown)
79PolyExtStep::Const(1073725457), // loc(unknown)
80PolyExtStep::Const(40), // loc(unknown)
81PolyExtStep::Const(1140850688), // loc(unknown)
82PolyExtStep::Const(1073741824), // loc(unknown)
83PolyExtStep::Const(1342177281), // loc(unknown)
84PolyExtStep::Const(22), // loc(unknown)
85PolyExtStep::ConstExt(0,0,0,0), // loc(unknown)
86PolyExtStep::Const(17), // loc(unknown)
87PolyExtStep::Const(18), // loc(unknown)
88PolyExtStep::Const(21), // loc(unknown)
89PolyExtStep::Const(1073725450), // loc(unknown)
90PolyExtStep::Const(1509949441), // loc(unknown)
91PolyExtStep::Const(1073725451), // loc(unknown)
92PolyExtStep::Const(1073725452), // loc(unknown)
93PolyExtStep::Const(1073725453), // loc(unknown)
94PolyExtStep::ConstExt(1,0,0,0), // loc(unknown)
95PolyExtStep::Const(24), // loc(unknown)
96PolyExtStep::Const(30719), // loc(unknown)
97PolyExtStep::Const(30720), // loc(unknown)
98PolyExtStep::Const(1761607681), // loc(unknown)
99PolyExtStep::Const(4194304), // loc(unknown)
100PolyExtStep::Const(25), // loc(unknown)
101PolyExtStep::Const(262278199), // loc(unknown)
102PolyExtStep::Const(127253399), // loc(unknown)
103PolyExtStep::Const(314968988), // loc(unknown)
104PolyExtStep::Const(246143118), // loc(unknown)
105PolyExtStep::Const(157582794), // loc(unknown)
106PolyExtStep::Const(118043943), // loc(unknown)
107PolyExtStep::Const(454905424), // loc(unknown)
108PolyExtStep::Const(815798990), // loc(unknown)
109PolyExtStep::Const(1004040026), // loc(unknown)
110PolyExtStep::Const(1773108264), // loc(unknown)
111PolyExtStep::Const(1066694495), // loc(unknown)
112PolyExtStep::Const(1930780904), // loc(unknown)
113PolyExtStep::Const(1180307149), // loc(unknown)
114PolyExtStep::Const(1464793095), // loc(unknown)
115PolyExtStep::Const(1660766320), // loc(unknown)
116PolyExtStep::Const(1389166148), // loc(unknown)
117PolyExtStep::Const(343354132), // loc(unknown)
118PolyExtStep::Const(1307439985), // loc(unknown)
119PolyExtStep::Const(638242172), // loc(unknown)
120PolyExtStep::Const(525458520), // loc(unknown)
121PolyExtStep::Const(1964135730), // loc(unknown)
122PolyExtStep::Const(1751797115), // loc(unknown)
123PolyExtStep::Const(1421525369), // loc(unknown)
124PolyExtStep::Const(831813382), // loc(unknown)
125PolyExtStep::Const(989176635), // loc(unknown)
126PolyExtStep::Const(241306552), // loc(unknown)
127PolyExtStep::Const(1507936940), // loc(unknown)
128PolyExtStep::Const(1687379185), // loc(unknown)
129PolyExtStep::Const(1150912935), // loc(unknown)
130PolyExtStep::Const(1917549072), // loc(unknown)
131PolyExtStep::Const(1201063290), // loc(unknown)
132PolyExtStep::Const(395622276), // loc(unknown)
133PolyExtStep::Const(1997503974), // loc(unknown)
134PolyExtStep::Const(716894289), // loc(unknown)
135PolyExtStep::Const(897025192), // loc(unknown)
136PolyExtStep::Const(1282239129), // loc(unknown)
137PolyExtStep::Const(1737016378), // loc(unknown)
138PolyExtStep::Const(686842369), // loc(unknown)
139PolyExtStep::Const(622609176), // loc(unknown)
140PolyExtStep::Const(1339793538), // loc(unknown)
141PolyExtStep::Const(1518763784), // loc(unknown)
142PolyExtStep::Const(1989924532), // loc(unknown)
143PolyExtStep::Const(1170029417), // loc(unknown)
144PolyExtStep::Const(1917861751), // loc(unknown)
145PolyExtStep::Const(1333667262), // loc(unknown)
146PolyExtStep::Const(540703332), // loc(unknown)
147PolyExtStep::Const(1845603984), // loc(unknown)
148PolyExtStep::Const(695835963), // loc(unknown)
149PolyExtStep::Const(862495875), // loc(unknown)
150PolyExtStep::Const(447555988), // loc(unknown)
151PolyExtStep::Const(1910423126), // loc(unknown)
152PolyExtStep::Const(1099252725), // loc(unknown)
153PolyExtStep::Const(1584033957), // loc(unknown)
154PolyExtStep::Const(1079030649), // loc(unknown)
155PolyExtStep::Const(1622328571), // loc(unknown)
156PolyExtStep::Const(1908416316), // loc(unknown)
157PolyExtStep::Const(1549062383), // loc(unknown)
158PolyExtStep::Const(623051854), // loc(unknown)
159PolyExtStep::Const(162510541), // loc(unknown)
160PolyExtStep::Const(1608853840), // loc(unknown)
161PolyExtStep::Const(538103555), // loc(unknown)
162PolyExtStep::Const(1424297384), // loc(unknown)
163PolyExtStep::Const(552696906), // loc(unknown)
164PolyExtStep::Const(946500736), // loc(unknown)
165PolyExtStep::Const(1215259350), // loc(unknown)
166PolyExtStep::Const(855276054), // loc(unknown)
167PolyExtStep::Const(1664590951), // loc(unknown)
168PolyExtStep::Const(217046702), // loc(unknown)
169PolyExtStep::Const(142102402), // loc(unknown)
170PolyExtStep::Const(1257820264), // loc(unknown)
171PolyExtStep::Const(27129487), // loc(unknown)
172PolyExtStep::Const(1147522062), // loc(unknown)
173PolyExtStep::Const(1291790245), // loc(unknown)
174PolyExtStep::Const(1781980094), // loc(unknown)
175PolyExtStep::Const(273790406), // loc(unknown)
176PolyExtStep::Const(1239734761), // loc(unknown)
177PolyExtStep::Const(1221257987), // loc(unknown)
178PolyExtStep::Const(51256176), // loc(unknown)
179PolyExtStep::Const(172614232), // loc(unknown)
180PolyExtStep::Const(306391314), // loc(unknown)
181PolyExtStep::Const(1647670797), // loc(unknown)
182PolyExtStep::Const(53007114), // loc(unknown)
183PolyExtStep::Const(1269493554), // loc(unknown)
184PolyExtStep::Const(1338899225), // loc(unknown)
185PolyExtStep::Const(1740472809), // loc(unknown)
186PolyExtStep::Const(1454563174), // loc(unknown)
187PolyExtStep::Const(204228775), // loc(unknown)
188PolyExtStep::Const(588764636), // loc(unknown)
189PolyExtStep::Const(1718628547), // loc(unknown)
190PolyExtStep::Const(427731030), // loc(unknown)
191PolyExtStep::Const(825405577), // loc(unknown)
192PolyExtStep::Const(342857858), // loc(unknown)
193PolyExtStep::Const(1290028279), // loc(unknown)
194PolyExtStep::Const(608401422), // loc(unknown)
195PolyExtStep::Const(1587822577), // loc(unknown)
196PolyExtStep::Const(128479034), // loc(unknown)
197PolyExtStep::Const(1040977421), // loc(unknown)
198PolyExtStep::Const(1792450386), // loc(unknown)
199PolyExtStep::Const(1470845646), // loc(unknown)
200PolyExtStep::Const(1363837384), // loc(unknown)
201PolyExtStep::Const(1878280202), // loc(unknown)
202PolyExtStep::Const(434078361), // loc(unknown)
203PolyExtStep::Const(1946596189), // loc(unknown)
204PolyExtStep::Const(875839332), // loc(unknown)
205PolyExtStep::Const(463976218), // loc(unknown)
206PolyExtStep::Const(976057819), // loc(unknown)
207PolyExtStep::Const(48375137), // loc(unknown)
208PolyExtStep::Const(1549779579), // loc(unknown)
209PolyExtStep::Const(1679178250), // loc(unknown)
210PolyExtStep::Const(530151394), // loc(unknown)
211PolyExtStep::Const(1629316321), // loc(unknown)
212PolyExtStep::Const(1854174607), // loc(unknown)
213PolyExtStep::Const(720724951), // loc(unknown)
214PolyExtStep::Const(14387587), // loc(unknown)
215PolyExtStep::Const(1883820770), // loc(unknown)
216PolyExtStep::Const(205609311), // loc(unknown)
217PolyExtStep::Const(1136469704), // loc(unknown)
218PolyExtStep::Const(1439947916), // loc(unknown)
219PolyExtStep::Const(723038058), // loc(unknown)
220PolyExtStep::Const(53041581), // loc(unknown)
221PolyExtStep::Const(150307788), // loc(unknown)
222PolyExtStep::Const(755691969), // loc(unknown)
223PolyExtStep::Const(1715719711), // loc(unknown)
224PolyExtStep::Const(1545325389), // loc(unknown)
225PolyExtStep::Const(989618631), // loc(unknown)
226PolyExtStep::Const(1401020792), // loc(unknown)
227PolyExtStep::Const(930036496), // loc(unknown)
228PolyExtStep::Const(238616145), // loc(unknown)
229PolyExtStep::Const(1006235079), // loc(unknown)
230PolyExtStep::Const(942439428), // loc(unknown)
231PolyExtStep::Const(1649953458), // loc(unknown)
232PolyExtStep::Const(1647665372), // loc(unknown)
233PolyExtStep::Const(708123747), // loc(unknown)
234PolyExtStep::Const(925018226), // loc(unknown)
235PolyExtStep::Const(78845751), // loc(unknown)
236PolyExtStep::Const(1889603648), // loc(unknown)
237PolyExtStep::Const(993455846), // loc(unknown)
238PolyExtStep::Const(140621810), // loc(unknown)
239PolyExtStep::Const(117294666), // loc(unknown)
240PolyExtStep::Const(790726260), // loc(unknown)
241PolyExtStep::Const(1213686459), // loc(unknown)
242PolyExtStep::Const(390340387), // loc(unknown)
243PolyExtStep::Const(714957516), // loc(unknown)
244PolyExtStep::Const(1209164052), // loc(unknown)
245PolyExtStep::Const(1827572010), // loc(unknown)
246PolyExtStep::Const(1507649755), // loc(unknown)
247PolyExtStep::Const(1042892522), // loc(unknown)
248PolyExtStep::Const(760115692), // loc(unknown)
249PolyExtStep::Const(1841795381), // loc(unknown)
250PolyExtStep::Const(457372011), // loc(unknown)
251PolyExtStep::Const(1748789933), // loc(unknown)
252PolyExtStep::Const(1478577620), // loc(unknown)
253PolyExtStep::Const(76770019), // loc(unknown)
254PolyExtStep::Const(1293938517), // loc(unknown)
255PolyExtStep::Const(1150410028), // loc(unknown)
256PolyExtStep::Const(1065075039), // loc(unknown)
257PolyExtStep::Const(1198261138), // loc(unknown)
258PolyExtStep::Const(59510015), // loc(unknown)
259PolyExtStep::Const(1402624179), // loc(unknown)
260PolyExtStep::Const(158646617), // loc(unknown)
261PolyExtStep::Const(890243564), // loc(unknown)
262PolyExtStep::Const(1463323727), // loc(unknown)
263PolyExtStep::Const(1080533265), // loc(unknown)
264PolyExtStep::Const(192082241), // loc(unknown)
265PolyExtStep::Const(1891637550), // loc(unknown)
266PolyExtStep::Const(1950429111), // loc(unknown)
267PolyExtStep::Const(1663353317), // loc(unknown)
268PolyExtStep::Const(1567618575), // loc(unknown)
269PolyExtStep::Const(1380248020), // loc(unknown)
270PolyExtStep::Const(1608891156), // loc(unknown)
271PolyExtStep::Const(1672219447), // loc(unknown)
272PolyExtStep::Const(1262312258), // loc(unknown)
273PolyExtStep::Const(162506101), // loc(unknown)
274PolyExtStep::Const(809508074), // loc(unknown)
275PolyExtStep::Const(1303271640), // loc(unknown)
276PolyExtStep::Const(1393671120), // loc(unknown)
277PolyExtStep::Const(641665156), // loc(unknown)
278PolyExtStep::Const(1090783436), // loc(unknown)
279PolyExtStep::Const(1111203133), // loc(unknown)
280PolyExtStep::Const(1296144415), // loc(unknown)
281PolyExtStep::Const(202271745), // loc(unknown)
282PolyExtStep::Const(459826664), // loc(unknown)
283PolyExtStep::Const(781141772), // loc(unknown)
284PolyExtStep::Const(1832911930), // loc(unknown)
285PolyExtStep::Const(228520958), // loc(unknown)
286PolyExtStep::Const(813674331), // loc(unknown)
287PolyExtStep::Const(1889898), // loc(unknown)
288PolyExtStep::Const(1124078057), // loc(unknown)
289PolyExtStep::Const(738091882), // loc(unknown)
290PolyExtStep::Const(1003792297), // loc(unknown)
291PolyExtStep::Const(1896271507), // loc(unknown)
292PolyExtStep::Const(1206940496), // loc(unknown)
293PolyExtStep::Const(497520322), // loc(unknown)
294PolyExtStep::Const(1930103076), // loc(unknown)
295PolyExtStep::Const(1052077299), // loc(unknown)
296PolyExtStep::Const(1540960371), // loc(unknown)
297PolyExtStep::Const(924863639), // loc(unknown)
298PolyExtStep::Const(1365519753), // loc(unknown)
299PolyExtStep::Const(1726563304), // loc(unknown)
300PolyExtStep::Const(440300254), // loc(unknown)
301PolyExtStep::Const(1891545577), // loc(unknown)
302PolyExtStep::Const(822033215), // loc(unknown)
303PolyExtStep::Const(1111544260), // loc(unknown)
304PolyExtStep::Const(308575117), // loc(unknown)
305PolyExtStep::Const(1708681573), // loc(unknown)
306PolyExtStep::Const(1240419708), // loc(unknown)
307PolyExtStep::Const(1199068823), // loc(unknown)
308PolyExtStep::Const(1186174623), // loc(unknown)
309PolyExtStep::Const(1551596046), // loc(unknown)
310PolyExtStep::Const(1886977120), // loc(unknown)
311PolyExtStep::Const(1327682690), // loc(unknown)
312PolyExtStep::Const(1210751726), // loc(unknown)
313PolyExtStep::Const(1810596765), // loc(unknown)
314PolyExtStep::Const(1083257840), // loc(unknown)
315PolyExtStep::Const(375892129), // loc(unknown)
316PolyExtStep::Const(111593398), // loc(unknown)
317PolyExtStep::Const(1867716110), // loc(unknown)
318PolyExtStep::Const(658182609), // loc(unknown)
319PolyExtStep::Const(51866717), // loc(unknown)
320PolyExtStep::Const(1928969209), // loc(unknown)
321PolyExtStep::Const(1942928017), // loc(unknown)
322PolyExtStep::Const(1558116381), // loc(unknown)
323PolyExtStep::Const(20525701), // loc(unknown)
324PolyExtStep::Const(1188752902), // loc(unknown)
325PolyExtStep::Const(106789798), // loc(unknown)
326PolyExtStep::Const(1389833583), // loc(unknown)
327PolyExtStep::Const(98371040), // loc(unknown)
328PolyExtStep::Const(1001081699), // loc(unknown)
329PolyExtStep::Const(1792686146), // loc(unknown)
330PolyExtStep::Const(801504236), // loc(unknown)
331PolyExtStep::Const(1997365680), // loc(unknown)
332PolyExtStep::Const(1461037801), // loc(unknown)
333PolyExtStep::Const(65998480), // loc(unknown)
334PolyExtStep::Const(1974912880), // loc(unknown)
335PolyExtStep::Const(606789471), // loc(unknown)
336PolyExtStep::Const(13683276), // loc(unknown)
337PolyExtStep::Const(918610824), // loc(unknown)
338PolyExtStep::Const(1073725454), // loc(unknown)
339PolyExtStep::Const(33), // loc(unknown)
340PolyExtStep::Const(34), // loc(unknown)
341PolyExtStep::Const(47), // loc(unknown)
342PolyExtStep::Const(36), // loc(unknown)
343PolyExtStep::Const(1073725445), // loc(unknown)
344PolyExtStep::Const(1073725447), // loc(unknown)
345PolyExtStep::Const(41), // loc(unknown)
346PolyExtStep::ConstExt(128,0,0,0), // loc(unknown)
347PolyExtStep::ConstExt(16384,0,0,0), // loc(unknown)
348PolyExtStep::ConstExt(256,0,0,0), // loc(unknown)
349PolyExtStep::Const(1140850680), // loc(unknown)
350PolyExtStep::Const(1140850681), // loc(unknown)
351PolyExtStep::Const(1140850682), // loc(unknown)
352PolyExtStep::Const(1140850683), // loc(unknown)
353PolyExtStep::Const(1140850684), // loc(unknown)
354PolyExtStep::Const(1140850685), // loc(unknown)
355PolyExtStep::Const(1140850686), // loc(unknown)
356PolyExtStep::Const(1140850687), // loc(unknown)
357PolyExtStep::Const(1073725592), // loc(unknown)
358PolyExtStep::Const(1073725593), // loc(unknown)
359PolyExtStep::Const(1073725594), // loc(unknown)
360PolyExtStep::Const(1073725595), // loc(unknown)
361PolyExtStep::Const(1073725596), // loc(unknown)
362PolyExtStep::Const(1073725597), // loc(unknown)
363PolyExtStep::Const(1073725598), // loc(unknown)
364PolyExtStep::Const(1073725599), // loc(unknown)
365PolyExtStep::Const(1073726464), // loc(unknown)
366PolyExtStep::Const(1073725568), // loc(unknown)
367PolyExtStep::Const(12320), // loc(unknown)
368PolyExtStep::Const(1073725584), // loc(unknown)
369PolyExtStep::Const(1073725585), // loc(unknown)
370PolyExtStep::Const(1073725586), // loc(unknown)
371PolyExtStep::Const(1073725587), // loc(unknown)
372PolyExtStep::Const(1073725588), // loc(unknown)
373PolyExtStep::Const(1073725589), // loc(unknown)
374PolyExtStep::Const(1073725590), // loc(unknown)
375PolyExtStep::Const(1073725591), // loc(unknown)
376PolyExtStep::Const(1073725504), // loc(unknown)
377PolyExtStep::Const(1073725572), // loc(unknown)
378PolyExtStep::Const(1073725573), // loc(unknown)
379PolyExtStep::Const(1875997790), // loc(unknown)
380PolyExtStep::ConstExt(0,1,0,0), // loc(unknown)
381PolyExtStep::True, // All Constraints
382PolyExtStep::Get(143), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :46:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
383PolyExtStep::Sub(1, 354), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :46:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
384PolyExtStep::Mul(354, 355), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :46:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
385PolyExtStep::AndEqz(0, 356), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :46:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
386PolyExtStep::Get(140), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
387PolyExtStep::Sub(357, 2), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
388PolyExtStep::AndEqz(0, 358), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
389PolyExtStep::Get(120), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
390PolyExtStep::Sub(0, 359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
391PolyExtStep::AndEqz(2, 360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
392PolyExtStep::AndCond(1, 354, 3), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :48:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
393PolyExtStep::Get(121), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :52:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
394PolyExtStep::Add(361, 1), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :52:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
395PolyExtStep::Sub(362, 359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :52:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
396PolyExtStep::AndEqz(0, 363), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :52:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
397PolyExtStep::AndCond(4, 355, 5), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :48:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
398PolyExtStep::Get(136), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :55:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
399PolyExtStep::Mul(355, 364), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :55:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
400PolyExtStep::Get(138), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
401PolyExtStep::Mul(355, 366), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
402PolyExtStep::Mul(355, 357), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :59:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
403PolyExtStep::Get(142), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :61:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
404PolyExtStep::Mul(355, 369), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :61:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
405PolyExtStep::Add(370, 354), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :61:61) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
406PolyExtStep::Get(144), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :65:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
407PolyExtStep::Get(145), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :66:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
408PolyExtStep::Get(146), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
409PolyExtStep::Sub(1, 374), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
410PolyExtStep::Mul(374, 375), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
411PolyExtStep::AndEqz(6, 376), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
412PolyExtStep::Get(147), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
413PolyExtStep::Sub(1, 377), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
414PolyExtStep::Mul(377, 378), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
415PolyExtStep::AndEqz(7, 379), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
416PolyExtStep::Get(148), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
417PolyExtStep::Sub(1, 380), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
418PolyExtStep::Mul(380, 381), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
419PolyExtStep::AndEqz(8, 382), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
420PolyExtStep::Get(149), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
421PolyExtStep::Sub(1, 383), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
422PolyExtStep::Mul(383, 384), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
423PolyExtStep::AndEqz(9, 385), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
424PolyExtStep::Get(150), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
425PolyExtStep::Sub(1, 386), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
426PolyExtStep::Mul(386, 387), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
427PolyExtStep::AndEqz(10, 388), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
428PolyExtStep::Get(151), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
429PolyExtStep::Sub(1, 389), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
430PolyExtStep::Mul(389, 390), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
431PolyExtStep::AndEqz(11, 391), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
432PolyExtStep::Get(152), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
433PolyExtStep::Sub(1, 392), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
434PolyExtStep::Mul(392, 393), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
435PolyExtStep::AndEqz(12, 394), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
436PolyExtStep::Get(153), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
437PolyExtStep::Sub(1, 395), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
438PolyExtStep::Mul(395, 396), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
439PolyExtStep::AndEqz(13, 397), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
440PolyExtStep::Add(374, 377), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
441PolyExtStep::Add(398, 380), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
442PolyExtStep::Add(399, 383), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
443PolyExtStep::Add(400, 386), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
444PolyExtStep::Add(401, 389), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
445PolyExtStep::Add(402, 392), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
446PolyExtStep::Add(403, 395), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
447PolyExtStep::Sub(404, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
448PolyExtStep::AndEqz(14, 405), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
449PolyExtStep::Mul(380, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
450PolyExtStep::Mul(383, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
451PolyExtStep::Mul(386, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
452PolyExtStep::Mul(389, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
453PolyExtStep::Mul(392, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
454PolyExtStep::Mul(395, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
455PolyExtStep::Add(377, 406), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
456PolyExtStep::Add(412, 407), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
457PolyExtStep::Add(413, 408), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
458PolyExtStep::Add(414, 409), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
459PolyExtStep::Add(415, 410), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
460PolyExtStep::Add(416, 411), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
461PolyExtStep::Sub(417, 373), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
462PolyExtStep::AndEqz(15, 418), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :69:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
463PolyExtStep::Get(122), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
464PolyExtStep::Sub(1, 419), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
465PolyExtStep::Mul(419, 420), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
466PolyExtStep::AndEqz(16, 421), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
467PolyExtStep::Get(123), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
468PolyExtStep::Sub(1, 422), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
469PolyExtStep::Mul(422, 423), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
470PolyExtStep::AndEqz(17, 424), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
471PolyExtStep::Get(124), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
472PolyExtStep::Sub(1, 425), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
473PolyExtStep::Mul(425, 426), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
474PolyExtStep::AndEqz(18, 427), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
475PolyExtStep::Get(125), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
476PolyExtStep::Sub(1, 428), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
477PolyExtStep::Mul(428, 429), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
478PolyExtStep::AndEqz(19, 430), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
479PolyExtStep::Get(126), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
480PolyExtStep::Sub(1, 431), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
481PolyExtStep::Mul(431, 432), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
482PolyExtStep::AndEqz(20, 433), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
483PolyExtStep::Get(127), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
484PolyExtStep::Sub(1, 434), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
485PolyExtStep::Mul(434, 435), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
486PolyExtStep::AndEqz(21, 436), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
487PolyExtStep::Get(128), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
488PolyExtStep::Sub(1, 437), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
489PolyExtStep::Mul(437, 438), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
490PolyExtStep::AndEqz(22, 439), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
491PolyExtStep::Get(129), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
492PolyExtStep::Sub(1, 440), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
493PolyExtStep::Mul(440, 441), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
494PolyExtStep::AndEqz(23, 442), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
495PolyExtStep::Get(130), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
496PolyExtStep::Sub(1, 443), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
497PolyExtStep::Mul(443, 444), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
498PolyExtStep::AndEqz(24, 445), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
499PolyExtStep::Get(131), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
500PolyExtStep::Sub(1, 446), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
501PolyExtStep::Mul(446, 447), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
502PolyExtStep::AndEqz(25, 448), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
503PolyExtStep::Get(132), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
504PolyExtStep::Sub(1, 449), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
505PolyExtStep::Mul(449, 450), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
506PolyExtStep::AndEqz(26, 451), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
507PolyExtStep::Get(133), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
508PolyExtStep::Sub(1, 452), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
509PolyExtStep::Mul(452, 453), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
510PolyExtStep::AndEqz(27, 454), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
511PolyExtStep::Get(134), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
512PolyExtStep::Sub(1, 455), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
513PolyExtStep::Mul(455, 456), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
514PolyExtStep::AndEqz(28, 457), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
515PolyExtStep::Add(419, 422), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
516PolyExtStep::Add(458, 425), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
517PolyExtStep::Add(459, 428), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
518PolyExtStep::Add(460, 431), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
519PolyExtStep::Add(461, 434), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
520PolyExtStep::Add(462, 437), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
521PolyExtStep::Add(463, 440), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
522PolyExtStep::Add(464, 443), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
523PolyExtStep::Add(465, 446), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
524PolyExtStep::Add(466, 449), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
525PolyExtStep::Add(467, 452), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
526PolyExtStep::Add(468, 455), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
527PolyExtStep::Sub(469, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
528PolyExtStep::AndEqz(29, 470), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
529PolyExtStep::Mul(425, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
530PolyExtStep::Mul(428, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
531PolyExtStep::Mul(431, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
532PolyExtStep::Mul(434, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
533PolyExtStep::Mul(437, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
534PolyExtStep::Mul(440, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
535PolyExtStep::Mul(443, 12), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
536PolyExtStep::Mul(446, 11), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
537PolyExtStep::Mul(449, 10), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
538PolyExtStep::Mul(452, 9), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
539PolyExtStep::Mul(455, 8), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
540PolyExtStep::Add(422, 471), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
541PolyExtStep::Add(482, 472), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
542PolyExtStep::Add(483, 473), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
543PolyExtStep::Add(484, 474), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
544PolyExtStep::Add(485, 475), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
545PolyExtStep::Add(486, 476), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
546PolyExtStep::Add(487, 477), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
547PolyExtStep::Add(488, 478), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
548PolyExtStep::Add(489, 479), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
549PolyExtStep::Add(490, 480), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
550PolyExtStep::Add(491, 481), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
551PolyExtStep::Sub(492, 372), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
552PolyExtStep::AndEqz(30, 493), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
553PolyExtStep::Sub(368, 13), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
554PolyExtStep::Mul(371, 16), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
555PolyExtStep::Sub(1, 371), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:41) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
556PolyExtStep::Mul(496, 15), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:49) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
557PolyExtStep::Add(495, 497), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:31) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
558PolyExtStep::Sub(498, 367), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
559PolyExtStep::Mul(367, 14), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
560PolyExtStep::Mul(371, 30), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
561PolyExtStep::Mul(496, 31), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:63) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
562PolyExtStep::Add(501, 502), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:44) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
563PolyExtStep::Add(365, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( SimpleOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :77:20) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:12) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
564PolyExtStep::Mul(504, 374), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
565PolyExtStep::Mul(504, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
566PolyExtStep::Mul(504, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
567PolyExtStep::Mul(504, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
568PolyExtStep::Mul(504, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
569PolyExtStep::Mul(504, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
570PolyExtStep::Mul(504, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
571PolyExtStep::Mul(504, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
572PolyExtStep::Add(505, 506), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
573PolyExtStep::Add(513, 507), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
574PolyExtStep::Add(514, 508), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
575PolyExtStep::Add(515, 509), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
576PolyExtStep::Add(516, 510), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
577PolyExtStep::Add(517, 511), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
578PolyExtStep::Add(518, 512), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
579PolyExtStep::Mul(367, 374), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
580PolyExtStep::Mul(367, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
581PolyExtStep::Mul(367, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
582PolyExtStep::Mul(367, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
583PolyExtStep::Mul(367, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
584PolyExtStep::Mul(367, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
585PolyExtStep::Mul(367, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
586PolyExtStep::Mul(367, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
587PolyExtStep::Add(520, 521), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
588PolyExtStep::Add(528, 522), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
589PolyExtStep::Add(529, 523), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
590PolyExtStep::Add(530, 524), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
591PolyExtStep::Add(531, 525), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
592PolyExtStep::Add(532, 526), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
593PolyExtStep::Add(533, 527), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
594PolyExtStep::Get(347), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :19:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
595PolyExtStep::Get(359), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :20:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
596PolyExtStep::Mul(359, 7), // loc(callsite( builtin Mul at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:17) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
597PolyExtStep::Sub(535, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
598PolyExtStep::AndEqz(0, 538), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
599PolyExtStep::Add(537, 1), // loc(callsite( builtin Add at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:19) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
600PolyExtStep::Sub(536, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
601PolyExtStep::AndEqz(32, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :29:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
602PolyExtStep::AndEqz(33, 494), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
603PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
604PolyExtStep::Sub(1, 541), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
605PolyExtStep::Mul(541, 542), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
606PolyExtStep::Sub(7, 541), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
607PolyExtStep::Mul(543, 544), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
608PolyExtStep::Sub(6, 541), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
609PolyExtStep::Mul(545, 546), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
610PolyExtStep::AndEqz(34, 547), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
611PolyExtStep::Get(467), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
612PolyExtStep::Get(473), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
613PolyExtStep::Sub(548, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
614PolyExtStep::AndEqz(35, 550), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
615PolyExtStep::Sub(549, 499), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
616PolyExtStep::AndEqz(36, 551), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
617PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
618PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
619PolyExtStep::Sub(1, 552), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
620PolyExtStep::Mul(552, 554), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
621PolyExtStep::AndEqz(37, 555), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
622PolyExtStep::Mul(367, 553), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
623PolyExtStep::Sub(556, 554), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
624PolyExtStep::AndEqz(38, 557), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
625PolyExtStep::Mul(552, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
626PolyExtStep::AndEqz(39, 558), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
627PolyExtStep::Mul(552, 553), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
628PolyExtStep::AndEqz(40, 559), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
629PolyExtStep::AndEqz(41, 552), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
630PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
631PolyExtStep::Get(497), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
632PolyExtStep::Sub(560, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
633PolyExtStep::AndEqz(42, 562), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
634PolyExtStep::Mul(561, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
635PolyExtStep::Add(563, 541), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
636PolyExtStep::Sub(564, 365), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
637PolyExtStep::AndEqz(43, 565), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
638PolyExtStep::Add(500, 561), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
639PolyExtStep::AndEqz(44, 541), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
640PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
641PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
642PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
643PolyExtStep::Get(521), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
644PolyExtStep::Get(527), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
645PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
646PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
647PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
648PolyExtStep::Get(551), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
649PolyExtStep::Sub(567, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
650PolyExtStep::AndEqz(45, 576), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
651PolyExtStep::Sub(572, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
652PolyExtStep::AndEqz(46, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
653PolyExtStep::Sub(573, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
654PolyExtStep::AndEqz(47, 578), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
655PolyExtStep::AndEqz(48, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
656PolyExtStep::Sub(568, 566), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
657PolyExtStep::AndEqz(49, 579), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
658PolyExtStep::Sub(570, 574), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
659PolyExtStep::AndEqz(50, 580), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
660PolyExtStep::Sub(571, 575), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
661PolyExtStep::AndEqz(51, 581), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
662PolyExtStep::Sub(573, 569), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
663PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
664PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
665PolyExtStep::Sub(583, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
666PolyExtStep::AndEqz(52, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
667PolyExtStep::Sub(584, 582), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
668PolyExtStep::AndEqz(53, 586), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
669PolyExtStep::Get(365), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
670PolyExtStep::Sub(1, 587), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
671PolyExtStep::Mul(587, 588), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
672PolyExtStep::AndEqz(54, 589), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
673PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
674PolyExtStep::Sub(1, 590), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
675PolyExtStep::Mul(590, 591), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
676PolyExtStep::Sub(7, 590), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
677PolyExtStep::Mul(592, 593), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
678PolyExtStep::Sub(6, 590), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
679PolyExtStep::Mul(594, 595), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
680PolyExtStep::AndEqz(55, 596), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
681PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
682PolyExtStep::Sub(1, 597), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
683PolyExtStep::Mul(597, 598), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
684PolyExtStep::Sub(7, 597), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
685PolyExtStep::Mul(599, 600), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
686PolyExtStep::Sub(6, 597), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
687PolyExtStep::Mul(601, 602), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
688PolyExtStep::AndEqz(56, 603), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
689PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
690PolyExtStep::Sub(1, 604), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
691PolyExtStep::Mul(604, 605), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
692PolyExtStep::Sub(7, 604), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
693PolyExtStep::Mul(606, 607), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
694PolyExtStep::Sub(6, 604), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
695PolyExtStep::Mul(608, 609), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
696PolyExtStep::AndEqz(57, 610), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
697PolyExtStep::Get(389), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
698PolyExtStep::Sub(1, 611), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
699PolyExtStep::Mul(611, 612), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
700PolyExtStep::Sub(7, 611), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
701PolyExtStep::Mul(613, 614), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
702PolyExtStep::Sub(6, 611), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
703PolyExtStep::Mul(615, 616), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
704PolyExtStep::AndEqz(58, 617), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
705PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
706PolyExtStep::Sub(1, 618), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
707PolyExtStep::Mul(618, 619), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
708PolyExtStep::Sub(7, 618), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
709PolyExtStep::Mul(620, 621), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
710PolyExtStep::Sub(6, 618), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
711PolyExtStep::Mul(622, 623), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
712PolyExtStep::AndEqz(59, 624), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
713PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
714PolyExtStep::Sub(1, 625), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
715PolyExtStep::Mul(625, 626), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
716PolyExtStep::AndEqz(60, 627), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
717PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
718PolyExtStep::Sub(1, 628), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
719PolyExtStep::Mul(628, 629), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
720PolyExtStep::Sub(7, 628), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
721PolyExtStep::Mul(630, 631), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
722PolyExtStep::Sub(6, 628), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
723PolyExtStep::Mul(632, 633), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
724PolyExtStep::AndEqz(61, 634), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
725PolyExtStep::Get(413), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
726PolyExtStep::Sub(1, 635), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
727PolyExtStep::Mul(635, 636), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
728PolyExtStep::Sub(7, 635), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
729PolyExtStep::Mul(637, 638), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
730PolyExtStep::Sub(6, 635), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
731PolyExtStep::Mul(639, 640), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
732PolyExtStep::AndEqz(62, 641), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
733PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
734PolyExtStep::Sub(1, 642), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
735PolyExtStep::Mul(642, 643), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
736PolyExtStep::AndEqz(63, 644), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
737PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
738PolyExtStep::Sub(1, 645), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
739PolyExtStep::Mul(645, 646), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
740PolyExtStep::AndEqz(64, 647), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
741PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
742PolyExtStep::Sub(1, 648), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
743PolyExtStep::Mul(648, 649), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
744PolyExtStep::Sub(7, 648), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
745PolyExtStep::Mul(650, 651), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
746PolyExtStep::Sub(6, 648), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
747PolyExtStep::Mul(652, 653), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
748PolyExtStep::AndEqz(65, 654), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
749PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
750PolyExtStep::Sub(1, 655), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
751PolyExtStep::Mul(655, 656), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
752PolyExtStep::Sub(7, 655), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
753PolyExtStep::Mul(657, 658), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
754PolyExtStep::Sub(6, 655), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
755PolyExtStep::Mul(659, 660), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
756PolyExtStep::AndEqz(66, 661), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
757PolyExtStep::Get(443), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
758PolyExtStep::Sub(1, 662), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
759PolyExtStep::Mul(662, 663), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
760PolyExtStep::Sub(7, 662), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
761PolyExtStep::Mul(664, 665), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
762PolyExtStep::Sub(6, 662), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
763PolyExtStep::Mul(666, 667), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
764PolyExtStep::AndEqz(67, 668), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
765PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
766PolyExtStep::Sub(1, 669), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
767PolyExtStep::Mul(669, 670), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
768PolyExtStep::AndEqz(68, 671), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
769PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :34:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
770PolyExtStep::Mul(587, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
771PolyExtStep::Mul(590, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
772PolyExtStep::Add(673, 674), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
773PolyExtStep::Mul(597, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
774PolyExtStep::Add(675, 676), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
775PolyExtStep::Mul(604, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
776PolyExtStep::Add(677, 678), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
777PolyExtStep::Mul(611, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
778PolyExtStep::Add(679, 680), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
779PolyExtStep::Mul(618, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
780PolyExtStep::Add(681, 682), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
781PolyExtStep::Mul(625, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
782PolyExtStep::Add(683, 684), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
783PolyExtStep::Mul(628, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
784PolyExtStep::Add(685, 686), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
785PolyExtStep::Add(687, 635), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
786PolyExtStep::Sub(575, 688), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
787PolyExtStep::AndEqz(69, 689), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
788PolyExtStep::Mul(642, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
789PolyExtStep::Mul(645, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
790PolyExtStep::Add(690, 691), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
791PolyExtStep::Mul(648, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
792PolyExtStep::Add(692, 693), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
793PolyExtStep::Mul(655, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
794PolyExtStep::Add(694, 695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
795PolyExtStep::Mul(662, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
796PolyExtStep::Add(696, 697), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
797PolyExtStep::Mul(669, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
798PolyExtStep::Add(698, 699), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
799PolyExtStep::Add(700, 672), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
800PolyExtStep::Sub(574, 701), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
801PolyExtStep::AndEqz(70, 702), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
802PolyExtStep::Mul(628, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
803PolyExtStep::Mul(635, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
804PolyExtStep::Add(703, 704), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
805PolyExtStep::Add(705, 642), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
806PolyExtStep::Mul(611, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
807PolyExtStep::Mul(618, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
808PolyExtStep::Add(707, 708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
809PolyExtStep::Add(709, 625), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
810PolyExtStep::Mul(655, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
811PolyExtStep::Mul(662, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
812PolyExtStep::Add(711, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
813PolyExtStep::Add(713, 669), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
814PolyExtStep::Mul(590, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
815PolyExtStep::Mul(597, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
816PolyExtStep::Add(715, 716), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
817PolyExtStep::Add(717, 604), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
818PolyExtStep::Mul(587, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
819PolyExtStep::Add(719, 718), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
820PolyExtStep::Mul(645, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
821PolyExtStep::Add(721, 648), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
822PolyExtStep::Mul(587, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
823PolyExtStep::Mul(720, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
824PolyExtStep::Add(723, 724), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
825PolyExtStep::Add(725, 710), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
826PolyExtStep::Mul(587, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
827PolyExtStep::Add(503, 706), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
828PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
829PolyExtStep::Sub(728, 729), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
830PolyExtStep::AndEqz(71, 730), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
831PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
832PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
833PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
834PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
835PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
836PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
837PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
838PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
839PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
840PolyExtStep::Sub(731, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
841PolyExtStep::AndEqz(72, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
842PolyExtStep::Sub(736, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
843PolyExtStep::AndEqz(73, 741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
844PolyExtStep::Sub(737, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
845PolyExtStep::AndEqz(74, 742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
846PolyExtStep::AndEqz(75, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
847PolyExtStep::Sub(732, 729), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
848PolyExtStep::AndEqz(76, 743), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
849PolyExtStep::Sub(734, 738), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
850PolyExtStep::AndEqz(77, 744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
851PolyExtStep::Sub(735, 739), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
852PolyExtStep::AndEqz(78, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
853PolyExtStep::Sub(737, 733), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
854PolyExtStep::Get(611), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
855PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
856PolyExtStep::Sub(747, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
857PolyExtStep::AndEqz(79, 749), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
858PolyExtStep::Sub(748, 746), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
859PolyExtStep::AndEqz(80, 750), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
860PolyExtStep::Add(503, 710), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
861PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
862PolyExtStep::Sub(751, 752), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
863PolyExtStep::AndEqz(81, 753), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
864PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
865PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
866PolyExtStep::Get(636), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
867PolyExtStep::Get(641), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
868PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
869PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
870PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
871PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
872PolyExtStep::Get(666), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
873PolyExtStep::Sub(754, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
874PolyExtStep::AndEqz(82, 763), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
875PolyExtStep::Sub(759, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
876PolyExtStep::AndEqz(83, 764), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
877PolyExtStep::Sub(760, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
878PolyExtStep::AndEqz(84, 765), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
879PolyExtStep::AndEqz(85, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
880PolyExtStep::Sub(755, 752), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
881PolyExtStep::AndEqz(86, 766), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
882PolyExtStep::Sub(757, 761), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
883PolyExtStep::AndEqz(87, 767), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
884PolyExtStep::Sub(758, 762), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
885PolyExtStep::AndEqz(88, 768), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
886PolyExtStep::Sub(760, 756), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
887PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
888PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
889PolyExtStep::Sub(770, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
890PolyExtStep::AndEqz(89, 772), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
891PolyExtStep::Sub(771, 769), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
892PolyExtStep::AndEqz(90, 773), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :11:25) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
893PolyExtStep::Sub(672, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :89:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
894PolyExtStep::AndEqz(0, 774), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :89:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
895PolyExtStep::AndEqz(92, 722), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :89:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
896PolyExtStep::AndEqz(93, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :89:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
897PolyExtStep::Get(154), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
898PolyExtStep::AndEqz(94, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
899PolyExtStep::Get(158), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
900PolyExtStep::AndEqz(95, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
901PolyExtStep::Get(162), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
902PolyExtStep::AndEqz(96, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
903PolyExtStep::Get(166), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
904PolyExtStep::AndEqz(97, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
905PolyExtStep::Get(173), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
906PolyExtStep::AndEqz(98, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
907PolyExtStep::AndCond(91, 374, 99), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
908PolyExtStep::Sub(720, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :94:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
909PolyExtStep::AndEqz(93, 780), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :94:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
910PolyExtStep::AndEqz(101, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
911PolyExtStep::AndEqz(102, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
912PolyExtStep::AndEqz(103, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
913PolyExtStep::AndEqz(104, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
914PolyExtStep::AndEqz(105, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
915PolyExtStep::AndCond(100, 377, 106), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
916PolyExtStep::Sub(722, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :99:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
917PolyExtStep::AndEqz(92, 781), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :99:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
918PolyExtStep::AndEqz(108, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :99:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
919PolyExtStep::Get(686), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
920PolyExtStep::Sub(1, 782), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
921PolyExtStep::Mul(782, 783), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
922PolyExtStep::AndEqz(109, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
923PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
924PolyExtStep::Sub(1, 785), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
925PolyExtStep::Mul(785, 786), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
926PolyExtStep::AndEqz(110, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
927PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
928PolyExtStep::Sub(1, 788), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
929PolyExtStep::Mul(788, 789), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
930PolyExtStep::AndEqz(111, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
931PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
932PolyExtStep::Sub(1, 791), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
933PolyExtStep::Mul(791, 792), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
934PolyExtStep::AndEqz(112, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
935PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
936PolyExtStep::Sub(1, 794), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
937PolyExtStep::Mul(794, 795), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
938PolyExtStep::AndEqz(113, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
939PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
940PolyExtStep::Sub(1, 797), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
941PolyExtStep::Mul(797, 798), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
942PolyExtStep::AndEqz(114, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
943PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
944PolyExtStep::Sub(1, 800), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
945PolyExtStep::Mul(800, 801), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
946PolyExtStep::AndEqz(115, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
947PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
948PolyExtStep::Sub(1, 803), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
949PolyExtStep::Mul(803, 804), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
950PolyExtStep::AndEqz(116, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
951PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
952PolyExtStep::Sub(1, 806), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
953PolyExtStep::Mul(806, 807), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
954PolyExtStep::AndEqz(117, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
955PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
956PolyExtStep::Sub(1, 809), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
957PolyExtStep::Mul(809, 810), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
958PolyExtStep::AndEqz(118, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
959PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
960PolyExtStep::Sub(1, 812), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
961PolyExtStep::Mul(812, 813), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
962PolyExtStep::AndEqz(119, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
963PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
964PolyExtStep::Sub(1, 815), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
965PolyExtStep::Mul(815, 816), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
966PolyExtStep::AndEqz(120, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
967PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
968PolyExtStep::Sub(1, 818), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
969PolyExtStep::Mul(818, 819), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
970PolyExtStep::AndEqz(121, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
971PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
972PolyExtStep::Sub(1, 821), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
973PolyExtStep::Mul(821, 822), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
974PolyExtStep::AndEqz(122, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
975PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
976PolyExtStep::Sub(1, 824), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
977PolyExtStep::Mul(824, 825), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
978PolyExtStep::AndEqz(123, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
979PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
980PolyExtStep::Sub(1, 827), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
981PolyExtStep::Mul(827, 828), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
982PolyExtStep::AndEqz(124, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
983PolyExtStep::Mul(785, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
984PolyExtStep::Mul(788, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
985PolyExtStep::Mul(791, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
986PolyExtStep::Mul(794, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
987PolyExtStep::Mul(797, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
988PolyExtStep::Mul(800, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
989PolyExtStep::Mul(803, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
990PolyExtStep::Mul(806, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
991PolyExtStep::Mul(809, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
992PolyExtStep::Mul(812, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
993PolyExtStep::Mul(815, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
994PolyExtStep::Mul(818, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
995PolyExtStep::Mul(821, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
996PolyExtStep::Mul(824, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
997PolyExtStep::Mul(827, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
998PolyExtStep::Add(782, 830), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
999PolyExtStep::Add(845, 831), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1000PolyExtStep::Add(846, 832), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1001PolyExtStep::Add(847, 833), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1002PolyExtStep::Add(848, 834), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1003PolyExtStep::Add(849, 835), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1004PolyExtStep::Add(850, 836), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1005PolyExtStep::Add(851, 837), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1006PolyExtStep::Add(852, 838), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1007PolyExtStep::Add(853, 839), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1008PolyExtStep::Add(854, 840), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1009PolyExtStep::Add(855, 841), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1010PolyExtStep::Add(856, 842), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1011PolyExtStep::Add(857, 843), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1012PolyExtStep::Add(858, 844), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1013PolyExtStep::Sub(738, 859), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1014PolyExtStep::AndEqz(125, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1015PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1016PolyExtStep::Sub(1, 861), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1017PolyExtStep::Mul(861, 862), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1018PolyExtStep::AndEqz(126, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1019PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1020PolyExtStep::Sub(1, 864), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1021PolyExtStep::Mul(864, 865), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1022PolyExtStep::AndEqz(127, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1023PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1024PolyExtStep::Sub(1, 867), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1025PolyExtStep::Mul(867, 868), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1026PolyExtStep::AndEqz(128, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1027PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1028PolyExtStep::Sub(1, 870), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1029PolyExtStep::Mul(870, 871), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1030PolyExtStep::AndEqz(129, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1031PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1032PolyExtStep::Sub(1, 873), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1033PolyExtStep::Mul(873, 874), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1034PolyExtStep::AndEqz(130, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1035PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1036PolyExtStep::Sub(1, 876), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1037PolyExtStep::Mul(876, 877), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1038PolyExtStep::AndEqz(131, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1039PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1040PolyExtStep::Sub(1, 879), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1041PolyExtStep::Mul(879, 880), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1042PolyExtStep::AndEqz(132, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1043PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1044PolyExtStep::Sub(1, 882), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1045PolyExtStep::Mul(882, 883), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1046PolyExtStep::AndEqz(133, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1047PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1048PolyExtStep::Sub(1, 885), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1049PolyExtStep::Mul(885, 886), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1050PolyExtStep::AndEqz(134, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1051PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1052PolyExtStep::Sub(1, 888), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1053PolyExtStep::Mul(888, 889), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1054PolyExtStep::AndEqz(135, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1055PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1056PolyExtStep::Sub(1, 891), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1057PolyExtStep::Mul(891, 892), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1058PolyExtStep::AndEqz(136, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1059PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1060PolyExtStep::Sub(1, 894), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1061PolyExtStep::Mul(894, 895), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1062PolyExtStep::AndEqz(137, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1063PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1064PolyExtStep::Sub(1, 897), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1065PolyExtStep::Mul(897, 898), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1066PolyExtStep::AndEqz(138, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1067PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1068PolyExtStep::Sub(1, 900), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1069PolyExtStep::Mul(900, 901), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1070PolyExtStep::AndEqz(139, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1071PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1072PolyExtStep::Sub(1, 903), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1073PolyExtStep::Mul(903, 904), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1074PolyExtStep::AndEqz(140, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1075PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1076PolyExtStep::Sub(1, 906), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1077PolyExtStep::Mul(906, 907), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1078PolyExtStep::AndEqz(141, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1079PolyExtStep::Mul(864, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1080PolyExtStep::Mul(867, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1081PolyExtStep::Mul(870, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1082PolyExtStep::Mul(873, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1083PolyExtStep::Mul(876, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1084PolyExtStep::Mul(879, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1085PolyExtStep::Mul(882, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1086PolyExtStep::Mul(885, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1087PolyExtStep::Mul(888, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1088PolyExtStep::Mul(891, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1089PolyExtStep::Mul(894, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1090PolyExtStep::Mul(897, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1091PolyExtStep::Mul(900, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1092PolyExtStep::Mul(903, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1093PolyExtStep::Mul(906, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1094PolyExtStep::Add(861, 909), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1095PolyExtStep::Add(924, 910), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1096PolyExtStep::Add(925, 911), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1097PolyExtStep::Add(926, 912), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1098PolyExtStep::Add(927, 913), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1099PolyExtStep::Add(928, 914), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1100PolyExtStep::Add(929, 915), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1101PolyExtStep::Add(930, 916), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1102PolyExtStep::Add(931, 917), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1103PolyExtStep::Add(932, 918), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1104PolyExtStep::Add(933, 919), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1105PolyExtStep::Add(934, 920), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1106PolyExtStep::Add(935, 921), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1107PolyExtStep::Add(936, 922), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1108PolyExtStep::Add(937, 923), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1109PolyExtStep::Sub(761, 938), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1110PolyExtStep::AndEqz(142, 939), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1111PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1112PolyExtStep::Sub(1, 940), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1113PolyExtStep::Mul(940, 941), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1114PolyExtStep::AndEqz(143, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1115PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1116PolyExtStep::Sub(1, 943), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1117PolyExtStep::Mul(943, 944), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1118PolyExtStep::AndEqz(144, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1119PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1120PolyExtStep::Sub(1, 946), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1121PolyExtStep::Mul(946, 947), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1122PolyExtStep::AndEqz(145, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1123PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1124PolyExtStep::Sub(1, 949), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1125PolyExtStep::Mul(949, 950), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1126PolyExtStep::AndEqz(146, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1127PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1128PolyExtStep::Sub(1, 952), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1129PolyExtStep::Mul(952, 953), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1130PolyExtStep::AndEqz(147, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1131PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1132PolyExtStep::Sub(1, 955), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1133PolyExtStep::Mul(955, 956), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1134PolyExtStep::AndEqz(148, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1135PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1136PolyExtStep::Sub(1, 958), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1137PolyExtStep::Mul(958, 959), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1138PolyExtStep::AndEqz(149, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1139PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1140PolyExtStep::Sub(1, 961), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1141PolyExtStep::Mul(961, 962), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1142PolyExtStep::AndEqz(150, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1143PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1144PolyExtStep::Sub(1, 964), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1145PolyExtStep::Mul(964, 965), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1146PolyExtStep::AndEqz(151, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1147PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1148PolyExtStep::Sub(1, 967), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1149PolyExtStep::Mul(967, 968), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1150PolyExtStep::AndEqz(152, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1151PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1152PolyExtStep::Sub(1, 970), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1153PolyExtStep::Mul(970, 971), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1154PolyExtStep::AndEqz(153, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1155PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1156PolyExtStep::Sub(1, 973), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1157PolyExtStep::Mul(973, 974), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1158PolyExtStep::AndEqz(154, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1159PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1160PolyExtStep::Sub(1, 976), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1161PolyExtStep::Mul(976, 977), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1162PolyExtStep::AndEqz(155, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1163PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1164PolyExtStep::Sub(1, 979), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1165PolyExtStep::Mul(979, 980), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1166PolyExtStep::AndEqz(156, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1167PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1168PolyExtStep::Sub(1, 982), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1169PolyExtStep::Mul(982, 983), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1170PolyExtStep::AndEqz(157, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1171PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1172PolyExtStep::Sub(1, 985), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1173PolyExtStep::Mul(985, 986), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1174PolyExtStep::AndEqz(158, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1175PolyExtStep::Mul(943, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1176PolyExtStep::Mul(946, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1177PolyExtStep::Mul(949, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1178PolyExtStep::Mul(952, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1179PolyExtStep::Mul(955, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1180PolyExtStep::Mul(958, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1181PolyExtStep::Mul(961, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1182PolyExtStep::Mul(964, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1183PolyExtStep::Mul(967, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1184PolyExtStep::Mul(970, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1185PolyExtStep::Mul(973, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1186PolyExtStep::Mul(976, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1187PolyExtStep::Mul(979, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1188PolyExtStep::Mul(982, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1189PolyExtStep::Mul(985, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1190PolyExtStep::Add(940, 988), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1191PolyExtStep::Add(1003, 989), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1192PolyExtStep::Add(1004, 990), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1193PolyExtStep::Add(1005, 991), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1194PolyExtStep::Add(1006, 992), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1195PolyExtStep::Add(1007, 993), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1196PolyExtStep::Add(1008, 994), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1197PolyExtStep::Add(1009, 995), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1198PolyExtStep::Add(1010, 996), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1199PolyExtStep::Add(1011, 997), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1200PolyExtStep::Add(1012, 998), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1201PolyExtStep::Add(1013, 999), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1202PolyExtStep::Add(1014, 1000), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1203PolyExtStep::Add(1015, 1001), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1204PolyExtStep::Add(1016, 1002), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1205PolyExtStep::Sub(739, 1017), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1206PolyExtStep::AndEqz(159, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1207PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1208PolyExtStep::Sub(1, 1019), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1209PolyExtStep::Mul(1019, 1020), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1210PolyExtStep::AndEqz(160, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1211PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1212PolyExtStep::Sub(1, 1022), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1213PolyExtStep::Mul(1022, 1023), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1214PolyExtStep::AndEqz(161, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1215PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1216PolyExtStep::Sub(1, 1025), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1217PolyExtStep::Mul(1025, 1026), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1218PolyExtStep::AndEqz(162, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1219PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1220PolyExtStep::Sub(1, 1028), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1221PolyExtStep::Mul(1028, 1029), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1222PolyExtStep::AndEqz(163, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1223PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1224PolyExtStep::Sub(1, 1031), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1225PolyExtStep::Mul(1031, 1032), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1226PolyExtStep::AndEqz(164, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1227PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1228PolyExtStep::Sub(1, 1034), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1229PolyExtStep::Mul(1034, 1035), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1230PolyExtStep::AndEqz(165, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1231PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1232PolyExtStep::Sub(1, 1037), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1233PolyExtStep::Mul(1037, 1038), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1234PolyExtStep::AndEqz(166, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1235PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1236PolyExtStep::Sub(1, 1040), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1237PolyExtStep::Mul(1040, 1041), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1238PolyExtStep::AndEqz(167, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1239PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1240PolyExtStep::Sub(1, 1043), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1241PolyExtStep::Mul(1043, 1044), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1242PolyExtStep::AndEqz(168, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1243PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1244PolyExtStep::Sub(1, 1046), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1245PolyExtStep::Mul(1046, 1047), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1246PolyExtStep::AndEqz(169, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1247PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1248PolyExtStep::Sub(1, 1049), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1249PolyExtStep::Mul(1049, 1050), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1250PolyExtStep::AndEqz(170, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1251PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1252PolyExtStep::Sub(1, 1052), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1253PolyExtStep::Mul(1052, 1053), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1254PolyExtStep::AndEqz(171, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1255PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1256PolyExtStep::Sub(1, 1055), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1257PolyExtStep::Mul(1055, 1056), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1258PolyExtStep::AndEqz(172, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1259PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1260PolyExtStep::Sub(1, 1058), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1261PolyExtStep::Mul(1058, 1059), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1262PolyExtStep::AndEqz(173, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1263PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1264PolyExtStep::Sub(1, 1061), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1265PolyExtStep::Mul(1061, 1062), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1266PolyExtStep::AndEqz(174, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1267PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1268PolyExtStep::Sub(1, 1064), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1269PolyExtStep::Mul(1064, 1065), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1270PolyExtStep::AndEqz(175, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1271PolyExtStep::Mul(1022, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1272PolyExtStep::Mul(1025, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1273PolyExtStep::Mul(1028, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1274PolyExtStep::Mul(1031, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1275PolyExtStep::Mul(1034, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1276PolyExtStep::Mul(1037, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1277PolyExtStep::Mul(1040, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1278PolyExtStep::Mul(1043, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1279PolyExtStep::Mul(1046, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1280PolyExtStep::Mul(1049, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1281PolyExtStep::Mul(1052, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1282PolyExtStep::Mul(1055, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1283PolyExtStep::Mul(1058, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1284PolyExtStep::Mul(1061, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1285PolyExtStep::Mul(1064, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1286PolyExtStep::Add(1019, 1067), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1287PolyExtStep::Add(1082, 1068), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1288PolyExtStep::Add(1083, 1069), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1289PolyExtStep::Add(1084, 1070), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1290PolyExtStep::Add(1085, 1071), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1291PolyExtStep::Add(1086, 1072), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1292PolyExtStep::Add(1087, 1073), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1293PolyExtStep::Add(1088, 1074), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1294PolyExtStep::Add(1089, 1075), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1295PolyExtStep::Add(1090, 1076), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1296PolyExtStep::Add(1091, 1077), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1297PolyExtStep::Add(1092, 1078), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1298PolyExtStep::Add(1093, 1079), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1299PolyExtStep::Add(1094, 1080), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1300PolyExtStep::Add(1095, 1081), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1301PolyExtStep::Sub(762, 1096), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1302PolyExtStep::AndEqz(176, 1097), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1303PolyExtStep::AndEqz(177, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1304PolyExtStep::AndEqz(178, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1305PolyExtStep::AndEqz(179, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1306PolyExtStep::AndEqz(180, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1307PolyExtStep::AndEqz(181, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1308PolyExtStep::AndCond(107, 380, 182), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1309PolyExtStep::Sub(722, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :104:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1310PolyExtStep::AndEqz(92, 1098), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :104:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1311PolyExtStep::AndEqz(184, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :104:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1312PolyExtStep::AndEqz(185, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1313PolyExtStep::AndEqz(186, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1314PolyExtStep::AndEqz(187, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1315PolyExtStep::AndEqz(188, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1316PolyExtStep::AndEqz(189, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1317PolyExtStep::AndEqz(190, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1318PolyExtStep::AndEqz(191, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1319PolyExtStep::AndEqz(192, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1320PolyExtStep::AndEqz(193, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1321PolyExtStep::AndEqz(194, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1322PolyExtStep::AndEqz(195, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1323PolyExtStep::AndEqz(196, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1324PolyExtStep::AndEqz(197, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1325PolyExtStep::AndEqz(198, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1326PolyExtStep::AndEqz(199, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1327PolyExtStep::AndEqz(200, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1328PolyExtStep::AndEqz(201, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1329PolyExtStep::AndEqz(202, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1330PolyExtStep::AndEqz(203, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1331PolyExtStep::AndEqz(204, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1332PolyExtStep::AndEqz(205, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1333PolyExtStep::AndEqz(206, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1334PolyExtStep::AndEqz(207, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1335PolyExtStep::AndEqz(208, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1336PolyExtStep::AndEqz(209, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1337PolyExtStep::AndEqz(210, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1338PolyExtStep::AndEqz(211, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1339PolyExtStep::AndEqz(212, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1340PolyExtStep::AndEqz(213, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1341PolyExtStep::AndEqz(214, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1342PolyExtStep::AndEqz(215, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1343PolyExtStep::AndEqz(216, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1344PolyExtStep::AndEqz(217, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1345PolyExtStep::AndEqz(218, 939), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1346PolyExtStep::AndEqz(219, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1347PolyExtStep::AndEqz(220, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1348PolyExtStep::AndEqz(221, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1349PolyExtStep::AndEqz(222, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1350PolyExtStep::AndEqz(223, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1351PolyExtStep::AndEqz(224, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1352PolyExtStep::AndEqz(225, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1353PolyExtStep::AndEqz(226, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1354PolyExtStep::AndEqz(227, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1355PolyExtStep::AndEqz(228, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1356PolyExtStep::AndEqz(229, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1357PolyExtStep::AndEqz(230, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1358PolyExtStep::AndEqz(231, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1359PolyExtStep::AndEqz(232, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1360PolyExtStep::AndEqz(233, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1361PolyExtStep::AndEqz(234, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1362PolyExtStep::AndEqz(235, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1363PolyExtStep::AndEqz(236, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1364PolyExtStep::AndEqz(237, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1365PolyExtStep::AndEqz(238, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1366PolyExtStep::AndEqz(239, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1367PolyExtStep::AndEqz(240, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1368PolyExtStep::AndEqz(241, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1369PolyExtStep::AndEqz(242, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1370PolyExtStep::AndEqz(243, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1371PolyExtStep::AndEqz(244, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1372PolyExtStep::AndEqz(245, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1373PolyExtStep::AndEqz(246, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1374PolyExtStep::AndEqz(247, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1375PolyExtStep::AndEqz(248, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1376PolyExtStep::AndEqz(249, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1377PolyExtStep::AndEqz(250, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1378PolyExtStep::AndEqz(251, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1379PolyExtStep::AndEqz(252, 1097), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1380PolyExtStep::AndEqz(253, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1381PolyExtStep::AndEqz(254, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1382PolyExtStep::AndEqz(255, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1383PolyExtStep::AndEqz(256, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1384PolyExtStep::AndEqz(257, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1385PolyExtStep::AndCond(183, 383, 258), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1386PolyExtStep::Sub(722, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :109:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1387PolyExtStep::AndEqz(92, 1099), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :109:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1388PolyExtStep::AndEqz(260, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :109:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1389PolyExtStep::AndEqz(261, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1390PolyExtStep::AndEqz(262, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1391PolyExtStep::AndEqz(263, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1392PolyExtStep::AndEqz(264, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1393PolyExtStep::AndEqz(265, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1394PolyExtStep::AndEqz(266, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1395PolyExtStep::AndEqz(267, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1396PolyExtStep::AndEqz(268, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1397PolyExtStep::AndEqz(269, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1398PolyExtStep::AndEqz(270, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1399PolyExtStep::AndEqz(271, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1400PolyExtStep::AndEqz(272, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1401PolyExtStep::AndEqz(273, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1402PolyExtStep::AndEqz(274, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1403PolyExtStep::AndEqz(275, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1404PolyExtStep::AndEqz(276, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1405PolyExtStep::AndEqz(277, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1406PolyExtStep::AndEqz(278, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1407PolyExtStep::AndEqz(279, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1408PolyExtStep::AndEqz(280, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1409PolyExtStep::AndEqz(281, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1410PolyExtStep::AndEqz(282, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1411PolyExtStep::AndEqz(283, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1412PolyExtStep::AndEqz(284, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1413PolyExtStep::AndEqz(285, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1414PolyExtStep::AndEqz(286, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1415PolyExtStep::AndEqz(287, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1416PolyExtStep::AndEqz(288, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1417PolyExtStep::AndEqz(289, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1418PolyExtStep::AndEqz(290, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1419PolyExtStep::AndEqz(291, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1420PolyExtStep::AndEqz(292, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1421PolyExtStep::AndEqz(293, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1422PolyExtStep::AndEqz(294, 939), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1423PolyExtStep::AndEqz(295, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1424PolyExtStep::AndEqz(296, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1425PolyExtStep::AndEqz(297, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1426PolyExtStep::AndEqz(298, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1427PolyExtStep::AndEqz(299, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1428PolyExtStep::AndEqz(300, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1429PolyExtStep::AndEqz(301, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1430PolyExtStep::AndEqz(302, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1431PolyExtStep::AndEqz(303, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1432PolyExtStep::AndEqz(304, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1433PolyExtStep::AndEqz(305, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1434PolyExtStep::AndEqz(306, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1435PolyExtStep::AndEqz(307, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1436PolyExtStep::AndEqz(308, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1437PolyExtStep::AndEqz(309, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1438PolyExtStep::AndEqz(310, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1439PolyExtStep::AndEqz(311, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1440PolyExtStep::AndEqz(312, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1441PolyExtStep::AndEqz(313, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1442PolyExtStep::AndEqz(314, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1443PolyExtStep::AndEqz(315, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1444PolyExtStep::AndEqz(316, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1445PolyExtStep::AndEqz(317, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1446PolyExtStep::AndEqz(318, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1447PolyExtStep::AndEqz(319, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1448PolyExtStep::AndEqz(320, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1449PolyExtStep::AndEqz(321, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1450PolyExtStep::AndEqz(322, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1451PolyExtStep::AndEqz(323, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1452PolyExtStep::AndEqz(324, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1453PolyExtStep::AndEqz(325, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1454PolyExtStep::AndEqz(326, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1455PolyExtStep::AndEqz(327, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1456PolyExtStep::AndEqz(328, 1097), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1457PolyExtStep::AndEqz(329, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1458PolyExtStep::AndEqz(330, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1459PolyExtStep::AndEqz(331, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1460PolyExtStep::AndEqz(332, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1461PolyExtStep::AndEqz(333, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1462PolyExtStep::AndCond(259, 386, 334), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1463PolyExtStep::Sub(722, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :114:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1464PolyExtStep::Add(738, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1465PolyExtStep::Sub(1101, 761), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1466PolyExtStep::Add(739, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1467PolyExtStep::Sub(1103, 762), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1468PolyExtStep::AndEqz(92, 1100), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :114:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1469PolyExtStep::AndEqz(336, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :114:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1470PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1471PolyExtStep::Sub(775, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1472PolyExtStep::AndEqz(337, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1473PolyExtStep::AndEqz(338, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1474PolyExtStep::Mul(782, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1475PolyExtStep::Add(1107, 1105), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1476PolyExtStep::Sub(1102, 1108), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1477PolyExtStep::AndEqz(339, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1478PolyExtStep::Add(1104, 782), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1479PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1480PolyExtStep::Sub(776, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1481PolyExtStep::AndEqz(340, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1482PolyExtStep::AndEqz(341, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1483PolyExtStep::Mul(785, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1484PolyExtStep::Add(1113, 1111), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1485PolyExtStep::Sub(1110, 1114), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1486PolyExtStep::AndEqz(342, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1487PolyExtStep::AndEqz(343, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1488PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1489PolyExtStep::Sub(777, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1490PolyExtStep::AndEqz(344, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1491PolyExtStep::Mul(788, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1492PolyExtStep::Mul(1116, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1493PolyExtStep::Add(1118, 1119), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1494PolyExtStep::Sub(739, 1120), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1495PolyExtStep::AndEqz(345, 1121), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1496PolyExtStep::AndEqz(346, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1497PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1498PolyExtStep::Sub(778, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1499PolyExtStep::AndEqz(347, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1500PolyExtStep::Mul(791, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1501PolyExtStep::Mul(1122, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1502PolyExtStep::Add(1124, 1125), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1503PolyExtStep::Sub(762, 1126), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1504PolyExtStep::AndEqz(348, 1127), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1505PolyExtStep::AndEqz(349, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1506PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1507PolyExtStep::Sub(779, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1508PolyExtStep::AndEqz(350, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1509PolyExtStep::Mul(794, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1510PolyExtStep::Mul(1128, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1511PolyExtStep::Add(1130, 1131), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1512PolyExtStep::Sub(1111, 1132), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1513PolyExtStep::AndEqz(351, 1133), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1514PolyExtStep::Mul(788, 792), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1515PolyExtStep::Mul(1134, 795), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:32) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1516PolyExtStep::Mul(789, 791), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:54) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1517PolyExtStep::Mul(1136, 794), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:58) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1518PolyExtStep::Add(1135, 1137), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:43) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1519PolyExtStep::Sub(1138, 797), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1520PolyExtStep::AndEqz(352, 1139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1521PolyExtStep::Add(797, 794), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1522PolyExtStep::Mul(797, 7), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:47) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1523PolyExtStep::Mul(1141, 794), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:51) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1524PolyExtStep::Sub(1140, 1142), // loc(callsite( builtin Sub at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:42) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1525PolyExtStep::Sub(1143, 800), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1526PolyExtStep::AndEqz(353, 1144), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1527PolyExtStep::AndCond(335, 389, 354), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1528PolyExtStep::Sub(722, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :120:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1529PolyExtStep::AndEqz(92, 1145), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :120:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1530PolyExtStep::AndEqz(356, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :120:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1531PolyExtStep::AndEqz(357, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1532PolyExtStep::AndEqz(358, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1533PolyExtStep::AndEqz(359, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1534PolyExtStep::AndEqz(360, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1535PolyExtStep::AndEqz(361, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1536PolyExtStep::AndEqz(362, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1537PolyExtStep::AndEqz(363, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1538PolyExtStep::AndEqz(364, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1539PolyExtStep::AndEqz(365, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1540PolyExtStep::AndCond(355, 392, 366), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1541PolyExtStep::Sub(672, 38), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :126:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1542PolyExtStep::AndEqz(0, 1146), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :126:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1543PolyExtStep::AndEqz(368, 722), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :126:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1544PolyExtStep::AndEqz(369, 775), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1545PolyExtStep::AndEqz(370, 776), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1546PolyExtStep::AndEqz(371, 777), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1547PolyExtStep::AndEqz(372, 778), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1548PolyExtStep::AndEqz(373, 779), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1549PolyExtStep::AndCond(367, 395, 374), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1550PolyExtStep::Add(738, 761), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1551PolyExtStep::Mul(1147, 374), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1552PolyExtStep::Mul(1102, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1553PolyExtStep::Get(686), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1554PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1555PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1556PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1557PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1558PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1559PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1560PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1561PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1562PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1563PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1564PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1565PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1566PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1567PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1568PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1569PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1570PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1571PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1572PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1573PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1574PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1575PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1576PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1577PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1578PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1579PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1580PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1581PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1582PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1583PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1584PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1585PolyExtStep::Mul(1150, 1166), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1586PolyExtStep::Mul(1151, 1167), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1587PolyExtStep::Mul(1152, 1168), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1588PolyExtStep::Mul(1153, 1169), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1589PolyExtStep::Mul(1154, 1170), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1590PolyExtStep::Mul(1155, 1171), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1591PolyExtStep::Mul(1156, 1172), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1592PolyExtStep::Mul(1157, 1173), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1593PolyExtStep::Mul(1158, 1174), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1594PolyExtStep::Mul(1159, 1175), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1595PolyExtStep::Mul(1160, 1176), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1596PolyExtStep::Mul(1161, 1177), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1597PolyExtStep::Mul(1162, 1178), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1598PolyExtStep::Mul(1163, 1179), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1599PolyExtStep::Mul(1164, 1180), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1600PolyExtStep::Mul(1165, 1181), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1601PolyExtStep::Mul(1183, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1602PolyExtStep::Mul(1184, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1603PolyExtStep::Mul(1185, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1604PolyExtStep::Mul(1186, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1605PolyExtStep::Mul(1187, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1606PolyExtStep::Mul(1188, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1607PolyExtStep::Mul(1189, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1608PolyExtStep::Mul(1190, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1609PolyExtStep::Mul(1191, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1610PolyExtStep::Mul(1192, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1611PolyExtStep::Mul(1193, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1612PolyExtStep::Mul(1194, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1613PolyExtStep::Mul(1195, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1614PolyExtStep::Mul(1196, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1615PolyExtStep::Mul(1197, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1616PolyExtStep::Add(1182, 1198), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1617PolyExtStep::Add(1213, 1199), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1618PolyExtStep::Add(1214, 1200), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1619PolyExtStep::Add(1215, 1201), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1620PolyExtStep::Add(1216, 1202), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1621PolyExtStep::Add(1217, 1203), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1622PolyExtStep::Add(1218, 1204), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1623PolyExtStep::Add(1219, 1205), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1624PolyExtStep::Add(1220, 1206), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1625PolyExtStep::Add(1221, 1207), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1626PolyExtStep::Add(1222, 1208), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1627PolyExtStep::Add(1223, 1209), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1628PolyExtStep::Add(1224, 1210), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1629PolyExtStep::Add(1225, 1211), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1630PolyExtStep::Add(1226, 1212), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1631PolyExtStep::Mul(1227, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:27) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1632PolyExtStep::Sub(1147, 1228), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1633PolyExtStep::Mul(1229, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1634PolyExtStep::Sub(1147, 1227), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1635PolyExtStep::Mul(1231, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1636PolyExtStep::Mul(1227, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1637PolyExtStep::Mul(1156, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1638PolyExtStep::Sub(1, 1151), // loc(callsite( builtin Sub at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :120:27) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1639PolyExtStep::Mul(1235, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1640PolyExtStep::Add(738, 726), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1641PolyExtStep::Mul(1237, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1642PolyExtStep::Add(1148, 1149), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1643PolyExtStep::Add(1239, 1230), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1644PolyExtStep::Add(1240, 1232), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1645PolyExtStep::Add(1241, 1233), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1646PolyExtStep::Add(1242, 1234), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1647PolyExtStep::Add(1243, 1236), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1648PolyExtStep::Add(1244, 1238), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1649PolyExtStep::Add(739, 762), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1650PolyExtStep::Mul(1246, 374), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1651PolyExtStep::Mul(1104, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1652PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1653PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1654PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1655PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1656PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1657PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1658PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1659PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1660PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1661PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1662PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1663PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1664PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1665PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1666PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1667PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1668PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1669PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1670PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1671PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1672PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1673PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1674PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1675PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1676PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1677PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1678PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1679PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1680PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1681PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1682PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1683PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1684PolyExtStep::Mul(1249, 1265), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1685PolyExtStep::Mul(1250, 1266), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1686PolyExtStep::Mul(1251, 1267), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1687PolyExtStep::Mul(1252, 1268), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1688PolyExtStep::Mul(1253, 1269), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1689PolyExtStep::Mul(1254, 1270), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1690PolyExtStep::Mul(1255, 1271), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1691PolyExtStep::Mul(1256, 1272), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1692PolyExtStep::Mul(1257, 1273), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1693PolyExtStep::Mul(1258, 1274), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1694PolyExtStep::Mul(1259, 1275), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1695PolyExtStep::Mul(1260, 1276), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1696PolyExtStep::Mul(1261, 1277), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1697PolyExtStep::Mul(1262, 1278), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1698PolyExtStep::Mul(1263, 1279), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1699PolyExtStep::Mul(1264, 1280), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1700PolyExtStep::Mul(1282, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1701PolyExtStep::Mul(1283, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1702PolyExtStep::Mul(1284, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1703PolyExtStep::Mul(1285, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1704PolyExtStep::Mul(1286, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1705PolyExtStep::Mul(1287, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1706PolyExtStep::Mul(1288, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1707PolyExtStep::Mul(1289, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1708PolyExtStep::Mul(1290, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1709PolyExtStep::Mul(1291, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1710PolyExtStep::Mul(1292, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1711PolyExtStep::Mul(1293, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1712PolyExtStep::Mul(1294, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1713PolyExtStep::Mul(1295, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1714PolyExtStep::Mul(1296, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1715PolyExtStep::Add(1281, 1297), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1716PolyExtStep::Add(1312, 1298), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1717PolyExtStep::Add(1313, 1299), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1718PolyExtStep::Add(1314, 1300), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1719PolyExtStep::Add(1315, 1301), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1720PolyExtStep::Add(1316, 1302), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1721PolyExtStep::Add(1317, 1303), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1722PolyExtStep::Add(1318, 1304), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1723PolyExtStep::Add(1319, 1305), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1724PolyExtStep::Add(1320, 1306), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1725PolyExtStep::Add(1321, 1307), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1726PolyExtStep::Add(1322, 1308), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1727PolyExtStep::Add(1323, 1309), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1728PolyExtStep::Add(1324, 1310), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1729PolyExtStep::Add(1325, 1311), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1730PolyExtStep::Mul(1326, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:59) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1731PolyExtStep::Sub(1246, 1327), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1732PolyExtStep::Mul(1328, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1733PolyExtStep::Sub(1246, 1326), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1734PolyExtStep::Mul(1330, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1735PolyExtStep::Mul(1326, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1736PolyExtStep::Add(739, 727), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1737PolyExtStep::Mul(1333, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1738PolyExtStep::Add(1247, 1248), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1739PolyExtStep::Add(1335, 1329), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1740PolyExtStep::Add(1336, 1331), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1741PolyExtStep::Add(1337, 1332), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1742PolyExtStep::Add(1338, 1334), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1743PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1744PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1745PolyExtStep::Sub(1340, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1746PolyExtStep::AndEqz(375, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1747PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1748PolyExtStep::Sub(1, 1343), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1749PolyExtStep::Mul(1343, 1344), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1750PolyExtStep::AndEqz(376, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1751PolyExtStep::Mul(1343, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1752PolyExtStep::Add(1346, 1341), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1753PolyExtStep::Sub(1245, 1347), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1754PolyExtStep::AndEqz(377, 1348), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1755PolyExtStep::Add(1339, 1343), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1756PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1757PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1758PolyExtStep::Sub(1350, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1759PolyExtStep::AndEqz(378, 1352), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1760PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1761PolyExtStep::Sub(1, 1353), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1762PolyExtStep::Mul(1353, 1354), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1763PolyExtStep::AndEqz(379, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1764PolyExtStep::Mul(1353, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1765PolyExtStep::Add(1356, 1351), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1766PolyExtStep::Sub(1349, 1357), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1767PolyExtStep::AndEqz(380, 1358), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1768PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1769PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1770PolyExtStep::Sub(1359, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1771PolyExtStep::AndEqz(381, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1772PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1773PolyExtStep::Sub(1, 1362), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1774PolyExtStep::Mul(1362, 1363), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1775PolyExtStep::AndEqz(382, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1776PolyExtStep::Mul(1362, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1777PolyExtStep::Add(1365, 1360), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1778PolyExtStep::Sub(519, 1366), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1779PolyExtStep::AndEqz(383, 1367), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1780PolyExtStep::Add(534, 1362), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1781PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1782PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1783PolyExtStep::Sub(1369, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1784PolyExtStep::AndEqz(384, 1371), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1785PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1786PolyExtStep::Sub(1, 1372), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1787PolyExtStep::Mul(1372, 1373), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1788PolyExtStep::AndEqz(385, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1789PolyExtStep::Mul(1372, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1790PolyExtStep::Add(1375, 1370), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1791PolyExtStep::Sub(1368, 1376), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1792PolyExtStep::AndEqz(386, 1377), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1793PolyExtStep::Get(257), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1794PolyExtStep::Get(263), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1795PolyExtStep::Sub(1, 1378), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1796PolyExtStep::Mul(1378, 1380), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1797PolyExtStep::AndEqz(387, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1798PolyExtStep::Mul(714, 1379), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1799PolyExtStep::Sub(1382, 1380), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1800PolyExtStep::AndEqz(388, 1383), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1801PolyExtStep::Mul(1378, 714), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1802PolyExtStep::AndEqz(389, 1384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1803PolyExtStep::Mul(1378, 1379), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1804PolyExtStep::AndEqz(390, 1385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1805PolyExtStep::Mul(1380, 404), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :43:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1806PolyExtStep::Mul(1386, 714), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1807PolyExtStep::Sub(1, 1386), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1808PolyExtStep::Mul(1388, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1809PolyExtStep::Add(503, 1389), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1810PolyExtStep::Add(1390, 1387), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1811PolyExtStep::Get(269), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1812PolyExtStep::Sub(1391, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1813PolyExtStep::AndEqz(391, 1393), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1814PolyExtStep::Get(281), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1815PolyExtStep::Get(275), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1816PolyExtStep::Get(287), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1817PolyExtStep::Get(305), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1818PolyExtStep::Get(311), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1819PolyExtStep::Get(317), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1820PolyExtStep::Get(323), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1821PolyExtStep::Sub(1394, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1822PolyExtStep::AndEqz(392, 1401), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1823PolyExtStep::Sub(1397, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1824PolyExtStep::AndEqz(393, 1402), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1825PolyExtStep::Sub(1398, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1826PolyExtStep::AndEqz(394, 1403), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1827PolyExtStep::AndEqz(395, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1828PolyExtStep::Sub(1395, 1392), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1829PolyExtStep::AndEqz(396, 1404), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1830PolyExtStep::Sub(1398, 1396), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1831PolyExtStep::Get(329), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1832PolyExtStep::Get(335), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1833PolyExtStep::Sub(1406, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1834PolyExtStep::AndEqz(397, 1408), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1835PolyExtStep::Sub(1407, 1405), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1836PolyExtStep::AndEqz(398, 1409), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1837PolyExtStep::Sub(1399, 1341), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1838PolyExtStep::AndEqz(399, 1410), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1839PolyExtStep::Sub(1400, 1351), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1840PolyExtStep::AndEqz(400, 1411), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1841PolyExtStep::AndCond(31, 419, 401), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
1842PolyExtStep::Mul(669, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1843PolyExtStep::Add(723, 1412), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1844PolyExtStep::Mul(718, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:61) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1845PolyExtStep::Add(1413, 1414), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1846PolyExtStep::Add(1415, 711), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:72) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1847PolyExtStep::Add(1416, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:86) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :46:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1848PolyExtStep::AndEqz(368, 781), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :131:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1849PolyExtStep::AndEqz(403, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1850PolyExtStep::AndEqz(404, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1851PolyExtStep::AndEqz(405, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1852PolyExtStep::AndEqz(406, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1853PolyExtStep::AndEqz(407, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1854PolyExtStep::AndEqz(408, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1855PolyExtStep::AndEqz(409, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1856PolyExtStep::AndEqz(410, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1857PolyExtStep::AndEqz(411, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1858PolyExtStep::AndEqz(412, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1859PolyExtStep::AndEqz(413, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1860PolyExtStep::AndEqz(414, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1861PolyExtStep::AndEqz(415, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1862PolyExtStep::AndEqz(416, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1863PolyExtStep::AndEqz(417, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1864PolyExtStep::AndEqz(418, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1865PolyExtStep::AndEqz(419, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1866PolyExtStep::AndEqz(420, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1867PolyExtStep::AndEqz(421, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1868PolyExtStep::AndEqz(422, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1869PolyExtStep::AndEqz(423, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1870PolyExtStep::AndEqz(424, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1871PolyExtStep::AndEqz(425, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1872PolyExtStep::AndEqz(426, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1873PolyExtStep::AndEqz(427, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1874PolyExtStep::AndEqz(428, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1875PolyExtStep::AndEqz(429, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1876PolyExtStep::AndEqz(430, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1877PolyExtStep::AndEqz(431, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1878PolyExtStep::AndEqz(432, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1879PolyExtStep::AndEqz(433, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1880PolyExtStep::AndEqz(434, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1881PolyExtStep::AndEqz(435, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1882PolyExtStep::Sub(726, 938), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1883PolyExtStep::AndEqz(436, 1418), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1884PolyExtStep::AndEqz(437, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1885PolyExtStep::AndEqz(438, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1886PolyExtStep::AndEqz(439, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1887PolyExtStep::AndEqz(440, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1888PolyExtStep::AndEqz(441, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1889PolyExtStep::AndEqz(442, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1890PolyExtStep::AndEqz(443, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1891PolyExtStep::AndEqz(444, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1892PolyExtStep::AndEqz(445, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1893PolyExtStep::AndEqz(446, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1894PolyExtStep::AndEqz(447, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1895PolyExtStep::AndEqz(448, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1896PolyExtStep::AndEqz(449, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1897PolyExtStep::AndEqz(450, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1898PolyExtStep::AndEqz(451, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1899PolyExtStep::AndEqz(452, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1900PolyExtStep::AndEqz(453, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1901PolyExtStep::AndEqz(454, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1902PolyExtStep::AndEqz(455, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1903PolyExtStep::AndEqz(456, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1904PolyExtStep::AndEqz(457, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1905PolyExtStep::AndEqz(458, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1906PolyExtStep::AndEqz(459, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1907PolyExtStep::AndEqz(460, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1908PolyExtStep::AndEqz(461, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1909PolyExtStep::AndEqz(462, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1910PolyExtStep::AndEqz(463, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1911PolyExtStep::AndEqz(464, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1912PolyExtStep::AndEqz(465, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1913PolyExtStep::AndEqz(466, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1914PolyExtStep::AndEqz(467, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1915PolyExtStep::AndEqz(468, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1916PolyExtStep::AndEqz(469, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1917PolyExtStep::Sub(727, 1096), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1918PolyExtStep::AndEqz(470, 1419), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1919PolyExtStep::AndEqz(471, 775), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1920PolyExtStep::AndEqz(472, 776), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1921PolyExtStep::AndEqz(473, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1922PolyExtStep::AndEqz(474, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1923PolyExtStep::AndEqz(475, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1924PolyExtStep::AndCond(91, 374, 476), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1925PolyExtStep::AndEqz(368, 1098), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :136:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1926PolyExtStep::AndEqz(478, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1927PolyExtStep::AndEqz(479, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1928PolyExtStep::AndEqz(480, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1929PolyExtStep::AndEqz(481, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1930PolyExtStep::AndEqz(482, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1931PolyExtStep::AndEqz(483, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1932PolyExtStep::AndEqz(484, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1933PolyExtStep::AndEqz(485, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1934PolyExtStep::AndEqz(486, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1935PolyExtStep::AndEqz(487, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1936PolyExtStep::AndEqz(488, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1937PolyExtStep::AndEqz(489, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1938PolyExtStep::AndEqz(490, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1939PolyExtStep::AndEqz(491, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1940PolyExtStep::AndEqz(492, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1941PolyExtStep::AndEqz(493, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1942PolyExtStep::AndEqz(494, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1943PolyExtStep::AndEqz(495, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1944PolyExtStep::AndEqz(496, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1945PolyExtStep::AndEqz(497, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1946PolyExtStep::AndEqz(498, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1947PolyExtStep::AndEqz(499, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1948PolyExtStep::AndEqz(500, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1949PolyExtStep::AndEqz(501, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1950PolyExtStep::AndEqz(502, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1951PolyExtStep::AndEqz(503, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1952PolyExtStep::AndEqz(504, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1953PolyExtStep::AndEqz(505, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1954PolyExtStep::AndEqz(506, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1955PolyExtStep::AndEqz(507, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1956PolyExtStep::AndEqz(508, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1957PolyExtStep::AndEqz(509, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1958PolyExtStep::AndEqz(510, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1959PolyExtStep::AndEqz(511, 1418), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1960PolyExtStep::AndEqz(512, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1961PolyExtStep::AndEqz(513, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1962PolyExtStep::AndEqz(514, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1963PolyExtStep::AndEqz(515, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1964PolyExtStep::AndEqz(516, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1965PolyExtStep::AndEqz(517, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1966PolyExtStep::AndEqz(518, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1967PolyExtStep::AndEqz(519, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1968PolyExtStep::AndEqz(520, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1969PolyExtStep::AndEqz(521, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1970PolyExtStep::AndEqz(522, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1971PolyExtStep::AndEqz(523, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1972PolyExtStep::AndEqz(524, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1973PolyExtStep::AndEqz(525, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1974PolyExtStep::AndEqz(526, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1975PolyExtStep::AndEqz(527, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1976PolyExtStep::AndEqz(528, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1977PolyExtStep::AndEqz(529, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1978PolyExtStep::AndEqz(530, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1979PolyExtStep::AndEqz(531, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1980PolyExtStep::AndEqz(532, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1981PolyExtStep::AndEqz(533, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1982PolyExtStep::AndEqz(534, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1983PolyExtStep::AndEqz(535, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1984PolyExtStep::AndEqz(536, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1985PolyExtStep::AndEqz(537, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1986PolyExtStep::AndEqz(538, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1987PolyExtStep::AndEqz(539, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1988PolyExtStep::AndEqz(540, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1989PolyExtStep::AndEqz(541, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1990PolyExtStep::AndEqz(542, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1991PolyExtStep::AndEqz(543, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1992PolyExtStep::AndEqz(544, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1993PolyExtStep::AndEqz(545, 1419), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1994PolyExtStep::AndEqz(546, 775), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1995PolyExtStep::AndEqz(547, 776), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1996PolyExtStep::AndEqz(548, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1997PolyExtStep::AndEqz(549, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1998PolyExtStep::AndEqz(550, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1999PolyExtStep::AndCond(477, 377, 551), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2000PolyExtStep::AndEqz(368, 1099), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :141:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2001PolyExtStep::AndEqz(553, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2002PolyExtStep::AndEqz(554, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2003PolyExtStep::AndEqz(555, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2004PolyExtStep::AndEqz(556, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2005PolyExtStep::AndEqz(557, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2006PolyExtStep::AndEqz(558, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2007PolyExtStep::AndEqz(559, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2008PolyExtStep::AndEqz(560, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2009PolyExtStep::AndEqz(561, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2010PolyExtStep::AndEqz(562, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2011PolyExtStep::AndEqz(563, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2012PolyExtStep::AndEqz(564, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2013PolyExtStep::AndEqz(565, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2014PolyExtStep::AndEqz(566, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2015PolyExtStep::AndEqz(567, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2016PolyExtStep::AndEqz(568, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2017PolyExtStep::AndEqz(569, 860), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2018PolyExtStep::AndEqz(570, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2019PolyExtStep::AndEqz(571, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2020PolyExtStep::AndEqz(572, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2021PolyExtStep::AndEqz(573, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2022PolyExtStep::AndEqz(574, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2023PolyExtStep::AndEqz(575, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2024PolyExtStep::AndEqz(576, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2025PolyExtStep::AndEqz(577, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2026PolyExtStep::AndEqz(578, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2027PolyExtStep::AndEqz(579, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2028PolyExtStep::AndEqz(580, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2029PolyExtStep::AndEqz(581, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2030PolyExtStep::AndEqz(582, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2031PolyExtStep::AndEqz(583, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2032PolyExtStep::AndEqz(584, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2033PolyExtStep::AndEqz(585, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2034PolyExtStep::AndEqz(586, 1418), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2035PolyExtStep::AndEqz(587, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2036PolyExtStep::AndEqz(588, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2037PolyExtStep::AndEqz(589, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2038PolyExtStep::AndEqz(590, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2039PolyExtStep::AndEqz(591, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2040PolyExtStep::AndEqz(592, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2041PolyExtStep::AndEqz(593, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2042PolyExtStep::AndEqz(594, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2043PolyExtStep::AndEqz(595, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2044PolyExtStep::AndEqz(596, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2045PolyExtStep::AndEqz(597, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2046PolyExtStep::AndEqz(598, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2047PolyExtStep::AndEqz(599, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2048PolyExtStep::AndEqz(600, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2049PolyExtStep::AndEqz(601, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2050PolyExtStep::AndEqz(602, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2051PolyExtStep::AndEqz(603, 1018), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2052PolyExtStep::AndEqz(604, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2053PolyExtStep::AndEqz(605, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2054PolyExtStep::AndEqz(606, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2055PolyExtStep::AndEqz(607, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2056PolyExtStep::AndEqz(608, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2057PolyExtStep::AndEqz(609, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2058PolyExtStep::AndEqz(610, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2059PolyExtStep::AndEqz(611, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2060PolyExtStep::AndEqz(612, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2061PolyExtStep::AndEqz(613, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2062PolyExtStep::AndEqz(614, 1051), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2063PolyExtStep::AndEqz(615, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2064PolyExtStep::AndEqz(616, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2065PolyExtStep::AndEqz(617, 1060), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2066PolyExtStep::AndEqz(618, 1063), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2067PolyExtStep::AndEqz(619, 1066), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2068PolyExtStep::AndEqz(620, 1419), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2069PolyExtStep::AndEqz(621, 775), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2070PolyExtStep::AndEqz(622, 776), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2071PolyExtStep::AndEqz(623, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2072PolyExtStep::AndEqz(624, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2073PolyExtStep::AndEqz(625, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2074PolyExtStep::AndCond(552, 380, 626), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2075PolyExtStep::Sub(1101, 726), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2076PolyExtStep::Sub(1103, 727), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2077PolyExtStep::AndEqz(368, 1100), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :146:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2078PolyExtStep::AndEqz(628, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2079PolyExtStep::AndEqz(629, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2080PolyExtStep::Sub(1420, 1108), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2081PolyExtStep::AndEqz(630, 1422), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2082PolyExtStep::Add(1421, 782), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2083PolyExtStep::AndEqz(631, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2084PolyExtStep::AndEqz(632, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2085PolyExtStep::Sub(1423, 1114), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2086PolyExtStep::AndEqz(633, 1424), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2087PolyExtStep::AndEqz(634, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2088PolyExtStep::AndEqz(635, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2089PolyExtStep::AndEqz(636, 1121), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2090PolyExtStep::AndEqz(637, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2091PolyExtStep::AndEqz(638, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2092PolyExtStep::Sub(727, 1126), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2093PolyExtStep::AndEqz(639, 1425), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2094PolyExtStep::AndEqz(640, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2095PolyExtStep::AndEqz(641, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2096PolyExtStep::AndEqz(642, 1133), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2097PolyExtStep::AndEqz(643, 1139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2098PolyExtStep::AndEqz(644, 1144), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2099PolyExtStep::AndCond(627, 383, 645), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2100PolyExtStep::AndEqz(368, 1145), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :152:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2101PolyExtStep::AndEqz(647, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2102PolyExtStep::AndEqz(648, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2103PolyExtStep::AndEqz(649, 1422), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2104PolyExtStep::AndEqz(650, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2105PolyExtStep::AndEqz(651, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2106PolyExtStep::AndEqz(652, 1424), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2107PolyExtStep::AndEqz(653, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2108PolyExtStep::AndEqz(654, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2109PolyExtStep::AndEqz(655, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2110PolyExtStep::AndCond(646, 386, 656), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2111PolyExtStep::Sub(672, 39), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :158:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2112PolyExtStep::Sub(738, 761), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:25) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2113PolyExtStep::Sub(739, 762), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2114PolyExtStep::AndEqz(0, 1426), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :158:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2115PolyExtStep::AndEqz(658, 722), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :158:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2116PolyExtStep::AndEqz(659, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2117PolyExtStep::Mul(1427, 785), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2118PolyExtStep::Sub(1429, 783), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2119PolyExtStep::AndEqz(660, 1430), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2120PolyExtStep::Mul(782, 1427), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2121PolyExtStep::AndEqz(661, 1431), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2122PolyExtStep::Mul(782, 785), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2123PolyExtStep::AndEqz(662, 1432), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2124PolyExtStep::AndEqz(663, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2125PolyExtStep::Mul(1428, 791), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2126PolyExtStep::Sub(1433, 789), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2127PolyExtStep::AndEqz(664, 1434), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2128PolyExtStep::Mul(788, 1428), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2129PolyExtStep::AndEqz(665, 1435), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2130PolyExtStep::Mul(788, 791), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2131PolyExtStep::AndEqz(666, 1436), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2132PolyExtStep::Mul(782, 788), // loc(callsite( builtin Mul at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:27) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2133PolyExtStep::Sub(1437, 794), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2134PolyExtStep::AndEqz(667, 1438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2135PolyExtStep::AndEqz(668, 775), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2136PolyExtStep::AndEqz(669, 776), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2137PolyExtStep::AndEqz(670, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2138PolyExtStep::AndEqz(671, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2139PolyExtStep::AndEqz(672, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2140PolyExtStep::AndCond(657, 389, 673), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2141PolyExtStep::Sub(722, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :164:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2142PolyExtStep::AndEqz(658, 1439), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :164:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2143PolyExtStep::AndEqz(675, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2144PolyExtStep::AndEqz(676, 1430), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2145PolyExtStep::AndEqz(677, 1431), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2146PolyExtStep::AndEqz(678, 1432), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2147PolyExtStep::AndEqz(679, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2148PolyExtStep::AndEqz(680, 1434), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2149PolyExtStep::AndEqz(681, 1435), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2150PolyExtStep::AndEqz(682, 1436), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2151PolyExtStep::AndEqz(683, 1438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2152PolyExtStep::AndEqz(684, 775), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2153PolyExtStep::AndEqz(685, 776), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2154PolyExtStep::AndEqz(686, 777), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2155PolyExtStep::AndEqz(687, 778), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2156PolyExtStep::AndEqz(688, 779), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2157PolyExtStep::AndCond(674, 392, 689), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2158PolyExtStep::AndEqz(658, 781), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :170:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2159PolyExtStep::AndEqz(691, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2160PolyExtStep::AndEqz(692, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2161PolyExtStep::AndEqz(693, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2162PolyExtStep::AndEqz(694, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2163PolyExtStep::AndEqz(695, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2164PolyExtStep::AndEqz(696, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2165PolyExtStep::AndEqz(697, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2166PolyExtStep::AndEqz(698, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2167PolyExtStep::AndEqz(699, 1121), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2168PolyExtStep::AndEqz(700, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2169PolyExtStep::AndEqz(701, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2170PolyExtStep::AndEqz(702, 1127), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2171PolyExtStep::AndEqz(703, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2172PolyExtStep::AndEqz(704, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2173PolyExtStep::AndEqz(705, 1133), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2174PolyExtStep::AndEqz(706, 1139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2175PolyExtStep::AndEqz(707, 1144), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2176PolyExtStep::AndCond(690, 395, 708), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2177PolyExtStep::Sub(1237, 1228), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2178PolyExtStep::Mul(1440, 374), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2179PolyExtStep::Sub(1237, 1227), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2180PolyExtStep::Mul(1442, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2181PolyExtStep::Mul(1227, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2182PolyExtStep::Mul(1156, 383), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2183PolyExtStep::Mul(1235, 386), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2184PolyExtStep::Add(1441, 1443), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2185PolyExtStep::Add(1447, 1444), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2186PolyExtStep::Add(1448, 1445), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2187PolyExtStep::Add(1449, 1446), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2188PolyExtStep::Sub(1333, 1327), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2189PolyExtStep::Mul(1451, 374), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2190PolyExtStep::Sub(1333, 1326), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2191PolyExtStep::Mul(1453, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2192PolyExtStep::Mul(1326, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2193PolyExtStep::Add(1452, 1454), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2194PolyExtStep::Add(1456, 1455), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2195PolyExtStep::Add(365, 1417), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2196PolyExtStep::Mul(1154, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2197PolyExtStep::Sub(1, 1154), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2198PolyExtStep::Mul(1460, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2199PolyExtStep::Add(1459, 1461), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2200PolyExtStep::Mul(1462, 389), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2201PolyExtStep::Mul(1460, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2202PolyExtStep::Sub(1, 1460), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2203PolyExtStep::Mul(1465, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2204PolyExtStep::Add(1464, 1466), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2205PolyExtStep::Mul(1467, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2206PolyExtStep::Mul(1156, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2207PolyExtStep::Sub(1, 1156), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2208PolyExtStep::Mul(1470, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2209PolyExtStep::Add(1469, 1471), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2210PolyExtStep::Mul(1472, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2211PolyExtStep::Add(516, 1463), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2212PolyExtStep::Add(1474, 1468), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2213PolyExtStep::Add(1475, 1473), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2214PolyExtStep::Add(367, 727), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2215PolyExtStep::Mul(1154, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2216PolyExtStep::Mul(1460, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2217PolyExtStep::Add(1478, 1479), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2218PolyExtStep::Mul(1480, 389), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2219PolyExtStep::Mul(1460, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2220PolyExtStep::Mul(1465, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2221PolyExtStep::Add(1482, 1483), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2222PolyExtStep::Mul(1484, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2223PolyExtStep::Mul(1156, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2224PolyExtStep::Mul(1470, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2225PolyExtStep::Add(1486, 1487), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2226PolyExtStep::Mul(1488, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2227PolyExtStep::Add(531, 1481), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2228PolyExtStep::Add(1490, 1485), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2229PolyExtStep::Add(1491, 1489), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2230PolyExtStep::AndEqz(709, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2231PolyExtStep::AndEqz(710, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2232PolyExtStep::Sub(1450, 1347), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2233PolyExtStep::AndEqz(711, 1493), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2234PolyExtStep::Add(1457, 1343), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2235PolyExtStep::AndEqz(712, 1352), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2236PolyExtStep::AndEqz(713, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2237PolyExtStep::Sub(1494, 1357), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2238PolyExtStep::AndEqz(714, 1495), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2239PolyExtStep::AndEqz(715, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2240PolyExtStep::AndEqz(716, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2241PolyExtStep::Sub(1476, 1366), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2242PolyExtStep::AndEqz(717, 1496), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2243PolyExtStep::Add(1492, 1362), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2244PolyExtStep::AndEqz(718, 1371), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2245PolyExtStep::AndEqz(719, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2246PolyExtStep::Sub(1497, 1376), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2247PolyExtStep::AndEqz(720, 1498), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2248PolyExtStep::AndEqz(721, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2249PolyExtStep::AndEqz(722, 1383), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2250PolyExtStep::AndEqz(723, 1384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2251PolyExtStep::AndEqz(724, 1385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2252PolyExtStep::Mul(1380, 401), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :43:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2253PolyExtStep::Mul(1499, 714), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2254PolyExtStep::Sub(1, 1499), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2255PolyExtStep::Mul(1501, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2256PolyExtStep::Add(503, 1502), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2257PolyExtStep::Add(1503, 1500), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2258PolyExtStep::Sub(1504, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2259PolyExtStep::AndEqz(725, 1505), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2260PolyExtStep::AndEqz(726, 1401), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2261PolyExtStep::AndEqz(727, 1402), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2262PolyExtStep::AndEqz(728, 1403), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2263PolyExtStep::AndEqz(729, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2264PolyExtStep::AndEqz(730, 1404), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2265PolyExtStep::AndEqz(731, 1408), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2266PolyExtStep::AndEqz(732, 1409), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2267PolyExtStep::AndEqz(733, 1410), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2268PolyExtStep::AndEqz(734, 1411), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :57:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2269PolyExtStep::AndCond(402, 422, 735), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
2270PolyExtStep::Add(383, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2271PolyExtStep::Add(1506, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2272PolyExtStep::Add(1507, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2273PolyExtStep::Add(508, 509), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2274PolyExtStep::Add(523, 524), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2275PolyExtStep::Mul(365, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2276PolyExtStep::Mul(722, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2277PolyExtStep::Add(690, 1512), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2278PolyExtStep::Mul(625, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2279PolyExtStep::Add(1513, 1514), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:33) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2280PolyExtStep::Add(1515, 1414), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:51) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2281PolyExtStep::Add(1516, 707), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:70) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2282PolyExtStep::Add(1517, 708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:85) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2283PolyExtStep::Mul(587, 40), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:7) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2284PolyExtStep::Add(1519, 686), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2285PolyExtStep::Add(1520, 635), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :62:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2286PolyExtStep::Sub(722, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :176:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2287PolyExtStep::AndEqz(658, 1522), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :176:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2288PolyExtStep::AndEqz(737, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2289PolyExtStep::AndEqz(738, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2290PolyExtStep::AndEqz(739, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2291PolyExtStep::AndEqz(740, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2292PolyExtStep::AndEqz(741, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2293PolyExtStep::AndEqz(742, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2294PolyExtStep::AndEqz(743, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2295PolyExtStep::AndEqz(744, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2296PolyExtStep::AndEqz(745, 1121), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2297PolyExtStep::AndEqz(746, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2298PolyExtStep::AndEqz(747, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2299PolyExtStep::AndEqz(748, 1127), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2300PolyExtStep::AndEqz(749, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2301PolyExtStep::AndEqz(750, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2302PolyExtStep::AndEqz(751, 1133), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2303PolyExtStep::AndEqz(752, 1139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2304PolyExtStep::AndEqz(753, 1144), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2305PolyExtStep::AndCond(91, 374, 754), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2306PolyExtStep::AndEqz(658, 1098), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :182:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2307PolyExtStep::AndEqz(756, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2308PolyExtStep::AndEqz(757, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2309PolyExtStep::AndEqz(758, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2310PolyExtStep::AndEqz(759, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2311PolyExtStep::AndEqz(760, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2312PolyExtStep::AndEqz(761, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2313PolyExtStep::AndEqz(762, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2314PolyExtStep::AndEqz(763, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2315PolyExtStep::AndEqz(764, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2316PolyExtStep::AndCond(755, 377, 765), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2317PolyExtStep::AndEqz(658, 1099), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :188:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2318PolyExtStep::AndEqz(767, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2319PolyExtStep::AndEqz(768, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2320PolyExtStep::AndEqz(769, 1109), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2321PolyExtStep::AndEqz(770, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2322PolyExtStep::AndEqz(771, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2323PolyExtStep::AndEqz(772, 1115), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2324PolyExtStep::AndEqz(773, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2325PolyExtStep::AndEqz(774, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2326PolyExtStep::AndEqz(775, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2327PolyExtStep::AndCond(766, 380, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2328PolyExtStep::Sub(672, 41), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :194:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2329PolyExtStep::AndEqz(0, 1523), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :194:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2330PolyExtStep::AndEqz(778, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2331PolyExtStep::AndEqz(779, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2332PolyExtStep::AndEqz(780, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2333PolyExtStep::AndEqz(781, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2334PolyExtStep::AndEqz(782, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2335PolyExtStep::AndCond(777, 383, 783), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2336PolyExtStep::Sub(672, 42), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :201:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2337PolyExtStep::AndEqz(0, 1524), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :201:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2338PolyExtStep::AndEqz(785, 722), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :201:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2339PolyExtStep::AndEqz(786, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2340PolyExtStep::AndEqz(787, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2341PolyExtStep::AndEqz(788, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2342PolyExtStep::AndEqz(789, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2343PolyExtStep::AndEqz(790, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2344PolyExtStep::AndCond(784, 386, 791), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2345PolyExtStep::Sub(672, 43), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :208:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2346PolyExtStep::AndEqz(0, 1525), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :208:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2347PolyExtStep::AndEqz(793, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2348PolyExtStep::AndEqz(794, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2349PolyExtStep::AndEqz(795, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2350PolyExtStep::AndEqz(796, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2351PolyExtStep::AndEqz(797, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2352PolyExtStep::AndCond(792, 389, 798), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2353PolyExtStep::Sub(672, 44), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :213:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2354PolyExtStep::AndEqz(0, 1526), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :213:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2355PolyExtStep::AndEqz(800, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2356PolyExtStep::AndEqz(801, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2357PolyExtStep::AndEqz(802, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2358PolyExtStep::AndEqz(803, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2359PolyExtStep::AndEqz(804, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2360PolyExtStep::AndCond(799, 392, 805), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2361PolyExtStep::Sub(672, 45), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :219:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2362PolyExtStep::AndEqz(0, 1527), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :219:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2363PolyExtStep::AndEqz(807, 722), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :219:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2364PolyExtStep::AndEqz(808, 720), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :219:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2365PolyExtStep::AndEqz(809, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2366PolyExtStep::AndEqz(810, 776), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2367PolyExtStep::AndEqz(811, 777), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2368PolyExtStep::AndEqz(812, 778), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2369PolyExtStep::AndEqz(813, 779), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2370PolyExtStep::AndCond(806, 395, 814), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2371PolyExtStep::Mul(694, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2372PolyExtStep::Add(365, 694), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2373PolyExtStep::Mul(1529, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2374PolyExtStep::Add(1509, 1528), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2375PolyExtStep::Add(1531, 1530), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2376PolyExtStep::Mul(575, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2377PolyExtStep::Add(367, 575), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2378PolyExtStep::Mul(1534, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2379PolyExtStep::Add(1510, 1533), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2380PolyExtStep::Add(1536, 1535), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2381PolyExtStep::Mul(1470, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2382PolyExtStep::Sub(1, 1470), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2383PolyExtStep::Mul(1539, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2384PolyExtStep::Add(1538, 1540), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2385PolyExtStep::Mul(1541, 374), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2386PolyExtStep::Mul(1235, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2387PolyExtStep::Sub(1, 1235), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2388PolyExtStep::Mul(1544, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2389PolyExtStep::Add(1543, 1545), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2390PolyExtStep::Mul(1546, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2391PolyExtStep::Mul(1544, 1458), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2392PolyExtStep::Sub(1, 1544), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2393PolyExtStep::Mul(1549, 504), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2394PolyExtStep::Add(1548, 1550), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2395PolyExtStep::Mul(1551, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2396PolyExtStep::Add(365, 1518), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :197:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2397PolyExtStep::Mul(1553, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2398PolyExtStep::Mul(1237, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2399PolyExtStep::Add(1542, 1547), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2400PolyExtStep::Add(1556, 1552), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2401PolyExtStep::Add(1557, 1554), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2402PolyExtStep::Add(1558, 1555), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2403PolyExtStep::Add(1559, 510), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2404PolyExtStep::Add(1560, 511), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2405PolyExtStep::Add(1561, 1511), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2406PolyExtStep::Mul(1470, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2407PolyExtStep::Mul(1539, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2408PolyExtStep::Add(1563, 1564), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2409PolyExtStep::Mul(1565, 374), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2410PolyExtStep::Mul(1235, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2411PolyExtStep::Mul(1544, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2412PolyExtStep::Add(1567, 1568), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2413PolyExtStep::Mul(1569, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2414PolyExtStep::Mul(1544, 1477), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2415PolyExtStep::Mul(1549, 367), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2416PolyExtStep::Add(1571, 1572), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :82:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2417PolyExtStep::Mul(1573, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2418PolyExtStep::Add(367, 1521), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :197:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2419PolyExtStep::Mul(1575, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2420PolyExtStep::Mul(1333, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2421PolyExtStep::Add(1566, 1570), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2422PolyExtStep::Add(1578, 1574), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2423PolyExtStep::Add(1579, 1576), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2424PolyExtStep::Add(1580, 1577), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2425PolyExtStep::Add(1581, 525), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2426PolyExtStep::Add(1582, 526), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2427PolyExtStep::Add(1583, 527), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2428PolyExtStep::AndEqz(815, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2429PolyExtStep::AndEqz(816, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2430PolyExtStep::Sub(1532, 1347), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2431PolyExtStep::AndEqz(817, 1585), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2432PolyExtStep::Add(1537, 1343), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2433PolyExtStep::AndEqz(818, 1352), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2434PolyExtStep::AndEqz(819, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2435PolyExtStep::Sub(1586, 1357), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2436PolyExtStep::AndEqz(820, 1587), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :22:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2437PolyExtStep::AndEqz(821, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2438PolyExtStep::AndEqz(822, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2439PolyExtStep::Sub(1562, 1366), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2440PolyExtStep::AndEqz(823, 1588), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2441PolyExtStep::Add(1584, 1362), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2442PolyExtStep::AndEqz(824, 1371), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2443PolyExtStep::AndEqz(825, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2444PolyExtStep::Sub(1589, 1376), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2445PolyExtStep::AndEqz(826, 1590), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2446PolyExtStep::AndEqz(827, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2447PolyExtStep::AndEqz(828, 1383), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2448PolyExtStep::AndEqz(829, 1384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2449PolyExtStep::AndEqz(830, 1385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2450PolyExtStep::Mul(1380, 1508), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :43:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2451PolyExtStep::Mul(1591, 714), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2452PolyExtStep::Sub(1, 1591), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2453PolyExtStep::Mul(1593, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2454PolyExtStep::Add(503, 1594), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2455PolyExtStep::Add(1595, 1592), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2456PolyExtStep::Sub(1596, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2457PolyExtStep::AndEqz(831, 1597), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2458PolyExtStep::AndEqz(832, 1401), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2459PolyExtStep::AndEqz(833, 1402), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2460PolyExtStep::AndEqz(834, 1403), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2461PolyExtStep::AndEqz(835, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2462PolyExtStep::AndEqz(836, 1404), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2463PolyExtStep::AndEqz(837, 1408), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2464PolyExtStep::AndEqz(838, 1409), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2465PolyExtStep::AndEqz(839, 1410), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2466PolyExtStep::AndEqz(840, 1411), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :73:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2467PolyExtStep::AndCond(736, 425, 841), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
2468PolyExtStep::Sub(536, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2469PolyExtStep::AndEqz(0, 1598), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2470PolyExtStep::Sub(590, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2471PolyExtStep::AndEqz(843, 1599), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2472PolyExtStep::AndEqz(844, 494), // loc(callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :8:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2473PolyExtStep::Sub(1, 549), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2474PolyExtStep::Mul(549, 1600), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2475PolyExtStep::Sub(7, 549), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2476PolyExtStep::Mul(1601, 1602), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2477PolyExtStep::Sub(6, 549), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2478PolyExtStep::Mul(1603, 1604), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2479PolyExtStep::AndEqz(845, 1605), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2480PolyExtStep::Sub(552, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2481PolyExtStep::AndEqz(846, 1606), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2482PolyExtStep::Sub(553, 499), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2483PolyExtStep::AndEqz(847, 1607), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2484PolyExtStep::Sub(1, 560), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2485PolyExtStep::Mul(560, 1608), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2486PolyExtStep::AndEqz(848, 1609), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2487PolyExtStep::Mul(367, 561), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2488PolyExtStep::Sub(1610, 1608), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2489PolyExtStep::AndEqz(849, 1611), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2490PolyExtStep::Mul(560, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2491PolyExtStep::AndEqz(850, 1612), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2492PolyExtStep::Mul(560, 561), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2493PolyExtStep::AndEqz(851, 1613), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2494PolyExtStep::AndEqz(852, 560), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2495PolyExtStep::Sub(568, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2496PolyExtStep::AndEqz(853, 1614), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2497PolyExtStep::Mul(567, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2498PolyExtStep::Add(1615, 549), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2499PolyExtStep::Sub(1616, 365), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2500PolyExtStep::AndEqz(854, 1617), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2501PolyExtStep::Add(500, 567), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2502PolyExtStep::AndEqz(855, 549), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2503PolyExtStep::Sub(570, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2504PolyExtStep::AndEqz(856, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2505PolyExtStep::Sub(574, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2506PolyExtStep::AndEqz(857, 1620), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2507PolyExtStep::Sub(575, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2508PolyExtStep::AndEqz(858, 1621), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2509PolyExtStep::AndEqz(859, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2510PolyExtStep::Sub(569, 1618), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2511PolyExtStep::AndEqz(860, 1622), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2512PolyExtStep::Sub(572, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2513PolyExtStep::AndEqz(861, 1623), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2514PolyExtStep::Sub(573, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2515PolyExtStep::AndEqz(862, 1624), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2516PolyExtStep::Sub(575, 571), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2517PolyExtStep::Sub(732, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2518PolyExtStep::AndEqz(863, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2519PolyExtStep::Sub(731, 1625), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2520PolyExtStep::AndEqz(864, 1627), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2521PolyExtStep::AndEqz(865, 599), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2522PolyExtStep::AndEqz(866, 610), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2523PolyExtStep::AndEqz(867, 617), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2524PolyExtStep::AndEqz(868, 624), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2525PolyExtStep::Sub(7, 625), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2526PolyExtStep::Mul(627, 1628), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2527PolyExtStep::Sub(6, 625), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2528PolyExtStep::Mul(1629, 1630), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2529PolyExtStep::AndEqz(869, 1631), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2530PolyExtStep::AndEqz(870, 634), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2531PolyExtStep::AndEqz(871, 637), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2532PolyExtStep::Sub(7, 642), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2533PolyExtStep::Mul(644, 1632), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2534PolyExtStep::Sub(6, 642), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2535PolyExtStep::Mul(1633, 1634), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2536PolyExtStep::AndEqz(872, 1635), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2537PolyExtStep::Sub(7, 645), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2538PolyExtStep::Mul(647, 1636), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2539PolyExtStep::Sub(6, 645), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2540PolyExtStep::Mul(1637, 1638), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2541PolyExtStep::AndEqz(873, 1639), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2542PolyExtStep::AndEqz(874, 650), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2543PolyExtStep::AndEqz(875, 657), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2544PolyExtStep::AndEqz(876, 668), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2545PolyExtStep::Sub(7, 669), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2546PolyExtStep::Mul(671, 1640), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2547PolyExtStep::Sub(6, 669), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2548PolyExtStep::Mul(1641, 1642), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2549PolyExtStep::AndEqz(877, 1643), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2550PolyExtStep::Sub(1, 672), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2551PolyExtStep::Mul(672, 1644), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2552PolyExtStep::Sub(7, 672), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2553PolyExtStep::Mul(1645, 1646), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2554PolyExtStep::Sub(6, 672), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2555PolyExtStep::Mul(1647, 1648), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2556PolyExtStep::AndEqz(878, 1649), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2557PolyExtStep::AndEqz(879, 543), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2558PolyExtStep::Mul(597, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2559PolyExtStep::Mul(604, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2560PolyExtStep::Add(1650, 1651), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2561PolyExtStep::Mul(611, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2562PolyExtStep::Add(1652, 1653), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2563PolyExtStep::Mul(618, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2564PolyExtStep::Add(1654, 1655), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2565PolyExtStep::Mul(625, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2566PolyExtStep::Add(1656, 1657), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2567PolyExtStep::Mul(628, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2568PolyExtStep::Add(1658, 1659), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2569PolyExtStep::Mul(635, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2570PolyExtStep::Add(1660, 1661), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2571PolyExtStep::Mul(642, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2572PolyExtStep::Add(1662, 1663), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2573PolyExtStep::Add(1664, 645), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2574PolyExtStep::Sub(584, 1665), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2575PolyExtStep::AndEqz(880, 1666), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2576PolyExtStep::Mul(648, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2577PolyExtStep::Mul(655, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2578PolyExtStep::Add(1667, 1668), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2579PolyExtStep::Mul(662, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2580PolyExtStep::Add(1669, 1670), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2581PolyExtStep::Mul(669, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2582PolyExtStep::Add(1671, 1672), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2583PolyExtStep::Mul(672, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2584PolyExtStep::Add(1673, 1674), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2585PolyExtStep::Mul(541, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2586PolyExtStep::Add(1675, 1676), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2587PolyExtStep::Add(1677, 548), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2588PolyExtStep::Sub(583, 1678), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2589PolyExtStep::AndEqz(881, 1679), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2590PolyExtStep::Mul(642, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2591PolyExtStep::Mul(645, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2592PolyExtStep::Add(1680, 1681), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2593PolyExtStep::Add(1682, 648), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2594PolyExtStep::Mul(625, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2595PolyExtStep::Mul(628, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2596PolyExtStep::Add(1684, 1685), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2597PolyExtStep::Add(1686, 635), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2598PolyExtStep::Mul(669, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2599PolyExtStep::Mul(672, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2600PolyExtStep::Add(1688, 1689), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2601PolyExtStep::Add(1690, 541), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2602PolyExtStep::Mul(604, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2603PolyExtStep::Mul(611, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2604PolyExtStep::Add(1692, 1693), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2605PolyExtStep::Add(1694, 618), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2606PolyExtStep::Mul(597, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2607PolyExtStep::Add(1696, 1695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2608PolyExtStep::Mul(655, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2609PolyExtStep::Add(1698, 662), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2610PolyExtStep::Add(503, 1683), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2611PolyExtStep::Sub(1700, 754), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2612PolyExtStep::AndEqz(882, 1701), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2613PolyExtStep::Sub(734, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2614PolyExtStep::AndEqz(883, 1702), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2615PolyExtStep::Sub(738, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2616PolyExtStep::AndEqz(884, 1703), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2617PolyExtStep::Sub(739, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2618PolyExtStep::AndEqz(885, 1704), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2619PolyExtStep::AndEqz(886, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2620PolyExtStep::Sub(733, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2621PolyExtStep::AndEqz(887, 1705), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2622PolyExtStep::Sub(736, 747), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2623PolyExtStep::AndEqz(888, 1706), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2624PolyExtStep::Sub(737, 748), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2625PolyExtStep::AndEqz(889, 1707), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2626PolyExtStep::Sub(739, 735), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2627PolyExtStep::Sub(729, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2628PolyExtStep::AndEqz(890, 1709), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2629PolyExtStep::Sub(755, 1708), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2630PolyExtStep::AndEqz(891, 1710), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2631PolyExtStep::Add(503, 1687), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2632PolyExtStep::Sub(1711, 785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2633PolyExtStep::AndEqz(892, 1712), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2634PolyExtStep::Sub(757, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2635PolyExtStep::AndEqz(893, 1713), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2636PolyExtStep::Sub(761, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2637PolyExtStep::AndEqz(894, 1714), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2638PolyExtStep::Sub(762, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2639PolyExtStep::AndEqz(895, 1715), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2640PolyExtStep::AndEqz(896, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2641PolyExtStep::Sub(756, 785), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2642PolyExtStep::AndEqz(897, 1716), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2643PolyExtStep::Sub(759, 770), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2644PolyExtStep::AndEqz(898, 1717), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2645PolyExtStep::Sub(760, 771), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2646PolyExtStep::AndEqz(899, 1718), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2647PolyExtStep::Sub(762, 758), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2648PolyExtStep::Sub(752, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2649PolyExtStep::AndEqz(900, 1720), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2650PolyExtStep::Sub(782, 1719), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2651PolyExtStep::AndEqz(901, 1721), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :12:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2652PolyExtStep::Sub(548, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :48:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2653PolyExtStep::Sub(1699, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :48:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2654PolyExtStep::AndEqz(0, 1722), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :48:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2655PolyExtStep::AndEqz(903, 1723), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :48:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2656PolyExtStep::AndEqz(904, 1697), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :48:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2657PolyExtStep::AndEqz(905, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2658PolyExtStep::AndEqz(906, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2659PolyExtStep::AndEqz(907, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2660PolyExtStep::AndEqz(908, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2661PolyExtStep::AndEqz(909, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2662PolyExtStep::Mul(791, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2663PolyExtStep::Mul(794, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2664PolyExtStep::Mul(797, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2665PolyExtStep::Mul(800, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2666PolyExtStep::Add(788, 1724), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2667PolyExtStep::Add(1728, 1725), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2668PolyExtStep::Add(1729, 1726), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2669PolyExtStep::Add(1730, 1727), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2670PolyExtStep::AndEqz(910, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2671PolyExtStep::Mul(1105, 24), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:4) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2672PolyExtStep::Add(1732, 1731), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2673PolyExtStep::Sub(1733, 770), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2674PolyExtStep::AndEqz(911, 1734), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2675PolyExtStep::Mul(788, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2676PolyExtStep::Add(1735, 789), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2677PolyExtStep::Mul(791, 1736), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2678PolyExtStep::Mul(1737, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2679PolyExtStep::Mul(792, 1736), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2680PolyExtStep::Add(1738, 1739), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2681PolyExtStep::Mul(794, 1740), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2682PolyExtStep::Mul(1741, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2683PolyExtStep::Mul(795, 1740), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2684PolyExtStep::Add(1742, 1743), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2685PolyExtStep::Sub(1744, 803), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2686PolyExtStep::AndEqz(912, 1745), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2687PolyExtStep::Mul(797, 803), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2688PolyExtStep::Mul(1746, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2689PolyExtStep::Mul(798, 803), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2690PolyExtStep::Add(1747, 1748), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2691PolyExtStep::Mul(801, 1749), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2692PolyExtStep::Sub(1750, 806), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2693PolyExtStep::AndEqz(913, 1751), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2694PolyExtStep::Mul(800, 1749), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2695PolyExtStep::Sub(1752, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2696PolyExtStep::AndEqz(914, 1753), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2697PolyExtStep::Sub(1343, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2698PolyExtStep::AndEqz(915, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2699PolyExtStep::Sub(1351, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2700PolyExtStep::AndEqz(916, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2701PolyExtStep::AndEqz(917, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2702PolyExtStep::Sub(1362, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2703PolyExtStep::AndEqz(918, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2704PolyExtStep::Sub(1370, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2705PolyExtStep::AndEqz(919, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2706PolyExtStep::AndEqz(920, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2707PolyExtStep::Mul(1353, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2708PolyExtStep::Add(1350, 1758), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2709PolyExtStep::Sub(747, 1759), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2710PolyExtStep::AndEqz(921, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2711PolyExtStep::Mul(1372, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2712PolyExtStep::Add(1360, 1761), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2713PolyExtStep::Mul(812, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2714PolyExtStep::Add(1762, 1763), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2715PolyExtStep::Sub(748, 1764), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2716PolyExtStep::AndEqz(922, 1765), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2717PolyExtStep::Mul(1372, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2718PolyExtStep::Mul(812, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2719PolyExtStep::Add(1766, 1767), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2720PolyExtStep::Sub(1369, 1768), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2721PolyExtStep::AndEqz(923, 1769), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2722PolyExtStep::Sub(1378, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2723PolyExtStep::AndEqz(924, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2724PolyExtStep::Sub(1392, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2725PolyExtStep::AndEqz(925, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2726PolyExtStep::Sub(1394, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2727PolyExtStep::AndEqz(926, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2728PolyExtStep::Get(293), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2729PolyExtStep::Get(299), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :10:27) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2730PolyExtStep::Sub(1773, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2731PolyExtStep::AndEqz(927, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2732PolyExtStep::AndEqz(928, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2733PolyExtStep::AndEqz(929, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2734PolyExtStep::Mul(1395, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2735PolyExtStep::Add(1379, 1776), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2736PolyExtStep::Sub(806, 1777), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2737PolyExtStep::AndEqz(930, 1778), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2738PolyExtStep::Mul(1398, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2739PolyExtStep::Add(1396, 1779), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2740PolyExtStep::Mul(815, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2741PolyExtStep::Add(1780, 1781), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2742PolyExtStep::Sub(809, 1782), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2743PolyExtStep::AndEqz(931, 1783), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2744PolyExtStep::Mul(1398, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2745PolyExtStep::Mul(815, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2746PolyExtStep::Add(1784, 1785), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2747PolyExtStep::Sub(1774, 1786), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2748PolyExtStep::AndEqz(932, 1787), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2749PolyExtStep::AndEqz(933, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2750PolyExtStep::AndEqz(934, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2751PolyExtStep::Mul(818, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2752PolyExtStep::Mul(1111, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2753PolyExtStep::Add(1788, 1789), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2754PolyExtStep::Sub(0, 1790), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2755PolyExtStep::AndEqz(935, 1791), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2756PolyExtStep::Mul(1350, 1379), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2757PolyExtStep::Mul(1350, 1395), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2758PolyExtStep::Mul(1353, 1379), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2759PolyExtStep::Add(1793, 1794), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2760PolyExtStep::Mul(1795, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2761PolyExtStep::Add(1792, 1796), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2762PolyExtStep::AndEqz(936, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2763PolyExtStep::Sub(1399, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2764PolyExtStep::AndEqz(937, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2765PolyExtStep::AndEqz(938, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2766PolyExtStep::AndEqz(939, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2767PolyExtStep::Mul(824, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2768PolyExtStep::Add(1799, 821), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2769PolyExtStep::Mul(1800, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2770PolyExtStep::Mul(1400, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2771PolyExtStep::Add(1801, 1802), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2772PolyExtStep::Add(1803, 1116), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2773PolyExtStep::Sub(1797, 1804), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2774PolyExtStep::AndEqz(940, 1805), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2775PolyExtStep::Mul(1800, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2776PolyExtStep::Add(1806, 1400), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2777PolyExtStep::Mul(1350, 1396), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2778PolyExtStep::Add(1807, 1808), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2779PolyExtStep::Mul(1353, 1395), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2780PolyExtStep::Add(1809, 1810), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2781PolyExtStep::Mul(1360, 1379), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2782PolyExtStep::Add(1811, 1812), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2783PolyExtStep::Mul(1350, 1774), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2784PolyExtStep::Mul(1353, 1396), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2785PolyExtStep::Add(1814, 1815), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2786PolyExtStep::Mul(1360, 1395), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2787PolyExtStep::Add(1816, 1817), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2788PolyExtStep::Mul(1369, 1379), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2789PolyExtStep::Add(1818, 1819), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2790PolyExtStep::Mul(1820, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2791PolyExtStep::Add(1813, 1821), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2792PolyExtStep::AndEqz(941, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2793PolyExtStep::AndEqz(942, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2794PolyExtStep::AndEqz(943, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2795PolyExtStep::AndEqz(944, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2796PolyExtStep::Mul(861, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2797PolyExtStep::Add(1823, 827), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2798PolyExtStep::Mul(1824, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2799PolyExtStep::Mul(1407, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2800PolyExtStep::Add(1825, 1826), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2801PolyExtStep::Add(1827, 1122), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2802PolyExtStep::Sub(1822, 1828), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2803PolyExtStep::AndEqz(945, 1829), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2804PolyExtStep::Mul(1824, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2805PolyExtStep::Add(1830, 1407), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2806PolyExtStep::Add(1831, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2807PolyExtStep::Mul(1353, 1774), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2808PolyExtStep::Add(1832, 1833), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2809PolyExtStep::Mul(1360, 1396), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2810PolyExtStep::Add(1834, 1835), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2811PolyExtStep::Mul(1369, 1395), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2812PolyExtStep::Add(1836, 1837), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2813PolyExtStep::Mul(1360, 1774), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2814PolyExtStep::Mul(1369, 1396), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2815PolyExtStep::Add(1839, 1840), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2816PolyExtStep::Mul(1841, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2817PolyExtStep::Add(1838, 1842), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2818PolyExtStep::AndEqz(946, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2819PolyExtStep::Get(341), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2820PolyExtStep::Sub(1844, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2821PolyExtStep::AndEqz(947, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2822PolyExtStep::AndEqz(948, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2823PolyExtStep::AndEqz(949, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2824PolyExtStep::Mul(867, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2825PolyExtStep::Add(1846, 864), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2826PolyExtStep::Mul(1847, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2827PolyExtStep::Mul(535, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2828PolyExtStep::Add(1848, 1849), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2829PolyExtStep::Add(1850, 1128), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2830PolyExtStep::Sub(1843, 1851), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2831PolyExtStep::AndEqz(950, 1852), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2832PolyExtStep::Mul(1847, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2833PolyExtStep::Add(1853, 535), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2834PolyExtStep::Add(1854, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2835PolyExtStep::Mul(1369, 1774), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2836PolyExtStep::Add(1855, 1856), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2837PolyExtStep::AndEqz(951, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2838PolyExtStep::Sub(1857, 1341), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2839PolyExtStep::Mul(1858, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2840PolyExtStep::AndEqz(952, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2841PolyExtStep::AndEqz(953, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2842PolyExtStep::Mul(873, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2843PolyExtStep::Add(1860, 870), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2844PolyExtStep::Sub(1859, 1861), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2845PolyExtStep::AndEqz(954, 1862), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2846PolyExtStep::AndCond(902, 374, 955), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2847PolyExtStep::Sub(548, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :55:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2848PolyExtStep::AndEqz(0, 1863), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :55:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2849PolyExtStep::AndEqz(957, 1723), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :55:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2850PolyExtStep::AndEqz(958, 1697), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :55:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2851PolyExtStep::AndEqz(959, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2852PolyExtStep::AndEqz(960, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2853PolyExtStep::AndEqz(961, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2854PolyExtStep::AndEqz(962, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2855PolyExtStep::AndEqz(963, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2856PolyExtStep::AndEqz(964, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2857PolyExtStep::Sub(1733, 1687), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2858PolyExtStep::AndEqz(965, 1864), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2859PolyExtStep::AndEqz(966, 1745), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2860PolyExtStep::AndEqz(967, 1751), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2861PolyExtStep::AndEqz(968, 1753), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2862PolyExtStep::AndEqz(969, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2863PolyExtStep::AndEqz(970, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2864PolyExtStep::AndEqz(971, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2865PolyExtStep::AndEqz(972, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2866PolyExtStep::AndEqz(973, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2867PolyExtStep::AndEqz(974, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2868PolyExtStep::AndEqz(975, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2869PolyExtStep::AndEqz(976, 1765), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2870PolyExtStep::AndEqz(977, 1769), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2871PolyExtStep::AndEqz(978, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2872PolyExtStep::AndEqz(979, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2873PolyExtStep::AndEqz(980, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2874PolyExtStep::AndEqz(981, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2875PolyExtStep::AndEqz(982, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2876PolyExtStep::AndEqz(983, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2877PolyExtStep::AndEqz(984, 1778), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2878PolyExtStep::AndEqz(985, 1783), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2879PolyExtStep::AndEqz(986, 1787), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2880PolyExtStep::AndEqz(987, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2881PolyExtStep::AndEqz(988, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2882PolyExtStep::AndEqz(989, 1791), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2883PolyExtStep::AndEqz(990, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2884PolyExtStep::AndEqz(991, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2885PolyExtStep::AndEqz(992, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2886PolyExtStep::AndEqz(993, 826), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2887PolyExtStep::AndEqz(994, 1805), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2888PolyExtStep::AndEqz(995, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2889PolyExtStep::AndEqz(996, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2890PolyExtStep::AndEqz(997, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2891PolyExtStep::AndEqz(998, 863), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2892PolyExtStep::AndEqz(999, 1829), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2893PolyExtStep::AndEqz(1000, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2894PolyExtStep::AndEqz(1001, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2895PolyExtStep::AndEqz(1002, 866), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2896PolyExtStep::AndEqz(1003, 869), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2897PolyExtStep::AndEqz(1004, 1852), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2898PolyExtStep::AndEqz(1005, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2899PolyExtStep::AndEqz(1006, 872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2900PolyExtStep::AndEqz(1007, 875), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2901PolyExtStep::AndEqz(1008, 1862), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2902PolyExtStep::AndCond(956, 377, 1009), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2903PolyExtStep::Sub(1697, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :62:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2904PolyExtStep::AndEqz(903, 1699), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :62:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2905PolyExtStep::AndEqz(1011, 1865), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :62:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2906PolyExtStep::AndEqz(1012, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2907PolyExtStep::AndEqz(1013, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2908PolyExtStep::AndEqz(1014, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2909PolyExtStep::AndEqz(1015, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2910PolyExtStep::AndEqz(1016, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2911PolyExtStep::AndEqz(1017, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2912PolyExtStep::AndEqz(1018, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2913PolyExtStep::Add(1762, 1118), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2914PolyExtStep::Sub(748, 1866), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2915PolyExtStep::AndEqz(1019, 1867), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2916PolyExtStep::Mul(788, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2917PolyExtStep::Add(1766, 1868), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2918PolyExtStep::Sub(1369, 1869), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2919PolyExtStep::AndEqz(1020, 1870), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2920PolyExtStep::AndEqz(1021, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2921PolyExtStep::AndEqz(1022, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2922PolyExtStep::AndEqz(1023, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2923PolyExtStep::AndEqz(1024, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2924PolyExtStep::AndEqz(1025, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2925PolyExtStep::AndEqz(1026, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2926PolyExtStep::Sub(770, 1777), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2927PolyExtStep::AndEqz(1027, 1871), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2928PolyExtStep::Add(1780, 1124), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2929PolyExtStep::Sub(771, 1872), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2930PolyExtStep::AndEqz(1028, 1873), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2931PolyExtStep::Mul(791, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2932PolyExtStep::Add(1784, 1874), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2933PolyExtStep::Sub(1774, 1875), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2934PolyExtStep::AndEqz(1029, 1876), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2935PolyExtStep::AndEqz(1030, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2936PolyExtStep::AndEqz(1031, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2937PolyExtStep::Mul(1105, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2938PolyExtStep::Add(1130, 1877), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2939PolyExtStep::Sub(0, 1878), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2940PolyExtStep::AndEqz(1032, 1879), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2941PolyExtStep::AndEqz(1033, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2942PolyExtStep::AndEqz(1034, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2943PolyExtStep::AndEqz(1035, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2944PolyExtStep::AndEqz(1036, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2945PolyExtStep::Mul(800, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2946PolyExtStep::Add(1880, 797), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2947PolyExtStep::Mul(1881, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2948PolyExtStep::Add(1882, 1802), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2949PolyExtStep::Add(1883, 1111), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2950PolyExtStep::Sub(1797, 1884), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2951PolyExtStep::AndEqz(1037, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2952PolyExtStep::Mul(1881, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2953PolyExtStep::Add(1886, 1400), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2954PolyExtStep::Add(1887, 1808), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2955PolyExtStep::Add(1888, 1810), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2956PolyExtStep::Add(1889, 1812), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2957PolyExtStep::Add(1890, 1821), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2958PolyExtStep::AndEqz(1038, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2959PolyExtStep::AndEqz(1039, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2960PolyExtStep::AndEqz(1040, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2961PolyExtStep::AndEqz(1041, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2962PolyExtStep::Mul(806, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2963PolyExtStep::Add(1892, 803), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2964PolyExtStep::Mul(1893, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2965PolyExtStep::Add(1894, 1826), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2966PolyExtStep::Add(1895, 1116), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2967PolyExtStep::Sub(1891, 1896), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2968PolyExtStep::AndEqz(1042, 1897), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2969PolyExtStep::Mul(1893, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2970PolyExtStep::Add(1898, 1407), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2971PolyExtStep::Add(1899, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2972PolyExtStep::Add(1900, 1833), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2973PolyExtStep::Add(1901, 1835), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2974PolyExtStep::Add(1902, 1837), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2975PolyExtStep::Add(1903, 1842), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2976PolyExtStep::AndEqz(1043, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2977PolyExtStep::AndEqz(1044, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2978PolyExtStep::AndEqz(1045, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2979PolyExtStep::AndEqz(1046, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2980PolyExtStep::Mul(812, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2981PolyExtStep::Add(1905, 809), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2982PolyExtStep::Mul(1906, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2983PolyExtStep::Add(1907, 1849), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2984PolyExtStep::Add(1908, 1122), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2985PolyExtStep::Sub(1904, 1909), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2986PolyExtStep::AndEqz(1047, 1910), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2987PolyExtStep::Mul(1906, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2988PolyExtStep::Add(1911, 535), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2989PolyExtStep::Add(1912, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2990PolyExtStep::Add(1913, 1856), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2991PolyExtStep::AndEqz(1048, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2992PolyExtStep::Sub(1914, 1128), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2993PolyExtStep::Mul(1915, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2994PolyExtStep::AndEqz(1049, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2995PolyExtStep::AndEqz(1050, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2996PolyExtStep::Mul(818, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2997PolyExtStep::Add(1917, 815), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2998PolyExtStep::Sub(1916, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2999PolyExtStep::AndEqz(1051, 1919), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3000PolyExtStep::AndEqz(1052, 1340), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3001PolyExtStep::AndCond(1010, 380, 1053), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3002PolyExtStep::AndEqz(904, 1865), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :68:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3003PolyExtStep::AndEqz(1055, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3004PolyExtStep::AndEqz(1056, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3005PolyExtStep::AndEqz(1057, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3006PolyExtStep::AndEqz(1058, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3007PolyExtStep::AndEqz(1059, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3008PolyExtStep::AndEqz(1060, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3009PolyExtStep::AndEqz(1061, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3010PolyExtStep::AndEqz(1062, 1867), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3011PolyExtStep::AndEqz(1063, 1870), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3012PolyExtStep::AndEqz(1064, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3013PolyExtStep::AndEqz(1065, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3014PolyExtStep::AndEqz(1066, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3015PolyExtStep::AndEqz(1067, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3016PolyExtStep::AndEqz(1068, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3017PolyExtStep::AndEqz(1069, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3018PolyExtStep::AndEqz(1070, 1871), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3019PolyExtStep::AndEqz(1071, 1873), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3020PolyExtStep::AndEqz(1072, 1876), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3021PolyExtStep::AndEqz(1073, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3022PolyExtStep::AndEqz(1074, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3023PolyExtStep::AndEqz(1075, 1879), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3024PolyExtStep::AndEqz(1076, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3025PolyExtStep::AndEqz(1077, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3026PolyExtStep::AndEqz(1078, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3027PolyExtStep::AndEqz(1079, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3028PolyExtStep::AndEqz(1080, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3029PolyExtStep::AndEqz(1081, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3030PolyExtStep::AndEqz(1082, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3031PolyExtStep::AndEqz(1083, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3032PolyExtStep::AndEqz(1084, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3033PolyExtStep::AndEqz(1085, 1897), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3034PolyExtStep::Mul(1759, 791), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3035PolyExtStep::Sub(1900, 1920), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3036PolyExtStep::Mul(1777, 788), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3037PolyExtStep::Sub(1921, 1922), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3038PolyExtStep::Add(1923, 1833), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3039PolyExtStep::Add(1924, 1835), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3040PolyExtStep::Add(1925, 1837), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3041PolyExtStep::Add(1926, 1842), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3042PolyExtStep::AndEqz(1086, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3043PolyExtStep::AndEqz(1087, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3044PolyExtStep::AndEqz(1088, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3045PolyExtStep::AndEqz(1089, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3046PolyExtStep::Sub(1927, 1909), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3047PolyExtStep::AndEqz(1090, 1928), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3048PolyExtStep::Mul(1369, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3049PolyExtStep::Add(1360, 1929), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3050PolyExtStep::Mul(1930, 791), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3051PolyExtStep::Sub(1913, 1931), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3052PolyExtStep::Mul(1774, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3053PolyExtStep::Add(1396, 1933), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3054PolyExtStep::Mul(1934, 788), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3055PolyExtStep::Sub(1932, 1935), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3056PolyExtStep::Add(1936, 1856), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3057PolyExtStep::AndEqz(1091, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3058PolyExtStep::Sub(1937, 1128), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3059PolyExtStep::Mul(1938, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3060PolyExtStep::AndEqz(1092, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3061PolyExtStep::AndEqz(1093, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3062PolyExtStep::Sub(1939, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3063PolyExtStep::AndEqz(1094, 1940), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3064PolyExtStep::AndEqz(1095, 1340), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3065PolyExtStep::AndCond(1054, 383, 1096), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3066PolyExtStep::Sub(1699, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :74:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3067PolyExtStep::AndEqz(903, 1941), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :74:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3068PolyExtStep::AndEqz(1098, 1865), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :74:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3069PolyExtStep::AndEqz(1099, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3070PolyExtStep::AndEqz(1100, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3071PolyExtStep::AndEqz(1101, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3072PolyExtStep::AndEqz(1102, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3073PolyExtStep::AndEqz(1103, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3074PolyExtStep::AndEqz(1104, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3075PolyExtStep::AndEqz(1105, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3076PolyExtStep::AndEqz(1106, 1867), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3077PolyExtStep::AndEqz(1107, 1870), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3078PolyExtStep::AndEqz(1108, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3079PolyExtStep::AndEqz(1109, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3080PolyExtStep::AndEqz(1110, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3081PolyExtStep::AndEqz(1111, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3082PolyExtStep::AndEqz(1112, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3083PolyExtStep::AndEqz(1113, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3084PolyExtStep::AndEqz(1114, 1871), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3085PolyExtStep::AndEqz(1115, 1873), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3086PolyExtStep::AndEqz(1116, 1876), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3087PolyExtStep::AndEqz(1117, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3088PolyExtStep::AndEqz(1118, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3089PolyExtStep::AndEqz(1119, 1879), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3090PolyExtStep::AndEqz(1120, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3091PolyExtStep::AndEqz(1121, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3092PolyExtStep::AndEqz(1122, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3093PolyExtStep::AndEqz(1123, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3094PolyExtStep::AndEqz(1124, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3095PolyExtStep::AndEqz(1125, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3096PolyExtStep::AndEqz(1126, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3097PolyExtStep::AndEqz(1127, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3098PolyExtStep::AndEqz(1128, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3099PolyExtStep::AndEqz(1129, 1897), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3100PolyExtStep::Sub(1900, 1922), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3101PolyExtStep::Add(1942, 1833), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3102PolyExtStep::Add(1943, 1835), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3103PolyExtStep::Add(1944, 1837), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3104PolyExtStep::Add(1945, 1842), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3105PolyExtStep::AndEqz(1130, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3106PolyExtStep::AndEqz(1131, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3107PolyExtStep::AndEqz(1132, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3108PolyExtStep::AndEqz(1133, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3109PolyExtStep::Sub(1946, 1909), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3110PolyExtStep::AndEqz(1134, 1947), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3111PolyExtStep::Sub(1913, 1935), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3112PolyExtStep::Add(1948, 1856), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3113PolyExtStep::AndEqz(1135, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3114PolyExtStep::Sub(1949, 1128), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3115PolyExtStep::Mul(1950, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3116PolyExtStep::AndEqz(1136, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3117PolyExtStep::AndEqz(1137, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3118PolyExtStep::Sub(1951, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3119PolyExtStep::AndEqz(1138, 1952), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3120PolyExtStep::AndEqz(1139, 1340), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3121PolyExtStep::AndCond(1097, 386, 1140), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3122PolyExtStep::Sub(1699, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :80:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3123PolyExtStep::AndEqz(903, 1953), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :80:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3124PolyExtStep::AndEqz(1142, 1865), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :80:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3125PolyExtStep::AndEqz(1143, 1754), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3126PolyExtStep::AndEqz(1144, 1755), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3127PolyExtStep::AndEqz(1145, 1361), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3128PolyExtStep::AndEqz(1146, 1756), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3129PolyExtStep::AndEqz(1147, 1757), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3130PolyExtStep::AndEqz(1148, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3131PolyExtStep::AndEqz(1149, 1760), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3132PolyExtStep::AndEqz(1150, 1867), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3133PolyExtStep::AndEqz(1151, 1870), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3134PolyExtStep::AndEqz(1152, 1770), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3135PolyExtStep::AndEqz(1153, 1771), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3136PolyExtStep::AndEqz(1154, 1772), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3137PolyExtStep::AndEqz(1155, 1775), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3138PolyExtStep::AndEqz(1156, 1402), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3139PolyExtStep::AndEqz(1157, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3140PolyExtStep::AndEqz(1158, 1871), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3141PolyExtStep::AndEqz(1159, 1873), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3142PolyExtStep::AndEqz(1160, 1876), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3143PolyExtStep::AndEqz(1161, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3144PolyExtStep::AndEqz(1162, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3145PolyExtStep::AndEqz(1163, 1879), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3146PolyExtStep::AndEqz(1164, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3147PolyExtStep::AndEqz(1165, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3148PolyExtStep::AndEqz(1166, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3149PolyExtStep::AndEqz(1167, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3150PolyExtStep::AndEqz(1168, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3151PolyExtStep::AndEqz(1169, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3152PolyExtStep::AndEqz(1170, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3153PolyExtStep::AndEqz(1171, 805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3154PolyExtStep::AndEqz(1172, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3155PolyExtStep::AndEqz(1173, 1897), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3156PolyExtStep::AndEqz(1174, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3157PolyExtStep::AndEqz(1175, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3158PolyExtStep::AndEqz(1176, 811), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3159PolyExtStep::AndEqz(1177, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3160PolyExtStep::AndEqz(1178, 1910), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3161PolyExtStep::AndEqz(1179, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3162PolyExtStep::AndEqz(1180, 817), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3163PolyExtStep::AndEqz(1181, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3164PolyExtStep::AndEqz(1182, 1919), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3165PolyExtStep::AndEqz(1183, 1340), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3166PolyExtStep::AndCond(1141, 389, 1184), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3167PolyExtStep::AndEqz(0, 17), // loc(callsite( IllegalMulOp ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :17:6) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3168PolyExtStep::AndEqz(1186, 775), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3169PolyExtStep::AndEqz(1187, 776), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3170PolyExtStep::AndEqz(1188, 777), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3171PolyExtStep::AndEqz(1189, 778), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3172PolyExtStep::AndEqz(1190, 779), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3173PolyExtStep::AndEqz(1191, 1340), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3174PolyExtStep::AndEqz(1192, 1343), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3175PolyExtStep::AndEqz(1193, 1351), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3176PolyExtStep::AndEqz(1194, 1359), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3177PolyExtStep::AndEqz(1195, 1362), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3178PolyExtStep::AndEqz(1196, 1370), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3179PolyExtStep::AndEqz(1197, 1378), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3180PolyExtStep::AndEqz(1198, 1392), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3181PolyExtStep::AndEqz(1199, 1394), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3182PolyExtStep::AndEqz(1200, 1773), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3183PolyExtStep::AndEqz(1201, 1397), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3184PolyExtStep::AndEqz(1202, 1399), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3185PolyExtStep::AndEqz(1203, 1406), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3186PolyExtStep::AndEqz(1204, 1844), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3187PolyExtStep::AndCond(1185, 392, 1205), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3188PolyExtStep::AndCond(1206, 395, 1205), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3189PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3190PolyExtStep::Mul(1954, 374), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3191PolyExtStep::Mul(1954, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3192PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3193PolyExtStep::Mul(1957, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3194PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3195PolyExtStep::Mul(1959, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3196PolyExtStep::Mul(1959, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3197PolyExtStep::Mul(1959, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3198PolyExtStep::Add(1955, 1956), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3199PolyExtStep::Add(1963, 1958), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3200PolyExtStep::Add(1964, 1960), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3201PolyExtStep::Add(1965, 1961), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3202PolyExtStep::Add(1966, 1962), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3203PolyExtStep::Mul(1959, 374), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3204PolyExtStep::Mul(1959, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3205PolyExtStep::Mul(1954, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3206PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :41:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3207PolyExtStep::Mul(1971, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3208PolyExtStep::Mul(1971, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3209PolyExtStep::Mul(1971, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3210PolyExtStep::Add(1968, 1969), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3211PolyExtStep::Add(1975, 1970), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3212PolyExtStep::Add(1976, 1972), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3213PolyExtStep::Add(1977, 1973), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3214PolyExtStep::Add(1978, 1974), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3215PolyExtStep::AndEqz(1207, 878), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3216PolyExtStep::Mul(1691, 879), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3217PolyExtStep::Sub(1980, 877), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3218PolyExtStep::AndEqz(1208, 1981), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3219PolyExtStep::Mul(876, 1691), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3220PolyExtStep::AndEqz(1209, 1982), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3221PolyExtStep::Mul(876, 879), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3222PolyExtStep::AndEqz(1210, 1983), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3223PolyExtStep::Mul(877, 1691), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3224PolyExtStep::Sub(1, 877), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3225PolyExtStep::Mul(1985, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3226PolyExtStep::Add(503, 1986), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3227PolyExtStep::Add(1987, 1984), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3228PolyExtStep::Sub(1988, 882), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3229PolyExtStep::AndEqz(1211, 1989), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3230PolyExtStep::Sub(888, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3231PolyExtStep::AndEqz(1212, 1990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3232PolyExtStep::Sub(900, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3233PolyExtStep::AndEqz(1213, 1991), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3234PolyExtStep::Sub(903, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3235PolyExtStep::AndEqz(1214, 1992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3236PolyExtStep::AndEqz(1215, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3237PolyExtStep::Sub(885, 882), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3238PolyExtStep::AndEqz(1216, 1993), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3239PolyExtStep::Sub(903, 891), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3240PolyExtStep::Sub(943, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3241PolyExtStep::AndEqz(1217, 1995), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3242PolyExtStep::Sub(946, 1994), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3243PolyExtStep::AndEqz(1218, 1996), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3244PolyExtStep::Sub(906, 1967), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3245PolyExtStep::AndEqz(1219, 1997), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3246PolyExtStep::Sub(940, 1979), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3247PolyExtStep::AndEqz(1220, 1998), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3248PolyExtStep::Sub(949, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3249PolyExtStep::AndEqz(1221, 1999), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3250PolyExtStep::AndEqz(1222, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3251PolyExtStep::Mul(955, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3252PolyExtStep::Add(2000, 952), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3253PolyExtStep::Sub(504, 2001), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3254PolyExtStep::AndEqz(1223, 2002), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3255PolyExtStep::Add(367, 955), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3256PolyExtStep::Sub(958, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3257PolyExtStep::AndEqz(1224, 2004), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3258PolyExtStep::AndEqz(1225, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3259PolyExtStep::Mul(964, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3260PolyExtStep::Add(2005, 961), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3261PolyExtStep::Sub(2003, 2006), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3262PolyExtStep::AndEqz(1226, 2007), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3263PolyExtStep::AndCond(842, 428, 1227), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
3264PolyExtStep::Sub(552, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3265PolyExtStep::AndEqz(0, 2008), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3266PolyExtStep::Sub(560, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3267PolyExtStep::AndEqz(1229, 2009), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :22:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3268PolyExtStep::AndEqz(1230, 494), // loc(callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :8:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3269PolyExtStep::Sub(1, 735), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3270PolyExtStep::Mul(735, 2010), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3271PolyExtStep::Sub(7, 735), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3272PolyExtStep::Mul(2011, 2012), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3273PolyExtStep::Sub(6, 735), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3274PolyExtStep::Mul(2013, 2014), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3275PolyExtStep::AndEqz(1231, 2015), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3276PolyExtStep::AndEqz(1232, 741), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3277PolyExtStep::Sub(737, 499), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3278PolyExtStep::AndEqz(1233, 2016), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3279PolyExtStep::Sub(1, 738), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3280PolyExtStep::Mul(738, 2017), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3281PolyExtStep::AndEqz(1234, 2018), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3282PolyExtStep::Mul(367, 739), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3283PolyExtStep::Sub(2019, 2017), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3284PolyExtStep::AndEqz(1235, 2020), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3285PolyExtStep::Mul(738, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3286PolyExtStep::AndEqz(1236, 2021), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3287PolyExtStep::Mul(738, 739), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3288PolyExtStep::AndEqz(1237, 2022), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3289PolyExtStep::AndEqz(1238, 738), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3290PolyExtStep::AndEqz(1239, 749), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3291PolyExtStep::Mul(748, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3292PolyExtStep::Add(2023, 735), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3293PolyExtStep::Sub(2024, 365), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3294PolyExtStep::AndEqz(1240, 2025), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3295PolyExtStep::Add(500, 748), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3296PolyExtStep::AndEqz(1241, 735), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3297PolyExtStep::Sub(755, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3298PolyExtStep::AndEqz(1242, 2027), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3299PolyExtStep::Sub(758, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3300PolyExtStep::AndEqz(1243, 2028), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3301PolyExtStep::Sub(759, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3302PolyExtStep::AndEqz(1244, 2029), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3303PolyExtStep::AndEqz(1245, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3304PolyExtStep::Sub(729, 2026), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3305PolyExtStep::AndEqz(1246, 2030), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3306PolyExtStep::Sub(756, 760), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3307PolyExtStep::AndEqz(1247, 2031), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3308PolyExtStep::AndEqz(1248, 767), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3309PolyExtStep::Sub(759, 754), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3310PolyExtStep::Sub(762, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3311PolyExtStep::AndEqz(1249, 2033), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3312PolyExtStep::Sub(770, 2032), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3313PolyExtStep::AndEqz(1250, 2034), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3314PolyExtStep::Sub(1, 561), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3315PolyExtStep::Mul(561, 2035), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3316PolyExtStep::AndEqz(1251, 2036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3317PolyExtStep::Sub(1, 568), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3318PolyExtStep::Mul(568, 2037), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3319PolyExtStep::Sub(7, 568), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3320PolyExtStep::Mul(2038, 2039), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3321PolyExtStep::Sub(6, 568), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3322PolyExtStep::Mul(2040, 2041), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3323PolyExtStep::AndEqz(1252, 2042), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3324PolyExtStep::Sub(1, 567), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3325PolyExtStep::Mul(567, 2043), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3326PolyExtStep::Sub(7, 567), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3327PolyExtStep::Mul(2044, 2045), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3328PolyExtStep::Sub(6, 567), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3329PolyExtStep::Mul(2046, 2047), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3330PolyExtStep::AndEqz(1253, 2048), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3331PolyExtStep::Sub(1, 569), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3332PolyExtStep::Mul(569, 2049), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3333PolyExtStep::Sub(7, 569), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3334PolyExtStep::Mul(2050, 2051), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3335PolyExtStep::Sub(6, 569), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3336PolyExtStep::Mul(2052, 2053), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3337PolyExtStep::AndEqz(1254, 2054), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3338PolyExtStep::Sub(1, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3339PolyExtStep::Mul(570, 2055), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3340PolyExtStep::Sub(7, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3341PolyExtStep::Mul(2056, 2057), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3342PolyExtStep::Sub(6, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3343PolyExtStep::Mul(2058, 2059), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3344PolyExtStep::AndEqz(1255, 2060), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3345PolyExtStep::Sub(1, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3346PolyExtStep::Mul(571, 2061), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3347PolyExtStep::Sub(7, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3348PolyExtStep::Mul(2062, 2063), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3349PolyExtStep::Sub(6, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3350PolyExtStep::Mul(2064, 2065), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3351PolyExtStep::AndEqz(1256, 2066), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3352PolyExtStep::Sub(1, 572), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3353PolyExtStep::Mul(572, 2067), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3354PolyExtStep::AndEqz(1257, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3355PolyExtStep::Sub(1, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3356PolyExtStep::Mul(573, 2069), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3357PolyExtStep::Sub(7, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3358PolyExtStep::Mul(2070, 2071), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3359PolyExtStep::Sub(6, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3360PolyExtStep::Mul(2072, 2073), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3361PolyExtStep::AndEqz(1258, 2074), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3362PolyExtStep::Sub(1, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3363PolyExtStep::Mul(574, 2075), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3364PolyExtStep::Sub(7, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3365PolyExtStep::Mul(2076, 2077), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3366PolyExtStep::Sub(6, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3367PolyExtStep::Mul(2078, 2079), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3368PolyExtStep::AndEqz(1259, 2080), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3369PolyExtStep::Sub(1, 575), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3370PolyExtStep::Mul(575, 2081), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3371PolyExtStep::AndEqz(1260, 2082), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3372PolyExtStep::Sub(1, 583), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3373PolyExtStep::Mul(583, 2083), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3374PolyExtStep::AndEqz(1261, 2084), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3375PolyExtStep::Sub(1, 584), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3376PolyExtStep::Mul(584, 2085), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3377PolyExtStep::Sub(7, 584), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3378PolyExtStep::Mul(2086, 2087), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3379PolyExtStep::Sub(6, 584), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3380PolyExtStep::Mul(2088, 2089), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3381PolyExtStep::AndEqz(1262, 2090), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3382PolyExtStep::Sub(1, 732), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3383PolyExtStep::Mul(732, 2091), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3384PolyExtStep::Sub(7, 732), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3385PolyExtStep::Mul(2092, 2093), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3386PolyExtStep::Sub(6, 732), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3387PolyExtStep::Mul(2094, 2095), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3388PolyExtStep::AndEqz(1263, 2096), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3389PolyExtStep::Sub(1, 731), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3390PolyExtStep::Mul(731, 2097), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3391PolyExtStep::Sub(7, 731), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3392PolyExtStep::Mul(2098, 2099), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3393PolyExtStep::Sub(6, 731), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3394PolyExtStep::Mul(2100, 2101), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3395PolyExtStep::AndEqz(1264, 2102), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3396PolyExtStep::Sub(1, 733), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3397PolyExtStep::Mul(733, 2103), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3398PolyExtStep::AndEqz(1265, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3399PolyExtStep::Mul(561, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3400PolyExtStep::Mul(568, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3401PolyExtStep::Add(2105, 2106), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3402PolyExtStep::Mul(567, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3403PolyExtStep::Add(2107, 2108), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3404PolyExtStep::Mul(569, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3405PolyExtStep::Add(2109, 2110), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3406PolyExtStep::Mul(570, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3407PolyExtStep::Add(2111, 2112), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3408PolyExtStep::Mul(571, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3409PolyExtStep::Add(2113, 2114), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3410PolyExtStep::Mul(572, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3411PolyExtStep::Add(2115, 2116), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3412PolyExtStep::Mul(573, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3413PolyExtStep::Add(2117, 2118), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3414PolyExtStep::Add(2119, 574), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3415PolyExtStep::Sub(761, 2120), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3416PolyExtStep::AndEqz(1266, 2121), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3417PolyExtStep::Mul(575, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3418PolyExtStep::Mul(583, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3419PolyExtStep::Add(2122, 2123), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3420PolyExtStep::Mul(584, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3421PolyExtStep::Add(2124, 2125), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3422PolyExtStep::Mul(732, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3423PolyExtStep::Add(2126, 2127), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3424PolyExtStep::Mul(731, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3425PolyExtStep::Add(2128, 2129), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3426PolyExtStep::Mul(733, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3427PolyExtStep::Add(2130, 2131), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3428PolyExtStep::Add(2132, 734), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3429PolyExtStep::Sub(760, 2133), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3430PolyExtStep::AndEqz(1267, 2134), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3431PolyExtStep::Mul(573, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3432PolyExtStep::Mul(574, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3433PolyExtStep::Add(2135, 2136), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3434PolyExtStep::Add(2137, 575), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3435PolyExtStep::Mul(570, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3436PolyExtStep::Mul(571, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3437PolyExtStep::Add(2139, 2140), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3438PolyExtStep::Add(2141, 572), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3439PolyExtStep::Mul(732, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3440PolyExtStep::Mul(731, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3441PolyExtStep::Add(2143, 2144), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3442PolyExtStep::Add(2145, 733), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3443PolyExtStep::Mul(568, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3444PolyExtStep::Add(2147, 1615), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3445PolyExtStep::Add(2148, 569), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3446PolyExtStep::Mul(561, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3447PolyExtStep::Add(2150, 2149), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3448PolyExtStep::Mul(583, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3449PolyExtStep::Add(2152, 584), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3450PolyExtStep::Add(503, 2138), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3451PolyExtStep::Sub(2154, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3452PolyExtStep::AndEqz(1268, 2155), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3453PolyExtStep::Sub(752, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3454PolyExtStep::AndEqz(1269, 2156), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3455PolyExtStep::Sub(791, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3456PolyExtStep::AndEqz(1270, 2157), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3457PolyExtStep::Sub(794, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3458PolyExtStep::AndEqz(1271, 2158), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3459PolyExtStep::AndEqz(1272, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3460PolyExtStep::Sub(771, 809), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3461PolyExtStep::AndEqz(1273, 2159), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3462PolyExtStep::Sub(785, 797), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3463PolyExtStep::AndEqz(1274, 2160), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3464PolyExtStep::Sub(788, 800), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3465PolyExtStep::AndEqz(1275, 2161), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3466PolyExtStep::Sub(794, 782), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3467PolyExtStep::Sub(803, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3468PolyExtStep::AndEqz(1276, 2163), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3469PolyExtStep::Sub(806, 2162), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3470PolyExtStep::AndEqz(1277, 2164), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3471PolyExtStep::Add(503, 2142), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3472PolyExtStep::Sub(2165, 876), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3473PolyExtStep::AndEqz(1278, 2166), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3474PolyExtStep::Sub(815, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3475PolyExtStep::AndEqz(1279, 2167), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3476PolyExtStep::Sub(827, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3477PolyExtStep::AndEqz(1280, 2168), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3478PolyExtStep::Sub(861, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3479PolyExtStep::AndEqz(1281, 2169), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3480PolyExtStep::AndEqz(1282, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3481PolyExtStep::Sub(812, 876), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3482PolyExtStep::AndEqz(1283, 2170), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3483PolyExtStep::Sub(821, 864), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3484PolyExtStep::AndEqz(1284, 2171), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3485PolyExtStep::Sub(824, 867), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3486PolyExtStep::AndEqz(1285, 2172), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3487PolyExtStep::Sub(861, 818), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3488PolyExtStep::Sub(870, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3489PolyExtStep::AndEqz(1286, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3490PolyExtStep::Sub(873, 2173), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3491PolyExtStep::AndEqz(1287, 2175), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :12:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3492PolyExtStep::Sub(734, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3493PolyExtStep::Sub(2153, 4), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3494PolyExtStep::AndEqz(0, 2176), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3495PolyExtStep::AndEqz(1289, 2177), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3496PolyExtStep::AndEqz(1290, 2151), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3497PolyExtStep::AndEqz(1291, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3498PolyExtStep::AndEqz(1292, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3499PolyExtStep::AndEqz(1293, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3500PolyExtStep::AndEqz(1294, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3501PolyExtStep::AndEqz(1295, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3502PolyExtStep::Mul(882, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3503PolyExtStep::Mul(885, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3504PolyExtStep::Mul(888, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3505PolyExtStep::Mul(891, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3506PolyExtStep::Add(879, 2178), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3507PolyExtStep::Add(2182, 2179), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3508PolyExtStep::Add(2183, 2180), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3509PolyExtStep::Add(2184, 2181), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3510PolyExtStep::AndEqz(1296, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3511PolyExtStep::Add(1732, 2185), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3512PolyExtStep::Sub(2186, 864), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3513PolyExtStep::AndEqz(1297, 2187), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3514PolyExtStep::Mul(879, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3515PolyExtStep::Add(2188, 880), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3516PolyExtStep::Mul(882, 2189), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3517PolyExtStep::Mul(2190, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3518PolyExtStep::Mul(883, 2189), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3519PolyExtStep::Add(2191, 2192), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3520PolyExtStep::Mul(885, 2193), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3521PolyExtStep::Mul(2194, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3522PolyExtStep::Mul(886, 2193), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3523PolyExtStep::Add(2195, 2196), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3524PolyExtStep::Sub(2197, 894), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3525PolyExtStep::AndEqz(1298, 2198), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3526PolyExtStep::Mul(888, 894), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3527PolyExtStep::Mul(2199, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3528PolyExtStep::Mul(889, 894), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3529PolyExtStep::Add(2200, 2201), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3530PolyExtStep::Mul(892, 2202), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3531PolyExtStep::Sub(2203, 897), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3532PolyExtStep::AndEqz(1299, 2204), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3533PolyExtStep::Mul(891, 2202), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3534PolyExtStep::Sub(2205, 900), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3535PolyExtStep::AndEqz(1300, 2206), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3536PolyExtStep::AndEqz(1301, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3537PolyExtStep::AndEqz(1302, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3538PolyExtStep::AndEqz(1303, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3539PolyExtStep::AndEqz(1304, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3540PolyExtStep::AndEqz(1305, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3541PolyExtStep::Get(353), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3542PolyExtStep::Sub(2207, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3543PolyExtStep::AndEqz(1306, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3544PolyExtStep::Sub(587, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3545PolyExtStep::AndEqz(1307, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3546PolyExtStep::AndEqz(1308, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3547PolyExtStep::Mul(1407, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3548PolyExtStep::Add(1400, 2210), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3549PolyExtStep::Sub(903, 2211), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3550PolyExtStep::AndEqz(1309, 2212), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3551PolyExtStep::Mul(590, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3552PolyExtStep::Add(535, 2213), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3553PolyExtStep::Mul(940, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3554PolyExtStep::Add(2214, 2215), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3555PolyExtStep::Sub(906, 2216), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3556PolyExtStep::AndEqz(1310, 2217), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3557PolyExtStep::Mul(590, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3558PolyExtStep::Mul(940, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3559PolyExtStep::Add(2218, 2219), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3560PolyExtStep::Sub(536, 2220), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3561PolyExtStep::AndEqz(1311, 2221), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3562PolyExtStep::Sub(597, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3563PolyExtStep::AndEqz(1312, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3564PolyExtStep::Sub(611, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3565PolyExtStep::AndEqz(1313, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3566PolyExtStep::Sub(625, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3567PolyExtStep::AndEqz(1314, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3568PolyExtStep::Sub(635, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3569PolyExtStep::AndEqz(1315, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3570PolyExtStep::Sub(645, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3571PolyExtStep::AndEqz(1316, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3572PolyExtStep::AndEqz(1317, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3573PolyExtStep::Mul(618, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3574PolyExtStep::Add(604, 2227), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3575PolyExtStep::Sub(897, 2228), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3576PolyExtStep::AndEqz(1318, 2229), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3577PolyExtStep::Mul(648, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3578PolyExtStep::Add(628, 2230), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3579PolyExtStep::Mul(943, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3580PolyExtStep::Add(2231, 2232), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3581PolyExtStep::Sub(900, 2233), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3582PolyExtStep::AndEqz(1319, 2234), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3583PolyExtStep::Mul(648, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3584PolyExtStep::Mul(943, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3585PolyExtStep::Add(2235, 2236), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3586PolyExtStep::Sub(642, 2237), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3587PolyExtStep::AndEqz(1320, 2238), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3588PolyExtStep::AndEqz(1321, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3589PolyExtStep::AndEqz(1322, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3590PolyExtStep::Mul(946, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3591PolyExtStep::Add(2239, 1125), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3592PolyExtStep::Sub(1116, 2240), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3593PolyExtStep::AndEqz(1323, 2241), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3594PolyExtStep::Mul(1400, 604), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3595PolyExtStep::Add(1111, 2242), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3596PolyExtStep::Mul(1400, 618), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3597PolyExtStep::Mul(1407, 604), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3598PolyExtStep::Add(2244, 2245), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3599PolyExtStep::Mul(2246, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3600PolyExtStep::Add(2243, 2247), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3601PolyExtStep::AndEqz(1324, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3602PolyExtStep::Sub(655, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3603PolyExtStep::AndEqz(1325, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3604PolyExtStep::AndEqz(1326, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3605PolyExtStep::AndEqz(1327, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3606PolyExtStep::Mul(952, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3607PolyExtStep::Add(2250, 949), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3608PolyExtStep::Mul(2251, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3609PolyExtStep::Mul(662, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3610PolyExtStep::Add(2252, 2253), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3611PolyExtStep::Add(2254, 1128), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3612PolyExtStep::Sub(2248, 2255), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3613PolyExtStep::AndEqz(1328, 2256), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3614PolyExtStep::Mul(2251, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3615PolyExtStep::Add(2257, 662), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3616PolyExtStep::Add(1116, 2258), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3617PolyExtStep::Mul(1400, 628), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3618PolyExtStep::Add(2259, 2260), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3619PolyExtStep::Mul(1407, 618), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3620PolyExtStep::Add(2261, 2262), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3621PolyExtStep::Mul(535, 604), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3622PolyExtStep::Add(2263, 2264), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3623PolyExtStep::Mul(1400, 642), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3624PolyExtStep::Mul(1407, 628), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3625PolyExtStep::Add(2266, 2267), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3626PolyExtStep::Mul(535, 618), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3627PolyExtStep::Add(2268, 2269), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3628PolyExtStep::Mul(536, 604), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3629PolyExtStep::Add(2270, 2271), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3630PolyExtStep::Mul(2272, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3631PolyExtStep::Add(2265, 2273), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3632PolyExtStep::AndEqz(1329, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3633PolyExtStep::Sub(669, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3634PolyExtStep::AndEqz(1330, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3635PolyExtStep::AndEqz(1331, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3636PolyExtStep::AndEqz(1332, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3637PolyExtStep::Mul(958, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3638PolyExtStep::Add(2276, 955), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3639PolyExtStep::Mul(2277, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3640PolyExtStep::Mul(672, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3641PolyExtStep::Add(2278, 2279), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3642PolyExtStep::Add(2280, 1341), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3643PolyExtStep::Sub(2274, 2281), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3644PolyExtStep::AndEqz(1333, 2282), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3645PolyExtStep::Mul(2277, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3646PolyExtStep::Add(2283, 672), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3647PolyExtStep::Add(2284, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3648PolyExtStep::Mul(1407, 642), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3649PolyExtStep::Add(2285, 2286), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3650PolyExtStep::Mul(535, 628), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3651PolyExtStep::Add(2287, 2288), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3652PolyExtStep::Mul(536, 618), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3653PolyExtStep::Add(2289, 2290), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3654PolyExtStep::Mul(535, 642), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3655PolyExtStep::Mul(536, 628), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3656PolyExtStep::Add(2292, 2293), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3657PolyExtStep::Mul(2294, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3658PolyExtStep::Add(2291, 2295), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3659PolyExtStep::AndEqz(1334, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3660PolyExtStep::Sub(541, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3661PolyExtStep::AndEqz(1335, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3662PolyExtStep::AndEqz(1336, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3663PolyExtStep::AndEqz(1337, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3664PolyExtStep::Mul(964, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3665PolyExtStep::Add(2298, 961), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3666PolyExtStep::Mul(2299, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3667PolyExtStep::Mul(548, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3668PolyExtStep::Add(2300, 2301), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3669PolyExtStep::Add(2302, 1350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3670PolyExtStep::Sub(2296, 2303), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3671PolyExtStep::AndEqz(1338, 2304), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3672PolyExtStep::Mul(2299, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3673PolyExtStep::Add(2305, 548), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3674PolyExtStep::Add(2306, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3675PolyExtStep::Mul(536, 642), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3676PolyExtStep::Add(2307, 2308), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3677PolyExtStep::AndEqz(1339, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3678PolyExtStep::Sub(2309, 1353), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3679PolyExtStep::Mul(2310, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3680PolyExtStep::AndEqz(1340, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3681PolyExtStep::AndEqz(1341, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3682PolyExtStep::Mul(970, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3683PolyExtStep::Add(2312, 967), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3684PolyExtStep::Sub(2311, 2313), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3685PolyExtStep::AndEqz(1342, 2314), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3686PolyExtStep::Sub(1128, 797), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3687PolyExtStep::AndEqz(1343, 2315), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3688PolyExtStep::Sub(1341, 800), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3689PolyExtStep::AndEqz(1344, 2316), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3690PolyExtStep::AndEqz(1345, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3691PolyExtStep::Mul(973, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:36) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3692PolyExtStep::Sub(1350, 2317), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3693PolyExtStep::AndEqz(1346, 2318), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3694PolyExtStep::Sub(1353, 2317), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3695PolyExtStep::AndEqz(1347, 2319), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3696PolyExtStep::Add(897, 900), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3697PolyExtStep::AndEqz(1348, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3698PolyExtStep::Mul(2320, 979), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3699PolyExtStep::Sub(2321, 977), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3700PolyExtStep::AndEqz(1349, 2322), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3701PolyExtStep::Mul(976, 2320), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3702PolyExtStep::AndEqz(1350, 2323), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3703PolyExtStep::Mul(976, 979), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3704PolyExtStep::AndEqz(1351, 2324), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3705PolyExtStep::AndEqz(1352, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3706PolyExtStep::Mul(982, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:25) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3707PolyExtStep::Sub(800, 2325), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3708PolyExtStep::Mul(2326, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:40) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3709PolyExtStep::AndEqz(1353, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3710PolyExtStep::Sub(1360, 2327), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3711PolyExtStep::AndEqz(1354, 2328), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3712PolyExtStep::AndEqz(1355, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3713PolyExtStep::AndEqz(1356, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3714PolyExtStep::Mul(985, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3715PolyExtStep::Add(2329, 1369), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3716PolyExtStep::Sub(897, 2330), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3717PolyExtStep::AndEqz(1357, 2331), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3718PolyExtStep::Add(900, 985), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3719PolyExtStep::AndEqz(1358, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3720PolyExtStep::AndEqz(1359, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3721PolyExtStep::Mul(1019, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3722PolyExtStep::Add(2333, 1372), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3723PolyExtStep::Sub(2332, 2334), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3724PolyExtStep::AndEqz(1360, 2335), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3725PolyExtStep::AndEqz(1361, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3726PolyExtStep::AndEqz(1362, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3727PolyExtStep::Mul(1022, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3728PolyExtStep::Add(2336, 1379), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3729PolyExtStep::Sub(1111, 2337), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3730PolyExtStep::AndEqz(1363, 2338), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3731PolyExtStep::Add(1116, 1022), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3732PolyExtStep::AndEqz(1364, 1771), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3733PolyExtStep::AndEqz(1365, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3734PolyExtStep::Mul(1025, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3735PolyExtStep::Add(2340, 1395), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3736PolyExtStep::Sub(2339, 2341), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3737PolyExtStep::AndEqz(1366, 2342), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3738PolyExtStep::Sub(1111, 797), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3739PolyExtStep::Sub(1116, 800), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3740PolyExtStep::AndEqz(0, 2343), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3741PolyExtStep::AndEqz(1368, 2344), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3742PolyExtStep::AndEqz(1369, 1394), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3743PolyExtStep::AndEqz(1370, 1773), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3744PolyExtStep::AndCond(1367, 976, 1371), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3745PolyExtStep::Add(1379, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3746PolyExtStep::Sub(2345, 1369), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3747PolyExtStep::Add(1395, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3748PolyExtStep::Sub(2347, 1372), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3749PolyExtStep::AndEqz(0, 1772), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3750PolyExtStep::AndEqz(1373, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3751PolyExtStep::Mul(1028, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3752PolyExtStep::Add(2349, 1396), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3753PolyExtStep::Sub(2346, 2350), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3754PolyExtStep::AndEqz(1374, 2351), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3755PolyExtStep::Add(2348, 1028), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3756PolyExtStep::AndEqz(1375, 1775), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3757PolyExtStep::AndEqz(1376, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3758PolyExtStep::Mul(1031, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3759PolyExtStep::Add(2353, 1774), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3760PolyExtStep::Sub(2352, 2354), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3761PolyExtStep::AndEqz(1377, 2355), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3762PolyExtStep::Sub(1032, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3763PolyExtStep::AndEqz(1378, 2356), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3764PolyExtStep::AndCond(1372, 977, 1379), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :114:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3765PolyExtStep::AndEqz(1380, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3766PolyExtStep::AndCond(1288, 374, 1381), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3767PolyExtStep::Sub(2151, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :118:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3768PolyExtStep::Sub(16, 797), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3769PolyExtStep::Sub(16, 800), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3770PolyExtStep::AndEqz(1290, 2357), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :118:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3771PolyExtStep::AndEqz(1383, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3772PolyExtStep::AndEqz(1384, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3773PolyExtStep::AndEqz(1385, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3774PolyExtStep::AndEqz(1386, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3775PolyExtStep::AndEqz(1387, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3776PolyExtStep::AndEqz(1388, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3777PolyExtStep::AndEqz(1389, 2187), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3778PolyExtStep::AndEqz(1390, 2198), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3779PolyExtStep::AndEqz(1391, 2204), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3780PolyExtStep::AndEqz(1392, 2206), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3781PolyExtStep::AndEqz(1393, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3782PolyExtStep::AndEqz(1394, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :98:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3783PolyExtStep::Mul(903, 29), // loc(callsite( builtin Mul at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :99:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3784PolyExtStep::Add(1789, 2360), // loc(callsite( builtin Add at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :99:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3785PolyExtStep::Sub(800, 2361), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :99:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3786PolyExtStep::AndEqz(1395, 2362), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :99:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3787PolyExtStep::Mul(903, 2358), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3788PolyExtStep::Mul(904, 797), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3789PolyExtStep::Add(2363, 2364), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3790PolyExtStep::Mul(903, 2359), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3791PolyExtStep::Mul(904, 800), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3792PolyExtStep::Add(2366, 2367), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3793PolyExtStep::AndEqz(1396, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3794PolyExtStep::AndEqz(1397, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3795PolyExtStep::AndEqz(1398, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3796PolyExtStep::AndEqz(1399, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3797PolyExtStep::AndEqz(1400, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3798PolyExtStep::AndEqz(1401, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3799PolyExtStep::AndEqz(1402, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3800PolyExtStep::AndEqz(1403, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3801PolyExtStep::Sub(906, 2211), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3802PolyExtStep::AndEqz(1404, 2369), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3803PolyExtStep::Add(2214, 2232), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3804PolyExtStep::Sub(940, 2370), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3805PolyExtStep::AndEqz(1405, 2371), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3806PolyExtStep::Add(2218, 2236), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3807PolyExtStep::Sub(536, 2372), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3808PolyExtStep::AndEqz(1406, 2373), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3809PolyExtStep::AndEqz(1407, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3810PolyExtStep::AndEqz(1408, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3811PolyExtStep::AndEqz(1409, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3812PolyExtStep::AndEqz(1410, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3813PolyExtStep::AndEqz(1411, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3814PolyExtStep::AndEqz(1412, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3815PolyExtStep::AndEqz(1413, 2229), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3816PolyExtStep::Add(2231, 2239), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3817PolyExtStep::Sub(900, 2374), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3818PolyExtStep::AndEqz(1414, 2375), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3819PolyExtStep::Mul(946, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3820PolyExtStep::Add(2235, 2376), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3821PolyExtStep::Sub(642, 2377), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3822PolyExtStep::AndEqz(1415, 2378), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3823PolyExtStep::AndEqz(1416, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3824PolyExtStep::AndEqz(1417, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3825PolyExtStep::Mul(949, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3826PolyExtStep::Add(2379, 1131), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3827PolyExtStep::Sub(1122, 2380), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3828PolyExtStep::AndEqz(1418, 2381), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3829PolyExtStep::Add(1116, 2242), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3830PolyExtStep::Add(2382, 2247), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3831PolyExtStep::AndEqz(1419, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3832PolyExtStep::AndEqz(1420, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3833PolyExtStep::AndEqz(1421, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3834PolyExtStep::AndEqz(1422, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3835PolyExtStep::Mul(955, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3836PolyExtStep::Add(2384, 952), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3837PolyExtStep::Mul(2385, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3838PolyExtStep::Add(2386, 2253), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3839PolyExtStep::Add(2387, 1341), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3840PolyExtStep::Sub(2383, 2388), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3841PolyExtStep::AndEqz(1423, 2389), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3842PolyExtStep::Mul(2385, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3843PolyExtStep::Add(2390, 662), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3844PolyExtStep::Add(1122, 2391), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3845PolyExtStep::Add(2392, 2260), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3846PolyExtStep::Add(2393, 2262), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3847PolyExtStep::Add(2394, 2264), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3848PolyExtStep::Add(2395, 2273), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3849PolyExtStep::AndEqz(1424, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3850PolyExtStep::AndEqz(1425, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3851PolyExtStep::AndEqz(1426, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3852PolyExtStep::AndEqz(1427, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3853PolyExtStep::Mul(961, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3854PolyExtStep::Add(2397, 958), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3855PolyExtStep::Mul(2398, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3856PolyExtStep::Add(2399, 2279), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3857PolyExtStep::Add(2400, 1350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3858PolyExtStep::Sub(2396, 2401), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3859PolyExtStep::AndEqz(1428, 2402), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3860PolyExtStep::Mul(2398, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3861PolyExtStep::Add(2403, 672), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3862PolyExtStep::Add(2404, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3863PolyExtStep::Add(2405, 2286), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3864PolyExtStep::Add(2406, 2288), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3865PolyExtStep::Add(2407, 2290), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3866PolyExtStep::Add(2408, 2295), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3867PolyExtStep::AndEqz(1429, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3868PolyExtStep::AndEqz(1430, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3869PolyExtStep::AndEqz(1431, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3870PolyExtStep::AndEqz(1432, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3871PolyExtStep::Mul(967, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3872PolyExtStep::Add(2410, 964), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3873PolyExtStep::Mul(2411, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3874PolyExtStep::Add(2412, 2301), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3875PolyExtStep::Add(2413, 1353), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3876PolyExtStep::Sub(2409, 2414), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3877PolyExtStep::AndEqz(1433, 2415), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3878PolyExtStep::Mul(2411, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3879PolyExtStep::Add(2416, 548), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3880PolyExtStep::Add(2417, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3881PolyExtStep::Add(2418, 2308), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3882PolyExtStep::AndEqz(1434, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3883PolyExtStep::Sub(2419, 1360), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3884PolyExtStep::Mul(2420, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3885PolyExtStep::AndEqz(1435, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3886PolyExtStep::AndEqz(1436, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3887PolyExtStep::Mul(973, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3888PolyExtStep::Add(2422, 970), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3889PolyExtStep::Sub(2421, 2423), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3890PolyExtStep::AndEqz(1437, 2424), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3891PolyExtStep::Sub(1341, 2365), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3892PolyExtStep::AndEqz(1438, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3893PolyExtStep::Sub(1350, 2368), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3894PolyExtStep::AndEqz(1439, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3895PolyExtStep::AndEqz(1440, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3896PolyExtStep::Mul(976, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:36) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3897PolyExtStep::Sub(1353, 2427), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3898PolyExtStep::AndEqz(1441, 2428), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3899PolyExtStep::Sub(1360, 2427), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3900PolyExtStep::AndEqz(1442, 2429), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3901PolyExtStep::AndEqz(1443, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3902PolyExtStep::Mul(2320, 982), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3903PolyExtStep::Sub(2430, 980), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3904PolyExtStep::AndEqz(1444, 2431), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3905PolyExtStep::AndEqz(1445, 2321), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3906PolyExtStep::Mul(979, 982), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3907PolyExtStep::AndEqz(1446, 2432), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3908PolyExtStep::AndEqz(1447, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3909PolyExtStep::Sub(2368, 1002), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3910PolyExtStep::Mul(2433, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:40) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3911PolyExtStep::AndEqz(1448, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3912PolyExtStep::Sub(1369, 2434), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3913PolyExtStep::AndEqz(1449, 2435), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3914PolyExtStep::AndEqz(1450, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3915PolyExtStep::AndEqz(1451, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3916PolyExtStep::Sub(897, 2334), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3917PolyExtStep::AndEqz(1452, 2436), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3918PolyExtStep::Add(900, 1019), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3919PolyExtStep::AndEqz(1453, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3920PolyExtStep::AndEqz(1454, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3921PolyExtStep::Sub(2437, 2337), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3922PolyExtStep::AndEqz(1455, 2438), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3923PolyExtStep::AndEqz(1456, 1771), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3924PolyExtStep::AndEqz(1457, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3925PolyExtStep::Sub(1116, 2341), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3926PolyExtStep::AndEqz(1458, 2439), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3927PolyExtStep::Add(1122, 1025), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3928PolyExtStep::AndEqz(1459, 1772), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3929PolyExtStep::AndEqz(1460, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3930PolyExtStep::Sub(2440, 2350), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3931PolyExtStep::AndEqz(1461, 2441), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3932PolyExtStep::Sub(1116, 2365), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3933PolyExtStep::Sub(1122, 2368), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3934PolyExtStep::AndEqz(0, 2442), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3935PolyExtStep::AndEqz(1463, 2443), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3936PolyExtStep::AndEqz(1464, 1773), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3937PolyExtStep::AndEqz(1465, 1397), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3938PolyExtStep::AndCond(1462, 979, 1466), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3939PolyExtStep::Add(1395, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3940PolyExtStep::Sub(2444, 1372), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3941PolyExtStep::Add(1396, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3942PolyExtStep::Sub(2446, 1379), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3943PolyExtStep::AndEqz(0, 1775), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3944PolyExtStep::AndEqz(1468, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3945PolyExtStep::Sub(2445, 2354), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3946PolyExtStep::AndEqz(1469, 2448), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3947PolyExtStep::Add(2447, 1031), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3948PolyExtStep::AndEqz(1470, 1402), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3949PolyExtStep::AndEqz(1471, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3950PolyExtStep::Mul(1034, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3951PolyExtStep::Add(2450, 1398), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3952PolyExtStep::Sub(2449, 2451), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3953PolyExtStep::AndEqz(1472, 2452), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3954PolyExtStep::Sub(1035, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3955PolyExtStep::AndEqz(1473, 2453), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3956PolyExtStep::AndCond(1467, 980, 1474), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3957PolyExtStep::AndCond(1382, 377, 1475), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3958PolyExtStep::Sub(734, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3959PolyExtStep::AndEqz(0, 2454), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3960PolyExtStep::AndEqz(1477, 2177), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3961PolyExtStep::AndEqz(1478, 2151), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3962PolyExtStep::AndEqz(1479, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3963PolyExtStep::AndEqz(1480, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3964PolyExtStep::AndEqz(1481, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3965PolyExtStep::AndEqz(1482, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3966PolyExtStep::AndEqz(1483, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3967PolyExtStep::AndEqz(1484, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3968PolyExtStep::Sub(2186, 2142), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3969PolyExtStep::AndEqz(1485, 2455), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3970PolyExtStep::AndEqz(1486, 2198), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3971PolyExtStep::AndEqz(1487, 2204), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3972PolyExtStep::AndEqz(1488, 2206), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :127:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3973PolyExtStep::AndEqz(1489, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3974PolyExtStep::AndEqz(1490, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3975PolyExtStep::AndEqz(1491, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3976PolyExtStep::AndEqz(1492, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3977PolyExtStep::AndEqz(1493, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3978PolyExtStep::AndEqz(1494, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3979PolyExtStep::AndEqz(1495, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3980PolyExtStep::AndEqz(1496, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3981PolyExtStep::AndEqz(1497, 2212), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3982PolyExtStep::AndEqz(1498, 2217), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3983PolyExtStep::AndEqz(1499, 2221), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3984PolyExtStep::AndEqz(1500, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3985PolyExtStep::AndEqz(1501, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3986PolyExtStep::AndEqz(1502, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3987PolyExtStep::AndEqz(1503, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3988PolyExtStep::AndEqz(1504, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3989PolyExtStep::AndEqz(1505, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3990PolyExtStep::AndEqz(1506, 2229), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3991PolyExtStep::AndEqz(1507, 2234), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3992PolyExtStep::AndEqz(1508, 2238), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3993PolyExtStep::AndEqz(1509, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3994PolyExtStep::AndEqz(1510, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3995PolyExtStep::AndEqz(1511, 2241), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3996PolyExtStep::AndEqz(1512, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3997PolyExtStep::AndEqz(1513, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3998PolyExtStep::AndEqz(1514, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3999PolyExtStep::AndEqz(1515, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4000PolyExtStep::AndEqz(1516, 2256), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4001PolyExtStep::AndEqz(1517, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4002PolyExtStep::AndEqz(1518, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4003PolyExtStep::AndEqz(1519, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4004PolyExtStep::AndEqz(1520, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4005PolyExtStep::AndEqz(1521, 2282), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4006PolyExtStep::AndEqz(1522, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4007PolyExtStep::AndEqz(1523, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4008PolyExtStep::AndEqz(1524, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4009PolyExtStep::AndEqz(1525, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4010PolyExtStep::AndEqz(1526, 2304), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4011PolyExtStep::AndEqz(1527, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4012PolyExtStep::AndEqz(1528, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4013PolyExtStep::AndEqz(1529, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4014PolyExtStep::AndEqz(1530, 2314), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4015PolyExtStep::AndEqz(1531, 2315), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4016PolyExtStep::AndEqz(1532, 2316), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4017PolyExtStep::AndEqz(1533, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4018PolyExtStep::AndEqz(1534, 2318), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4019PolyExtStep::AndEqz(1535, 2319), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4020PolyExtStep::AndEqz(1536, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4021PolyExtStep::AndEqz(1537, 2322), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4022PolyExtStep::AndEqz(1538, 2323), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4023PolyExtStep::AndEqz(1539, 2324), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4024PolyExtStep::AndEqz(1540, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4025PolyExtStep::AndEqz(1541, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4026PolyExtStep::AndEqz(1542, 2328), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4027PolyExtStep::AndEqz(1543, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4028PolyExtStep::AndEqz(1544, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4029PolyExtStep::AndEqz(1545, 2331), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4030PolyExtStep::AndEqz(1546, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4031PolyExtStep::AndEqz(1547, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4032PolyExtStep::AndEqz(1548, 2335), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4033PolyExtStep::AndEqz(1549, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4034PolyExtStep::AndEqz(1550, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4035PolyExtStep::AndEqz(1551, 2338), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4036PolyExtStep::AndEqz(1552, 1771), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4037PolyExtStep::AndEqz(1553, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4038PolyExtStep::AndEqz(1554, 2342), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4039PolyExtStep::AndCond(1555, 976, 1371), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4040PolyExtStep::AndCond(1556, 977, 1379), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :128:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4041PolyExtStep::AndEqz(1557, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4042PolyExtStep::AndCond(1476, 380, 1558), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4043PolyExtStep::AndEqz(1478, 2357), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :132:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4044PolyExtStep::AndEqz(1560, 881), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4045PolyExtStep::AndEqz(1561, 884), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4046PolyExtStep::AndEqz(1562, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4047PolyExtStep::AndEqz(1563, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4048PolyExtStep::AndEqz(1564, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4049PolyExtStep::AndEqz(1565, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4050PolyExtStep::AndEqz(1566, 2455), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4051PolyExtStep::AndEqz(1567, 2198), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4052PolyExtStep::AndEqz(1568, 2204), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4053PolyExtStep::AndEqz(1569, 2206), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :133:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4054PolyExtStep::AndEqz(1570, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4055PolyExtStep::AndEqz(1571, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :98:24) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4056PolyExtStep::AndEqz(1572, 2362), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :99:11) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4057PolyExtStep::AndEqz(1573, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4058PolyExtStep::AndEqz(1574, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4059PolyExtStep::AndEqz(1575, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4060PolyExtStep::AndEqz(1576, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4061PolyExtStep::AndEqz(1577, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4062PolyExtStep::AndEqz(1578, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4063PolyExtStep::AndEqz(1579, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4064PolyExtStep::AndEqz(1580, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4065PolyExtStep::AndEqz(1581, 2369), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4066PolyExtStep::AndEqz(1582, 2371), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4067PolyExtStep::AndEqz(1583, 2373), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4068PolyExtStep::AndEqz(1584, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4069PolyExtStep::AndEqz(1585, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4070PolyExtStep::AndEqz(1586, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4071PolyExtStep::AndEqz(1587, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4072PolyExtStep::AndEqz(1588, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4073PolyExtStep::AndEqz(1589, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4074PolyExtStep::AndEqz(1590, 2229), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4075PolyExtStep::AndEqz(1591, 2375), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4076PolyExtStep::AndEqz(1592, 2378), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4077PolyExtStep::AndEqz(1593, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4078PolyExtStep::AndEqz(1594, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4079PolyExtStep::AndEqz(1595, 2381), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4080PolyExtStep::AndEqz(1596, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4081PolyExtStep::AndEqz(1597, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4082PolyExtStep::AndEqz(1598, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4083PolyExtStep::AndEqz(1599, 957), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4084PolyExtStep::AndEqz(1600, 2389), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4085PolyExtStep::AndEqz(1601, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4086PolyExtStep::AndEqz(1602, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4087PolyExtStep::AndEqz(1603, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4088PolyExtStep::AndEqz(1604, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4089PolyExtStep::AndEqz(1605, 2402), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4090PolyExtStep::AndEqz(1606, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4091PolyExtStep::AndEqz(1607, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4092PolyExtStep::AndEqz(1608, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4093PolyExtStep::AndEqz(1609, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4094PolyExtStep::AndEqz(1610, 2415), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4095PolyExtStep::AndEqz(1611, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4096PolyExtStep::AndEqz(1612, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4097PolyExtStep::AndEqz(1613, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4098PolyExtStep::AndEqz(1614, 2424), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4099PolyExtStep::AndEqz(1615, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4100PolyExtStep::AndEqz(1616, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4101PolyExtStep::AndEqz(1617, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4102PolyExtStep::AndEqz(1618, 2428), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4103PolyExtStep::AndEqz(1619, 2429), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4104PolyExtStep::AndEqz(1620, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4105PolyExtStep::AndEqz(1621, 2431), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4106PolyExtStep::AndEqz(1622, 2321), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4107PolyExtStep::AndEqz(1623, 2432), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4108PolyExtStep::AndEqz(1624, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4109PolyExtStep::AndEqz(1625, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4110PolyExtStep::AndEqz(1626, 2435), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4111PolyExtStep::AndEqz(1627, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4112PolyExtStep::AndEqz(1628, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4113PolyExtStep::AndEqz(1629, 2436), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4114PolyExtStep::AndEqz(1630, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4115PolyExtStep::AndEqz(1631, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4116PolyExtStep::AndEqz(1632, 2438), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4117PolyExtStep::AndEqz(1633, 1771), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4118PolyExtStep::AndEqz(1634, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4119PolyExtStep::AndEqz(1635, 2439), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4120PolyExtStep::AndEqz(1636, 1772), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4121PolyExtStep::AndEqz(1637, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4122PolyExtStep::AndEqz(1638, 2441), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4123PolyExtStep::AndCond(1639, 979, 1466), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4124PolyExtStep::AndCond(1640, 980, 1474), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4125PolyExtStep::AndCond(1559, 383, 1641), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4126PolyExtStep::Sub(2153, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4127PolyExtStep::Sub(2151, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4128PolyExtStep::Add(864, 867), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4129PolyExtStep::Sub(33, 864), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4130PolyExtStep::Sub(16, 867), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :78:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4131PolyExtStep::AndEqz(1289, 2456), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4132PolyExtStep::AndEqz(1643, 2457), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4133PolyExtStep::AndEqz(1644, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4134PolyExtStep::AndEqz(1645, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4135PolyExtStep::AndEqz(1646, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4136PolyExtStep::AndEqz(1647, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4137PolyExtStep::AndEqz(1648, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4138PolyExtStep::AndEqz(1649, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4139PolyExtStep::AndEqz(1650, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4140PolyExtStep::AndEqz(1651, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4141PolyExtStep::Sub(879, 2211), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4142PolyExtStep::AndEqz(1652, 2461), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4143PolyExtStep::Mul(885, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4144PolyExtStep::Add(2214, 2462), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4145PolyExtStep::Sub(882, 2463), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4146PolyExtStep::AndEqz(1653, 2464), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4147PolyExtStep::Mul(885, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4148PolyExtStep::Add(2218, 2465), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4149PolyExtStep::Sub(536, 2466), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4150PolyExtStep::AndEqz(1654, 2467), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4151PolyExtStep::AndEqz(1655, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4152PolyExtStep::AndEqz(1656, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4153PolyExtStep::AndEqz(1657, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4154PolyExtStep::AndEqz(1658, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4155PolyExtStep::AndEqz(1659, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4156PolyExtStep::AndEqz(1660, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4157PolyExtStep::Sub(864, 2228), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4158PolyExtStep::AndEqz(1661, 2468), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4159PolyExtStep::Mul(888, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4160PolyExtStep::Add(2231, 2469), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4161PolyExtStep::Sub(867, 2470), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4162PolyExtStep::AndEqz(1662, 2471), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4163PolyExtStep::Mul(888, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4164PolyExtStep::Add(2235, 2472), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4165PolyExtStep::Sub(642, 2473), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4166PolyExtStep::AndEqz(1663, 2474), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4167PolyExtStep::AndEqz(1664, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4168PolyExtStep::AndEqz(1665, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4169PolyExtStep::Mul(891, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4170PolyExtStep::Add(2475, 1119), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4171PolyExtStep::Sub(1111, 2476), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4172PolyExtStep::AndEqz(1666, 2477), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4173PolyExtStep::Add(1105, 2242), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4174PolyExtStep::Add(2478, 2247), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4175PolyExtStep::AndEqz(1667, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4176PolyExtStep::AndEqz(1668, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4177PolyExtStep::AndEqz(1669, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4178PolyExtStep::AndEqz(1670, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4179PolyExtStep::Mul(897, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4180PolyExtStep::Add(2480, 894), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4181PolyExtStep::Mul(2481, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4182PolyExtStep::Add(2482, 2253), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4183PolyExtStep::Add(2483, 1122), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4184PolyExtStep::Sub(2479, 2484), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4185PolyExtStep::AndEqz(1671, 2485), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4186PolyExtStep::Mul(2481, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4187PolyExtStep::Add(2486, 662), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4188PolyExtStep::Add(1111, 2487), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4189PolyExtStep::Add(2488, 2260), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4190PolyExtStep::Add(2489, 2262), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4191PolyExtStep::Add(2490, 2264), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4192PolyExtStep::Add(2491, 2273), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4193PolyExtStep::AndEqz(1672, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4194PolyExtStep::AndEqz(1673, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4195PolyExtStep::AndEqz(1674, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4196PolyExtStep::AndEqz(1675, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4197PolyExtStep::Mul(903, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4198PolyExtStep::Add(2493, 900), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4199PolyExtStep::Mul(2494, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4200PolyExtStep::Add(2495, 2279), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4201PolyExtStep::Add(2496, 1128), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4202PolyExtStep::Sub(2492, 2497), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4203PolyExtStep::AndEqz(1676, 2498), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4204PolyExtStep::Mul(2494, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4205PolyExtStep::Add(2499, 672), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4206PolyExtStep::Mul(891, 16), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4207PolyExtStep::Add(2500, 2501), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :141:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4208PolyExtStep::Add(2502, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4209PolyExtStep::Mul(2211, 888), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4210PolyExtStep::Sub(2503, 2504), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4211PolyExtStep::Mul(2228, 885), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4212PolyExtStep::Sub(2505, 2506), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4213PolyExtStep::Add(2507, 2286), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4214PolyExtStep::Add(2508, 2288), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4215PolyExtStep::Add(2509, 2290), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4216PolyExtStep::Add(2510, 2295), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4217PolyExtStep::AndEqz(1677, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4218PolyExtStep::AndEqz(1678, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4219PolyExtStep::AndEqz(1679, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4220PolyExtStep::AndEqz(1680, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4221PolyExtStep::Mul(940, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4222PolyExtStep::Add(2512, 906), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4223PolyExtStep::Mul(2513, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4224PolyExtStep::Add(2514, 2301), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4225PolyExtStep::Add(2515, 1341), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4226PolyExtStep::Sub(2511, 2516), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4227PolyExtStep::AndEqz(1681, 2517), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4228PolyExtStep::Mul(2513, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4229PolyExtStep::Add(2518, 548), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4230PolyExtStep::Add(2519, 2501), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :150:16) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4231PolyExtStep::Add(2520, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4232PolyExtStep::Mul(536, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4233PolyExtStep::Add(535, 2522), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4234PolyExtStep::Mul(2523, 888), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4235PolyExtStep::Sub(2521, 2524), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4236PolyExtStep::Mul(642, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4237PolyExtStep::Add(628, 2526), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4238PolyExtStep::Mul(2527, 885), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4239PolyExtStep::Sub(2525, 2528), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4240PolyExtStep::Add(2529, 2308), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4241PolyExtStep::AndEqz(1682, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4242PolyExtStep::Sub(2530, 1350), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4243PolyExtStep::Mul(2531, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4244PolyExtStep::AndEqz(1683, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4245PolyExtStep::AndEqz(1684, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4246PolyExtStep::Mul(946, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4247PolyExtStep::Add(2533, 943), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4248PolyExtStep::Sub(2532, 2534), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4249PolyExtStep::AndEqz(1685, 2535), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4250PolyExtStep::Sub(1122, 797), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4251PolyExtStep::AndEqz(1686, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4252PolyExtStep::Sub(1128, 800), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4253PolyExtStep::AndEqz(1687, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4254PolyExtStep::AndEqz(1688, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4255PolyExtStep::Mul(949, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:36) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4256PolyExtStep::Sub(1341, 2538), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4257PolyExtStep::AndEqz(1689, 2539), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4258PolyExtStep::Sub(1350, 2538), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4259PolyExtStep::AndEqz(1690, 2540), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4260PolyExtStep::AndEqz(1691, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4261PolyExtStep::Mul(2458, 955), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4262PolyExtStep::Sub(2541, 953), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4263PolyExtStep::AndEqz(1692, 2542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4264PolyExtStep::Mul(952, 2458), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4265PolyExtStep::AndEqz(1693, 2543), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4266PolyExtStep::Mul(952, 955), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4267PolyExtStep::AndEqz(1694, 2544), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4268PolyExtStep::AndEqz(1695, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4269PolyExtStep::Mul(958, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:25) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4270PolyExtStep::Sub(800, 2545), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4271PolyExtStep::Mul(2546, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:40) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4272PolyExtStep::AndEqz(1696, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4273PolyExtStep::Sub(1353, 2547), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4274PolyExtStep::AndEqz(1697, 2548), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4275PolyExtStep::Mul(888, 2459), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4276PolyExtStep::Mul(889, 864), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4277PolyExtStep::Add(2549, 2550), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4278PolyExtStep::Mul(888, 2460), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :78:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4279PolyExtStep::Mul(889, 867), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :78:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4280PolyExtStep::Add(2552, 2553), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :78:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4281PolyExtStep::AndEqz(1698, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4282PolyExtStep::AndEqz(1699, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4283PolyExtStep::Mul(961, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4284PolyExtStep::Add(2555, 1360), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4285PolyExtStep::Sub(2551, 2556), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4286PolyExtStep::AndEqz(1700, 2557), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4287PolyExtStep::Add(2554, 961), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4288PolyExtStep::AndEqz(1701, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4289PolyExtStep::AndEqz(1702, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4290PolyExtStep::Add(2005, 1369), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4291PolyExtStep::Sub(2558, 2559), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4292PolyExtStep::AndEqz(1703, 2560), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4293PolyExtStep::Sub(33, 1105), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4294PolyExtStep::Mul(958, 2561), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4295PolyExtStep::Mul(959, 1105), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4296PolyExtStep::Add(2562, 2563), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4297PolyExtStep::Sub(16, 1111), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :83:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4298PolyExtStep::Mul(958, 2565), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :83:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4299PolyExtStep::Mul(959, 1111), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :83:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4300PolyExtStep::Add(2566, 2567), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :83:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4301PolyExtStep::AndEqz(1704, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4302PolyExtStep::AndEqz(1705, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4303PolyExtStep::Mul(967, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4304PolyExtStep::Add(2569, 1372), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4305PolyExtStep::Sub(2564, 2570), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4306PolyExtStep::AndEqz(1706, 2571), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4307PolyExtStep::Add(2568, 967), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4308PolyExtStep::AndEqz(1707, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4309PolyExtStep::AndEqz(1708, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4310PolyExtStep::Mul(970, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4311PolyExtStep::Add(2573, 1379), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4312PolyExtStep::Sub(2572, 2574), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4313PolyExtStep::AndEqz(1709, 2575), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4314PolyExtStep::Sub(1105, 797), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4315PolyExtStep::Sub(1111, 800), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4316PolyExtStep::AndEqz(0, 2576), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4317PolyExtStep::AndEqz(1711, 2577), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :88:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4318PolyExtStep::AndEqz(1712, 1392), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4319PolyExtStep::AndEqz(1713, 1394), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4320PolyExtStep::AndCond(1710, 952, 1714), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4321PolyExtStep::Add(1372, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4322PolyExtStep::Sub(2578, 1360), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4323PolyExtStep::Add(1379, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4324PolyExtStep::Sub(2580, 1369), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4325PolyExtStep::AndEqz(0, 1771), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4326PolyExtStep::AndEqz(1716, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4327PolyExtStep::Mul(973, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4328PolyExtStep::Add(2582, 1395), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4329PolyExtStep::Sub(2579, 2583), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4330PolyExtStep::AndEqz(1717, 2584), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4331PolyExtStep::Add(2581, 973), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4332PolyExtStep::AndEqz(1718, 1772), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4333PolyExtStep::AndEqz(1719, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4334PolyExtStep::Mul(976, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4335PolyExtStep::Add(2586, 1396), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4336PolyExtStep::Sub(2585, 2587), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4337PolyExtStep::AndEqz(1720, 2588), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:31) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4338PolyExtStep::Sub(977, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4339PolyExtStep::AndEqz(1721, 2589), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4340PolyExtStep::AndCond(1715, 953, 1722), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4341PolyExtStep::AndEqz(1723, 1773), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4342PolyExtStep::AndEqz(1724, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4343PolyExtStep::AndCond(1642, 386, 1725), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4344PolyExtStep::AndEqz(1290, 2457), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :145:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4345PolyExtStep::AndEqz(1727, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4346PolyExtStep::AndEqz(1728, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4347PolyExtStep::AndEqz(1729, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4348PolyExtStep::AndEqz(1730, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4349PolyExtStep::AndEqz(1731, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4350PolyExtStep::AndEqz(1732, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4351PolyExtStep::AndEqz(1733, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4352PolyExtStep::AndEqz(1734, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4353PolyExtStep::AndEqz(1735, 2461), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4354PolyExtStep::AndEqz(1736, 2464), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4355PolyExtStep::AndEqz(1737, 2467), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4356PolyExtStep::AndEqz(1738, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4357PolyExtStep::AndEqz(1739, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4358PolyExtStep::AndEqz(1740, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4359PolyExtStep::AndEqz(1741, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4360PolyExtStep::AndEqz(1742, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4361PolyExtStep::AndEqz(1743, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4362PolyExtStep::AndEqz(1744, 2468), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4363PolyExtStep::AndEqz(1745, 2471), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4364PolyExtStep::AndEqz(1746, 2474), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4365PolyExtStep::AndEqz(1747, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4366PolyExtStep::AndEqz(1748, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4367PolyExtStep::AndEqz(1749, 2477), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4368PolyExtStep::AndEqz(1750, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4369PolyExtStep::AndEqz(1751, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4370PolyExtStep::AndEqz(1752, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4371PolyExtStep::AndEqz(1753, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4372PolyExtStep::AndEqz(1754, 2485), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4373PolyExtStep::AndEqz(1755, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4374PolyExtStep::AndEqz(1756, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4375PolyExtStep::AndEqz(1757, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4376PolyExtStep::AndEqz(1758, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4377PolyExtStep::AndEqz(1759, 2498), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4378PolyExtStep::Add(2500, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4379PolyExtStep::Add(2590, 2286), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4380PolyExtStep::Add(2591, 2288), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4381PolyExtStep::Add(2592, 2290), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4382PolyExtStep::Add(2593, 2295), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4383PolyExtStep::AndEqz(1760, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4384PolyExtStep::AndEqz(1761, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4385PolyExtStep::AndEqz(1762, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4386PolyExtStep::AndEqz(1763, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4387PolyExtStep::Sub(2594, 2516), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4388PolyExtStep::AndEqz(1764, 2595), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4389PolyExtStep::Add(2519, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4390PolyExtStep::Add(2596, 2308), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4391PolyExtStep::AndEqz(1765, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4392PolyExtStep::Sub(2597, 1350), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4393PolyExtStep::Mul(2598, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4394PolyExtStep::AndEqz(1766, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4395PolyExtStep::AndEqz(1767, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4396PolyExtStep::Sub(2599, 2534), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4397PolyExtStep::AndEqz(1768, 2600), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4398PolyExtStep::AndEqz(1769, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4399PolyExtStep::AndEqz(1770, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4400PolyExtStep::AndEqz(1771, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4401PolyExtStep::AndEqz(1772, 2539), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4402PolyExtStep::AndEqz(1773, 2540), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4403PolyExtStep::AndEqz(1774, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4404PolyExtStep::AndEqz(1775, 2542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4405PolyExtStep::AndEqz(1776, 2543), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4406PolyExtStep::AndEqz(1777, 2544), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4407PolyExtStep::AndEqz(1778, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4408PolyExtStep::AndEqz(1779, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4409PolyExtStep::AndEqz(1780, 2548), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4410PolyExtStep::AndEqz(1781, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4411PolyExtStep::AndEqz(1782, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4412PolyExtStep::Sub(864, 2556), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4413PolyExtStep::AndEqz(1783, 2601), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4414PolyExtStep::Add(867, 961), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4415PolyExtStep::AndEqz(1784, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4416PolyExtStep::AndEqz(1785, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4417PolyExtStep::Sub(2602, 2559), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4418PolyExtStep::AndEqz(1786, 2603), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4419PolyExtStep::AndEqz(1787, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4420PolyExtStep::AndEqz(1788, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4421PolyExtStep::Sub(1105, 2570), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4422PolyExtStep::AndEqz(1789, 2604), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4423PolyExtStep::Add(1111, 967), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4424PolyExtStep::AndEqz(1790, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4425PolyExtStep::AndEqz(1791, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4426PolyExtStep::Sub(2605, 2574), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4427PolyExtStep::AndEqz(1792, 2606), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4428PolyExtStep::AndCond(1793, 952, 1714), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4429PolyExtStep::AndCond(1794, 953, 1722), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :146:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4430PolyExtStep::AndEqz(1795, 1773), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4431PolyExtStep::AndEqz(1796, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4432PolyExtStep::AndCond(1726, 389, 1797), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4433PolyExtStep::Sub(2153, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4434PolyExtStep::AndEqz(1289, 2607), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4435PolyExtStep::AndEqz(1799, 2457), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4436PolyExtStep::AndEqz(1800, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4437PolyExtStep::AndEqz(1801, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4438PolyExtStep::AndEqz(1802, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4439PolyExtStep::AndEqz(1803, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4440PolyExtStep::AndEqz(1804, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4441PolyExtStep::AndEqz(1805, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4442PolyExtStep::AndEqz(1806, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4443PolyExtStep::AndEqz(1807, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4444PolyExtStep::AndEqz(1808, 2461), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4445PolyExtStep::AndEqz(1809, 2464), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4446PolyExtStep::AndEqz(1810, 2467), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4447PolyExtStep::AndEqz(1811, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4448PolyExtStep::AndEqz(1812, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4449PolyExtStep::AndEqz(1813, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4450PolyExtStep::AndEqz(1814, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4451PolyExtStep::AndEqz(1815, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4452PolyExtStep::AndEqz(1816, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4453PolyExtStep::AndEqz(1817, 2468), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4454PolyExtStep::AndEqz(1818, 2471), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4455PolyExtStep::AndEqz(1819, 2474), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4456PolyExtStep::AndEqz(1820, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4457PolyExtStep::AndEqz(1821, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4458PolyExtStep::AndEqz(1822, 2477), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4459PolyExtStep::AndEqz(1823, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4460PolyExtStep::AndEqz(1824, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4461PolyExtStep::AndEqz(1825, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4462PolyExtStep::AndEqz(1826, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4463PolyExtStep::AndEqz(1827, 2485), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4464PolyExtStep::AndEqz(1828, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4465PolyExtStep::AndEqz(1829, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4466PolyExtStep::AndEqz(1830, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4467PolyExtStep::AndEqz(1831, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4468PolyExtStep::AndEqz(1832, 2498), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4469PolyExtStep::AndEqz(1833, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4470PolyExtStep::AndEqz(1834, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4471PolyExtStep::AndEqz(1835, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4472PolyExtStep::AndEqz(1836, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4473PolyExtStep::AndEqz(1837, 2517), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4474PolyExtStep::AndEqz(1838, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4475PolyExtStep::AndEqz(1839, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4476PolyExtStep::AndEqz(1840, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4477PolyExtStep::AndEqz(1841, 2535), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4478PolyExtStep::AndEqz(1842, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4479PolyExtStep::AndEqz(1843, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4480PolyExtStep::AndEqz(1844, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4481PolyExtStep::AndEqz(1845, 2539), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4482PolyExtStep::AndEqz(1846, 2540), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4483PolyExtStep::AndEqz(1847, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4484PolyExtStep::AndEqz(1848, 2542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4485PolyExtStep::AndEqz(1849, 2543), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4486PolyExtStep::AndEqz(1850, 2544), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4487PolyExtStep::AndEqz(1851, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4488PolyExtStep::AndEqz(1852, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4489PolyExtStep::AndEqz(1853, 2548), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4490PolyExtStep::AndEqz(1854, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4491PolyExtStep::AndEqz(1855, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4492PolyExtStep::AndEqz(1856, 2557), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4493PolyExtStep::AndEqz(1857, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4494PolyExtStep::AndEqz(1858, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4495PolyExtStep::AndEqz(1859, 2560), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4496PolyExtStep::AndEqz(1860, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4497PolyExtStep::AndEqz(1861, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4498PolyExtStep::AndEqz(1862, 2571), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4499PolyExtStep::AndEqz(1863, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4500PolyExtStep::AndEqz(1864, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4501PolyExtStep::AndEqz(1865, 2575), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4502PolyExtStep::AndCond(1866, 952, 1714), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4503PolyExtStep::AndCond(1867, 953, 1722), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4504PolyExtStep::AndEqz(1868, 1773), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4505PolyExtStep::AndEqz(1869, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4506PolyExtStep::AndCond(1798, 392, 1870), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4507PolyExtStep::Sub(2153, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4508PolyExtStep::AndEqz(1289, 2608), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4509PolyExtStep::AndEqz(1872, 2457), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4510PolyExtStep::AndEqz(1873, 1106), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4511PolyExtStep::AndEqz(1874, 1112), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4512PolyExtStep::AndEqz(1875, 1798), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4513PolyExtStep::AndEqz(1876, 1408), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4514PolyExtStep::AndEqz(1877, 1845), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4515PolyExtStep::AndEqz(1878, 2208), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4516PolyExtStep::AndEqz(1879, 2209), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4517PolyExtStep::AndEqz(1880, 887), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4518PolyExtStep::AndEqz(1881, 2461), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4519PolyExtStep::AndEqz(1882, 2464), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4520PolyExtStep::AndEqz(1883, 2467), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4521PolyExtStep::AndEqz(1884, 2222), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4522PolyExtStep::AndEqz(1885, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4523PolyExtStep::AndEqz(1886, 2224), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4524PolyExtStep::AndEqz(1887, 2225), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4525PolyExtStep::AndEqz(1888, 2226), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4526PolyExtStep::AndEqz(1889, 890), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4527PolyExtStep::AndEqz(1890, 2468), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4528PolyExtStep::AndEqz(1891, 2471), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4529PolyExtStep::AndEqz(1892, 2474), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4530PolyExtStep::AndEqz(1893, 893), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4531PolyExtStep::AndEqz(1894, 1117), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4532PolyExtStep::AndEqz(1895, 2477), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4533PolyExtStep::AndEqz(1896, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4534PolyExtStep::AndEqz(1897, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4535PolyExtStep::AndEqz(1898, 896), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4536PolyExtStep::AndEqz(1899, 899), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4537PolyExtStep::AndEqz(1900, 2485), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4538PolyExtStep::AndEqz(1901, 1129), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4539PolyExtStep::AndEqz(1902, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4540PolyExtStep::AndEqz(1903, 902), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4541PolyExtStep::AndEqz(1904, 905), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4542PolyExtStep::AndEqz(1905, 2498), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4543PolyExtStep::AndEqz(1906, 1342), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4544PolyExtStep::AndEqz(1907, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4545PolyExtStep::AndEqz(1908, 908), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4546PolyExtStep::AndEqz(1909, 942), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4547PolyExtStep::AndEqz(1910, 2595), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4548PolyExtStep::AndEqz(1911, 1754), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4549PolyExtStep::AndEqz(1912, 945), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4550PolyExtStep::AndEqz(1913, 948), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4551PolyExtStep::AndEqz(1914, 2600), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :61:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4552PolyExtStep::AndEqz(1915, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4553PolyExtStep::AndEqz(1916, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :63:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4554PolyExtStep::AndEqz(1917, 951), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :65:30) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4555PolyExtStep::AndEqz(1918, 2539), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4556PolyExtStep::AndEqz(1919, 2540), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4557PolyExtStep::AndEqz(1920, 954), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4558PolyExtStep::AndEqz(1921, 2542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4559PolyExtStep::AndEqz(1922, 2543), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4560PolyExtStep::AndEqz(1923, 2544), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :68:20) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4561PolyExtStep::AndEqz(1924, 960), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :70:26) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4562PolyExtStep::AndEqz(1925, 1755), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4563PolyExtStep::AndEqz(1926, 2548), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :72:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4564PolyExtStep::AndEqz(1927, 1361), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4565PolyExtStep::AndEqz(1928, 963), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4566PolyExtStep::AndEqz(1929, 2601), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4567PolyExtStep::AndEqz(1930, 1756), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4568PolyExtStep::AndEqz(1931, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4569PolyExtStep::AndEqz(1932, 2603), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4570PolyExtStep::AndEqz(1933, 1757), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4571PolyExtStep::AndEqz(1934, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4572PolyExtStep::AndEqz(1935, 2604), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4573PolyExtStep::AndEqz(1936, 1770), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4574PolyExtStep::AndEqz(1937, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4575PolyExtStep::AndEqz(1938, 2606), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4576PolyExtStep::AndCond(1939, 952, 1714), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4577PolyExtStep::AndCond(1940, 953, 1722), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :87:4) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4578PolyExtStep::AndEqz(1941, 1773), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4579PolyExtStep::AndEqz(1942, 1397), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4580PolyExtStep::AndCond(1871, 395, 1943), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4581PolyExtStep::Mul(1180, 374), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4582PolyExtStep::Sub(16, 1181), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4583PolyExtStep::Mul(1180, 2610), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4584PolyExtStep::Sub(1, 1180), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:29) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4585PolyExtStep::Mul(2612, 1181), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4586PolyExtStep::Add(2611, 2613), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4587PolyExtStep::Mul(2614, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4588PolyExtStep::Mul(1180, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4589PolyExtStep::Mul(2614, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4590PolyExtStep::Mul(1172, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4591PolyExtStep::Mul(1172, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4592PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :55:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :151:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4593PolyExtStep::Mul(2620, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4594PolyExtStep::Mul(2620, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4595PolyExtStep::Add(2609, 2615), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4596PolyExtStep::Add(2623, 2616), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4597PolyExtStep::Add(2624, 2617), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4598PolyExtStep::Add(2625, 2618), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4599PolyExtStep::Add(2626, 2619), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4600PolyExtStep::Add(2627, 2621), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4601PolyExtStep::Add(2628, 2622), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4602PolyExtStep::Mul(1181, 374), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4603PolyExtStep::Sub(16, 1249), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4604PolyExtStep::Mul(1180, 2631), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4605PolyExtStep::Mul(2612, 1249), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4606PolyExtStep::Add(2632, 2633), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :104:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :122:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4607PolyExtStep::Mul(2634, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4608PolyExtStep::Mul(1181, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4609PolyExtStep::Mul(2634, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4610PolyExtStep::Mul(1173, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4611PolyExtStep::Mul(1173, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4612PolyExtStep::Mul(1957, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4613PolyExtStep::Mul(1957, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4614PolyExtStep::Add(2630, 2635), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4615PolyExtStep::Add(2642, 2636), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4616PolyExtStep::Add(2643, 2637), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4617PolyExtStep::Add(2644, 2638), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4618PolyExtStep::Add(2645, 2639), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4619PolyExtStep::Add(2646, 2640), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4620PolyExtStep::Add(2647, 2641), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4621PolyExtStep::AndEqz(1944, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4622PolyExtStep::Mul(2146, 1040), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4623PolyExtStep::Sub(2649, 1038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4624PolyExtStep::AndEqz(1945, 2650), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4625PolyExtStep::Mul(1037, 2146), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4626PolyExtStep::AndEqz(1946, 2651), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4627PolyExtStep::Mul(1037, 1040), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4628PolyExtStep::AndEqz(1947, 2652), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4629PolyExtStep::Mul(1038, 2146), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4630PolyExtStep::Sub(1, 1038), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4631PolyExtStep::Mul(2654, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4632PolyExtStep::Add(503, 2655), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4633PolyExtStep::Add(2656, 2653), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4634PolyExtStep::Sub(2657, 1043), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4635PolyExtStep::AndEqz(1948, 2658), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4636PolyExtStep::Get(770), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4637PolyExtStep::Get(771), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4638PolyExtStep::Sub(1049, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4639PolyExtStep::AndEqz(1949, 2661), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4640PolyExtStep::Sub(1061, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4641PolyExtStep::AndEqz(1950, 2662), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4642PolyExtStep::Sub(1064, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4643PolyExtStep::AndEqz(1951, 2663), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4644PolyExtStep::AndEqz(1952, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4645PolyExtStep::Sub(1046, 1043), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4646PolyExtStep::AndEqz(1953, 2664), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4647PolyExtStep::Sub(1064, 1052), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4648PolyExtStep::Get(772), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4649PolyExtStep::Get(773), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4650PolyExtStep::Sub(2666, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4651PolyExtStep::AndEqz(1954, 2668), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4652PolyExtStep::Sub(2667, 2665), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4653PolyExtStep::AndEqz(1955, 2669), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4654PolyExtStep::Sub(2659, 2629), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4655PolyExtStep::AndEqz(1956, 2670), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4656PolyExtStep::Sub(2660, 2648), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4657PolyExtStep::AndEqz(1957, 2671), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :34:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4658PolyExtStep::Get(774), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4659PolyExtStep::Get(775), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4660PolyExtStep::Sub(2672, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4661PolyExtStep::AndEqz(1958, 2674), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4662PolyExtStep::Get(776), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4663PolyExtStep::Sub(1, 2675), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4664PolyExtStep::Mul(2675, 2676), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4665PolyExtStep::AndEqz(1959, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4666PolyExtStep::Mul(2675, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4667PolyExtStep::Add(2678, 2673), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4668PolyExtStep::Sub(504, 2679), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4669PolyExtStep::AndEqz(1960, 2680), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4670PolyExtStep::Add(367, 2675), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4671PolyExtStep::Get(777), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4672PolyExtStep::Get(778), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4673PolyExtStep::Sub(2682, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4674PolyExtStep::AndEqz(1961, 2684), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4675PolyExtStep::Get(779), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4676PolyExtStep::Sub(1, 2685), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4677PolyExtStep::Mul(2685, 2686), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4678PolyExtStep::AndEqz(1962, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4679PolyExtStep::Mul(2685, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4680PolyExtStep::Add(2688, 2683), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4681PolyExtStep::Sub(2681, 2689), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4682PolyExtStep::AndEqz(1963, 2690), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4683PolyExtStep::AndCond(1228, 431, 1964), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
4684PolyExtStep::Sub(1128, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :49:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4685PolyExtStep::AndEqz(0, 2691), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :49:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4686PolyExtStep::Sub(1341, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :49:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4687PolyExtStep::AndEqz(1966, 2692), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :49:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4688PolyExtStep::AndEqz(1967, 494), // loc(callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :8:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4689PolyExtStep::Sub(1, 1773), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4690PolyExtStep::Mul(1773, 2693), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4691PolyExtStep::Sub(7, 1773), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4692PolyExtStep::Mul(2694, 2695), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4693PolyExtStep::Sub(6, 1773), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4694PolyExtStep::Mul(2696, 2697), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4695PolyExtStep::AndEqz(1968, 2698), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4696PolyExtStep::Sub(1774, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4697PolyExtStep::AndEqz(1969, 2699), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4698PolyExtStep::Sub(1397, 499), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4699PolyExtStep::AndEqz(1970, 2700), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4700PolyExtStep::Sub(1, 1398), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4701PolyExtStep::Mul(1398, 2701), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4702PolyExtStep::AndEqz(1971, 2702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4703PolyExtStep::Mul(367, 1399), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4704PolyExtStep::Sub(2703, 2701), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4705PolyExtStep::AndEqz(1972, 2704), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4706PolyExtStep::Mul(1398, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4707PolyExtStep::AndEqz(1973, 2705), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4708PolyExtStep::Mul(1398, 1399), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4709PolyExtStep::AndEqz(1974, 2706), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4710PolyExtStep::AndEqz(1975, 1398), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4711PolyExtStep::Sub(1400, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4712PolyExtStep::AndEqz(1976, 2707), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4713PolyExtStep::Mul(1406, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4714PolyExtStep::Add(2708, 1773), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4715PolyExtStep::Sub(2709, 365), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4716PolyExtStep::AndEqz(1977, 2710), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4717PolyExtStep::Add(500, 1406), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4718PolyExtStep::AndEqz(1978, 1773), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4719PolyExtStep::Sub(1844, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4720PolyExtStep::AndEqz(1979, 2712), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4721PolyExtStep::AndEqz(1980, 2209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4722PolyExtStep::Sub(590, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4723PolyExtStep::AndEqz(1981, 2713), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4724PolyExtStep::AndEqz(1982, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4725PolyExtStep::Sub(1407, 2711), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4726PolyExtStep::AndEqz(1983, 2714), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4727PolyExtStep::Sub(2207, 597), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4728PolyExtStep::AndEqz(1984, 2715), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4729PolyExtStep::Sub(536, 604), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4730PolyExtStep::AndEqz(1985, 2716), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4731PolyExtStep::Sub(590, 535), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4732PolyExtStep::AndEqz(1986, 2223), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4733PolyExtStep::Sub(618, 2717), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4734PolyExtStep::AndEqz(1987, 2718), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4735PolyExtStep::AndEqz(1988, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4736PolyExtStep::Sub(1, 1350), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4737PolyExtStep::Mul(1350, 2719), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4738PolyExtStep::Sub(7, 1350), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4739PolyExtStep::Mul(2720, 2721), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4740PolyExtStep::Sub(6, 1350), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4741PolyExtStep::Mul(2722, 2723), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4742PolyExtStep::AndEqz(1989, 2724), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4743PolyExtStep::Sub(1, 1351), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4744PolyExtStep::Mul(1351, 2725), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4745PolyExtStep::Sub(7, 1351), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4746PolyExtStep::Mul(2726, 2727), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4747PolyExtStep::Sub(6, 1351), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4748PolyExtStep::Mul(2728, 2729), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4749PolyExtStep::AndEqz(1990, 2730), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4750PolyExtStep::Sub(7, 1353), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4751PolyExtStep::Mul(1355, 2731), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4752PolyExtStep::Sub(6, 1353), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4753PolyExtStep::Mul(2732, 2733), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4754PolyExtStep::AndEqz(1991, 2734), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4755PolyExtStep::Sub(1, 1359), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4756PolyExtStep::Mul(1359, 2735), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4757PolyExtStep::Sub(7, 1359), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4758PolyExtStep::Mul(2736, 2737), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4759PolyExtStep::Sub(6, 1359), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4760PolyExtStep::Mul(2738, 2739), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4761PolyExtStep::AndEqz(1992, 2740), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4762PolyExtStep::Sub(1, 1360), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4763PolyExtStep::Mul(1360, 2741), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4764PolyExtStep::Sub(7, 1360), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4765PolyExtStep::Mul(2742, 2743), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4766PolyExtStep::Sub(6, 1360), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4767PolyExtStep::Mul(2744, 2745), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4768PolyExtStep::AndEqz(1993, 2746), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4769PolyExtStep::AndEqz(1994, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4770PolyExtStep::Sub(1, 1369), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4771PolyExtStep::Mul(1369, 2747), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4772PolyExtStep::Sub(7, 1369), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4773PolyExtStep::Mul(2748, 2749), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4774PolyExtStep::Sub(6, 1369), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4775PolyExtStep::Mul(2750, 2751), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4776PolyExtStep::AndEqz(1995, 2752), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4777PolyExtStep::Sub(1, 1370), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4778PolyExtStep::Mul(1370, 2753), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4779PolyExtStep::Sub(7, 1370), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4780PolyExtStep::Mul(2754, 2755), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4781PolyExtStep::Sub(6, 1370), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4782PolyExtStep::Mul(2756, 2757), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4783PolyExtStep::AndEqz(1996, 2758), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4784PolyExtStep::AndEqz(1997, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4785PolyExtStep::AndEqz(1998, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4786PolyExtStep::Sub(1, 1379), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4787PolyExtStep::Mul(1379, 2759), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4788PolyExtStep::Sub(7, 1379), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4789PolyExtStep::Mul(2760, 2761), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4790PolyExtStep::Sub(6, 1379), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4791PolyExtStep::Mul(2762, 2763), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4792PolyExtStep::AndEqz(1999, 2764), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4793PolyExtStep::Sub(1, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4794PolyExtStep::Mul(1392, 2765), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4795PolyExtStep::Sub(7, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4796PolyExtStep::Mul(2766, 2767), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4797PolyExtStep::Sub(6, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4798PolyExtStep::Mul(2768, 2769), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4799PolyExtStep::AndEqz(2000, 2770), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4800PolyExtStep::Sub(1, 1395), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4801PolyExtStep::Mul(1395, 2771), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4802PolyExtStep::Sub(7, 1395), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4803PolyExtStep::Mul(2772, 2773), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4804PolyExtStep::Sub(6, 1395), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4805PolyExtStep::Mul(2774, 2775), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4806PolyExtStep::AndEqz(2001, 2776), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4807PolyExtStep::Sub(1, 1394), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4808PolyExtStep::Mul(1394, 2777), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4809PolyExtStep::AndEqz(2002, 2778), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4810PolyExtStep::Mul(1343, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4811PolyExtStep::Mul(1350, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4812PolyExtStep::Add(2779, 2780), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4813PolyExtStep::Mul(1351, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4814PolyExtStep::Add(2781, 2782), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4815PolyExtStep::Mul(1353, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4816PolyExtStep::Add(2783, 2784), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4817PolyExtStep::Mul(1359, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4818PolyExtStep::Add(2785, 2786), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4819PolyExtStep::Mul(1360, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4820PolyExtStep::Add(2787, 2788), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4821PolyExtStep::Mul(1362, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4822PolyExtStep::Add(2789, 2790), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4823PolyExtStep::Mul(1369, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4824PolyExtStep::Add(2791, 2792), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4825PolyExtStep::Add(2793, 1370), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4826PolyExtStep::Sub(604, 2794), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4827PolyExtStep::AndEqz(2003, 2795), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4828PolyExtStep::Mul(1372, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4829PolyExtStep::Mul(1378, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4830PolyExtStep::Add(2796, 2797), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4831PolyExtStep::Mul(1379, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4832PolyExtStep::Add(2798, 2799), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4833PolyExtStep::Mul(1392, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4834PolyExtStep::Add(2800, 2801), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4835PolyExtStep::Add(2802, 1776), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4836PolyExtStep::Mul(1394, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4837PolyExtStep::Add(2803, 2804), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4838PolyExtStep::Add(2805, 1396), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4839PolyExtStep::Sub(597, 2806), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4840PolyExtStep::AndEqz(2004, 2807), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4841PolyExtStep::Mul(1369, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4842PolyExtStep::Mul(1370, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4843PolyExtStep::Add(2808, 2809), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4844PolyExtStep::Add(2810, 1372), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4845PolyExtStep::Mul(1359, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4846PolyExtStep::Mul(1360, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4847PolyExtStep::Add(2812, 2813), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4848PolyExtStep::Add(2814, 1362), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4849PolyExtStep::Mul(1392, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4850PolyExtStep::Mul(1395, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4851PolyExtStep::Add(2816, 2817), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4852PolyExtStep::Add(2818, 1394), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4853PolyExtStep::Mul(1350, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4854PolyExtStep::Mul(1351, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4855PolyExtStep::Add(2820, 2821), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4856PolyExtStep::Add(2822, 1353), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4857PolyExtStep::Mul(1343, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4858PolyExtStep::Add(2824, 2823), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4859PolyExtStep::Mul(1378, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4860PolyExtStep::Add(2826, 1379), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4861PolyExtStep::Mul(1343, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4862PolyExtStep::Mul(2825, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4863PolyExtStep::Add(2828, 2829), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4864PolyExtStep::Add(2830, 2815), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4865PolyExtStep::Mul(1343, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4866PolyExtStep::Add(503, 2811), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4867PolyExtStep::Sub(2833, 548), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4868PolyExtStep::AndEqz(2005, 2834), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4869PolyExtStep::Sub(628, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4870PolyExtStep::AndEqz(2006, 2835), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4871PolyExtStep::Sub(648, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4872PolyExtStep::AndEqz(2007, 2836), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4873PolyExtStep::Sub(655, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4874PolyExtStep::AndEqz(2008, 2837), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4875PolyExtStep::AndEqz(2009, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4876PolyExtStep::Sub(625, 548), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4877PolyExtStep::AndEqz(2010, 2838), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4878PolyExtStep::Sub(642, 662), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4879PolyExtStep::AndEqz(2011, 2839), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4880PolyExtStep::Sub(645, 669), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4881PolyExtStep::AndEqz(2012, 2840), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4882PolyExtStep::Sub(655, 635), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4883PolyExtStep::Sub(672, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4884PolyExtStep::AndEqz(2013, 2842), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4885PolyExtStep::Sub(541, 2841), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4886PolyExtStep::AndEqz(2014, 2843), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4887PolyExtStep::Add(662, 2831), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4888PolyExtStep::Add(669, 2832), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4889PolyExtStep::Sub(549, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4890PolyExtStep::AndEqz(2015, 2846), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4891PolyExtStep::Sub(1, 553), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4892PolyExtStep::Mul(553, 2847), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4893PolyExtStep::AndEqz(2016, 2848), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4894PolyExtStep::Mul(553, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4895PolyExtStep::Add(2849, 552), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4896PolyExtStep::Sub(2844, 2850), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4897PolyExtStep::AndEqz(2017, 2851), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4898PolyExtStep::Add(2845, 553), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4899PolyExtStep::AndEqz(2018, 562), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4900PolyExtStep::AndEqz(2019, 2038), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4901PolyExtStep::Mul(568, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4902PolyExtStep::Add(2853, 561), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4903PolyExtStep::Sub(2852, 2854), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4904PolyExtStep::AndEqz(2020, 2855), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4905PolyExtStep::AndEqz(2021, 2044), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4906PolyExtStep::AndEqz(2022, 2050), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4907PolyExtStep::Mul(569, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4908PolyExtStep::Add(2856, 567), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4909PolyExtStep::Sub(498, 561), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4910PolyExtStep::Sub(570, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4911PolyExtStep::AndEqz(2023, 2859), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4912PolyExtStep::Sub(571, 2858), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4913PolyExtStep::AndEqz(2024, 2860), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4914PolyExtStep::AndEqz(2025, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4915PolyExtStep::Mul(561, 573), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4916PolyExtStep::Sub(2861, 2067), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4917PolyExtStep::AndEqz(2026, 2862), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4918PolyExtStep::Mul(572, 561), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4919PolyExtStep::AndEqz(2027, 2863), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4920PolyExtStep::Mul(572, 573), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4921PolyExtStep::AndEqz(2028, 2864), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4922PolyExtStep::AndEqz(2029, 572), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4923PolyExtStep::AndEqz(2030, 1620), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4924PolyExtStep::Mul(575, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4925PolyExtStep::Add(2865, 2857), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4926PolyExtStep::Sub(2866, 552), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4927PolyExtStep::AndEqz(2031, 2867), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4928PolyExtStep::Mul(561, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4929PolyExtStep::Add(2868, 575), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4930PolyExtStep::Sub(584, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4931PolyExtStep::AndEqz(2032, 2870), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4932PolyExtStep::Sub(734, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4933PolyExtStep::AndEqz(2033, 2871), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4934PolyExtStep::Sub(735, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4935PolyExtStep::AndEqz(2034, 2872), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4936PolyExtStep::AndEqz(2035, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4937PolyExtStep::Sub(583, 2869), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4938PolyExtStep::AndEqz(2036, 2873), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4939PolyExtStep::Sub(731, 736), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4940PolyExtStep::AndEqz(2037, 2874), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4941PolyExtStep::Sub(733, 737), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4942PolyExtStep::AndEqz(2038, 2875), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4943PolyExtStep::Sub(735, 732), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4944PolyExtStep::AndEqz(2039, 1703), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4945PolyExtStep::Sub(739, 2876), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4946PolyExtStep::AndEqz(2040, 2877), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4947PolyExtStep::Sub(1396, 6), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :85:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4948PolyExtStep::Mul(569, 737), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:24) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4949PolyExtStep::Mul(2049, 736), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:69) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4950PolyExtStep::Add(2879, 2880), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:42) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4951PolyExtStep::AndEqz(0, 2878), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :85:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4952PolyExtStep::AndEqz(2042, 2827), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :85:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4953PolyExtStep::AndEqz(2043, 1106), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4954PolyExtStep::AndEqz(2044, 1112), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4955PolyExtStep::Mul(1111, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4956PolyExtStep::Add(2882, 1105), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4957PolyExtStep::Sub(2881, 2883), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4958PolyExtStep::AndEqz(2045, 2884), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4959PolyExtStep::Mul(567, 1111), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4960PolyExtStep::Mul(2043, 1105), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4961PolyExtStep::Add(2885, 2886), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4962PolyExtStep::Sub(1, 747), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4963PolyExtStep::Mul(747, 2888), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4964PolyExtStep::AndEqz(2046, 2889), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4965PolyExtStep::AndEqz(2047, 1117), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4966PolyExtStep::Mul(747, 25), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4967PolyExtStep::Add(2890, 1119), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4968PolyExtStep::Sub(2887, 2891), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4969PolyExtStep::AndEqz(2048, 2892), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4970PolyExtStep::AndEqz(2049, 778), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4971PolyExtStep::AndCond(2041, 374, 2050), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4972PolyExtStep::Sub(2827, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :96:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4973PolyExtStep::AndEqz(2042, 2893), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :96:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4974PolyExtStep::AndEqz(2052, 567), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :97:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4975PolyExtStep::AndEqz(2053, 2889), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :99:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4976PolyExtStep::AndEqz(2054, 1123), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :100:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4977PolyExtStep::Mul(747, 29), // loc(callsite( builtin Mul at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4978PolyExtStep::Add(2894, 1125), // loc(callsite( builtin Add at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4979PolyExtStep::Sub(2881, 2895), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4980PolyExtStep::AndEqz(2055, 2896), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4981PolyExtStep::AndEqz(2056, 775), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4982PolyExtStep::AndEqz(2057, 776), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4983PolyExtStep::AndEqz(2058, 777), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4984PolyExtStep::AndCond(2051, 377, 2059), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4985PolyExtStep::Sub(2827, 7), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :106:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4986PolyExtStep::AndEqz(2042, 2897), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :106:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4987PolyExtStep::AndEqz(2061, 567), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :107:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4988PolyExtStep::AndEqz(2062, 569), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :108:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4989PolyExtStep::AndEqz(2063, 775), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4990PolyExtStep::AndEqz(2064, 776), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4991PolyExtStep::AndEqz(2065, 777), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4992PolyExtStep::AndEqz(2066, 778), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4993PolyExtStep::AndCond(2060, 380, 2067), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4994PolyExtStep::Sub(2827, 5), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :113:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4995PolyExtStep::AndEqz(2042, 2898), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :113:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4996PolyExtStep::AndEqz(2069, 1106), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :115:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4997PolyExtStep::AndEqz(2070, 1112), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :115:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4998PolyExtStep::AndEqz(2071, 2884), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :115:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4999PolyExtStep::AndEqz(2072, 777), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5000PolyExtStep::AndEqz(2073, 778), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5001PolyExtStep::AndCond(2068, 383, 2074), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5002PolyExtStep::Sub(2827, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :121:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5003PolyExtStep::AndEqz(2042, 2899), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :121:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5004PolyExtStep::AndEqz(2076, 567), // loc(callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :122:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5005PolyExtStep::AndEqz(2077, 775), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5006PolyExtStep::AndEqz(2078, 776), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5007PolyExtStep::AndEqz(2079, 777), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5008PolyExtStep::AndEqz(2080, 778), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5009PolyExtStep::AndCond(2075, 386, 2081), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5010PolyExtStep::AndCond(2082, 389, 1190), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5011PolyExtStep::AndCond(2083, 392, 1190), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5012PolyExtStep::AndCond(2084, 395, 1190), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5013PolyExtStep::Mul(567, 1957), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5014PolyExtStep::Mul(2043, 2620), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5015PolyExtStep::Add(2900, 2901), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5016PolyExtStep::Get(611), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5017PolyExtStep::Mul(2903, 50), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5018PolyExtStep::Add(2902, 2904), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5019PolyExtStep::Mul(2905, 374), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5020PolyExtStep::Mul(2881, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5021PolyExtStep::Mul(736, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5022PolyExtStep::Mul(2902, 383), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5023PolyExtStep::Mul(2881, 386), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5024PolyExtStep::Add(2906, 2907), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5025PolyExtStep::Add(2911, 2908), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5026PolyExtStep::Add(2912, 2909), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5027PolyExtStep::Add(2913, 2910), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5028PolyExtStep::Mul(2903, 16), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5029PolyExtStep::Mul(2915, 374), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5030PolyExtStep::Mul(2915, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5031PolyExtStep::Mul(737, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5032PolyExtStep::Add(2916, 2917), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5033PolyExtStep::Add(2919, 2918), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5034PolyExtStep::Sub(1, 748), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5035PolyExtStep::Mul(748, 2921), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5036PolyExtStep::AndEqz(2085, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5037PolyExtStep::Mul(2819, 729), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5038PolyExtStep::Sub(2923, 2921), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5039PolyExtStep::AndEqz(2086, 2924), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5040PolyExtStep::Mul(748, 2819), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5041PolyExtStep::AndEqz(2087, 2925), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5042PolyExtStep::Mul(748, 729), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5043PolyExtStep::AndEqz(2088, 2926), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :42:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5044PolyExtStep::Mul(2921, 2819), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :44:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5045PolyExtStep::Sub(1, 2921), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:90) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5046PolyExtStep::Mul(2928, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:102) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5047PolyExtStep::Add(503, 2929), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:85) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5048PolyExtStep::Add(2930, 2927), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:106) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5049PolyExtStep::Sub(2931, 755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5050PolyExtStep::AndEqz(2089, 2932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :45:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5051PolyExtStep::Sub(756, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5052PolyExtStep::AndEqz(2090, 2933), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5053PolyExtStep::Sub(760, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5054PolyExtStep::AndEqz(2091, 2934), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5055PolyExtStep::Sub(761, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5056PolyExtStep::AndEqz(2092, 2935), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5057PolyExtStep::AndEqz(2093, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5058PolyExtStep::Sub(754, 755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5059PolyExtStep::AndEqz(2094, 2936), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5060PolyExtStep::Sub(761, 757), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5061PolyExtStep::Sub(771, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5062PolyExtStep::AndEqz(2095, 2938), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5063PolyExtStep::Sub(752, 2937), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5064PolyExtStep::AndEqz(2096, 2939), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5065PolyExtStep::Sub(762, 2914), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5066PolyExtStep::AndEqz(2097, 2940), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5067PolyExtStep::Sub(770, 2920), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5068PolyExtStep::AndEqz(2098, 2941), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :46:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :61:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5069PolyExtStep::Sub(782, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5070PolyExtStep::AndEqz(2099, 2942), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5071PolyExtStep::AndEqz(2100, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5072PolyExtStep::Mul(788, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5073PolyExtStep::Add(2943, 785), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5074PolyExtStep::Sub(504, 2944), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5075PolyExtStep::AndEqz(2101, 2945), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5076PolyExtStep::Add(367, 788), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5077PolyExtStep::AndEqz(2102, 2157), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5078PolyExtStep::AndEqz(2103, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5079PolyExtStep::Mul(797, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5080PolyExtStep::Add(2947, 794), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5081PolyExtStep::Sub(2946, 2948), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5082PolyExtStep::AndEqz(2104, 2949), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5083PolyExtStep::AndCond(1965, 434, 2105), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
5084PolyExtStep::Add(2830, 2819), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :67:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :20:32) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5085PolyExtStep::Add(503, 2815), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5086PolyExtStep::Sub(2951, 573), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5087PolyExtStep::AndEqz(2015, 2952), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5088PolyExtStep::Sub(552, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5089PolyExtStep::AndEqz(2107, 2953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5090PolyExtStep::AndEqz(2108, 1614), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5091PolyExtStep::Sub(567, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5092PolyExtStep::AndEqz(2109, 2954), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5093PolyExtStep::AndEqz(2110, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5094PolyExtStep::Sub(549, 573), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5095PolyExtStep::AndEqz(2111, 2955), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5096PolyExtStep::Sub(560, 569), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5097PolyExtStep::AndEqz(2112, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5098PolyExtStep::Sub(561, 570), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5099PolyExtStep::AndEqz(2113, 2957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5100PolyExtStep::Sub(567, 553), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5101PolyExtStep::Sub(571, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5102PolyExtStep::AndEqz(2114, 2959), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5103PolyExtStep::Sub(572, 2958), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5104PolyExtStep::AndEqz(2115, 2960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :22:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5105PolyExtStep::Add(662, 2950), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5106PolyExtStep::AndEqz(2116, 1620), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5107PolyExtStep::AndEqz(2117, 2084), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5108PolyExtStep::Mul(583, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5109PolyExtStep::Add(2962, 575), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5110PolyExtStep::Sub(2961, 2963), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5111PolyExtStep::AndEqz(2118, 2964), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5112PolyExtStep::Add(2845, 583), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5113PolyExtStep::Sub(584, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5114PolyExtStep::AndEqz(2119, 2966), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5115PolyExtStep::AndEqz(2120, 2098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5116PolyExtStep::Mul(731, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5117PolyExtStep::Add(2967, 732), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5118PolyExtStep::Sub(2965, 2968), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5119PolyExtStep::AndEqz(2121, 2969), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :23:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5120PolyExtStep::AndEqz(2122, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5121PolyExtStep::Sub(1, 734), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5122PolyExtStep::Mul(734, 2970), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5123PolyExtStep::AndEqz(2123, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5124PolyExtStep::Mul(734, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5125PolyExtStep::Add(2972, 733), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5126PolyExtStep::Sub(498, 732), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5127PolyExtStep::Sub(735, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5128PolyExtStep::AndEqz(2124, 2975), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5129PolyExtStep::Sub(736, 2974), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5130PolyExtStep::AndEqz(2125, 2976), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5131PolyExtStep::Sub(1, 737), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5132PolyExtStep::Mul(737, 2977), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5133PolyExtStep::AndEqz(2126, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5134PolyExtStep::Mul(732, 738), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5135PolyExtStep::Sub(2979, 2977), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5136PolyExtStep::AndEqz(2127, 2980), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5137PolyExtStep::Mul(737, 732), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5138PolyExtStep::AndEqz(2128, 2981), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5139PolyExtStep::Mul(737, 738), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5140PolyExtStep::AndEqz(2129, 2982), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5141PolyExtStep::AndEqz(2130, 737), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5142PolyExtStep::Sub(739, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5143PolyExtStep::AndEqz(2131, 2983), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5144PolyExtStep::Mul(747, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5145PolyExtStep::Add(2984, 2973), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5146PolyExtStep::Sub(2985, 575), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5147PolyExtStep::AndEqz(2132, 2986), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5148PolyExtStep::Mul(732, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5149PolyExtStep::Add(2987, 747), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5150PolyExtStep::Sub(729, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5151PolyExtStep::AndEqz(2133, 2989), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5152PolyExtStep::Sub(757, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5153PolyExtStep::AndEqz(2134, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5154PolyExtStep::Sub(758, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5155PolyExtStep::AndEqz(2135, 2991), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5156PolyExtStep::AndEqz(2136, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5157PolyExtStep::Sub(748, 2988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5158PolyExtStep::AndEqz(2137, 2992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5159PolyExtStep::Sub(754, 759), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5160PolyExtStep::AndEqz(2138, 2993), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5161PolyExtStep::AndEqz(2139, 2031), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5162PolyExtStep::Sub(758, 755), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5163PolyExtStep::AndEqz(2140, 1714), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5164PolyExtStep::Sub(762, 2994), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5165PolyExtStep::AndEqz(2141, 2995), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :68:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5166PolyExtStep::Sub(1396, 51), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :128:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5167PolyExtStep::Mul(734, 760), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:24) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5168PolyExtStep::Mul(2970, 759), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:69) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5169PolyExtStep::Add(2997, 2998), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:42) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5170PolyExtStep::AndEqz(0, 2996), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :67:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :128:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5171PolyExtStep::AndEqz(2143, 2827), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :128:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5172PolyExtStep::AndEqz(2144, 1106), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5173PolyExtStep::AndEqz(2145, 1112), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5174PolyExtStep::Sub(2999, 2883), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5175PolyExtStep::AndEqz(2146, 3000), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5176PolyExtStep::AndEqz(2147, 1117), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5177PolyExtStep::AndEqz(2148, 1123), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5178PolyExtStep::Mul(1122, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5179PolyExtStep::Add(3001, 1116), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5180PolyExtStep::Sub(569, 3002), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5181PolyExtStep::AndEqz(2149, 3003), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5182PolyExtStep::AndCond(2142, 374, 2150), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5183PolyExtStep::AndEqz(2143, 2893), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :146:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5184PolyExtStep::AndEqz(2152, 733), // loc(callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :147:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5185PolyExtStep::AndEqz(2153, 775), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5186PolyExtStep::AndEqz(2154, 776), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5187PolyExtStep::AndEqz(2155, 777), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5188PolyExtStep::AndEqz(2156, 778), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5189PolyExtStep::AndCond(2151, 377, 2157), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5190PolyExtStep::AndEqz(2143, 2897), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :68:18) at callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :158:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5191PolyExtStep::AndEqz(2159, 733), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :159:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5192PolyExtStep::AndEqz(2160, 734), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :160:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5193PolyExtStep::AndEqz(2161, 775), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5194PolyExtStep::AndEqz(2162, 776), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5195PolyExtStep::AndEqz(2163, 777), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5196PolyExtStep::AndEqz(2164, 778), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5197PolyExtStep::AndCond(2158, 380, 2165), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5198PolyExtStep::AndCond(2166, 383, 1190), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5199PolyExtStep::AndCond(2167, 386, 1190), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5200PolyExtStep::AndCond(2168, 389, 1190), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5201PolyExtStep::AndCond(2169, 392, 1190), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5202PolyExtStep::AndCond(2170, 395, 1190), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5203PolyExtStep::Mul(733, 2620), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :136:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5204PolyExtStep::Mul(2103, 1954), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :136:37) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5205PolyExtStep::Add(3004, 3005), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :136:22) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5206PolyExtStep::Mul(2103, 1957), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5207PolyExtStep::Mul(733, 1954), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:44) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5208PolyExtStep::Add(3007, 3008), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5209PolyExtStep::Mul(3009, 20), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5210PolyExtStep::Add(3006, 3010), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :136:41) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5211PolyExtStep::Mul(734, 759), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :140:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5212PolyExtStep::Mul(2970, 3011), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :140:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5213PolyExtStep::Add(3012, 3013), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :140:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5214PolyExtStep::Mul(3014, 374), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5215PolyExtStep::Mul(2970, 569), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :152:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5216PolyExtStep::Add(3012, 3016), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :152:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5217PolyExtStep::Mul(3017, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5218PolyExtStep::Mul(569, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5219PolyExtStep::Add(3015, 3018), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5220PolyExtStep::Add(3020, 3019), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5221PolyExtStep::Mul(2970, 760), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:13) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5222PolyExtStep::Mul(734, 3011), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5223PolyExtStep::Add(3022, 3023), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5224PolyExtStep::Mul(3024, 374), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5225PolyExtStep::Mul(734, 569), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5226PolyExtStep::Add(3022, 3026), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5227PolyExtStep::Mul(3027, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5228PolyExtStep::Mul(570, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5229PolyExtStep::Add(3025, 3028), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5230PolyExtStep::Add(3030, 3029), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5231PolyExtStep::Sub(771, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5232PolyExtStep::AndEqz(2171, 3032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5233PolyExtStep::Sub(788, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5234PolyExtStep::AndEqz(2172, 3033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5235PolyExtStep::Sub(791, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5236PolyExtStep::AndEqz(2173, 3034), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5237PolyExtStep::AndEqz(2174, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5238PolyExtStep::Sub(770, 2988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5239PolyExtStep::AndEqz(2175, 3035), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5240PolyExtStep::Sub(791, 752), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5241PolyExtStep::Sub(800, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5242PolyExtStep::AndEqz(2176, 3037), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5243PolyExtStep::Sub(803, 3036), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5244PolyExtStep::AndEqz(2177, 3038), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5245PolyExtStep::Sub(794, 3021), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5246PolyExtStep::AndEqz(2178, 3039), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5247PolyExtStep::Sub(797, 3031), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5248PolyExtStep::AndEqz(2179, 3040), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :29:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :79:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5249PolyExtStep::Sub(806, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5250PolyExtStep::AndEqz(2180, 3041), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5251PolyExtStep::AndEqz(2181, 814), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5252PolyExtStep::Mul(812, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5253PolyExtStep::Add(3042, 809), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5254PolyExtStep::Sub(504, 3043), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5255PolyExtStep::AndEqz(2182, 3044), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5256PolyExtStep::Add(367, 812), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5257PolyExtStep::Sub(815, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5258PolyExtStep::AndEqz(2183, 3046), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5259PolyExtStep::AndEqz(2184, 823), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5260PolyExtStep::Mul(821, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5261PolyExtStep::Add(3047, 818), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5262PolyExtStep::Sub(3045, 3048), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5263PolyExtStep::AndEqz(2185, 3049), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5264PolyExtStep::AndCond(2106, 437, 2186), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
5265PolyExtStep::Sub(368, 1), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :31:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5266PolyExtStep::Add(365, 367), // loc(callsite( builtin Add at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:31) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5267PolyExtStep::Sub(371, 1), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :71:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5268PolyExtStep::Sub(368, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5269PolyExtStep::Sub(368, 4), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5270PolyExtStep::Sub(368, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5271PolyExtStep::Sub(368, 2), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5272PolyExtStep::Sub(1061, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5273PolyExtStep::AndEqz(0, 3057), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5274PolyExtStep::Sub(2659, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5275PolyExtStep::AndEqz(2188, 3058), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5276PolyExtStep::AndEqz(0, 368), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5277PolyExtStep::Sub(775, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5278PolyExtStep::AndEqz(2190, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5279PolyExtStep::Sub(1116, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5280PolyExtStep::AndEqz(2191, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5281PolyExtStep::Sub(778, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5282PolyExtStep::AndEqz(2192, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5283PolyExtStep::AndEqz(2193, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5284PolyExtStep::Sub(1105, 322), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5285PolyExtStep::AndEqz(2194, 3062), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5286PolyExtStep::Sub(1111, 1122), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5287PolyExtStep::AndEqz(2195, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5288PolyExtStep::Sub(777, 779), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5289PolyExtStep::AndEqz(2196, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5290PolyExtStep::GetGlobal(0, 38), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5291PolyExtStep::Sub(3065, 1122), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5292PolyExtStep::AndEqz(2197, 3066), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5293PolyExtStep::GetGlobal(0, 39), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5294PolyExtStep::Sub(3067, 779), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5295PolyExtStep::AndEqz(2198, 3068), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5296PolyExtStep::Sub(1128, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5297PolyExtStep::AndEqz(2199, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5298PolyExtStep::AndEqz(2200, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5299PolyExtStep::Sub(1353, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5300PolyExtStep::AndEqz(2201, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5301PolyExtStep::AndEqz(2202, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5302PolyExtStep::Sub(1340, 323), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5303PolyExtStep::AndEqz(2203, 3071), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5304PolyExtStep::Sub(1343, 1359), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5305PolyExtStep::AndEqz(2204, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5306PolyExtStep::Sub(1350, 1360), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5307PolyExtStep::AndEqz(2205, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5308PolyExtStep::GetGlobal(0, 40), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5309PolyExtStep::Sub(3074, 1359), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5310PolyExtStep::AndEqz(2206, 3075), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5311PolyExtStep::GetGlobal(0, 41), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5312PolyExtStep::Sub(3076, 1360), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5313PolyExtStep::AndEqz(2207, 3077), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5314PolyExtStep::Sub(1362, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5315PolyExtStep::AndEqz(2208, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5316PolyExtStep::Sub(1379, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5317PolyExtStep::AndEqz(2209, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5318PolyExtStep::Sub(1392, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5319PolyExtStep::AndEqz(2210, 3080), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5320PolyExtStep::AndEqz(2211, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5321PolyExtStep::Sub(1369, 324), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5322PolyExtStep::AndEqz(2212, 3081), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5323PolyExtStep::Sub(1372, 1395), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5324PolyExtStep::AndEqz(2213, 3082), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5325PolyExtStep::Sub(1378, 1394), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5326PolyExtStep::AndEqz(2214, 3083), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5327PolyExtStep::GetGlobal(0, 42), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5328PolyExtStep::Sub(3084, 1395), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5329PolyExtStep::AndEqz(2215, 3085), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5330PolyExtStep::GetGlobal(0, 43), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5331PolyExtStep::Sub(3086, 1394), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5332PolyExtStep::AndEqz(2216, 3087), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5333PolyExtStep::Sub(1396, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5334PolyExtStep::AndEqz(2217, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5335PolyExtStep::AndEqz(2218, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5336PolyExtStep::Sub(1400, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5337PolyExtStep::AndEqz(2219, 3089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5338PolyExtStep::AndEqz(2220, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5339PolyExtStep::Sub(1773, 325), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5340PolyExtStep::AndEqz(2221, 3090), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5341PolyExtStep::Sub(1397, 1406), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5342PolyExtStep::AndEqz(2222, 3091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5343PolyExtStep::Sub(1398, 1407), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5344PolyExtStep::AndEqz(2223, 3092), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5345PolyExtStep::GetGlobal(0, 44), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5346PolyExtStep::Sub(3093, 1406), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5347PolyExtStep::AndEqz(2224, 3094), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5348PolyExtStep::GetGlobal(0, 45), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5349PolyExtStep::Sub(3095, 1407), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5350PolyExtStep::AndEqz(2225, 3096), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5351PolyExtStep::AndEqz(2226, 2712), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5352PolyExtStep::Sub(590, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5353PolyExtStep::AndEqz(2227, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5354PolyExtStep::Sub(597, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5355PolyExtStep::AndEqz(2228, 3098), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5356PolyExtStep::AndEqz(2229, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5357PolyExtStep::Sub(535, 326), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5358PolyExtStep::AndEqz(2230, 3099), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5359PolyExtStep::AndEqz(2231, 2716), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5360PolyExtStep::Sub(587, 611), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5361PolyExtStep::AndEqz(2232, 3100), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5362PolyExtStep::GetGlobal(0, 46), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5363PolyExtStep::Sub(3101, 604), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5364PolyExtStep::AndEqz(2233, 3102), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5365PolyExtStep::GetGlobal(0, 47), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5366PolyExtStep::Sub(3103, 611), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5367PolyExtStep::AndEqz(2234, 3104), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5368PolyExtStep::Sub(618, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5369PolyExtStep::AndEqz(2235, 3105), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5370PolyExtStep::AndEqz(2236, 2226), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5371PolyExtStep::Sub(648, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5372PolyExtStep::AndEqz(2237, 3106), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5373PolyExtStep::AndEqz(2238, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5374PolyExtStep::Sub(625, 327), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5375PolyExtStep::AndEqz(2239, 3107), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5376PolyExtStep::Sub(635, 655), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5377PolyExtStep::AndEqz(2240, 3108), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5378PolyExtStep::AndEqz(2241, 2839), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5379PolyExtStep::GetGlobal(0, 48), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5380PolyExtStep::Sub(3109, 655), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5381PolyExtStep::AndEqz(2242, 3110), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5382PolyExtStep::GetGlobal(0, 49), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5383PolyExtStep::Sub(3111, 662), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5384PolyExtStep::AndEqz(2243, 3112), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5385PolyExtStep::Sub(669, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5386PolyExtStep::AndEqz(2244, 3113), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5387PolyExtStep::AndEqz(2245, 1606), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5388PolyExtStep::Sub(553, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5389PolyExtStep::AndEqz(2246, 3114), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5390PolyExtStep::AndEqz(2247, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5391PolyExtStep::Sub(672, 328), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5392PolyExtStep::AndEqz(2248, 3115), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5393PolyExtStep::Sub(548, 560), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5394PolyExtStep::AndEqz(2249, 3116), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5395PolyExtStep::Sub(549, 561), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5396PolyExtStep::AndEqz(2250, 3117), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5397PolyExtStep::GetGlobal(0, 50), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5398PolyExtStep::Sub(3118, 560), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5399PolyExtStep::AndEqz(2251, 3119), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5400PolyExtStep::GetGlobal(0, 51), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5401PolyExtStep::Sub(3120, 561), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5402PolyExtStep::AndEqz(2252, 3121), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5403PolyExtStep::Sub(568, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5404PolyExtStep::AndEqz(2253, 3122), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5405PolyExtStep::AndEqz(2254, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5406PolyExtStep::AndEqz(2255, 578), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5407PolyExtStep::AndEqz(2256, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5408PolyExtStep::Sub(567, 329), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5409PolyExtStep::AndEqz(2257, 3123), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5410PolyExtStep::AndEqz(2258, 580), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5411PolyExtStep::AndEqz(2259, 581), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5412PolyExtStep::GetGlobal(0, 52), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5413PolyExtStep::Sub(3124, 574), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5414PolyExtStep::AndEqz(2260, 3125), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5415PolyExtStep::GetGlobal(0, 53), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5416PolyExtStep::Sub(3126, 575), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5417PolyExtStep::AndEqz(2261, 3127), // loc(callsite( ControlLoadRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :25:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :175:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5418PolyExtStep::AndEqz(2262, 583), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5419PolyExtStep::AndEqz(2263, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5420PolyExtStep::AndEqz(2264, 733), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5421PolyExtStep::AndEqz(2265, 735), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5422PolyExtStep::AndEqz(2266, 737), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5423PolyExtStep::AndEqz(2267, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5424PolyExtStep::AndEqz(2268, 748), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5425PolyExtStep::AndEqz(2269, 755), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5426PolyExtStep::AndEqz(2270, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5427PolyExtStep::AndEqz(2271, 758), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5428PolyExtStep::AndEqz(2272, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5429PolyExtStep::AndEqz(2273, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5430PolyExtStep::AndEqz(2274, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5431PolyExtStep::AndEqz(2275, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5432PolyExtStep::AndEqz(2276, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5433PolyExtStep::AndEqz(2277, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5434PolyExtStep::AndEqz(2278, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5435PolyExtStep::AndEqz(2279, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5436PolyExtStep::AndEqz(2280, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5437PolyExtStep::AndEqz(2281, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5438PolyExtStep::AndEqz(2282, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5439PolyExtStep::AndEqz(2283, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5440PolyExtStep::AndEqz(2284, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5441PolyExtStep::AndEqz(2285, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5442PolyExtStep::AndEqz(2286, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5443PolyExtStep::AndEqz(2287, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5444PolyExtStep::AndEqz(2288, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5445PolyExtStep::AndEqz(2289, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5446PolyExtStep::AndEqz(2290, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5447PolyExtStep::AndEqz(2291, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5448PolyExtStep::AndEqz(2292, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5449PolyExtStep::AndEqz(2293, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5450PolyExtStep::AndEqz(2294, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5451PolyExtStep::AndEqz(2295, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5452PolyExtStep::AndEqz(2296, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5453PolyExtStep::AndEqz(2297, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5454PolyExtStep::AndEqz(2298, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5455PolyExtStep::AndEqz(2299, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5456PolyExtStep::AndEqz(2300, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5457PolyExtStep::AndEqz(2301, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5458PolyExtStep::AndCond(2189, 374, 2302), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5459PolyExtStep::AndEqz(0, 3050), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :31:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5460PolyExtStep::AndEqz(2304, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5461PolyExtStep::Mul(3051, 1040), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5462PolyExtStep::Sub(3128, 1038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5463PolyExtStep::AndEqz(2305, 3129), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5464PolyExtStep::Mul(1037, 3051), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5465PolyExtStep::AndEqz(2306, 3130), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5466PolyExtStep::AndEqz(2307, 2652), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :33:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5467PolyExtStep::AndEqz(0, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5468PolyExtStep::AndEqz(2309, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5469PolyExtStep::AndEqz(2310, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5470PolyExtStep::AndEqz(2311, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5471PolyExtStep::Sub(1105, 350), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5472PolyExtStep::AndEqz(2312, 3131), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5473PolyExtStep::AndEqz(2313, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5474PolyExtStep::AndEqz(2314, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5475PolyExtStep::Sub(778, 776), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5476PolyExtStep::AndEqz(2315, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5477PolyExtStep::Sub(584, 3132), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5478PolyExtStep::AndEqz(2316, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5479PolyExtStep::AndEqz(2317, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5480PolyExtStep::AndEqz(2318, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5481PolyExtStep::AndEqz(2319, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5482PolyExtStep::AndEqz(2320, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5483PolyExtStep::Sub(1340, 351), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5484PolyExtStep::AndEqz(2321, 3134), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5485PolyExtStep::AndEqz(2322, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5486PolyExtStep::AndEqz(2323, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5487PolyExtStep::Sub(1353, 1341), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5488PolyExtStep::AndEqz(2324, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5489PolyExtStep::Sub(731, 3135), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5490PolyExtStep::AndEqz(2325, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :37:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5491PolyExtStep::AndEqz(2326, 1362), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5492PolyExtStep::AndEqz(2327, 1379), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5493PolyExtStep::AndEqz(2328, 1396), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5494PolyExtStep::AndEqz(2329, 1399), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5495PolyExtStep::AndEqz(2330, 1844), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5496PolyExtStep::AndEqz(2331, 590), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5497PolyExtStep::AndEqz(2332, 618), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5498PolyExtStep::AndEqz(2333, 645), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5499PolyExtStep::AndEqz(2334, 669), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5500PolyExtStep::AndEqz(2335, 552), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5501PolyExtStep::AndEqz(2336, 568), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5502PolyExtStep::AndEqz(2337, 572), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5503PolyExtStep::AndEqz(2338, 733), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5504PolyExtStep::AndEqz(2339, 735), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5505PolyExtStep::AndEqz(2340, 737), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5506PolyExtStep::AndEqz(2341, 739), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5507PolyExtStep::AndEqz(2342, 748), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5508PolyExtStep::AndEqz(2343, 755), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5509PolyExtStep::AndCond(2308, 1037, 2344), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5510PolyExtStep::GetGlobal(0, 0), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5511PolyExtStep::GetGlobal(0, 1), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5512PolyExtStep::Sub(778, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5513PolyExtStep::AndEqz(2310, 3139), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5514PolyExtStep::AndEqz(2346, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5515PolyExtStep::Sub(1105, 330), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5516PolyExtStep::AndEqz(2347, 3140), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5517PolyExtStep::AndEqz(2348, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5518PolyExtStep::AndEqz(2349, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5519PolyExtStep::Sub(1122, 3137), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5520PolyExtStep::AndEqz(2350, 3141), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5521PolyExtStep::Sub(779, 3138), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5522PolyExtStep::AndEqz(2351, 3142), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5523PolyExtStep::GetGlobal(0, 2), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5524PolyExtStep::GetGlobal(0, 3), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5525PolyExtStep::AndEqz(2352, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5526PolyExtStep::AndEqz(2353, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5527PolyExtStep::Sub(1353, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5528PolyExtStep::AndEqz(2354, 3145), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5529PolyExtStep::AndEqz(2355, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5530PolyExtStep::Sub(1340, 331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5531PolyExtStep::AndEqz(2356, 3146), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5532PolyExtStep::AndEqz(2357, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5533PolyExtStep::AndEqz(2358, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5534PolyExtStep::Sub(1359, 3143), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5535PolyExtStep::AndEqz(2359, 3147), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5536PolyExtStep::Sub(1360, 3144), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5537PolyExtStep::AndEqz(2360, 3148), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5538PolyExtStep::GetGlobal(0, 4), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5539PolyExtStep::GetGlobal(0, 5), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5540PolyExtStep::AndEqz(2361, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5541PolyExtStep::AndEqz(2362, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5542PolyExtStep::Sub(1392, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5543PolyExtStep::AndEqz(2363, 3151), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5544PolyExtStep::AndEqz(2364, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5545PolyExtStep::Sub(1369, 332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5546PolyExtStep::AndEqz(2365, 3152), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5547PolyExtStep::Sub(1392, 1370), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5548PolyExtStep::Sub(733, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5549PolyExtStep::AndEqz(2366, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5550PolyExtStep::Sub(734, 3153), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5551PolyExtStep::AndEqz(2367, 3155), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5552PolyExtStep::Sub(1395, 3149), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5553PolyExtStep::AndEqz(2368, 3156), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5554PolyExtStep::Sub(1394, 3150), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5555PolyExtStep::AndEqz(2369, 3157), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5556PolyExtStep::GetGlobal(0, 6), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5557PolyExtStep::GetGlobal(0, 7), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5558PolyExtStep::AndEqz(2370, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5559PolyExtStep::AndEqz(2371, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5560PolyExtStep::Sub(1400, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5561PolyExtStep::AndEqz(2372, 3160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5562PolyExtStep::AndEqz(2373, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5563PolyExtStep::Sub(1773, 333), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5564PolyExtStep::AndEqz(2374, 3161), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5565PolyExtStep::Sub(1400, 1774), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5566PolyExtStep::AndEqz(2375, 2975), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5567PolyExtStep::Sub(736, 3162), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5568PolyExtStep::AndEqz(2376, 3163), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5569PolyExtStep::Sub(1406, 3158), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5570PolyExtStep::AndEqz(2377, 3164), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5571PolyExtStep::Sub(1407, 3159), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5572PolyExtStep::AndEqz(2378, 3165), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5573PolyExtStep::GetGlobal(0, 8), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5574PolyExtStep::GetGlobal(0, 9), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5575PolyExtStep::AndEqz(2379, 2712), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5576PolyExtStep::AndEqz(2380, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5577PolyExtStep::Sub(597, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5578PolyExtStep::AndEqz(2381, 3168), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5579PolyExtStep::AndEqz(2382, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5580PolyExtStep::Sub(535, 334), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5581PolyExtStep::AndEqz(2383, 3169), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5582PolyExtStep::Sub(597, 2207), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5583PolyExtStep::Sub(737, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5584PolyExtStep::AndEqz(2384, 3171), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5585PolyExtStep::Sub(738, 3170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5586PolyExtStep::AndEqz(2385, 3172), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5587PolyExtStep::Sub(604, 3166), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5588PolyExtStep::AndEqz(2386, 3173), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5589PolyExtStep::Sub(611, 3167), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5590PolyExtStep::AndEqz(2387, 3174), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5591PolyExtStep::GetGlobal(0, 10), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5592PolyExtStep::GetGlobal(0, 11), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5593PolyExtStep::AndEqz(2388, 3105), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5594PolyExtStep::AndEqz(2389, 2226), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5595PolyExtStep::Sub(648, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5596PolyExtStep::AndEqz(2390, 3177), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5597PolyExtStep::AndEqz(2391, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5598PolyExtStep::Sub(625, 335), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5599PolyExtStep::AndEqz(2392, 3178), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5600PolyExtStep::Sub(648, 628), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5601PolyExtStep::AndEqz(2393, 2983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5602PolyExtStep::Sub(747, 3179), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5603PolyExtStep::AndEqz(2394, 3180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5604PolyExtStep::Sub(655, 3175), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5605PolyExtStep::AndEqz(2395, 3181), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5606PolyExtStep::Sub(662, 3176), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5607PolyExtStep::AndEqz(2396, 3182), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5608PolyExtStep::GetGlobal(0, 12), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5609PolyExtStep::GetGlobal(0, 13), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5610PolyExtStep::AndEqz(2397, 3113), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5611PolyExtStep::AndEqz(2398, 1606), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5612PolyExtStep::Sub(553, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5613PolyExtStep::AndEqz(2399, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5614PolyExtStep::AndEqz(2400, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5615PolyExtStep::Sub(672, 336), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5616PolyExtStep::AndEqz(2401, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5617PolyExtStep::Sub(553, 541), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5618PolyExtStep::Sub(748, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5619PolyExtStep::AndEqz(2402, 3188), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5620PolyExtStep::Sub(729, 3187), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5621PolyExtStep::AndEqz(2403, 3189), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5622PolyExtStep::Sub(560, 3183), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5623PolyExtStep::AndEqz(2404, 3190), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5624PolyExtStep::Sub(561, 3184), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5625PolyExtStep::AndEqz(2405, 3191), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5626PolyExtStep::GetGlobal(0, 14), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5627PolyExtStep::GetGlobal(0, 15), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :40:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5628PolyExtStep::AndEqz(2406, 3122), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5629PolyExtStep::AndEqz(2407, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5630PolyExtStep::Sub(573, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5631PolyExtStep::AndEqz(2408, 3194), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5632PolyExtStep::AndEqz(2409, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5633PolyExtStep::Sub(567, 337), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5634PolyExtStep::AndEqz(2410, 3195), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5635PolyExtStep::Sub(755, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5636PolyExtStep::AndEqz(2411, 3196), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5637PolyExtStep::Sub(754, 582), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5638PolyExtStep::AndEqz(2412, 3197), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5639PolyExtStep::Sub(574, 3192), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5640PolyExtStep::AndEqz(2413, 3198), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5641PolyExtStep::Sub(575, 3193), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5642PolyExtStep::AndEqz(2414, 3199), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :42:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5643PolyExtStep::AndCond(2345, 1038, 2415), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5644PolyExtStep::AndEqz(2416, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5645PolyExtStep::AndEqz(2417, 758), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5646PolyExtStep::AndEqz(2418, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5647PolyExtStep::AndEqz(2419, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5648PolyExtStep::AndEqz(2420, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5649PolyExtStep::AndEqz(2421, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5650PolyExtStep::AndEqz(2422, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5651PolyExtStep::AndEqz(2423, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5652PolyExtStep::AndEqz(2424, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5653PolyExtStep::AndEqz(2425, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5654PolyExtStep::AndEqz(2426, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5655PolyExtStep::AndEqz(2427, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5656PolyExtStep::AndEqz(2428, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5657PolyExtStep::AndEqz(2429, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5658PolyExtStep::AndEqz(2430, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5659PolyExtStep::AndEqz(2431, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5660PolyExtStep::AndEqz(2432, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5661PolyExtStep::AndEqz(2433, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5662PolyExtStep::AndEqz(2434, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5663PolyExtStep::AndEqz(2435, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5664PolyExtStep::AndEqz(2436, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5665PolyExtStep::AndEqz(2437, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5666PolyExtStep::AndEqz(2438, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5667PolyExtStep::AndEqz(2439, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5668PolyExtStep::AndEqz(2440, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5669PolyExtStep::AndEqz(2441, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5670PolyExtStep::AndEqz(2442, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5671PolyExtStep::AndEqz(2443, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5672PolyExtStep::AndEqz(2444, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5673PolyExtStep::AndEqz(2445, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5674PolyExtStep::AndEqz(2446, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5675PolyExtStep::AndEqz(2447, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5676PolyExtStep::AndCond(2303, 377, 2448), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5677PolyExtStep::Sub(371, 1037), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :50:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5678PolyExtStep::AndEqz(0, 3200), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :50:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5679PolyExtStep::AndEqz(2450, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5680PolyExtStep::AndEqz(2451, 1045), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5681PolyExtStep::Mul(1043, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5682PolyExtStep::Add(3201, 1040), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5683PolyExtStep::Mul(1037, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5684PolyExtStep::Mul(1038, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5685PolyExtStep::Add(3203, 3204), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5686PolyExtStep::Sub(3205, 367), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5687PolyExtStep::Sub(756, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5688PolyExtStep::AndEqz(2452, 3207), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5689PolyExtStep::Sub(757, 3206), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5690PolyExtStep::AndEqz(2453, 3208), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5691PolyExtStep::AndEqz(2454, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5692PolyExtStep::Mul(367, 1049), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5693PolyExtStep::Sub(3209, 1047), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5694PolyExtStep::AndEqz(2455, 3210), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5695PolyExtStep::Mul(1046, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5696PolyExtStep::AndEqz(2456, 3211), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5697PolyExtStep::Mul(1046, 1049), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5698PolyExtStep::AndEqz(2457, 3212), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5699PolyExtStep::AndEqz(2458, 1046), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5700PolyExtStep::AndEqz(2459, 2028), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5701PolyExtStep::Mul(759, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5702PolyExtStep::Add(3213, 3202), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5703PolyExtStep::Sub(3214, 365), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5704PolyExtStep::AndEqz(2460, 3215), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5705PolyExtStep::Add(500, 759), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :51:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5706PolyExtStep::AndEqz(2461, 3202), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :52:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5707PolyExtStep::AndEqz(2462, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5708PolyExtStep::AndEqz(2463, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5709PolyExtStep::AndEqz(2464, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5710PolyExtStep::AndEqz(2465, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5711PolyExtStep::Sub(1105, 3216), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5712PolyExtStep::AndEqz(2466, 3217), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5713PolyExtStep::AndEqz(2467, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5714PolyExtStep::AndEqz(2468, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5715PolyExtStep::AndEqz(2469, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5716PolyExtStep::AndEqz(2470, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :53:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5717PolyExtStep::AndEqz(2471, 779), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :54:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5718PolyExtStep::Sub(1122, 45), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :55:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5719PolyExtStep::AndEqz(2472, 3218), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :55:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5720PolyExtStep::AndEqz(2473, 494), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5721PolyExtStep::AndEqz(2474, 371), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5722PolyExtStep::AndEqz(2475, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5723PolyExtStep::AndEqz(2476, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5724PolyExtStep::AndEqz(2477, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5725PolyExtStep::AndEqz(2478, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5726PolyExtStep::Sub(1340, 338), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5727PolyExtStep::AndEqz(2479, 3219), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5728PolyExtStep::AndEqz(2480, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5729PolyExtStep::AndEqz(2481, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5730PolyExtStep::AndEqz(2482, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5731PolyExtStep::AndEqz(2483, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5732PolyExtStep::AndEqz(2484, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5733PolyExtStep::AndEqz(2485, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5734PolyExtStep::AndEqz(2486, 3151), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5735PolyExtStep::AndEqz(2487, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5736PolyExtStep::Sub(1369, 339), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5737PolyExtStep::AndEqz(2488, 3220), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5738PolyExtStep::AndEqz(2489, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5739PolyExtStep::AndEqz(2490, 3155), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5740PolyExtStep::Sub(1395, 365), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5741PolyExtStep::AndEqz(2491, 3221), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5742PolyExtStep::Sub(1394, 367), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5743PolyExtStep::AndEqz(2492, 3222), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5744PolyExtStep::AndEqz(2493, 1396), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5745PolyExtStep::AndEqz(2494, 1399), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5746PolyExtStep::AndEqz(2495, 1844), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5747PolyExtStep::AndEqz(2496, 590), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5748PolyExtStep::AndEqz(2497, 618), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5749PolyExtStep::AndEqz(2498, 645), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5750PolyExtStep::AndEqz(2499, 669), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5751PolyExtStep::AndEqz(2500, 552), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5752PolyExtStep::AndEqz(2501, 568), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5753PolyExtStep::AndEqz(2502, 572), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5754PolyExtStep::AndEqz(2503, 735), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5755PolyExtStep::AndEqz(2504, 737), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5756PolyExtStep::AndEqz(2505, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5757PolyExtStep::AndEqz(2506, 748), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5758PolyExtStep::AndEqz(2507, 755), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5759PolyExtStep::AndEqz(2508, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5760PolyExtStep::AndEqz(2509, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5761PolyExtStep::AndEqz(2510, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5762PolyExtStep::AndEqz(2511, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5763PolyExtStep::AndEqz(2512, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5764PolyExtStep::AndEqz(2513, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5765PolyExtStep::AndEqz(2514, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5766PolyExtStep::AndEqz(2515, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5767PolyExtStep::AndEqz(2516, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5768PolyExtStep::AndEqz(2517, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5769PolyExtStep::AndEqz(2518, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5770PolyExtStep::AndEqz(2519, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5771PolyExtStep::AndEqz(2520, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5772PolyExtStep::AndEqz(2521, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5773PolyExtStep::AndEqz(2522, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5774PolyExtStep::AndEqz(2523, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5775PolyExtStep::AndEqz(2524, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5776PolyExtStep::AndEqz(2525, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5777PolyExtStep::AndEqz(2526, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5778PolyExtStep::AndEqz(2527, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5779PolyExtStep::AndEqz(2528, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5780PolyExtStep::AndEqz(2529, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5781PolyExtStep::AndEqz(2530, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5782PolyExtStep::AndEqz(2531, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5783PolyExtStep::AndEqz(2532, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5784PolyExtStep::AndEqz(2533, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5785PolyExtStep::AndEqz(2534, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5786PolyExtStep::AndEqz(2535, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5787PolyExtStep::AndEqz(2536, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5788PolyExtStep::AndEqz(2537, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5789PolyExtStep::AndCond(2449, 380, 2538), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5790PolyExtStep::Sub(779, 340), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :68:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5791PolyExtStep::AndEqz(2471, 3223), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :68:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5792PolyExtStep::AndEqz(2540, 3218), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :69:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5793PolyExtStep::AndEqz(2541, 494), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :70:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5794PolyExtStep::AndEqz(2542, 3052), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :71:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5795PolyExtStep::AndEqz(2543, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5796PolyExtStep::AndEqz(2544, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5797PolyExtStep::AndEqz(2545, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5798PolyExtStep::AndEqz(2546, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5799PolyExtStep::Sub(1340, 339), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5800PolyExtStep::AndEqz(2547, 3224), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5801PolyExtStep::AndEqz(2548, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5802PolyExtStep::AndEqz(2549, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5803PolyExtStep::AndEqz(2550, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5804PolyExtStep::AndEqz(2551, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :72:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5805PolyExtStep::Add(1359, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5806PolyExtStep::AndEqz(2552, 2934), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5807PolyExtStep::AndEqz(2553, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5808PolyExtStep::Mul(1052, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5809PolyExtStep::Add(3226, 761), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5810PolyExtStep::Sub(3225, 3227), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5811PolyExtStep::AndEqz(2554, 3228), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5812PolyExtStep::Add(1360, 1052), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5813PolyExtStep::AndEqz(2555, 2033), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5814PolyExtStep::AndEqz(2556, 1057), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5815PolyExtStep::Mul(1055, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5816PolyExtStep::Add(3230, 770), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5817PolyExtStep::Sub(3229, 3231), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5818PolyExtStep::AndEqz(2557, 3232), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :178:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5819PolyExtStep::AndEqz(2558, 1362), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5820PolyExtStep::AndEqz(2559, 1379), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5821PolyExtStep::AndEqz(2560, 1396), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5822PolyExtStep::AndEqz(2561, 1399), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5823PolyExtStep::AndEqz(2562, 1844), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5824PolyExtStep::AndEqz(2563, 590), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5825PolyExtStep::AndEqz(2564, 618), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5826PolyExtStep::AndEqz(2565, 645), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5827PolyExtStep::AndEqz(2566, 669), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5828PolyExtStep::AndEqz(2567, 552), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5829PolyExtStep::AndEqz(2568, 568), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5830PolyExtStep::AndEqz(2569, 572), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5831PolyExtStep::AndEqz(2570, 733), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5832PolyExtStep::AndEqz(2571, 735), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5833PolyExtStep::AndEqz(2572, 737), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5834PolyExtStep::AndEqz(2573, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5835PolyExtStep::AndEqz(2574, 748), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5836PolyExtStep::AndEqz(2575, 755), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5837PolyExtStep::AndEqz(2576, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5838PolyExtStep::AndEqz(2577, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5839PolyExtStep::AndEqz(2578, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5840PolyExtStep::AndEqz(2579, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5841PolyExtStep::AndEqz(2580, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5842PolyExtStep::AndEqz(2581, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5843PolyExtStep::AndEqz(2582, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5844PolyExtStep::AndEqz(2583, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5845PolyExtStep::AndEqz(2584, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5846PolyExtStep::AndEqz(2585, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5847PolyExtStep::AndEqz(2586, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5848PolyExtStep::AndEqz(2587, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5849PolyExtStep::AndEqz(2588, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5850PolyExtStep::AndEqz(2589, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5851PolyExtStep::AndEqz(2590, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5852PolyExtStep::AndEqz(2591, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5853PolyExtStep::AndEqz(2592, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5854PolyExtStep::AndEqz(2593, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5855PolyExtStep::AndEqz(2594, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5856PolyExtStep::AndEqz(2595, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5857PolyExtStep::AndEqz(2596, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5858PolyExtStep::AndEqz(2597, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5859PolyExtStep::AndEqz(2598, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5860PolyExtStep::AndEqz(2599, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5861PolyExtStep::AndEqz(2600, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5862PolyExtStep::AndEqz(2601, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5863PolyExtStep::AndEqz(2602, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5864PolyExtStep::AndEqz(2603, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5865PolyExtStep::AndCond(2539, 383, 2604), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5866PolyExtStep::AndEqz(0, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5867PolyExtStep::Mul(3051, 1043), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5868PolyExtStep::Sub(3233, 1041), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5869PolyExtStep::AndEqz(2606, 3234), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5870PolyExtStep::AndEqz(2607, 3128), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5871PolyExtStep::Mul(1040, 1043), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5872PolyExtStep::AndEqz(2608, 3235), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5873PolyExtStep::AndEqz(0, 3053), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5874PolyExtStep::AndEqz(2610, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5875PolyExtStep::AndEqz(2611, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5876PolyExtStep::AndEqz(2612, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5877PolyExtStep::AndEqz(2613, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5878PolyExtStep::Sub(1105, 341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5879PolyExtStep::AndEqz(2614, 3236), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5880PolyExtStep::AndEqz(2615, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5881PolyExtStep::AndEqz(2616, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5882PolyExtStep::AndEqz(2617, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5883PolyExtStep::AndEqz(2618, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5884PolyExtStep::AndEqz(2619, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5885PolyExtStep::AndEqz(2620, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5886PolyExtStep::AndEqz(2621, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5887PolyExtStep::AndEqz(2622, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5888PolyExtStep::Sub(1340, 342), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5889PolyExtStep::AndEqz(2623, 3237), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5890PolyExtStep::AndEqz(2624, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5891PolyExtStep::AndEqz(2625, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5892PolyExtStep::AndEqz(2626, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5893PolyExtStep::AndEqz(2627, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5894PolyExtStep::AndEqz(2628, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5895PolyExtStep::AndEqz(2629, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5896PolyExtStep::AndEqz(2630, 3080), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5897PolyExtStep::AndEqz(2631, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5898PolyExtStep::Sub(1369, 343), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5899PolyExtStep::AndEqz(2632, 3238), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5900PolyExtStep::AndEqz(2633, 3082), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5901PolyExtStep::AndEqz(2634, 3083), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5902PolyExtStep::AndEqz(2635, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5903PolyExtStep::AndEqz(2636, 3155), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5904PolyExtStep::AndEqz(2637, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5905PolyExtStep::AndEqz(2638, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5906PolyExtStep::AndEqz(2639, 3089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5907PolyExtStep::AndEqz(2640, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5908PolyExtStep::Sub(1773, 344), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5909PolyExtStep::AndEqz(2641, 3239), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5910PolyExtStep::AndEqz(2642, 3091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5911PolyExtStep::AndEqz(2643, 3092), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5912PolyExtStep::AndEqz(2644, 2975), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5913PolyExtStep::AndEqz(2645, 3163), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5914PolyExtStep::AndEqz(2646, 2712), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5915PolyExtStep::AndEqz(2647, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5916PolyExtStep::AndEqz(2648, 3098), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5917PolyExtStep::AndEqz(2649, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5918PolyExtStep::Sub(535, 345), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5919PolyExtStep::AndEqz(2650, 3240), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5920PolyExtStep::AndEqz(2651, 2716), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5921PolyExtStep::AndEqz(2652, 3100), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5922PolyExtStep::AndEqz(2653, 3171), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5923PolyExtStep::AndEqz(2654, 3172), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5924PolyExtStep::AndEqz(2655, 3105), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5925PolyExtStep::AndEqz(2656, 2226), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5926PolyExtStep::AndEqz(2657, 3106), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5927PolyExtStep::AndEqz(2658, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5928PolyExtStep::Sub(625, 346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5929PolyExtStep::AndEqz(2659, 3241), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5930PolyExtStep::AndEqz(2660, 3108), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5931PolyExtStep::AndEqz(2661, 2839), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5932PolyExtStep::AndEqz(2662, 2983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5933PolyExtStep::AndEqz(2663, 3180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5934PolyExtStep::AndEqz(2664, 3113), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5935PolyExtStep::AndEqz(2665, 1606), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5936PolyExtStep::AndEqz(2666, 3114), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5937PolyExtStep::AndEqz(2667, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5938PolyExtStep::Sub(672, 347), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5939PolyExtStep::AndEqz(2668, 3242), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5940PolyExtStep::AndEqz(2669, 3116), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5941PolyExtStep::AndEqz(2670, 3117), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5942PolyExtStep::AndEqz(2671, 3188), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5943PolyExtStep::AndEqz(2672, 3189), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5944PolyExtStep::AndEqz(2673, 3122), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5945PolyExtStep::AndEqz(2674, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5946PolyExtStep::AndEqz(2675, 578), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5947PolyExtStep::AndEqz(2676, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5948PolyExtStep::Sub(567, 348), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5949PolyExtStep::AndEqz(2677, 3243), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5950PolyExtStep::AndEqz(2678, 580), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5951PolyExtStep::AndEqz(2679, 581), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5952PolyExtStep::AndEqz(2680, 3196), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5953PolyExtStep::AndEqz(2681, 3197), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :86:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5954PolyExtStep::GetGlobal(0, 17), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5955PolyExtStep::Sub(1122, 3244), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5956PolyExtStep::AndEqz(2682, 3245), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5957PolyExtStep::GetGlobal(0, 18), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5958PolyExtStep::Sub(779, 3246), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5959PolyExtStep::AndEqz(2683, 3247), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5960PolyExtStep::GetGlobal(0, 19), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5961PolyExtStep::Sub(1359, 3248), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5962PolyExtStep::AndEqz(2684, 3249), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5963PolyExtStep::GetGlobal(0, 20), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5964PolyExtStep::Sub(1360, 3250), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5965PolyExtStep::AndEqz(2685, 3251), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5966PolyExtStep::GetGlobal(0, 21), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5967PolyExtStep::Sub(1395, 3252), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5968PolyExtStep::AndEqz(2686, 3253), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5969PolyExtStep::GetGlobal(0, 22), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5970PolyExtStep::Sub(1394, 3254), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5971PolyExtStep::AndEqz(2687, 3255), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5972PolyExtStep::GetGlobal(0, 23), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5973PolyExtStep::Sub(1406, 3256), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5974PolyExtStep::AndEqz(2688, 3257), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5975PolyExtStep::GetGlobal(0, 24), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5976PolyExtStep::Sub(1407, 3258), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5977PolyExtStep::AndEqz(2689, 3259), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5978PolyExtStep::GetGlobal(0, 25), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5979PolyExtStep::Sub(604, 3260), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5980PolyExtStep::AndEqz(2690, 3261), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5981PolyExtStep::GetGlobal(0, 26), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5982PolyExtStep::Sub(611, 3262), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5983PolyExtStep::AndEqz(2691, 3263), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5984PolyExtStep::GetGlobal(0, 27), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5985PolyExtStep::Sub(655, 3264), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5986PolyExtStep::AndEqz(2692, 3265), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5987PolyExtStep::GetGlobal(0, 28), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5988PolyExtStep::Sub(662, 3266), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5989PolyExtStep::AndEqz(2693, 3267), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5990PolyExtStep::GetGlobal(0, 29), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5991PolyExtStep::Sub(560, 3268), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5992PolyExtStep::AndEqz(2694, 3269), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5993PolyExtStep::GetGlobal(0, 30), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5994PolyExtStep::Sub(561, 3270), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5995PolyExtStep::AndEqz(2695, 3271), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5996PolyExtStep::GetGlobal(0, 31), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5997PolyExtStep::Sub(574, 3272), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5998PolyExtStep::AndEqz(2696, 3273), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5999PolyExtStep::GetGlobal(0, 32), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6000PolyExtStep::Sub(575, 3274), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6001PolyExtStep::AndEqz(2697, 3275), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :85:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6002PolyExtStep::GetGlobal(0, 16), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :83:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6003PolyExtStep::Sub(1, 3276), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :88:10) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6004PolyExtStep::GetGlobal(0, 71), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :89:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6005PolyExtStep::Sub(0, 3278), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :89:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6006PolyExtStep::AndEqz(0, 3279), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :89:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6007PolyExtStep::GetGlobal(0, 70), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :90:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6008PolyExtStep::Sub(0, 3280), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :90:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6009PolyExtStep::AndEqz(2699, 3281), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :90:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6010PolyExtStep::GetGlobal(0, 73), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6011PolyExtStep::Sub(0, 3282), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6012PolyExtStep::AndEqz(2700, 3283), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6013PolyExtStep::GetGlobal(0, 72), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :92:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6014PolyExtStep::Sub(0, 3284), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :92:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6015PolyExtStep::AndEqz(2701, 3285), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :92:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6016PolyExtStep::AndCond(2698, 3277, 2702), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :88:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6017PolyExtStep::AndCond(2609, 1040, 2703), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6018PolyExtStep::Sub(368, 1037), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :100:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6019PolyExtStep::AndEqz(0, 3286), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :100:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6020PolyExtStep::Sub(1037, 13), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :101:7) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6021PolyExtStep::Sub(1037, 5), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :101:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6022PolyExtStep::Mul(3287, 3288), // loc(callsite( builtin Mul at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :101:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6023PolyExtStep::AndEqz(2705, 3289), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :101:57) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6024PolyExtStep::Mul(3287, 352), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:54) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6025PolyExtStep::Sub(3290, 3276), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6026PolyExtStep::AndEqz(2706, 3291), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6027PolyExtStep::AndEqz(2707, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6028PolyExtStep::AndEqz(2708, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6029PolyExtStep::AndEqz(2709, 3139), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6030PolyExtStep::AndEqz(2710, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6031PolyExtStep::AndEqz(2711, 3131), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6032PolyExtStep::AndEqz(2712, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6033PolyExtStep::AndEqz(2713, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6034PolyExtStep::Sub(1122, 365), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6035PolyExtStep::AndEqz(2714, 3292), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6036PolyExtStep::Sub(779, 367), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6037PolyExtStep::AndEqz(2715, 3293), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6038PolyExtStep::AndEqz(2716, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6039PolyExtStep::AndEqz(2717, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6040PolyExtStep::AndEqz(2718, 3145), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6041PolyExtStep::AndEqz(2719, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6042PolyExtStep::AndEqz(2720, 3134), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6043PolyExtStep::AndEqz(2721, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6044PolyExtStep::AndEqz(2722, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6045PolyExtStep::Sub(1359, 371), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6046PolyExtStep::AndEqz(2723, 3294), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6047PolyExtStep::AndEqz(2724, 1360), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :107:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6048PolyExtStep::AndEqz(2725, 1362), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6049PolyExtStep::AndEqz(2726, 1379), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6050PolyExtStep::AndEqz(2727, 1396), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6051PolyExtStep::AndEqz(2728, 1399), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6052PolyExtStep::AndEqz(2729, 1844), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6053PolyExtStep::AndEqz(2730, 590), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6054PolyExtStep::AndEqz(2731, 618), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6055PolyExtStep::AndEqz(2732, 645), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6056PolyExtStep::AndEqz(2733, 669), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6057PolyExtStep::AndEqz(2734, 552), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6058PolyExtStep::AndEqz(2735, 568), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6059PolyExtStep::AndEqz(2736, 572), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6060PolyExtStep::AndEqz(2737, 733), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6061PolyExtStep::AndEqz(2738, 735), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6062PolyExtStep::AndEqz(2739, 737), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6063PolyExtStep::AndEqz(2740, 739), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6064PolyExtStep::AndEqz(2741, 748), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6065PolyExtStep::AndEqz(2742, 755), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6066PolyExtStep::AndCond(2704, 1041, 2743), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6067PolyExtStep::AndEqz(2744, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6068PolyExtStep::AndEqz(2745, 758), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6069PolyExtStep::AndEqz(2746, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6070PolyExtStep::AndEqz(2747, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6071PolyExtStep::AndEqz(2748, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6072PolyExtStep::AndEqz(2749, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6073PolyExtStep::AndEqz(2750, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6074PolyExtStep::AndEqz(2751, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6075PolyExtStep::AndEqz(2752, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6076PolyExtStep::AndEqz(2753, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6077PolyExtStep::AndEqz(2754, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6078PolyExtStep::AndEqz(2755, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6079PolyExtStep::AndEqz(2756, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6080PolyExtStep::AndEqz(2757, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6081PolyExtStep::AndEqz(2758, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6082PolyExtStep::AndEqz(2759, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6083PolyExtStep::AndEqz(2760, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6084PolyExtStep::AndEqz(2761, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6085PolyExtStep::AndEqz(2762, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6086PolyExtStep::AndEqz(2763, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6087PolyExtStep::AndEqz(2764, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6088PolyExtStep::AndEqz(2765, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6089PolyExtStep::AndEqz(2766, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6090PolyExtStep::AndEqz(2767, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6091PolyExtStep::AndEqz(2768, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6092PolyExtStep::AndEqz(2769, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6093PolyExtStep::AndEqz(2770, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6094PolyExtStep::AndEqz(2771, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6095PolyExtStep::AndEqz(2772, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6096PolyExtStep::AndEqz(2773, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6097PolyExtStep::AndEqz(2774, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6098PolyExtStep::AndEqz(2775, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6099PolyExtStep::AndCond(2605, 386, 2776), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6100PolyExtStep::AndEqz(0, 3054), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6101PolyExtStep::AndEqz(2778, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6102PolyExtStep::AndEqz(2779, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6103PolyExtStep::AndEqz(2780, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6104PolyExtStep::AndEqz(2781, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6105PolyExtStep::AndEqz(2782, 3062), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6106PolyExtStep::AndEqz(2783, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6107PolyExtStep::AndEqz(2784, 3133), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6108PolyExtStep::AndEqz(2785, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6109PolyExtStep::AndEqz(2786, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6110PolyExtStep::AndEqz(2787, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6111PolyExtStep::AndEqz(2788, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6112PolyExtStep::AndEqz(2789, 3071), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6113PolyExtStep::AndEqz(2790, 1626), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6114PolyExtStep::AndEqz(2791, 3136), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6115PolyExtStep::AndEqz(2792, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6116PolyExtStep::AndEqz(2793, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6117PolyExtStep::AndEqz(2794, 3080), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6118PolyExtStep::AndEqz(2795, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6119PolyExtStep::AndEqz(2796, 3081), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6120PolyExtStep::AndEqz(2797, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6121PolyExtStep::AndEqz(2798, 3155), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6122PolyExtStep::AndEqz(2799, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6123PolyExtStep::AndEqz(2800, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6124PolyExtStep::AndEqz(2801, 3089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6125PolyExtStep::AndEqz(2802, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6126PolyExtStep::AndEqz(2803, 3090), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6127PolyExtStep::AndEqz(2804, 2975), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6128PolyExtStep::AndEqz(2805, 3163), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6129PolyExtStep::AndEqz(2806, 2712), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6130PolyExtStep::AndEqz(2807, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6131PolyExtStep::AndEqz(2808, 3098), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6132PolyExtStep::AndEqz(2809, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6133PolyExtStep::AndEqz(2810, 3099), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6134PolyExtStep::AndEqz(2811, 3171), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6135PolyExtStep::AndEqz(2812, 3172), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6136PolyExtStep::AndEqz(2813, 3105), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6137PolyExtStep::AndEqz(2814, 2226), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6138PolyExtStep::AndEqz(2815, 3106), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6139PolyExtStep::AndEqz(2816, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6140PolyExtStep::AndEqz(2817, 3107), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6141PolyExtStep::AndEqz(2818, 2983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6142PolyExtStep::AndEqz(2819, 3180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6143PolyExtStep::AndEqz(2820, 3113), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6144PolyExtStep::AndEqz(2821, 1606), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6145PolyExtStep::AndEqz(2822, 3114), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6146PolyExtStep::AndEqz(2823, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6147PolyExtStep::AndEqz(2824, 3115), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6148PolyExtStep::AndEqz(2825, 3188), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6149PolyExtStep::AndEqz(2826, 3189), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6150PolyExtStep::AndEqz(2827, 3122), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6151PolyExtStep::AndEqz(2828, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6152PolyExtStep::AndEqz(2829, 578), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6153PolyExtStep::AndEqz(2830, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6154PolyExtStep::AndEqz(2831, 3123), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6155PolyExtStep::AndEqz(2832, 3196), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6156PolyExtStep::AndEqz(2833, 3197), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :117:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6157PolyExtStep::GetGlobal(0, 54), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6158PolyExtStep::Sub(1111, 3295), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6159PolyExtStep::AndEqz(2834, 3296), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6160PolyExtStep::GetGlobal(0, 55), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6161PolyExtStep::Sub(777, 3297), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6162PolyExtStep::AndEqz(2835, 3298), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6163PolyExtStep::GetGlobal(0, 56), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6164PolyExtStep::Sub(1343, 3299), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6165PolyExtStep::AndEqz(2836, 3300), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6166PolyExtStep::GetGlobal(0, 57), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6167PolyExtStep::Sub(1350, 3301), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6168PolyExtStep::AndEqz(2837, 3302), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6169PolyExtStep::GetGlobal(0, 58), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6170PolyExtStep::Sub(1372, 3303), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6171PolyExtStep::AndEqz(2838, 3304), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6172PolyExtStep::GetGlobal(0, 59), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6173PolyExtStep::Sub(1378, 3305), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6174PolyExtStep::AndEqz(2839, 3306), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6175PolyExtStep::GetGlobal(0, 60), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6176PolyExtStep::Sub(1397, 3307), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6177PolyExtStep::AndEqz(2840, 3308), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6178PolyExtStep::GetGlobal(0, 61), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6179PolyExtStep::Sub(1398, 3309), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6180PolyExtStep::AndEqz(2841, 3310), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6181PolyExtStep::GetGlobal(0, 62), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6182PolyExtStep::Sub(536, 3311), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6183PolyExtStep::AndEqz(2842, 3312), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6184PolyExtStep::GetGlobal(0, 63), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6185PolyExtStep::Sub(587, 3313), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6186PolyExtStep::AndEqz(2843, 3314), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6187PolyExtStep::GetGlobal(0, 64), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6188PolyExtStep::Sub(635, 3315), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6189PolyExtStep::AndEqz(2844, 3316), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6190PolyExtStep::GetGlobal(0, 65), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6191PolyExtStep::Sub(642, 3317), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6192PolyExtStep::AndEqz(2845, 3318), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6193PolyExtStep::GetGlobal(0, 66), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6194PolyExtStep::Sub(548, 3319), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6195PolyExtStep::AndEqz(2846, 3320), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6196PolyExtStep::GetGlobal(0, 67), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6197PolyExtStep::Sub(549, 3321), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6198PolyExtStep::AndEqz(2847, 3322), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6199PolyExtStep::GetGlobal(0, 68), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6200PolyExtStep::Sub(570, 3323), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6201PolyExtStep::AndEqz(2848, 3324), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6202PolyExtStep::GetGlobal(0, 69), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6203PolyExtStep::Sub(571, 3325), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6204PolyExtStep::AndEqz(2849, 3326), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :180:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6205PolyExtStep::AndEqz(2850, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6206PolyExtStep::AndEqz(2851, 758), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6207PolyExtStep::AndEqz(2852, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6208PolyExtStep::AndEqz(2853, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6209PolyExtStep::AndEqz(2854, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6210PolyExtStep::AndEqz(2855, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6211PolyExtStep::AndEqz(2856, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6212PolyExtStep::AndEqz(2857, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6213PolyExtStep::AndEqz(2858, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6214PolyExtStep::AndEqz(2859, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6215PolyExtStep::AndEqz(2860, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6216PolyExtStep::AndEqz(2861, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6217PolyExtStep::AndEqz(2862, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6218PolyExtStep::AndEqz(2863, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6219PolyExtStep::AndEqz(2864, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6220PolyExtStep::AndEqz(2865, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6221PolyExtStep::AndEqz(2866, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6222PolyExtStep::AndEqz(2867, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6223PolyExtStep::AndEqz(2868, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6224PolyExtStep::AndEqz(2869, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6225PolyExtStep::AndEqz(2870, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6226PolyExtStep::AndEqz(2871, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6227PolyExtStep::AndEqz(2872, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6228PolyExtStep::AndEqz(2873, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6229PolyExtStep::AndEqz(2874, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6230PolyExtStep::AndEqz(2875, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6231PolyExtStep::AndEqz(2876, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6232PolyExtStep::AndEqz(2877, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6233PolyExtStep::AndEqz(2878, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6234PolyExtStep::AndEqz(2879, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6235PolyExtStep::AndEqz(2880, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6236PolyExtStep::AndEqz(2881, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6237PolyExtStep::AndCond(2777, 389, 2882), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6238PolyExtStep::AndEqz(0, 3055), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6239PolyExtStep::Sub(365, 1043), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :125:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6240PolyExtStep::AndEqz(2884, 3327), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :125:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6241PolyExtStep::Sub(371, 1046), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :126:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6242PolyExtStep::AndEqz(2885, 3328), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :126:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6243PolyExtStep::Add(1043, 1), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6244PolyExtStep::Add(1043, 7), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6245PolyExtStep::Add(1043, 6), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6246PolyExtStep::Add(1043, 5), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6247PolyExtStep::Add(1043, 4), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6248PolyExtStep::Add(1043, 3), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6249PolyExtStep::Add(1043, 2), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6250PolyExtStep::Add(1043, 12), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6251PolyExtStep::Add(1043, 11), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6252PolyExtStep::Add(1043, 10), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6253PolyExtStep::Add(1043, 9), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6254PolyExtStep::Add(1043, 8), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6255PolyExtStep::Add(1043, 34), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6256PolyExtStep::Add(1043, 35), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6257PolyExtStep::Add(1043, 36), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :131:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6258PolyExtStep::Add(1043, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :135:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6259PolyExtStep::Sub(3344, 33), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6260PolyExtStep::Sub(757, 1043), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6261PolyExtStep::AndEqz(0, 3346), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6262PolyExtStep::Sub(759, 3329), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6263PolyExtStep::AndEqz(2887, 3347), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6264PolyExtStep::Sub(761, 3330), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6265PolyExtStep::AndEqz(2888, 3348), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6266PolyExtStep::Sub(770, 3331), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6267PolyExtStep::AndEqz(2889, 3349), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6268PolyExtStep::Sub(752, 3332), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6269PolyExtStep::AndEqz(2890, 3350), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6270PolyExtStep::Sub(785, 3333), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6271PolyExtStep::AndEqz(2891, 3351), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6272PolyExtStep::Sub(791, 3334), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6273PolyExtStep::AndEqz(2892, 3352), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6274PolyExtStep::Sub(797, 3335), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6275PolyExtStep::AndEqz(2893, 3353), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6276PolyExtStep::Sub(803, 3336), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6277PolyExtStep::AndEqz(2894, 3354), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6278PolyExtStep::Sub(809, 3337), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6279PolyExtStep::AndEqz(2895, 3355), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6280PolyExtStep::Sub(815, 3338), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6281PolyExtStep::AndEqz(2896, 3356), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6282PolyExtStep::Sub(821, 3339), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6283PolyExtStep::AndEqz(2897, 3357), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6284PolyExtStep::Sub(827, 3340), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6285PolyExtStep::AndEqz(2898, 3358), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6286PolyExtStep::Sub(864, 3341), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6287PolyExtStep::AndEqz(2899, 3359), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6288PolyExtStep::Sub(870, 3342), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6289PolyExtStep::AndEqz(2900, 3360), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6290PolyExtStep::Sub(876, 3343), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6291PolyExtStep::AndEqz(2901, 3361), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :133:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6292PolyExtStep::AndEqz(2902, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6293PolyExtStep::Mul(3345, 1040), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6294PolyExtStep::Sub(3362, 1038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6295PolyExtStep::AndEqz(2903, 3363), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6296PolyExtStep::Mul(1037, 3345), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6297PolyExtStep::AndEqz(2904, 3364), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6298PolyExtStep::AndEqz(2905, 2652), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :136:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6299PolyExtStep::AndEqz(2906, 879), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6300PolyExtStep::AndEqz(2907, 885), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6301PolyExtStep::AndEqz(2908, 891), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6302PolyExtStep::AndEqz(2909, 897), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6303PolyExtStep::AndEqz(2910, 903), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6304PolyExtStep::AndEqz(2911, 940), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6305PolyExtStep::AndEqz(2912, 946), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6306PolyExtStep::AndEqz(2913, 952), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6307PolyExtStep::AndEqz(2914, 958), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6308PolyExtStep::AndEqz(2915, 964), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6309PolyExtStep::AndEqz(2916, 970), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6310PolyExtStep::AndEqz(2917, 976), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6311PolyExtStep::AndEqz(2918, 982), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6312PolyExtStep::AndEqz(2919, 1019), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6313PolyExtStep::AndEqz(2920, 1025), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6314PolyExtStep::AndEqz(2921, 1031), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6315PolyExtStep::AndCond(2886, 1046, 2922), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6316PolyExtStep::Sub(3344, 20), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6317PolyExtStep::Sub(882, 1043), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6318PolyExtStep::AndEqz(0, 3366), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6319PolyExtStep::Sub(888, 3329), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6320PolyExtStep::AndEqz(2924, 3367), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6321PolyExtStep::Sub(894, 3330), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6322PolyExtStep::AndEqz(2925, 3368), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6323PolyExtStep::Sub(900, 3331), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6324PolyExtStep::AndEqz(2926, 3369), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6325PolyExtStep::Sub(906, 3332), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6326PolyExtStep::AndEqz(2927, 3370), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6327PolyExtStep::Sub(943, 3333), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6328PolyExtStep::AndEqz(2928, 3371), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6329PolyExtStep::Sub(949, 3334), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6330PolyExtStep::AndEqz(2929, 3372), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6331PolyExtStep::Sub(955, 3335), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6332PolyExtStep::AndEqz(2930, 3373), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6333PolyExtStep::Sub(961, 3336), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6334PolyExtStep::AndEqz(2931, 3374), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6335PolyExtStep::Sub(967, 3337), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6336PolyExtStep::AndEqz(2932, 3375), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6337PolyExtStep::Sub(973, 3338), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6338PolyExtStep::AndEqz(2933, 3376), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6339PolyExtStep::Sub(979, 3339), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6340PolyExtStep::AndEqz(2934, 3377), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6341PolyExtStep::Sub(985, 3340), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6342PolyExtStep::AndEqz(2935, 3378), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6343PolyExtStep::Sub(1022, 3341), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6344PolyExtStep::AndEqz(2936, 3379), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6345PolyExtStep::Sub(1028, 3342), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6346PolyExtStep::AndEqz(2937, 3380), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6347PolyExtStep::Sub(1034, 3343), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6348PolyExtStep::AndEqz(2938, 3381), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6349PolyExtStep::AndEqz(2939, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6350PolyExtStep::Mul(3365, 1040), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6351PolyExtStep::Sub(3382, 1038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6352PolyExtStep::AndEqz(2940, 3383), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6353PolyExtStep::Mul(1037, 3365), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6354PolyExtStep::AndEqz(2941, 3384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6355PolyExtStep::AndEqz(2942, 2652), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :150:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6356PolyExtStep::AndEqz(2943, 756), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6357PolyExtStep::AndEqz(2944, 758), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6358PolyExtStep::AndEqz(2945, 760), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6359PolyExtStep::AndEqz(2946, 762), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6360PolyExtStep::AndEqz(2947, 771), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6361PolyExtStep::AndEqz(2948, 782), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6362PolyExtStep::AndEqz(2949, 788), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6363PolyExtStep::AndEqz(2950, 794), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6364PolyExtStep::AndEqz(2951, 800), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6365PolyExtStep::AndEqz(2952, 806), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6366PolyExtStep::AndEqz(2953, 812), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6367PolyExtStep::AndEqz(2954, 818), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6368PolyExtStep::AndEqz(2955, 824), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6369PolyExtStep::AndEqz(2956, 861), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6370PolyExtStep::AndEqz(2957, 867), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6371PolyExtStep::AndEqz(2958, 873), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6372PolyExtStep::AndCond(2923, 1047, 2959), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6373PolyExtStep::AndEqz(2960, 775), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6374PolyExtStep::AndEqz(2961, 1116), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6375PolyExtStep::AndEqz(2962, 1128), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6376PolyExtStep::AndEqz(2963, 1351), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6377PolyExtStep::AndEqz(2964, 1362), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6378PolyExtStep::AndEqz(2965, 1379), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6379PolyExtStep::AndEqz(2966, 1396), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6380PolyExtStep::AndEqz(2967, 1399), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6381PolyExtStep::AndEqz(2968, 1844), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6382PolyExtStep::AndEqz(2969, 590), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6383PolyExtStep::AndEqz(2970, 618), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6384PolyExtStep::AndEqz(2971, 645), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6385PolyExtStep::AndEqz(2972, 669), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6386PolyExtStep::AndEqz(2973, 552), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6387PolyExtStep::AndEqz(2974, 568), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6388PolyExtStep::AndEqz(2975, 572), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6389PolyExtStep::AndEqz(2976, 583), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6390PolyExtStep::AndEqz(2977, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6391PolyExtStep::AndEqz(2978, 733), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6392PolyExtStep::AndEqz(2979, 735), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6393PolyExtStep::AndEqz(2980, 737), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6394PolyExtStep::AndEqz(2981, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6395PolyExtStep::AndEqz(2982, 748), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6396PolyExtStep::AndEqz(2983, 755), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6397PolyExtStep::AndCond(2883, 392, 2984), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6398PolyExtStep::AndEqz(0, 3056), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6399PolyExtStep::Mul(496, 3277), // loc(callsite( builtin Mul at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :163:23) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6400PolyExtStep::Sub(1, 3385), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :163:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6401PolyExtStep::GetGlobal(0, 37), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :162:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6402PolyExtStep::Sub(359, 3387), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :165:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6403PolyExtStep::AndEqz(0, 585), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :165:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6404PolyExtStep::Sub(584, 3388), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :165:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6405PolyExtStep::AndEqz(2987, 3389), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :165:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6406PolyExtStep::AndCond(2986, 3385, 2988), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :163:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6407PolyExtStep::AndEqz(0, 583), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :163:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6408PolyExtStep::AndCond(2989, 3386, 2990), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :163:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :182:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6409PolyExtStep::AndEqz(2991, 775), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6410PolyExtStep::AndEqz(2992, 1116), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6411PolyExtStep::AndEqz(2993, 1128), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6412PolyExtStep::AndEqz(2994, 1351), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6413PolyExtStep::AndEqz(2995, 1362), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6414PolyExtStep::AndEqz(2996, 1379), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6415PolyExtStep::AndEqz(2997, 1396), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6416PolyExtStep::AndEqz(2998, 1399), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6417PolyExtStep::AndEqz(2999, 1844), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6418PolyExtStep::AndEqz(3000, 590), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6419PolyExtStep::AndEqz(3001, 618), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6420PolyExtStep::AndEqz(3002, 645), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6421PolyExtStep::AndEqz(3003, 669), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6422PolyExtStep::AndEqz(3004, 552), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6423PolyExtStep::AndEqz(3005, 568), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6424PolyExtStep::AndEqz(3006, 572), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6425PolyExtStep::AndEqz(3007, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6426PolyExtStep::AndEqz(3008, 733), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6427PolyExtStep::AndEqz(3009, 735), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6428PolyExtStep::AndEqz(3010, 737), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6429PolyExtStep::AndEqz(3011, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6430PolyExtStep::AndEqz(3012, 748), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6431PolyExtStep::AndEqz(3013, 755), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6432PolyExtStep::AndEqz(3014, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6433PolyExtStep::AndEqz(3015, 758), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6434PolyExtStep::AndEqz(3016, 760), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6435PolyExtStep::AndEqz(3017, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6436PolyExtStep::AndEqz(3018, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6437PolyExtStep::AndEqz(3019, 782), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6438PolyExtStep::AndEqz(3020, 788), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6439PolyExtStep::AndEqz(3021, 794), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6440PolyExtStep::AndEqz(3022, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6441PolyExtStep::AndEqz(3023, 806), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6442PolyExtStep::AndEqz(3024, 812), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6443PolyExtStep::AndEqz(3025, 818), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6444PolyExtStep::AndEqz(3026, 824), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6445PolyExtStep::AndEqz(3027, 861), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6446PolyExtStep::AndEqz(3028, 867), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6447PolyExtStep::AndEqz(3029, 873), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6448PolyExtStep::AndEqz(3030, 879), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6449PolyExtStep::AndEqz(3031, 885), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6450PolyExtStep::AndEqz(3032, 891), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6451PolyExtStep::AndEqz(3033, 897), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6452PolyExtStep::AndEqz(3034, 903), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6453PolyExtStep::AndEqz(3035, 940), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6454PolyExtStep::AndEqz(3036, 946), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6455PolyExtStep::AndEqz(3037, 952), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6456PolyExtStep::AndEqz(3038, 958), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6457PolyExtStep::AndEqz(3039, 964), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6458PolyExtStep::AndEqz(3040, 970), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6459PolyExtStep::AndEqz(3041, 976), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6460PolyExtStep::AndEqz(3042, 982), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6461PolyExtStep::AndEqz(3043, 1019), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6462PolyExtStep::AndEqz(3044, 1025), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6463PolyExtStep::AndEqz(3045, 1031), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6464PolyExtStep::AndCond(2985, 395, 3046), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6465PolyExtStep::AndCond(2187, 440, 3047), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
6466PolyExtStep::Sub(368, 11), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6467PolyExtStep::Sub(368, 10), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6468PolyExtStep::Sub(368, 9), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6469PolyExtStep::Sub(368, 8), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6470PolyExtStep::Sub(368, 34), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6471PolyExtStep::Mul(377, 5), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6472PolyExtStep::Mul(383, 13), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6473PolyExtStep::AndEqz(0, 2954), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6474PolyExtStep::Sub(570, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6475PolyExtStep::AndEqz(3049, 3397), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6476PolyExtStep::AndEqz(3050, 2062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6477PolyExtStep::AndEqz(3051, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6478PolyExtStep::Mul(572, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6479PolyExtStep::Add(3398, 571), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6480PolyExtStep::Sub(573, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6481PolyExtStep::AndEqz(3052, 3400), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6482PolyExtStep::Sub(574, 499), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6483PolyExtStep::AndEqz(3053, 3401), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6484PolyExtStep::AndEqz(3054, 2082), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6485PolyExtStep::Mul(367, 583), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6486PolyExtStep::Sub(3402, 2081), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6487PolyExtStep::AndEqz(3055, 3403), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6488PolyExtStep::Mul(575, 367), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6489PolyExtStep::AndEqz(3056, 3404), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6490PolyExtStep::Mul(575, 583), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6491PolyExtStep::AndEqz(3057, 3405), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6492PolyExtStep::AndEqz(3058, 575), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6493PolyExtStep::AndEqz(3059, 2966), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6494PolyExtStep::Mul(732, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6495PolyExtStep::Add(3406, 3399), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6496PolyExtStep::Sub(3407, 365), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6497PolyExtStep::AndEqz(3060, 3408), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6498PolyExtStep::Add(500, 732), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6499PolyExtStep::AndEqz(3061, 3399), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :203:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6500PolyExtStep::Sub(1105, 3409), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6501PolyExtStep::AndEqz(2312, 3410), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6502PolyExtStep::AndEqz(3063, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6503PolyExtStep::AndEqz(3064, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6504PolyExtStep::AndEqz(3065, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6505PolyExtStep::Sub(535, 3132), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6506PolyExtStep::AndEqz(3066, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6507PolyExtStep::AndEqz(3067, 494), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :27:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6508PolyExtStep::AndEqz(3068, 779), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :28:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6509PolyExtStep::AndEqz(3069, 3218), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :29:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6510PolyExtStep::AndEqz(3070, 3052), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :30:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6511PolyExtStep::AndEqz(3071, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6512PolyExtStep::AndEqz(3072, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6513PolyExtStep::AndEqz(3073, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6514PolyExtStep::AndEqz(3074, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6515PolyExtStep::Sub(1340, 52), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6516PolyExtStep::AndEqz(3075, 3412), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6517PolyExtStep::AndEqz(3076, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6518PolyExtStep::AndEqz(3077, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6519PolyExtStep::AndEqz(3078, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6520PolyExtStep::Sub(536, 3135), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6521PolyExtStep::AndEqz(3079, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6522PolyExtStep::AndEqz(3080, 1360), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :32:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6523PolyExtStep::AndEqz(3081, 2098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6524PolyExtStep::AndEqz(3082, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6525PolyExtStep::AndEqz(3083, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6526PolyExtStep::AndEqz(3084, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6527PolyExtStep::Sub(1, 736), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6528PolyExtStep::Mul(736, 3414), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6529PolyExtStep::AndEqz(3085, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6530PolyExtStep::AndEqz(3086, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6531PolyExtStep::Add(731, 733), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6532PolyExtStep::Add(3416, 734), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6533PolyExtStep::Add(3417, 735), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6534PolyExtStep::Add(3418, 736), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6535PolyExtStep::Add(3419, 737), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6536PolyExtStep::Sub(3420, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6537PolyExtStep::AndEqz(3087, 3421), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6538PolyExtStep::Mul(735, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6539PolyExtStep::Mul(736, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6540PolyExtStep::Mul(737, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6541PolyExtStep::Add(2973, 3422), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6542PolyExtStep::Add(3425, 3423), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6543PolyExtStep::Add(3426, 3424), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6544PolyExtStep::Sub(3427, 1359), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6545PolyExtStep::AndEqz(3088, 3428), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6546PolyExtStep::AndEqz(3089, 1362), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6547PolyExtStep::AndEqz(3090, 1379), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6548PolyExtStep::AndEqz(3091, 1396), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6549PolyExtStep::AndEqz(3092, 1399), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6550PolyExtStep::AndEqz(3093, 587), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6551PolyExtStep::AndEqz(3094, 597), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6552PolyExtStep::AndEqz(3095, 611), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6553PolyExtStep::AndEqz(3096, 625), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6554PolyExtStep::AndEqz(3097, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6555PolyExtStep::AndEqz(3098, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6556PolyExtStep::AndEqz(3099, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6557PolyExtStep::AndEqz(3100, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6558PolyExtStep::AndEqz(3101, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6559PolyExtStep::AndEqz(3102, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6560PolyExtStep::AndCond(3062, 374, 3103), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6561PolyExtStep::AndEqz(0, 3390), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6562PolyExtStep::AndEqz(3105, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6563PolyExtStep::AndEqz(3106, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6564PolyExtStep::AndEqz(3107, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6565PolyExtStep::AndEqz(3108, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6566PolyExtStep::Sub(1105, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6567PolyExtStep::AndEqz(3109, 3429), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6568PolyExtStep::AndEqz(3110, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6569PolyExtStep::AndEqz(3111, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6570PolyExtStep::AndEqz(3112, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6571PolyExtStep::AndEqz(3113, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6572PolyExtStep::AndEqz(3114, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6573PolyExtStep::AndEqz(3115, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6574PolyExtStep::AndEqz(3116, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6575PolyExtStep::AndEqz(3117, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6576PolyExtStep::Sub(1340, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6577PolyExtStep::AndEqz(3118, 3430), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6578PolyExtStep::AndEqz(3119, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6579PolyExtStep::AndEqz(3120, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6580PolyExtStep::AndEqz(3121, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6581PolyExtStep::AndEqz(3122, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6582PolyExtStep::Sub(1122, 3278), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6583PolyExtStep::AndEqz(3123, 3431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6584PolyExtStep::Sub(779, 3280), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6585PolyExtStep::AndEqz(3124, 3432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6586PolyExtStep::Sub(1359, 3282), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6587PolyExtStep::AndEqz(3125, 3433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6588PolyExtStep::Sub(1360, 3284), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6589PolyExtStep::AndEqz(3126, 3434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6590PolyExtStep::AndEqz(3127, 1362), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6591PolyExtStep::AndEqz(3128, 1379), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6592PolyExtStep::AndEqz(3129, 1396), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6593PolyExtStep::AndEqz(3130, 1399), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6594PolyExtStep::AndEqz(3131, 587), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6595PolyExtStep::AndEqz(3132, 597), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6596PolyExtStep::AndEqz(3133, 611), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6597PolyExtStep::AndEqz(3134, 625), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6598PolyExtStep::AndEqz(3135, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6599PolyExtStep::AndEqz(3136, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6600PolyExtStep::AndEqz(3137, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6601PolyExtStep::AndEqz(3138, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6602PolyExtStep::AndEqz(3139, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6603PolyExtStep::AndEqz(3140, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6604PolyExtStep::AndCond(3104, 377, 3141), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6605PolyExtStep::AndEqz(0, 3391), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6606PolyExtStep::AndEqz(3143, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6607PolyExtStep::AndEqz(3144, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6608PolyExtStep::AndEqz(3145, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6609PolyExtStep::AndEqz(3146, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6610PolyExtStep::AndEqz(3147, 3429), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6611PolyExtStep::AndEqz(3148, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6612PolyExtStep::AndEqz(3149, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6613PolyExtStep::AndEqz(3150, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6614PolyExtStep::AndEqz(3151, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6615PolyExtStep::AndEqz(3152, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6616PolyExtStep::AndEqz(3153, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6617PolyExtStep::AndEqz(3154, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6618PolyExtStep::AndEqz(3155, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6619PolyExtStep::AndEqz(3156, 3430), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6620PolyExtStep::AndEqz(3157, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6621PolyExtStep::AndEqz(3158, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6622PolyExtStep::AndEqz(3159, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6623PolyExtStep::AndEqz(3160, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6624PolyExtStep::AndEqz(3161, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6625PolyExtStep::AndEqz(3162, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6626PolyExtStep::AndEqz(3163, 3080), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6627PolyExtStep::AndEqz(3164, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6628PolyExtStep::Sub(1369, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6629PolyExtStep::AndEqz(3165, 3435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6630PolyExtStep::AndEqz(3166, 3082), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6631PolyExtStep::AndEqz(3167, 3083), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6632PolyExtStep::AndEqz(3168, 2209), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6633PolyExtStep::Sub(590, 3153), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6634PolyExtStep::AndEqz(3169, 3436), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6635PolyExtStep::AndEqz(3170, 1394), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :76:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6636PolyExtStep::AndEqz(3171, 2223), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6637PolyExtStep::Sub(1395, 618), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6638PolyExtStep::AndEqz(3172, 2224), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6639PolyExtStep::Sub(628, 3437), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6640PolyExtStep::AndEqz(3173, 3438), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6641PolyExtStep::AndEqz(3174, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6642PolyExtStep::AndEqz(3175, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6643PolyExtStep::AndEqz(3176, 3160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6644PolyExtStep::AndEqz(3177, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6645PolyExtStep::Sub(1773, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6646PolyExtStep::AndEqz(3178, 3439), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6647PolyExtStep::AndEqz(3179, 2222), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6648PolyExtStep::Sub(604, 3162), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6649PolyExtStep::AndEqz(3180, 3440), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6650PolyExtStep::Sub(1406, 618), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6651PolyExtStep::AndEqz(3181, 3441), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6652PolyExtStep::AndEqz(3182, 1407), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6653PolyExtStep::AndEqz(3183, 2225), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6654PolyExtStep::Add(1663, 731), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6655PolyExtStep::Sub(1359, 3442), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6656PolyExtStep::AndEqz(3184, 3443), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6657PolyExtStep::AndEqz(3185, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6658PolyExtStep::AndEqz(3186, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6659PolyExtStep::AndEqz(3187, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6660PolyExtStep::AndEqz(3188, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6661PolyExtStep::Add(733, 734), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6662PolyExtStep::Add(3444, 735), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6663PolyExtStep::Add(3445, 736), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6664PolyExtStep::Sub(3446, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6665PolyExtStep::AndEqz(3189, 3447), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6666PolyExtStep::Mul(735, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6667PolyExtStep::Mul(736, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6668PolyExtStep::Add(734, 3448), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6669PolyExtStep::Add(3450, 3449), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6670PolyExtStep::Sub(3451, 731), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6671PolyExtStep::AndEqz(3190, 3452), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6672PolyExtStep::AndEqz(3191, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6673PolyExtStep::Mul(642, 738), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6674PolyExtStep::Sub(3453, 2977), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6675PolyExtStep::AndEqz(3192, 3454), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6676PolyExtStep::Mul(737, 642), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6677PolyExtStep::AndEqz(3193, 3455), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6678PolyExtStep::AndEqz(3194, 2982), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6679PolyExtStep::Mul(737, 733), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6680PolyExtStep::Sub(3456, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6681PolyExtStep::AndEqz(3195, 3457), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6682PolyExtStep::Add(734, 735), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6683PolyExtStep::Add(3458, 736), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6684PolyExtStep::AndEqz(3196, 2226), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6685PolyExtStep::Mul(648, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6686PolyExtStep::Add(3460, 747), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6687PolyExtStep::Sub(618, 3461), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6688PolyExtStep::AndEqz(3197, 3462), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6689PolyExtStep::AndEqz(3198, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6690PolyExtStep::Sub(1, 729), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6691PolyExtStep::Mul(729, 3463), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6692PolyExtStep::AndEqz(3199, 3464), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6693PolyExtStep::Sub(1, 755), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6694PolyExtStep::Mul(755, 3465), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6695PolyExtStep::AndEqz(3200, 3466), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6696PolyExtStep::Sub(1, 754), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6697PolyExtStep::Mul(754, 3467), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
6698PolyExtStep::AndEqz(3201, 3468), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6699PolyExtStep::Add(748, 729), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6700PolyExtStep::Add(3469, 755), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6701PolyExtStep::Add(3470, 754), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6702PolyExtStep::Sub(3471, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6703PolyExtStep::AndEqz(3202, 3472), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6704PolyExtStep::Mul(755, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6705PolyExtStep::Mul(754, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6706PolyExtStep::Add(729, 3473), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6707PolyExtStep::Add(3475, 3474), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6708PolyExtStep::Sub(3476, 747), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6709PolyExtStep::AndEqz(3203, 3477), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6710PolyExtStep::Sub(1, 756), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6711PolyExtStep::Mul(756, 3478), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6712PolyExtStep::AndEqz(3204, 3479), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6713PolyExtStep::Mul(648, 757), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6714PolyExtStep::Sub(3480, 3478), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6715PolyExtStep::AndEqz(3205, 3481), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6716PolyExtStep::Mul(756, 648), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6717PolyExtStep::AndEqz(3206, 3482), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6718PolyExtStep::Mul(756, 757), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6719PolyExtStep::AndEqz(3207, 3483), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6720PolyExtStep::Mul(756, 748), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6721PolyExtStep::Sub(3484, 758), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6722PolyExtStep::AndEqz(3208, 3485), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6723PolyExtStep::Add(729, 755), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6724PolyExtStep::Add(3486, 754), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6725PolyExtStep::Mul(756, 3487), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6726PolyExtStep::Sub(3488, 759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6727PolyExtStep::AndEqz(3209, 3489), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6728PolyExtStep::Add(759, 3459), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6729PolyExtStep::Mul(759, 3459), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:51) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6730PolyExtStep::Sub(3490, 3491), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6731PolyExtStep::Sub(3492, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6732PolyExtStep::AndEqz(3210, 3493), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6733PolyExtStep::AndEqz(3211, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6734PolyExtStep::AndEqz(3212, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6735PolyExtStep::AndEqz(3213, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6736PolyExtStep::AndEqz(3214, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6737PolyExtStep::AndCond(3142, 380, 3215), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6738PolyExtStep::AndEqz(0, 3392), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6739PolyExtStep::AndEqz(3217, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6740PolyExtStep::AndEqz(3218, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6741PolyExtStep::AndEqz(3219, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6742PolyExtStep::AndEqz(3220, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6743PolyExtStep::AndEqz(3221, 3429), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6744PolyExtStep::AndEqz(3222, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6745PolyExtStep::AndEqz(3223, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6746PolyExtStep::AndEqz(3224, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6747PolyExtStep::AndEqz(3225, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6748PolyExtStep::AndEqz(3226, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6749PolyExtStep::AndEqz(3227, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6750PolyExtStep::AndEqz(3228, 3070), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6751PolyExtStep::AndEqz(3229, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6752PolyExtStep::AndEqz(3230, 3430), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6753PolyExtStep::AndEqz(3231, 3072), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6754PolyExtStep::AndEqz(3232, 3073), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6755PolyExtStep::AndEqz(3233, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6756PolyExtStep::AndEqz(3234, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6757PolyExtStep::AndEqz(3235, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6758PolyExtStep::AndEqz(3236, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6759PolyExtStep::AndEqz(3237, 3080), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6760PolyExtStep::AndEqz(3238, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6761PolyExtStep::AndEqz(3239, 3435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6762PolyExtStep::AndEqz(3240, 3082), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6763PolyExtStep::AndEqz(3241, 3083), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6764PolyExtStep::AndEqz(3242, 2209), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6765PolyExtStep::AndEqz(3243, 3436), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6766PolyExtStep::AndEqz(3244, 779), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :108:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6767PolyExtStep::AndEqz(3245, 1394), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :109:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6768PolyExtStep::AndEqz(3246, 2223), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :111:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6769PolyExtStep::AndEqz(3247, 2224), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6770PolyExtStep::AndEqz(3248, 3438), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6771PolyExtStep::AndEqz(3249, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6772PolyExtStep::AndEqz(3250, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6773PolyExtStep::AndEqz(3251, 3160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6774PolyExtStep::AndEqz(3252, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6775PolyExtStep::AndEqz(3253, 3439), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6776PolyExtStep::AndEqz(3254, 2222), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6777PolyExtStep::AndEqz(3255, 3440), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6778PolyExtStep::AndEqz(3256, 3441), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6779PolyExtStep::AndEqz(3257, 1407), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6780PolyExtStep::AndEqz(3258, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6781PolyExtStep::AndEqz(3259, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6782PolyExtStep::AndEqz(3260, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6783PolyExtStep::AndEqz(3261, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6784PolyExtStep::AndEqz(3262, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6785PolyExtStep::AndEqz(3263, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6786PolyExtStep::AndCond(3216, 383, 3264), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6787PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6788PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6789PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6790PolyExtStep::AndEqz(0, 3393), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6791PolyExtStep::Sub(3496, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6792PolyExtStep::AndEqz(3266, 2223), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6793PolyExtStep::Mul(618, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6794PolyExtStep::Add(3498, 731), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6795PolyExtStep::Sub(3497, 3499), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6796PolyExtStep::AndEqz(3267, 3500), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6797PolyExtStep::AndEqz(3268, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6798PolyExtStep::AndEqz(3269, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6799PolyExtStep::AndEqz(3270, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6800PolyExtStep::AndEqz(3271, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6801PolyExtStep::AndEqz(3272, 3447), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6802PolyExtStep::AndEqz(3273, 3452), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6803PolyExtStep::AndEqz(3274, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6804PolyExtStep::Mul(618, 738), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6805PolyExtStep::Sub(3501, 2977), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6806PolyExtStep::AndEqz(3275, 3502), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6807PolyExtStep::Mul(737, 618), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6808PolyExtStep::AndEqz(3276, 3503), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6809PolyExtStep::AndEqz(3277, 2982), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6810PolyExtStep::AndEqz(3278, 3457), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6811PolyExtStep::Mul(737, 3459), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6812PolyExtStep::Sub(3504, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6813PolyExtStep::AndEqz(3279, 3505), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6814PolyExtStep::Sub(3495, 6), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6815PolyExtStep::AndEqz(3280, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6816PolyExtStep::Mul(3506, 729), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6817PolyExtStep::Sub(3507, 2921), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6818PolyExtStep::AndEqz(3281, 3508), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6819PolyExtStep::Mul(748, 3506), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6820PolyExtStep::AndEqz(3282, 3509), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6821PolyExtStep::AndEqz(3283, 2926), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6822PolyExtStep::Add(747, 2921), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6823PolyExtStep::Mul(747, 2921), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:43) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6824PolyExtStep::Sub(3510, 3511), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6825PolyExtStep::Sub(3512, 755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6826PolyExtStep::AndEqz(3284, 3513), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6827PolyExtStep::AndEqz(3285, 3468), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6828PolyExtStep::Mul(3497, 756), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6829PolyExtStep::Sub(3514, 3467), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6830PolyExtStep::AndEqz(3286, 3515), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6831PolyExtStep::Mul(754, 3497), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6832PolyExtStep::AndEqz(3287, 3516), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6833PolyExtStep::Mul(754, 756), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6834PolyExtStep::AndEqz(3288, 3517), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6835PolyExtStep::Sub(1, 757), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6836PolyExtStep::Mul(757, 3518), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6837PolyExtStep::AndEqz(3289, 3519), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6838PolyExtStep::Sub(3495, 757), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6839PolyExtStep::Mul(3520, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6840PolyExtStep::Sub(1, 758), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6841PolyExtStep::Mul(758, 3522), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6842PolyExtStep::AndEqz(3290, 3523), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6843PolyExtStep::Sub(3521, 758), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6844PolyExtStep::AndEqz(3291, 3524), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6845PolyExtStep::AndEqz(3292, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6846PolyExtStep::AndEqz(3293, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6847PolyExtStep::AndEqz(3294, 3061), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6848PolyExtStep::AndEqz(3295, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6849PolyExtStep::Sub(1105, 3494), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6850PolyExtStep::AndEqz(3296, 3525), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6851PolyExtStep::AndEqz(3297, 3063), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6852PolyExtStep::AndEqz(3298, 3064), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6853PolyExtStep::AndEqz(3299, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6854PolyExtStep::AndEqz(3300, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6855PolyExtStep::AndEqz(3301, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6856PolyExtStep::AndEqz(3302, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6857PolyExtStep::AndEqz(3303, 3145), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6858PolyExtStep::AndEqz(3304, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6859PolyExtStep::Sub(1340, 3494), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6860PolyExtStep::AndEqz(3305, 3526), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6861PolyExtStep::AndEqz(3306, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6862PolyExtStep::AndEqz(3307, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6863PolyExtStep::Sub(1122, 1359), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6864PolyExtStep::AndEqz(0, 3527), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6865PolyExtStep::AndCond(3308, 758, 3309), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6866PolyExtStep::Sub(779, 1360), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6867PolyExtStep::AndEqz(0, 3528), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6868PolyExtStep::AndCond(3310, 3522, 3311), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6869PolyExtStep::Mul(758, 779), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6870PolyExtStep::Mul(3522, 1122), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6871PolyExtStep::Add(3529, 3530), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6872PolyExtStep::Mul(758, 1360), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6873PolyExtStep::Mul(3522, 1359), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:52) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6874PolyExtStep::Add(3532, 3533), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6875PolyExtStep::AndEqz(3312, 2249), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6876PolyExtStep::AndEqz(3313, 2275), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6877PolyExtStep::Add(1674, 662), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6878PolyExtStep::Sub(3531, 3535), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6879PolyExtStep::AndEqz(3314, 3536), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6880PolyExtStep::AndEqz(3315, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6881PolyExtStep::AndEqz(3316, 2846), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6882PolyExtStep::Mul(552, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6883PolyExtStep::Add(3537, 548), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6884PolyExtStep::Sub(3534, 3538), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6885PolyExtStep::AndEqz(3317, 3539), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6886PolyExtStep::Sub(662, 548), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6887PolyExtStep::AndEqz(0, 3540), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6888PolyExtStep::AndCond(3318, 757, 3319), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6889PolyExtStep::Sub(672, 552), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6890PolyExtStep::AndEqz(0, 3541), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6891PolyExtStep::AndCond(3320, 3518, 3321), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6892PolyExtStep::AndEqz(3322, 1362), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6893PolyExtStep::AndEqz(3323, 1379), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6894PolyExtStep::AndEqz(3324, 1396), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6895PolyExtStep::AndEqz(3325, 1399), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6896PolyExtStep::AndEqz(3326, 587), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6897PolyExtStep::AndEqz(3327, 597), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6898PolyExtStep::AndEqz(3328, 625), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6899PolyExtStep::AndEqz(3329, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6900PolyExtStep::AndEqz(3330, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6901PolyExtStep::AndCond(3265, 386, 3331), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6902PolyExtStep::AndEqz(0, 3394), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6903PolyExtStep::AndEqz(3333, 2223), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6904PolyExtStep::Sub(3496, 3499), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6905PolyExtStep::AndEqz(3334, 3542), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6906PolyExtStep::AndEqz(3335, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6907PolyExtStep::AndEqz(3336, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6908PolyExtStep::AndEqz(3337, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6909PolyExtStep::AndEqz(3338, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6910PolyExtStep::AndEqz(3339, 3447), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6911PolyExtStep::AndEqz(3340, 3452), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6912PolyExtStep::AndEqz(3341, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6913PolyExtStep::AndEqz(3342, 3502), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6914PolyExtStep::AndEqz(3343, 3503), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6915PolyExtStep::AndEqz(3344, 2982), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6916PolyExtStep::AndEqz(3345, 3457), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6917PolyExtStep::AndEqz(3346, 2224), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6918PolyExtStep::Add(686, 747), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6919PolyExtStep::Sub(618, 3543), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6920PolyExtStep::AndEqz(3347, 3544), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6921PolyExtStep::AndEqz(3348, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6922PolyExtStep::AndEqz(3349, 3464), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6923PolyExtStep::AndEqz(3350, 3466), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6924PolyExtStep::AndEqz(3351, 3468), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6925PolyExtStep::AndEqz(3352, 3472), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6926PolyExtStep::AndEqz(3353, 3477), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6927PolyExtStep::AndEqz(3354, 3479), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6928PolyExtStep::Mul(628, 757), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6929PolyExtStep::Sub(3545, 3478), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6930PolyExtStep::AndEqz(3355, 3546), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6931PolyExtStep::Mul(756, 628), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6932PolyExtStep::AndEqz(3356, 3547), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6933PolyExtStep::AndEqz(3357, 3483), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6934PolyExtStep::AndEqz(3358, 3485), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6935PolyExtStep::Add(3488, 3478), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6936PolyExtStep::Add(755, 754), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6937PolyExtStep::Mul(3549, 756), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6938PolyExtStep::Add(3550, 3478), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6939PolyExtStep::Add(3517, 3478), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6940PolyExtStep::Add(3548, 3551), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6941PolyExtStep::Add(3553, 3552), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6942PolyExtStep::Add(3554, 3478), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6943PolyExtStep::Mul(3548, 3494), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6944PolyExtStep::Sub(1, 3548), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6945PolyExtStep::Mul(3557, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6946PolyExtStep::Add(3556, 3558), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6947PolyExtStep::Sub(3559, 759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6948PolyExtStep::AndEqz(3359, 3560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6949PolyExtStep::AndEqz(3360, 3059), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6950PolyExtStep::AndEqz(3361, 3060), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6951PolyExtStep::AndEqz(3362, 3139), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6952PolyExtStep::AndEqz(3363, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6953PolyExtStep::Sub(1105, 759), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6954PolyExtStep::AndEqz(3364, 3561), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6955PolyExtStep::AndEqz(3365, 1845), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6956PolyExtStep::AndEqz(3366, 3411), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6957PolyExtStep::Add(3494, 1), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6958PolyExtStep::Mul(3551, 3562), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6959PolyExtStep::Sub(1, 3551), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6960PolyExtStep::Mul(3564, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6961PolyExtStep::Add(3563, 3565), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6962PolyExtStep::Sub(3566, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6963PolyExtStep::AndEqz(3367, 3567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6964PolyExtStep::AndEqz(3368, 3069), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6965PolyExtStep::AndEqz(3369, 1755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6966PolyExtStep::AndEqz(3370, 3145), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6967PolyExtStep::AndEqz(3371, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6968PolyExtStep::Sub(1340, 760), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6969PolyExtStep::AndEqz(3372, 3568), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6970PolyExtStep::AndEqz(3373, 2208), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6971PolyExtStep::AndEqz(3374, 3413), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6972PolyExtStep::Add(3494, 7), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6973PolyExtStep::Mul(3552, 3569), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6974PolyExtStep::Sub(1, 3552), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6975PolyExtStep::Mul(3571, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6976PolyExtStep::Add(3570, 3572), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6977PolyExtStep::Sub(3573, 761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6978PolyExtStep::AndEqz(3375, 3574), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6979PolyExtStep::AndEqz(3376, 3078), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6980PolyExtStep::AndEqz(3377, 3079), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6981PolyExtStep::AndEqz(3378, 3151), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6982PolyExtStep::AndEqz(3379, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6983PolyExtStep::Sub(1369, 761), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6984PolyExtStep::AndEqz(3380, 3575), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6985PolyExtStep::AndEqz(3381, 2209), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6986PolyExtStep::AndEqz(3382, 3436), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6987PolyExtStep::Add(3494, 6), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6988PolyExtStep::Mul(3478, 3576), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6989PolyExtStep::Sub(1, 3478), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6990PolyExtStep::Mul(3578, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6991PolyExtStep::Add(3577, 3579), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6992PolyExtStep::Sub(3580, 762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6993PolyExtStep::AndEqz(3383, 3581), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6994PolyExtStep::AndEqz(3384, 3088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6995PolyExtStep::AndEqz(3385, 1798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6996PolyExtStep::AndEqz(3386, 3160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6997PolyExtStep::AndEqz(3387, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6998PolyExtStep::Sub(1773, 762), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6999PolyExtStep::AndEqz(3388, 3582), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7000PolyExtStep::AndEqz(3389, 2222), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7001PolyExtStep::AndEqz(3390, 3440), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7002PolyExtStep::Sub(618, 3555), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:39) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7003PolyExtStep::Sub(1, 770), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7004PolyExtStep::Mul(770, 3584), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7005PolyExtStep::AndEqz(3391, 3585), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7006PolyExtStep::Mul(3583, 771), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7007PolyExtStep::Sub(3586, 3584), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7008PolyExtStep::AndEqz(3392, 3587), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7009PolyExtStep::Mul(770, 3583), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7010PolyExtStep::AndEqz(3393, 3588), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7011PolyExtStep::Mul(770, 771), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7012PolyExtStep::AndEqz(3394, 3589), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7013PolyExtStep::Sub(1, 3459), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7014PolyExtStep::Mul(770, 3590), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7015PolyExtStep::Sub(3591, 752), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7016PolyExtStep::AndEqz(3395, 3592), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7017PolyExtStep::AndEqz(3396, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7018PolyExtStep::AndEqz(3397, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7019PolyExtStep::AndEqz(3398, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7020PolyExtStep::AndEqz(3399, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7021PolyExtStep::AndEqz(3400, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7022PolyExtStep::AndEqz(3401, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7023PolyExtStep::AndCond(3332, 389, 3402), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7024PolyExtStep::AndEqz(1187, 1116), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7025PolyExtStep::AndEqz(3404, 1128), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7026PolyExtStep::AndEqz(3405, 1351), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7027PolyExtStep::AndEqz(3406, 1362), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7028PolyExtStep::AndEqz(3407, 1379), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7029PolyExtStep::AndEqz(3408, 1396), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7030PolyExtStep::AndEqz(3409, 1399), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7031PolyExtStep::AndEqz(3410, 1844), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7032PolyExtStep::AndEqz(3411, 2207), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7033PolyExtStep::AndEqz(3412, 587), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7034PolyExtStep::AndEqz(3413, 597), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7035PolyExtStep::AndEqz(3414, 611), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7036PolyExtStep::AndEqz(3415, 625), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7037PolyExtStep::AndEqz(3416, 635), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7038PolyExtStep::AndEqz(3417, 645), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7039PolyExtStep::AndEqz(3418, 655), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7040PolyExtStep::AndEqz(3419, 669), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7041PolyExtStep::AndEqz(3420, 541), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7042PolyExtStep::AndEqz(3421, 549), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7043PolyExtStep::AndCond(3403, 392, 3422), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7044PolyExtStep::AndCond(3423, 395, 3422), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7045PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7046PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7047PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7048PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7049PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7050PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7051PolyExtStep::Mul(3593, 11), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7052PolyExtStep::Mul(3594, 10), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7053PolyExtStep::Mul(3595, 9), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7054PolyExtStep::Mul(3596, 23), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7055PolyExtStep::Mul(3597, 24), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7056PolyExtStep::Mul(3598, 53), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7057PolyExtStep::Add(3599, 3600), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7058PolyExtStep::Add(3605, 3601), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7059PolyExtStep::Add(3606, 3602), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7060PolyExtStep::Add(3607, 3603), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7061PolyExtStep::Add(3608, 3604), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7062PolyExtStep::Mul(3609, 374), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7063PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7064PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7065PolyExtStep::Mul(3611, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7066PolyExtStep::Sub(1, 3611), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7067PolyExtStep::Mul(3614, 3612), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7068PolyExtStep::Mul(3615, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7069PolyExtStep::Add(3613, 3616), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7070PolyExtStep::Sub(1, 3612), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7071PolyExtStep::Mul(3614, 3618), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7072PolyExtStep::Mul(3619, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7073PolyExtStep::Add(3617, 3620), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:59) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7074PolyExtStep::Mul(3621, 380), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7075PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7076PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7077PolyExtStep::Mul(3624, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7078PolyExtStep::Sub(1, 3624), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7079PolyExtStep::Mul(3626, 3623), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7080PolyExtStep::Mul(3627, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7081PolyExtStep::Add(3625, 3628), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7082PolyExtStep::Sub(1, 3623), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7083PolyExtStep::Mul(3626, 3630), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7084PolyExtStep::Mul(3631, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:33) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7085PolyExtStep::Add(3629, 3632), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:50) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7086PolyExtStep::Mul(3633, 386), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7087PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7088PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7089PolyExtStep::Mul(3636, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7090PolyExtStep::Sub(1, 3636), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7091PolyExtStep::Mul(3638, 3635), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7092PolyExtStep::Mul(3639, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7093PolyExtStep::Add(3637, 3640), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7094PolyExtStep::Sub(1, 3635), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7095PolyExtStep::Mul(3638, 3642), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7096PolyExtStep::Mul(3643, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:41) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7097PolyExtStep::Add(3641, 3644), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:58) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7098PolyExtStep::Mul(3645, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7099PolyExtStep::Add(3610, 3395), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7100PolyExtStep::Add(3647, 3622), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7101PolyExtStep::Add(3648, 3396), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7102PolyExtStep::Add(3649, 3634), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7103PolyExtStep::Add(3650, 3646), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7104PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7105PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7106PolyExtStep::Mul(3652, 14), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7107PolyExtStep::Add(3654, 3653), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7108PolyExtStep::Mul(3655, 380), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7109PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7110PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7111PolyExtStep::Sub(1, 3658), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :128:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7112PolyExtStep::Add(3657, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7113PolyExtStep::Mul(3658, 3660), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7114PolyExtStep::Mul(3659, 3657), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:49) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7115PolyExtStep::Add(3661, 3662), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7116PolyExtStep::Mul(3663, 386), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7117PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7118PolyExtStep::Get(636), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7119PolyExtStep::Add(3665, 3623), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7120PolyExtStep::Add(3667, 3624), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7121PolyExtStep::Mul(3668, 3666), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:79) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7122PolyExtStep::Sub(1, 3666), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:108) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7123PolyExtStep::Add(3669, 3670), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7124PolyExtStep::Add(3623, 3624), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7125PolyExtStep::Mul(3672, 3666), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7126PolyExtStep::Add(3673, 3670), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7127PolyExtStep::Mul(3624, 3666), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7128PolyExtStep::Add(3675, 3670), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7129PolyExtStep::Add(3671, 3674), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7130PolyExtStep::Add(3677, 3676), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7131PolyExtStep::Add(3678, 3670), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7132PolyExtStep::Add(3657, 3679), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7133PolyExtStep::Mul(3680, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7134PolyExtStep::Add(3656, 3664), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7135PolyExtStep::Add(3682, 3681), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7136PolyExtStep::Mul(3593, 380), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7137PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7138PolyExtStep::Add(3685, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:36) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7139PolyExtStep::Mul(3659, 3686), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7140PolyExtStep::Mul(3687, 386), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7141PolyExtStep::Add(3684, 3688), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7142PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7143PolyExtStep::Mul(3690, 380), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7144PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7145PolyExtStep::Sub(3692, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :167:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7146PolyExtStep::Mul(3693, 386), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7147PolyExtStep::Mul(3679, 5), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7148PolyExtStep::Sub(3692, 3695), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7149PolyExtStep::Mul(3696, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7150PolyExtStep::Add(3691, 3694), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7151PolyExtStep::Add(3698, 3697), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7152PolyExtStep::Sub(3683, 553), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7153PolyExtStep::AndEqz(3424, 3700), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7154PolyExtStep::Sub(3689, 560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7155PolyExtStep::AndEqz(3425, 3701), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7156PolyExtStep::Sub(3699, 561), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7157PolyExtStep::AndEqz(3426, 3702), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7158PolyExtStep::Sub(3651, 5), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7159PolyExtStep::AndEqz(3427, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7160PolyExtStep::Mul(3703, 785), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7161PolyExtStep::Sub(3704, 783), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7162PolyExtStep::AndEqz(3428, 3705), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7163PolyExtStep::Mul(782, 3703), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7164PolyExtStep::AndEqz(3429, 3706), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7165PolyExtStep::AndEqz(3430, 1432), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7166PolyExtStep::Sub(3651, 13), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7167PolyExtStep::AndEqz(3431, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7168PolyExtStep::Mul(3707, 791), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7169PolyExtStep::Sub(3708, 789), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7170PolyExtStep::AndEqz(3432, 3709), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7171PolyExtStep::Mul(788, 3707), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7172PolyExtStep::AndEqz(3433, 3710), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7173PolyExtStep::AndEqz(3434, 1436), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7174PolyExtStep::Sub(3651, 23), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7175PolyExtStep::AndEqz(3435, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7176PolyExtStep::Mul(3711, 797), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7177PolyExtStep::Sub(3712, 795), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7178PolyExtStep::AndEqz(3436, 3713), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7179PolyExtStep::Mul(794, 3711), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7180PolyExtStep::AndEqz(3437, 3714), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7181PolyExtStep::Mul(794, 797), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7182PolyExtStep::AndEqz(3438, 3715), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7183PolyExtStep::Sub(3651, 24), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7184PolyExtStep::AndEqz(3439, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7185PolyExtStep::Mul(3716, 803), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7186PolyExtStep::Sub(3717, 801), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7187PolyExtStep::AndEqz(3440, 3718), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7188PolyExtStep::Mul(800, 3716), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7189PolyExtStep::AndEqz(3441, 3719), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7190PolyExtStep::Mul(800, 803), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7191PolyExtStep::AndEqz(3442, 3720), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7192PolyExtStep::Sub(3651, 53), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7193PolyExtStep::AndEqz(3443, 808), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7194PolyExtStep::Mul(3721, 809), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7195PolyExtStep::Sub(3722, 807), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7196PolyExtStep::AndEqz(3444, 3723), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7197PolyExtStep::Mul(806, 3721), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7198PolyExtStep::AndEqz(3445, 3724), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7199PolyExtStep::Mul(806, 809), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7200PolyExtStep::AndEqz(3446, 3725), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7201PolyExtStep::Add(782, 788), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7202PolyExtStep::Add(3726, 794), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:72) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7203PolyExtStep::Add(3727, 800), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:83) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7204PolyExtStep::Add(3728, 806), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:95) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7205PolyExtStep::Mul(3729, 5), // loc(callsite( builtin Mul at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:121) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7206PolyExtStep::Add(365, 3730), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7207PolyExtStep::Sub(812, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7208PolyExtStep::AndEqz(3447, 3732), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7209PolyExtStep::AndEqz(3448, 820), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7210PolyExtStep::Mul(818, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7211PolyExtStep::Add(3733, 815), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7212PolyExtStep::Sub(3731, 3734), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7213PolyExtStep::AndEqz(3449, 3735), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7214PolyExtStep::Add(367, 818), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7215PolyExtStep::Sub(821, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7216PolyExtStep::AndEqz(3450, 3737), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7217PolyExtStep::AndEqz(3451, 829), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7218PolyExtStep::Mul(827, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7219PolyExtStep::Add(3738, 824), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7220PolyExtStep::Sub(3736, 3739), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7221PolyExtStep::AndEqz(3452, 3740), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7222PolyExtStep::AndCond(3048, 443, 3453), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
7223PolyExtStep::Add(373, 23), // loc(callsite( builtin Add at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :468:42) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7224PolyExtStep::Sub(368, 3741), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :468:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7225PolyExtStep::Mul(371, 56), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :110:15) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7226PolyExtStep::Mul(3743, 55), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7227PolyExtStep::Sub(1, 3743), // loc(callsite( builtin Sub at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:46) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7228PolyExtStep::Mul(3745, 54), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:57) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7229PolyExtStep::Add(3744, 3746), // loc(callsite( builtin Add at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:32) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7230PolyExtStep::Sub(2666, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :467:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7231PolyExtStep::AndEqz(0, 3748), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :467:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7232PolyExtStep::Sub(2672, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :467:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7233PolyExtStep::AndEqz(3455, 3749), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :467:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7234PolyExtStep::AndEqz(3456, 3742), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :468:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7235PolyExtStep::Get(781), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7236PolyExtStep::Get(782), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7237PolyExtStep::Sub(1, 3750), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7238PolyExtStep::Mul(3750, 3752), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7239PolyExtStep::AndEqz(0, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7240PolyExtStep::Mul(3051, 3751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7241PolyExtStep::Sub(3754, 3752), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7242PolyExtStep::AndEqz(3458, 3755), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7243PolyExtStep::Mul(3750, 3051), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7244PolyExtStep::AndEqz(3459, 3756), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7245PolyExtStep::Mul(3750, 3751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7246PolyExtStep::AndEqz(3460, 3757), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7247PolyExtStep::Sub(0, 775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7248PolyExtStep::AndEqz(0, 3758), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7249PolyExtStep::Sub(0, 1105), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7250PolyExtStep::AndEqz(3462, 3759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7251PolyExtStep::Sub(3747, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7252PolyExtStep::AndEqz(3463, 3760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7253PolyExtStep::Sub(1, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7254PolyExtStep::AndEqz(3464, 3761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7255PolyExtStep::Sub(1, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7256PolyExtStep::AndEqz(3465, 3762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7257PolyExtStep::Sub(1, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7258PolyExtStep::AndEqz(3466, 3763), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7259PolyExtStep::Sub(57, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7260PolyExtStep::AndEqz(3467, 3764), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7261PolyExtStep::Sub(0, 1122), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7262PolyExtStep::AndEqz(3468, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7263PolyExtStep::Sub(0, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7264PolyExtStep::AndEqz(3469, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7265PolyExtStep::Sub(0, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7266PolyExtStep::AndEqz(3470, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7267PolyExtStep::Sub(371, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7268PolyExtStep::AndEqz(3471, 3768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7269PolyExtStep::Sub(0, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7270PolyExtStep::AndEqz(3472, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7271PolyExtStep::Sub(0, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7272PolyExtStep::AndEqz(3473, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7273PolyExtStep::Sub(0, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7274PolyExtStep::AndEqz(3474, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7275PolyExtStep::Sub(0, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7276PolyExtStep::AndEqz(3475, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7277PolyExtStep::Sub(0, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7278PolyExtStep::AndEqz(3476, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7279PolyExtStep::Sub(0, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7280PolyExtStep::AndEqz(3477, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7281PolyExtStep::Sub(0, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7282PolyExtStep::AndEqz(3478, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7283PolyExtStep::Sub(0, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7284PolyExtStep::AndEqz(3479, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7285PolyExtStep::Sub(0, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7286PolyExtStep::AndEqz(3480, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7287PolyExtStep::Sub(0, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7288PolyExtStep::AndEqz(3481, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7289PolyExtStep::Sub(0, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7290PolyExtStep::AndEqz(3482, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7291PolyExtStep::Sub(0, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7292PolyExtStep::AndEqz(3483, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7293PolyExtStep::Sub(0, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7294PolyExtStep::AndEqz(3484, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7295PolyExtStep::Sub(0, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7296PolyExtStep::AndEqz(3485, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7297PolyExtStep::Sub(0, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7298PolyExtStep::AndEqz(3486, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7299PolyExtStep::Sub(0, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7300PolyExtStep::AndEqz(3487, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7301PolyExtStep::Sub(0, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7302PolyExtStep::AndEqz(3488, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7303PolyExtStep::Sub(0, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7304PolyExtStep::AndEqz(3489, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7305PolyExtStep::Sub(0, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7306PolyExtStep::AndEqz(3490, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7307PolyExtStep::Sub(0, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7308PolyExtStep::AndEqz(3491, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7309PolyExtStep::Sub(0, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7310PolyExtStep::AndEqz(3492, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7311PolyExtStep::Sub(0, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7312PolyExtStep::AndEqz(3493, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7313PolyExtStep::Sub(0, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7314PolyExtStep::AndEqz(3494, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7315PolyExtStep::Sub(0, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7316PolyExtStep::AndEqz(3495, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7317PolyExtStep::Mul(2207, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7318PolyExtStep::Add(535, 3793), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7319PolyExtStep::Mul(3794, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7320PolyExtStep::Add(1844, 3795), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7321PolyExtStep::Mul(3796, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7322PolyExtStep::Add(1407, 3797), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7323PolyExtStep::Sub(3798, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7324PolyExtStep::AndEqz(3496, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7325PolyExtStep::AndEqz(3497, 536), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7326PolyExtStep::AndEqz(3498, 611), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7327PolyExtStep::AndEqz(3499, 635), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7328PolyExtStep::AndEqz(3500, 662), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7329PolyExtStep::AndEqz(3501, 548), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7330PolyExtStep::AndEqz(3502, 561), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7331PolyExtStep::AndEqz(3503, 570), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7332PolyExtStep::AndEqz(3504, 575), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7333PolyExtStep::AndEqz(3505, 821), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7334PolyExtStep::AndEqz(3506, 827), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7335PolyExtStep::AndEqz(3507, 864), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7336PolyExtStep::AndEqz(3508, 870), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7337PolyExtStep::AndCond(3461, 3750, 3509), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7338PolyExtStep::Sub(536, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7339PolyExtStep::AndEqz(0, 3800), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7340PolyExtStep::AndEqz(3511, 2223), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7341PolyExtStep::Sub(618, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7342PolyExtStep::AndEqz(3512, 3801), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7343PolyExtStep::AndEqz(3513, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7344PolyExtStep::Sub(587, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7345PolyExtStep::AndEqz(3514, 3802), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7346PolyExtStep::Sub(597, 625), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7347PolyExtStep::AndEqz(3515, 3803), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7348PolyExtStep::Sub(604, 628), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7349PolyExtStep::AndEqz(3516, 3804), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7350PolyExtStep::Sub(618, 590), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7351PolyExtStep::AndEqz(3517, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7352PolyExtStep::Sub(824, 3805), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7353PolyExtStep::AndEqz(3518, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7354PolyExtStep::Mul(628, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7355PolyExtStep::Mul(625, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7356PolyExtStep::Add(3807, 3808), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7357PolyExtStep::Sub(635, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7358PolyExtStep::AndEqz(3519, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7359PolyExtStep::Sub(662, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7360PolyExtStep::AndEqz(3520, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7361PolyExtStep::Sub(669, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7362PolyExtStep::AndEqz(3521, 3812), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7363PolyExtStep::AndEqz(3522, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7364PolyExtStep::Sub(642, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7365PolyExtStep::AndEqz(3523, 3813), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7366PolyExtStep::Sub(648, 672), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7367PolyExtStep::AndEqz(3524, 3814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7368PolyExtStep::Sub(655, 541), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7369PolyExtStep::AndEqz(3525, 3815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7370PolyExtStep::Sub(669, 645), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7371PolyExtStep::AndEqz(3526, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7372PolyExtStep::Sub(861, 3816), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7373PolyExtStep::AndEqz(3527, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7374PolyExtStep::Mul(541, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7375PolyExtStep::Mul(672, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7376PolyExtStep::Add(3818, 3819), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7377PolyExtStep::Sub(548, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7378PolyExtStep::AndEqz(3528, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7379PolyExtStep::Sub(561, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7380PolyExtStep::AndEqz(3529, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7381PolyExtStep::Sub(568, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7382PolyExtStep::AndEqz(3530, 3823), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7383PolyExtStep::AndEqz(3531, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7384PolyExtStep::Sub(549, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7385PolyExtStep::AndEqz(3532, 3824), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7386PolyExtStep::Sub(553, 567), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7387PolyExtStep::AndEqz(3533, 3825), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7388PolyExtStep::AndEqz(3534, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7389PolyExtStep::Sub(568, 552), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7390PolyExtStep::Sub(864, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7391PolyExtStep::AndEqz(3535, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7392PolyExtStep::Sub(867, 3826), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7393PolyExtStep::AndEqz(3536, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7394PolyExtStep::Mul(569, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7395PolyExtStep::Mul(567, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7396PolyExtStep::Add(3829, 3830), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7397PolyExtStep::AndEqz(3537, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7398PolyExtStep::Sub(575, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7399PolyExtStep::AndEqz(3538, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7400PolyExtStep::Sub(583, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7401PolyExtStep::AndEqz(3539, 3833), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7402PolyExtStep::AndEqz(3540, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7403PolyExtStep::Sub(571, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7404PolyExtStep::AndEqz(3541, 3834), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7405PolyExtStep::AndEqz(3542, 1624), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7406PolyExtStep::Sub(574, 732), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7407PolyExtStep::AndEqz(3543, 3835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7408PolyExtStep::Sub(583, 572), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7409PolyExtStep::AndEqz(3544, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7410PolyExtStep::Sub(873, 3836), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7411PolyExtStep::AndEqz(3545, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7412PolyExtStep::Sub(1, 2673), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7413PolyExtStep::Mul(2673, 3838), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7414PolyExtStep::AndEqz(3546, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7415PolyExtStep::Mul(3809, 2675), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7416PolyExtStep::Sub(3840, 3838), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7417PolyExtStep::AndEqz(3547, 3841), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7418PolyExtStep::Mul(2673, 3809), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7419PolyExtStep::AndEqz(3548, 3842), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7420PolyExtStep::Mul(2673, 2675), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7421PolyExtStep::AndEqz(3549, 3843), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7422PolyExtStep::Sub(1, 2682), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7423PolyExtStep::Mul(2682, 3844), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7424PolyExtStep::AndEqz(3550, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7425PolyExtStep::Sub(1, 2683), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7426PolyExtStep::Mul(2683, 3846), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7427PolyExtStep::AndEqz(3551, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7428PolyExtStep::Mul(2682, 29), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7429PolyExtStep::Mul(2683, 14), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:42) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7430PolyExtStep::Add(3848, 3849), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:33) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7431PolyExtStep::Sub(732, 3850), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7432PolyExtStep::AndEqz(3552, 3851), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7433PolyExtStep::Get(780), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7434PolyExtStep::AndEqz(3553, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7435PolyExtStep::Mul(584, 3852), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7436PolyExtStep::Sub(3853, 2686), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7437PolyExtStep::AndEqz(3554, 3854), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7438PolyExtStep::Mul(2685, 584), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7439PolyExtStep::AndEqz(3555, 3855), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7440PolyExtStep::Mul(2685, 3852), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7441PolyExtStep::AndEqz(3556, 3856), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7442PolyExtStep::Mul(2685, 13), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:6) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7443PolyExtStep::Mul(2686, 3838), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7444PolyExtStep::Mul(3858, 59), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7445PolyExtStep::Add(3857, 3859), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7446PolyExtStep::Sub(1, 3838), // loc(callsite( builtin Sub at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7447PolyExtStep::Mul(2686, 3861), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7448PolyExtStep::Mul(3862, 60), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:37) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7449PolyExtStep::Add(3860, 3863), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:58) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7450PolyExtStep::Sub(3838, 775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7451PolyExtStep::AndEqz(3557, 3865), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7452PolyExtStep::Sub(3809, 1105), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7453PolyExtStep::AndEqz(3558, 3866), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7454PolyExtStep::Sub(3831, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7455PolyExtStep::AndEqz(3559, 3867), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7456PolyExtStep::Sub(2682, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7457PolyExtStep::AndEqz(3560, 3868), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7458PolyExtStep::Sub(2683, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7459PolyExtStep::AndEqz(3561, 3869), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7460PolyExtStep::Sub(0, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7461PolyExtStep::AndEqz(3562, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7462PolyExtStep::Sub(3864, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7463PolyExtStep::AndEqz(3563, 3871), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7464PolyExtStep::AndEqz(3564, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7465PolyExtStep::Sub(3820, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7466PolyExtStep::AndEqz(3565, 3872), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7467PolyExtStep::Sub(584, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7468PolyExtStep::AndEqz(3566, 3873), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7469PolyExtStep::AndEqz(3567, 3768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7470PolyExtStep::AndEqz(3568, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7471PolyExtStep::AndEqz(3569, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7472PolyExtStep::AndEqz(3570, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7473PolyExtStep::AndEqz(3571, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7474PolyExtStep::AndEqz(3572, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7475PolyExtStep::AndEqz(3573, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7476PolyExtStep::AndEqz(3574, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7477PolyExtStep::AndEqz(3575, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7478PolyExtStep::AndEqz(3576, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7479PolyExtStep::AndEqz(3577, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7480PolyExtStep::AndEqz(3578, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7481PolyExtStep::AndEqz(3579, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7482PolyExtStep::AndEqz(3580, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7483PolyExtStep::AndEqz(3581, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7484PolyExtStep::AndEqz(3582, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7485PolyExtStep::AndEqz(3583, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7486PolyExtStep::AndEqz(3584, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7487PolyExtStep::AndEqz(3585, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7488PolyExtStep::AndEqz(3586, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7489PolyExtStep::AndEqz(3587, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7490PolyExtStep::AndEqz(3588, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7491PolyExtStep::AndEqz(3589, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7492PolyExtStep::AndEqz(3590, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7493PolyExtStep::AndEqz(3591, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7494PolyExtStep::AndEqz(3592, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7495PolyExtStep::AndCond(3510, 3752, 3593), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :471:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7496PolyExtStep::AndEqz(3594, 731), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7497PolyExtStep::AndEqz(3595, 737), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7498PolyExtStep::AndEqz(3596, 748), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7499PolyExtStep::AndEqz(3597, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7500PolyExtStep::AndEqz(3598, 761), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7501PolyExtStep::AndEqz(3599, 782), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7502PolyExtStep::AndEqz(3600, 794), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7503PolyExtStep::AndEqz(3601, 809), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7504PolyExtStep::AndEqz(3602, 876), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7505PolyExtStep::AndEqz(3603, 882), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7506PolyExtStep::AndEqz(3604, 888), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7507PolyExtStep::AndEqz(3605, 894), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7508PolyExtStep::AndEqz(3606, 900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7509PolyExtStep::AndEqz(3607, 903), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7510PolyExtStep::AndEqz(3608, 906), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7511PolyExtStep::AndEqz(3609, 943), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7512PolyExtStep::AndEqz(3610, 946), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7513PolyExtStep::AndEqz(3611, 949), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7514PolyExtStep::AndEqz(3612, 955), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7515PolyExtStep::AndEqz(3613, 958), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7516PolyExtStep::AndEqz(3614, 961), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7517PolyExtStep::AndEqz(3615, 967), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7518PolyExtStep::AndEqz(3616, 970), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7519PolyExtStep::AndEqz(3617, 973), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7520PolyExtStep::AndEqz(3618, 979), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7521PolyExtStep::AndEqz(3619, 982), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7522PolyExtStep::AndEqz(3620, 985), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7523PolyExtStep::AndEqz(3621, 1022), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7524PolyExtStep::AndEqz(3622, 1025), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7525PolyExtStep::AndEqz(3623, 1028), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7526PolyExtStep::AndEqz(3624, 1034), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7527PolyExtStep::AndEqz(3625, 1037), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7528PolyExtStep::AndEqz(3626, 1040), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7529PolyExtStep::AndEqz(3627, 1046), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7530PolyExtStep::AndEqz(3628, 1049), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7531PolyExtStep::AndEqz(3629, 1052), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7532PolyExtStep::AndEqz(3630, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7533PolyExtStep::AndEqz(3631, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7534PolyExtStep::AndCond(3457, 374, 3632), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7535PolyExtStep::Get(155), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7536PolyExtStep::Get(157), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7537PolyExtStep::Get(159), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7538PolyExtStep::Get(161), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7539PolyExtStep::Get(163), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7540PolyExtStep::Get(165), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7541PolyExtStep::Get(174), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7542PolyExtStep::Get(180), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7543PolyExtStep::Get(186), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7544PolyExtStep::Sub(587, 3875), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7545PolyExtStep::AndEqz(3514, 3883), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7546PolyExtStep::AndEqz(3634, 3803), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7547PolyExtStep::AndEqz(3635, 3804), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7548PolyExtStep::AndEqz(3636, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7549PolyExtStep::AndEqz(3637, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7550PolyExtStep::Mul(628, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7551PolyExtStep::Add(3884, 625), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7552PolyExtStep::Add(3875, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7553PolyExtStep::AndEqz(3638, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7554PolyExtStep::AndEqz(3639, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7555PolyExtStep::AndEqz(3640, 3812), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7556PolyExtStep::AndEqz(3641, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7557PolyExtStep::Sub(642, 3886), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7558PolyExtStep::AndEqz(3642, 3887), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7559PolyExtStep::AndEqz(3643, 3814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7560PolyExtStep::AndEqz(3644, 3815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7561PolyExtStep::AndEqz(3645, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7562PolyExtStep::AndEqz(3646, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7563PolyExtStep::Mul(541, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7564PolyExtStep::Add(3888, 672), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7565PolyExtStep::Add(3875, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7566PolyExtStep::AndEqz(3647, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7567PolyExtStep::AndEqz(3648, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7568PolyExtStep::AndEqz(3649, 3823), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7569PolyExtStep::AndEqz(3650, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7570PolyExtStep::Sub(549, 3890), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7571PolyExtStep::AndEqz(3651, 3891), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7572PolyExtStep::AndEqz(3652, 3825), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7573PolyExtStep::AndEqz(3653, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7574PolyExtStep::AndEqz(3654, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7575PolyExtStep::AndEqz(3655, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7576PolyExtStep::Mul(569, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7577PolyExtStep::Add(3892, 567), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7578PolyExtStep::Add(3875, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7579PolyExtStep::AndEqz(3656, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7580PolyExtStep::AndEqz(3657, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7581PolyExtStep::AndEqz(3658, 3833), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7582PolyExtStep::AndEqz(3659, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7583PolyExtStep::Sub(571, 3894), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7584PolyExtStep::AndEqz(3660, 3895), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7585PolyExtStep::AndEqz(3661, 1624), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7586PolyExtStep::AndEqz(3662, 3835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7587PolyExtStep::AndEqz(3663, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7588PolyExtStep::AndEqz(3664, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7589PolyExtStep::Mul(732, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7590PolyExtStep::Add(3896, 584), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7591PolyExtStep::Add(3875, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7592PolyExtStep::AndEqz(3665, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7593PolyExtStep::AndEqz(3666, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7594PolyExtStep::Sub(738, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7595PolyExtStep::AndEqz(3667, 3899), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7596PolyExtStep::AndEqz(3668, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7597PolyExtStep::Sub(733, 3898), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7598PolyExtStep::AndEqz(3669, 3900), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7599PolyExtStep::AndEqz(3670, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7600PolyExtStep::AndEqz(3671, 1706), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7601PolyExtStep::Sub(738, 734), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7602PolyExtStep::Sub(876, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7603PolyExtStep::AndEqz(3672, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7604PolyExtStep::Sub(879, 3901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7605PolyExtStep::AndEqz(3673, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7606PolyExtStep::Mul(747, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7607PolyExtStep::Add(3904, 739), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7608PolyExtStep::Add(3875, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7609PolyExtStep::Sub(748, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7610PolyExtStep::AndEqz(3674, 3907), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7611PolyExtStep::AndEqz(3675, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7612PolyExtStep::AndEqz(3676, 2991), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7613PolyExtStep::AndEqz(3677, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7614PolyExtStep::Sub(729, 3906), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7615PolyExtStep::AndEqz(3678, 3908), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7616PolyExtStep::AndEqz(3679, 2993), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7617PolyExtStep::AndEqz(3680, 2031), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7618PolyExtStep::Sub(882, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7619PolyExtStep::AndEqz(3681, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7620PolyExtStep::Sub(885, 2994), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7621PolyExtStep::AndEqz(3682, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7622PolyExtStep::Mul(760, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7623PolyExtStep::Add(3911, 759), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7624PolyExtStep::Add(3875, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7625PolyExtStep::Sub(761, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7626PolyExtStep::AndEqz(3683, 3914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7627PolyExtStep::AndEqz(3684, 2942), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7628PolyExtStep::Sub(785, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7629PolyExtStep::AndEqz(3685, 3915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7630PolyExtStep::AndEqz(3686, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7631PolyExtStep::Sub(762, 3913), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7632PolyExtStep::AndEqz(3687, 3916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7633PolyExtStep::Sub(771, 788), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7634PolyExtStep::AndEqz(3688, 3917), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7635PolyExtStep::Sub(752, 791), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7636PolyExtStep::AndEqz(3689, 3918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7637PolyExtStep::Sub(785, 770), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7638PolyExtStep::Sub(888, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7639PolyExtStep::AndEqz(3690, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7640PolyExtStep::Sub(891, 3919), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7641PolyExtStep::AndEqz(3691, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7642PolyExtStep::Mul(791, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7643PolyExtStep::Add(3922, 788), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7644PolyExtStep::Add(3875, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7645PolyExtStep::Sub(794, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7646PolyExtStep::AndEqz(3692, 3925), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7647PolyExtStep::Sub(809, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7648PolyExtStep::AndEqz(3693, 3926), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7649PolyExtStep::Sub(812, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7650PolyExtStep::AndEqz(3694, 3927), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7651PolyExtStep::AndEqz(3695, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7652PolyExtStep::Sub(797, 3924), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7653PolyExtStep::AndEqz(3696, 3928), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7654PolyExtStep::Sub(803, 815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7655PolyExtStep::AndEqz(3697, 3929), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7656PolyExtStep::Sub(806, 818), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7657PolyExtStep::AndEqz(3698, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7658PolyExtStep::Sub(812, 800), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7659PolyExtStep::Sub(894, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7660PolyExtStep::AndEqz(3699, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7661PolyExtStep::Sub(897, 3931), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7662PolyExtStep::AndEqz(3700, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7663PolyExtStep::Sub(3874, 775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7664PolyExtStep::AndEqz(3701, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7665PolyExtStep::Sub(3875, 1105), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7666PolyExtStep::AndEqz(3702, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7667PolyExtStep::Sub(3876, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7668PolyExtStep::AndEqz(3703, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7669PolyExtStep::Sub(3877, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7670PolyExtStep::AndEqz(3704, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7671PolyExtStep::Sub(3878, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7672PolyExtStep::AndEqz(3705, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7673PolyExtStep::Sub(3879, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7674PolyExtStep::AndEqz(3706, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7675PolyExtStep::Sub(60, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7676PolyExtStep::AndEqz(3707, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7677PolyExtStep::AndEqz(3708, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7678PolyExtStep::Sub(3880, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7679PolyExtStep::AndEqz(3709, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7680PolyExtStep::Sub(3881, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7681PolyExtStep::AndEqz(3710, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7682PolyExtStep::Sub(3882, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7683PolyExtStep::AndEqz(3711, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7684PolyExtStep::AndEqz(3712, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7685PolyExtStep::AndEqz(3713, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7686PolyExtStep::AndEqz(3714, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7687PolyExtStep::AndEqz(3715, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7688PolyExtStep::AndEqz(3716, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7689PolyExtStep::AndEqz(3717, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7690PolyExtStep::AndEqz(3718, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7691PolyExtStep::AndEqz(3719, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7692PolyExtStep::AndEqz(3720, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7693PolyExtStep::AndEqz(3721, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7694PolyExtStep::AndEqz(3722, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7695PolyExtStep::AndEqz(3723, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7696PolyExtStep::AndEqz(3724, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7697PolyExtStep::AndEqz(3725, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7698PolyExtStep::AndEqz(3726, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7699PolyExtStep::AndEqz(3727, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7700PolyExtStep::Sub(3885, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7701PolyExtStep::AndEqz(3728, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7702PolyExtStep::Sub(3889, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7703PolyExtStep::AndEqz(3729, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7704PolyExtStep::Sub(3893, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7705PolyExtStep::AndEqz(3730, 3946), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7706PolyExtStep::Sub(3897, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7707PolyExtStep::AndEqz(3731, 3947), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7708PolyExtStep::Sub(3905, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7709PolyExtStep::AndEqz(3732, 3948), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7710PolyExtStep::Sub(3912, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7711PolyExtStep::AndEqz(3733, 3949), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7712PolyExtStep::Sub(3923, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7713PolyExtStep::AndEqz(3734, 3950), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7714PolyExtStep::Sub(3734, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7715PolyExtStep::AndEqz(3735, 3951), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7716PolyExtStep::AndEqz(3736, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7717PolyExtStep::AndEqz(3737, 900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7718PolyExtStep::AndEqz(3738, 903), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7719PolyExtStep::AndEqz(3739, 906), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7720PolyExtStep::AndEqz(3740, 943), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7721PolyExtStep::AndEqz(3741, 946), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7722PolyExtStep::AndEqz(3742, 949), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7723PolyExtStep::AndEqz(3743, 955), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7724PolyExtStep::AndEqz(3744, 958), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7725PolyExtStep::AndEqz(3745, 961), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7726PolyExtStep::AndEqz(3746, 967), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7727PolyExtStep::AndEqz(3747, 970), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7728PolyExtStep::AndEqz(3748, 973), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7729PolyExtStep::AndEqz(3749, 979), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7730PolyExtStep::AndEqz(3750, 982), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7731PolyExtStep::AndEqz(3751, 985), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7732PolyExtStep::AndEqz(3752, 1022), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7733PolyExtStep::AndEqz(3753, 1025), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7734PolyExtStep::AndEqz(3754, 1028), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7735PolyExtStep::AndEqz(3755, 1034), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7736PolyExtStep::AndEqz(3756, 1037), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7737PolyExtStep::AndEqz(3757, 1040), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7738PolyExtStep::AndEqz(3758, 1046), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7739PolyExtStep::AndEqz(3759, 1049), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7740PolyExtStep::AndEqz(3760, 1052), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7741PolyExtStep::AndEqz(3761, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7742PolyExtStep::AndEqz(3762, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7743PolyExtStep::AndCond(3633, 377, 3763), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7744PolyExtStep::Get(168), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7745PolyExtStep::Get(192), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7746PolyExtStep::Get(198), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7747PolyExtStep::Get(204), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7748PolyExtStep::Get(210), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7749PolyExtStep::Get(216), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7750PolyExtStep::Get(222), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7751PolyExtStep::Get(228), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7752PolyExtStep::Get(234), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7753PolyExtStep::Get(240), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7754PolyExtStep::Get(246), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7755PolyExtStep::Get(252), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7756PolyExtStep::Get(258), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7757PolyExtStep::Get(264), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7758PolyExtStep::Get(270), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7759PolyExtStep::Get(276), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7760PolyExtStep::Get(282), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7761PolyExtStep::Get(288), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7762PolyExtStep::Get(294), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7763PolyExtStep::Get(300), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7764PolyExtStep::Get(306), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7765PolyExtStep::Get(312), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7766PolyExtStep::Get(318), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7767PolyExtStep::Get(324), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7768PolyExtStep::Get(330), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7769PolyExtStep::Get(354), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7770PolyExtStep::Get(348), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7771PolyExtStep::Mul(3977, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7772PolyExtStep::Add(3978, 3979), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7773PolyExtStep::Get(342), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7774PolyExtStep::Mul(3980, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7775PolyExtStep::Add(3981, 3982), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7776PolyExtStep::Get(336), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7777PolyExtStep::Mul(3983, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7778PolyExtStep::Add(3984, 3985), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7779PolyExtStep::Add(3877, 3952), // loc(callsite( builtin Add at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :232:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7780PolyExtStep::AndEqz(0, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7781PolyExtStep::AndEqz(3765, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7782PolyExtStep::Sub(1, 3852), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7783PolyExtStep::Mul(3852, 3988), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7784PolyExtStep::AndEqz(3766, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7785PolyExtStep::Add(2683, 2685), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7786PolyExtStep::Add(3990, 3852), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7787PolyExtStep::Sub(3991, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7788PolyExtStep::AndEqz(3767, 3992), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7789PolyExtStep::Mul(3852, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7790PolyExtStep::Add(2685, 3993), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7791PolyExtStep::Sub(3994, 3987), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7792PolyExtStep::AndEqz(3768, 3995), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7793PolyExtStep::Add(3880, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7794PolyExtStep::Add(3880, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7795PolyExtStep::Add(3880, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7796PolyExtStep::Add(3880, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7797PolyExtStep::Add(3880, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7798PolyExtStep::Add(3880, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7799PolyExtStep::Add(3880, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7800PolyExtStep::Add(3880, 12), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:65) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7801PolyExtStep::Add(3969, 3970), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7802PolyExtStep::Add(3971, 3972), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7803PolyExtStep::Mul(3970, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7804PolyExtStep::Add(4006, 4005), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7805PolyExtStep::Mul(3972, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7806PolyExtStep::Add(4008, 4004), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7807PolyExtStep::Mul(4005, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7808PolyExtStep::Add(4010, 4009), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7809PolyExtStep::Mul(4004, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7810PolyExtStep::Add(4012, 4007), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7811PolyExtStep::Add(4009, 4013), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7812PolyExtStep::Add(4007, 4011), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7813PolyExtStep::Add(3973, 3974), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7814PolyExtStep::Add(3975, 3976), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7815PolyExtStep::Mul(3974, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7816PolyExtStep::Add(4018, 4017), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7817PolyExtStep::Mul(3976, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7818PolyExtStep::Add(4020, 4016), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7819PolyExtStep::Mul(4017, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7820PolyExtStep::Add(4022, 4021), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7821PolyExtStep::Mul(4016, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7822PolyExtStep::Add(4024, 4019), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7823PolyExtStep::Add(4021, 4025), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7824PolyExtStep::Add(4019, 4023), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7825PolyExtStep::AndEqz(0, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7826PolyExtStep::AndEqz(3770, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7827PolyExtStep::AndEqz(3771, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7828PolyExtStep::Add(2673, 2675), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7829PolyExtStep::Add(4028, 2682), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7830PolyExtStep::Sub(4029, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7831PolyExtStep::AndEqz(3772, 4030), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7832PolyExtStep::Mul(2682, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7833PolyExtStep::Add(2675, 4031), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7834PolyExtStep::Sub(4032, 3879), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7835PolyExtStep::AndEqz(3773, 4033), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7836PolyExtStep::Sub(587, 3880), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7837PolyExtStep::AndEqz(3514, 4034), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7838PolyExtStep::AndEqz(3775, 3803), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7839PolyExtStep::AndEqz(3776, 3804), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7840PolyExtStep::AndEqz(3777, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7841PolyExtStep::AndEqz(3778, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7842PolyExtStep::AndCond(3774, 2673, 3779), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7843PolyExtStep::AndEqz(3777, 821), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7844PolyExtStep::AndCond(3780, 2675, 3781), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7845PolyExtStep::AndEqz(3775, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7846PolyExtStep::AndEqz(3783, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7847PolyExtStep::AndCond(3782, 2682, 3784), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7848PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7849PolyExtStep::Mul(4035, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7850PolyExtStep::Mul(4035, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7851PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7852PolyExtStep::Mul(4038, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7853PolyExtStep::Add(4036, 4037), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7854PolyExtStep::Add(4040, 4039), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7855PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7856PolyExtStep::Mul(4042, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7857PolyExtStep::Mul(4042, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7858PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7859PolyExtStep::Mul(4045, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7860PolyExtStep::Add(4043, 4044), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7861PolyExtStep::Add(4047, 4046), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7862PolyExtStep::Sub(4035, 4038), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7863PolyExtStep::Mul(4049, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7864PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7865PolyExtStep::Sub(3690, 4051), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7866PolyExtStep::Mul(4052, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7867PolyExtStep::Sub(4042, 4045), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7868PolyExtStep::Mul(4054, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7869PolyExtStep::Add(2673, 4053), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7870PolyExtStep::Add(4056, 4055), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7871PolyExtStep::AndEqz(0, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7872PolyExtStep::AndEqz(3786, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7873PolyExtStep::AndEqz(3787, 3812), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7874PolyExtStep::AndEqz(3788, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7875PolyExtStep::Sub(642, 3996), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7876PolyExtStep::AndEqz(3789, 4058), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7877PolyExtStep::AndEqz(3790, 3814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7878PolyExtStep::AndEqz(3791, 3815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7879PolyExtStep::AndEqz(3792, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7880PolyExtStep::AndEqz(3793, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7881PolyExtStep::AndCond(3785, 2673, 3794), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7882PolyExtStep::AndEqz(3792, 827), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7883PolyExtStep::AndCond(3795, 2675, 3796), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7884PolyExtStep::AndEqz(3790, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7885PolyExtStep::AndEqz(3798, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7886PolyExtStep::AndCond(3797, 2682, 3799), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7887PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7888PolyExtStep::Mul(4059, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7889PolyExtStep::Mul(4059, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7890PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7891PolyExtStep::Mul(4062, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7892PolyExtStep::Add(4060, 4061), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7893PolyExtStep::Add(4064, 4063), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7894PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7895PolyExtStep::Mul(4066, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7896PolyExtStep::Mul(4066, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7897PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7898PolyExtStep::Mul(4069, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7899PolyExtStep::Add(4067, 4068), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7900PolyExtStep::Add(4071, 4070), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7901PolyExtStep::Sub(4059, 4062), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7902PolyExtStep::Mul(4073, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7903PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7904PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7905PolyExtStep::Sub(4076, 4075), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7906PolyExtStep::Mul(4077, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7907PolyExtStep::Sub(4066, 4069), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7908PolyExtStep::Mul(4079, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7909PolyExtStep::Add(2673, 4078), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7910PolyExtStep::Add(4081, 4080), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7911PolyExtStep::AndEqz(0, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7912PolyExtStep::AndEqz(3801, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7913PolyExtStep::AndEqz(3802, 3823), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7914PolyExtStep::AndEqz(3803, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7915PolyExtStep::Sub(549, 3997), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7916PolyExtStep::AndEqz(3804, 4083), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7917PolyExtStep::AndEqz(3805, 3825), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7918PolyExtStep::AndEqz(3806, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7919PolyExtStep::AndEqz(3807, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7920PolyExtStep::AndEqz(3808, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7921PolyExtStep::AndCond(3800, 2673, 3809), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7922PolyExtStep::AndEqz(3807, 864), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7923PolyExtStep::AndCond(3810, 2675, 3811), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7924PolyExtStep::AndEqz(3805, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7925PolyExtStep::AndEqz(3813, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7926PolyExtStep::AndCond(3812, 2682, 3814), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7927PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7928PolyExtStep::Mul(4084, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7929PolyExtStep::Mul(4084, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7930PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7931PolyExtStep::Mul(4087, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7932PolyExtStep::Add(4085, 4086), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7933PolyExtStep::Add(4089, 4088), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7934PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7935PolyExtStep::Mul(4091, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7936PolyExtStep::Mul(4091, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7937PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7938PolyExtStep::Mul(4094, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7939PolyExtStep::Add(4092, 4093), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7940PolyExtStep::Add(4096, 4095), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7941PolyExtStep::Sub(4084, 4087), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7942PolyExtStep::Mul(4098, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7943PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7944PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7945PolyExtStep::Sub(4101, 4100), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7946PolyExtStep::Mul(4102, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7947PolyExtStep::Sub(4091, 4094), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7948PolyExtStep::Mul(4104, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7949PolyExtStep::Add(2673, 4103), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7950PolyExtStep::Add(4106, 4105), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7951PolyExtStep::AndEqz(0, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7952PolyExtStep::AndEqz(3816, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7953PolyExtStep::AndEqz(3817, 3833), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7954PolyExtStep::AndEqz(3818, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7955PolyExtStep::Sub(571, 3998), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7956PolyExtStep::AndEqz(3819, 4108), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7957PolyExtStep::AndEqz(3820, 1624), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7958PolyExtStep::AndEqz(3821, 3835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7959PolyExtStep::AndEqz(3822, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7960PolyExtStep::AndEqz(3823, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7961PolyExtStep::AndCond(3815, 2673, 3824), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7962PolyExtStep::AndEqz(3822, 870), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7963PolyExtStep::AndCond(3825, 2675, 3826), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7964PolyExtStep::AndEqz(3820, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7965PolyExtStep::AndEqz(3828, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7966PolyExtStep::AndCond(3827, 2682, 3829), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7967PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7968PolyExtStep::Mul(4109, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7969PolyExtStep::Mul(4109, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7970PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7971PolyExtStep::Mul(4112, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7972PolyExtStep::Add(4110, 4111), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7973PolyExtStep::Add(4114, 4113), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7974PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7975PolyExtStep::Mul(4116, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7976PolyExtStep::Mul(4116, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7977PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7978PolyExtStep::Mul(4119, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7979PolyExtStep::Add(4117, 4118), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7980PolyExtStep::Add(4121, 4120), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7981PolyExtStep::Sub(4109, 4112), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7982PolyExtStep::Mul(4123, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7983PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7984PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
7985PolyExtStep::Sub(4126, 4125), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7986PolyExtStep::Mul(4127, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7987PolyExtStep::Sub(4116, 4119), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7988PolyExtStep::Mul(4129, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7989PolyExtStep::Add(2673, 4128), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7990PolyExtStep::Add(4131, 4130), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7991PolyExtStep::AndEqz(0, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7992PolyExtStep::AndEqz(3831, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7993PolyExtStep::AndEqz(3832, 3899), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7994PolyExtStep::AndEqz(3833, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7995PolyExtStep::Sub(733, 3999), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7996PolyExtStep::AndEqz(3834, 4133), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7997PolyExtStep::AndEqz(3835, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7998PolyExtStep::AndEqz(3836, 1706), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7999PolyExtStep::AndEqz(3837, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8000PolyExtStep::AndEqz(3838, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8001PolyExtStep::AndCond(3830, 2673, 3839), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8002PolyExtStep::AndEqz(3837, 876), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8003PolyExtStep::AndCond(3840, 2675, 3841), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8004PolyExtStep::AndEqz(3835, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8005PolyExtStep::AndEqz(3843, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8006PolyExtStep::AndCond(3842, 2682, 3844), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8007PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8008PolyExtStep::Mul(4134, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8009PolyExtStep::Mul(4134, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8010PolyExtStep::Mul(3596, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8011PolyExtStep::Add(4135, 4136), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8012PolyExtStep::Add(4138, 4137), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8013PolyExtStep::Mul(2903, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8014PolyExtStep::Mul(2903, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8015PolyExtStep::Mul(3597, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8016PolyExtStep::Add(4140, 4141), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8017PolyExtStep::Add(4143, 4142), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8018PolyExtStep::Sub(4134, 3596), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8019PolyExtStep::Mul(4145, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8020PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8021PolyExtStep::Sub(4147, 3595), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8022PolyExtStep::Mul(4148, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8023PolyExtStep::Sub(2903, 3597), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8024PolyExtStep::Mul(4150, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8025PolyExtStep::Add(2673, 4149), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8026PolyExtStep::Add(4152, 4151), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8027PolyExtStep::AndEqz(0, 3907), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8028PolyExtStep::AndEqz(3846, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8029PolyExtStep::AndEqz(3847, 2991), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8030PolyExtStep::AndEqz(3848, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8031PolyExtStep::Sub(729, 4000), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8032PolyExtStep::AndEqz(3849, 4154), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8033PolyExtStep::AndEqz(3850, 2993), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8034PolyExtStep::AndEqz(3851, 2031), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8035PolyExtStep::AndEqz(3852, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8036PolyExtStep::AndEqz(3853, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8037PolyExtStep::AndCond(3845, 2673, 3854), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8038PolyExtStep::AndEqz(3852, 882), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8039PolyExtStep::AndCond(3855, 2675, 3856), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8040PolyExtStep::AndEqz(3850, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8041PolyExtStep::AndEqz(3858, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8042PolyExtStep::AndCond(3857, 2682, 3859), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8043PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8044PolyExtStep::Mul(4155, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8045PolyExtStep::Mul(4155, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8046PolyExtStep::Mul(3624, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8047PolyExtStep::Add(4156, 4157), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8048PolyExtStep::Add(4159, 4158), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8049PolyExtStep::Mul(3612, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8050PolyExtStep::Mul(3612, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8051PolyExtStep::Mul(3666, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8052PolyExtStep::Add(4161, 4162), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8053PolyExtStep::Add(4164, 4163), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8054PolyExtStep::Sub(4155, 3624), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8055PolyExtStep::Mul(4166, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8056PolyExtStep::Sub(3611, 3623), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8057PolyExtStep::Mul(4168, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8058PolyExtStep::Sub(3612, 3666), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8059PolyExtStep::Mul(4170, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8060PolyExtStep::Add(2673, 4169), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8061PolyExtStep::Add(4172, 4171), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8062PolyExtStep::AndEqz(0, 3914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8063PolyExtStep::AndEqz(3861, 2942), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8064PolyExtStep::AndEqz(3862, 3915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8065PolyExtStep::AndEqz(3863, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8066PolyExtStep::Sub(762, 4001), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8067PolyExtStep::AndEqz(3864, 4174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8068PolyExtStep::AndEqz(3865, 3917), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8069PolyExtStep::AndEqz(3866, 3918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8070PolyExtStep::AndEqz(3867, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8071PolyExtStep::AndEqz(3868, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8072PolyExtStep::AndCond(3860, 2673, 3869), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8073PolyExtStep::AndEqz(3867, 888), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8074PolyExtStep::AndCond(3870, 2675, 3871), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8075PolyExtStep::AndEqz(3865, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8076PolyExtStep::AndEqz(3873, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8077PolyExtStep::AndCond(3872, 2682, 3874), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8078PolyExtStep::Mul(1152, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8079PolyExtStep::Mul(1152, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8080PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8081PolyExtStep::Mul(4177, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8082PolyExtStep::Add(4175, 4176), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8083PolyExtStep::Add(4179, 4178), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8084PolyExtStep::Mul(1153, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8085PolyExtStep::Mul(1153, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8086PolyExtStep::Mul(3636, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8087PolyExtStep::Add(4181, 4182), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8088PolyExtStep::Add(4184, 4183), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8089PolyExtStep::Sub(1152, 4177), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8090PolyExtStep::Mul(4186, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8091PolyExtStep::Sub(1151, 3635), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8092PolyExtStep::Mul(4188, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8093PolyExtStep::Sub(1153, 3636), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8094PolyExtStep::Mul(4190, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8095PolyExtStep::Add(2673, 4189), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8096PolyExtStep::Add(4192, 4191), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8097PolyExtStep::AndEqz(0, 3925), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8098PolyExtStep::AndEqz(3876, 3926), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8099PolyExtStep::AndEqz(3877, 3927), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8100PolyExtStep::AndEqz(3878, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8101PolyExtStep::Sub(797, 4002), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8102PolyExtStep::AndEqz(3879, 4194), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8103PolyExtStep::AndEqz(3880, 3929), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8104PolyExtStep::AndEqz(3881, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8105PolyExtStep::AndEqz(3882, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8106PolyExtStep::AndEqz(3883, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8107PolyExtStep::AndCond(3875, 2673, 3884), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8108PolyExtStep::AndEqz(3882, 894), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8109PolyExtStep::AndCond(3885, 2675, 3886), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8110PolyExtStep::AndEqz(3880, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8111PolyExtStep::AndEqz(3888, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8112PolyExtStep::AndCond(3887, 2682, 3889), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8113PolyExtStep::Mul(1161, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8114PolyExtStep::Mul(1161, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8115PolyExtStep::Mul(1157, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8116PolyExtStep::Add(4195, 4196), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8117PolyExtStep::Add(4198, 4197), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8118PolyExtStep::Mul(1162, 2673), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8119PolyExtStep::Mul(1162, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8120PolyExtStep::Mul(1158, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8121PolyExtStep::Add(4200, 4201), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8122PolyExtStep::Add(4203, 4202), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8123PolyExtStep::Sub(1161, 1157), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8124PolyExtStep::Mul(4205, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8125PolyExtStep::Sub(1160, 1156), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8126PolyExtStep::Mul(4207, 2675), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8127PolyExtStep::Sub(1162, 1158), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8128PolyExtStep::Mul(4209, 2682), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8129PolyExtStep::Add(2673, 4208), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8130PolyExtStep::Add(4211, 4210), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8131PolyExtStep::GetGlobal(0, 36), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8132PolyExtStep::GetGlobal(0, 35), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8133PolyExtStep::Mul(4213, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8134PolyExtStep::Add(4214, 4215), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8135PolyExtStep::GetGlobal(0, 34), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8136PolyExtStep::Mul(4216, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8137PolyExtStep::Add(4217, 4218), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8138PolyExtStep::GetGlobal(0, 33), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8139PolyExtStep::Mul(4219, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8140PolyExtStep::Add(4220, 4221), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8141PolyExtStep::Mul(4222, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8142PolyExtStep::Add(4050, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8143PolyExtStep::Mul(4224, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8144PolyExtStep::Add(4225, 58), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8145PolyExtStep::Mul(4223, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8146PolyExtStep::Add(4057, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8147PolyExtStep::Mul(4228, 4223), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8148PolyExtStep::Add(4226, 4229), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8149PolyExtStep::Mul(4227, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8150PolyExtStep::Add(4074, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8151PolyExtStep::Mul(4232, 4227), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8152PolyExtStep::Add(4230, 4233), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8153PolyExtStep::Mul(4231, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8154PolyExtStep::Add(4082, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8155PolyExtStep::Mul(4236, 4231), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8156PolyExtStep::Add(4234, 4237), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8157PolyExtStep::Mul(4235, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8158PolyExtStep::Add(4099, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8159PolyExtStep::Mul(4240, 4235), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8160PolyExtStep::Add(4238, 4241), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8161PolyExtStep::Mul(4239, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8162PolyExtStep::Add(4107, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8163PolyExtStep::Mul(4244, 4239), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8164PolyExtStep::Add(4242, 4245), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8165PolyExtStep::Mul(4243, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8166PolyExtStep::Add(4124, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8167PolyExtStep::Mul(4248, 4243), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8168PolyExtStep::Add(4246, 4249), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8169PolyExtStep::Mul(4247, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8170PolyExtStep::Add(4132, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8171PolyExtStep::Mul(4252, 4247), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8172PolyExtStep::Add(4250, 4253), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8173PolyExtStep::Mul(4251, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8174PolyExtStep::Add(4146, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8175PolyExtStep::Mul(4256, 4251), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8176PolyExtStep::Add(4254, 4257), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8177PolyExtStep::Mul(4255, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8178PolyExtStep::Add(4153, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8179PolyExtStep::Mul(4260, 4255), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8180PolyExtStep::Add(4258, 4261), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8181PolyExtStep::Mul(4259, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8182PolyExtStep::Add(4167, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8183PolyExtStep::Mul(4264, 4259), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8184PolyExtStep::Add(4262, 4265), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8185PolyExtStep::Mul(4263, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8186PolyExtStep::Add(4173, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8187PolyExtStep::Mul(4268, 4263), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8188PolyExtStep::Add(4266, 4269), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8189PolyExtStep::Mul(4267, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8190PolyExtStep::Add(4187, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8191PolyExtStep::Mul(4272, 4267), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8192PolyExtStep::Add(4270, 4273), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8193PolyExtStep::Mul(4271, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8194PolyExtStep::Add(4193, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8195PolyExtStep::Mul(4276, 4271), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8196PolyExtStep::Add(4274, 4277), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8197PolyExtStep::Mul(4275, 4222), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8198PolyExtStep::Add(4206, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8199PolyExtStep::Mul(4280, 4275), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8200PolyExtStep::Add(4278, 4281), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8201PolyExtStep::Add(4212, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8202PolyExtStep::Mul(4283, 4279), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8203PolyExtStep::Add(4282, 4284), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8204PolyExtStep::Mul(4279, 4222), // loc(callsite( builtin ExtMul at callsite( Pow ( zirgen/circuit/rv32im/v2/dsl/poly.zir :10:4) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:29) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8205PolyExtStep::Mul(3986, 4286), // loc(callsite( builtin ExtMul at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:17) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8206PolyExtStep::Add(4287, 4285), // loc(callsite( builtin ExtAdd at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:10) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8207PolyExtStep::Add(4041, 4048), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8208PolyExtStep::Add(4065, 4072), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8209PolyExtStep::Mul(4048, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8210PolyExtStep::Add(4291, 4290), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8211PolyExtStep::Mul(4072, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8212PolyExtStep::Add(4293, 4289), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8213PolyExtStep::Mul(4290, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8214PolyExtStep::Add(4295, 4294), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8215PolyExtStep::Mul(4289, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8216PolyExtStep::Add(4297, 4292), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8217PolyExtStep::Add(4294, 4298), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8218PolyExtStep::Add(4292, 4296), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8219PolyExtStep::Add(4090, 4097), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8220PolyExtStep::Add(4115, 4122), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8221PolyExtStep::Mul(4097, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8222PolyExtStep::Add(4303, 4302), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8223PolyExtStep::Mul(4122, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8224PolyExtStep::Add(4305, 4301), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8225PolyExtStep::Mul(4302, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8226PolyExtStep::Add(4307, 4306), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8227PolyExtStep::Mul(4301, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8228PolyExtStep::Add(4309, 4304), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8229PolyExtStep::Add(4306, 4310), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8230PolyExtStep::Add(4304, 4308), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8231PolyExtStep::Add(4139, 4144), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8232PolyExtStep::Add(4160, 4165), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8233PolyExtStep::Mul(4144, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8234PolyExtStep::Add(4315, 4314), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8235PolyExtStep::Mul(4165, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8236PolyExtStep::Add(4317, 4313), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8237PolyExtStep::Mul(4314, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8238PolyExtStep::Add(4319, 4318), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8239PolyExtStep::Mul(4313, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8240PolyExtStep::Add(4321, 4316), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8241PolyExtStep::Add(4318, 4322), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8242PolyExtStep::Add(4316, 4320), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8243PolyExtStep::Add(4180, 4185), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8244PolyExtStep::Add(4199, 4204), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8245PolyExtStep::Mul(4185, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8246PolyExtStep::Add(4327, 4326), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8247PolyExtStep::Mul(4204, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8248PolyExtStep::Add(4329, 4325), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8249PolyExtStep::Mul(4326, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8250PolyExtStep::Add(4331, 4330), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8251PolyExtStep::Mul(4325, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8252PolyExtStep::Add(4333, 4328), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8253PolyExtStep::Add(4330, 4334), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8254PolyExtStep::Add(4328, 4332), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8255PolyExtStep::Add(4299, 4311), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8256PolyExtStep::Add(4298, 4310), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8257PolyExtStep::Add(4300, 4312), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8258PolyExtStep::Add(4296, 4308), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8259PolyExtStep::Add(4337, 4323), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8260PolyExtStep::Add(4338, 4322), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8261PolyExtStep::Add(4339, 4324), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8262PolyExtStep::Add(4340, 4320), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8263PolyExtStep::Add(4341, 4335), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8264PolyExtStep::Add(4342, 4334), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8265PolyExtStep::Add(4343, 4336), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8266PolyExtStep::Add(4344, 4332), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8267PolyExtStep::Add(4345, 4014), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8268PolyExtStep::Add(4346, 4013), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8269PolyExtStep::Add(4347, 4015), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8270PolyExtStep::Add(4348, 4011), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8271PolyExtStep::Add(4349, 4026), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8272PolyExtStep::Add(4350, 4025), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8273PolyExtStep::Add(4351, 4027), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8274PolyExtStep::Add(4352, 4023), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8275PolyExtStep::Add(4299, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8276PolyExtStep::Add(4298, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8277PolyExtStep::Add(4300, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8278PolyExtStep::Add(4296, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8279PolyExtStep::Add(4311, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8280PolyExtStep::Add(4310, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8281PolyExtStep::Add(4312, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8282PolyExtStep::Add(4308, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8283PolyExtStep::Add(4323, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8284PolyExtStep::Add(4322, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8285PolyExtStep::Add(4324, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8286PolyExtStep::Add(4320, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8287PolyExtStep::Add(4335, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8288PolyExtStep::Add(4334, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8289PolyExtStep::Add(4336, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8290PolyExtStep::Add(4332, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8291PolyExtStep::Add(4014, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8292PolyExtStep::Add(4013, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8293PolyExtStep::Add(4015, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8294PolyExtStep::Add(4011, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8295PolyExtStep::Add(4026, 4353), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8296PolyExtStep::Add(4025, 4354), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8297PolyExtStep::Add(4027, 4355), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8298PolyExtStep::Add(4023, 4356), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8299PolyExtStep::AndEqz(3890, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8300PolyExtStep::AndEqz(3891, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8301PolyExtStep::AndEqz(3892, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8302PolyExtStep::AndEqz(3893, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8303PolyExtStep::AndEqz(3894, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8304PolyExtStep::AndEqz(3895, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8305PolyExtStep::Sub(68, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8306PolyExtStep::AndEqz(3896, 4381), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8307PolyExtStep::AndEqz(3897, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8308PolyExtStep::Sub(4003, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8309PolyExtStep::AndEqz(3898, 4382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8310PolyExtStep::AndEqz(3899, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8311PolyExtStep::AndEqz(3900, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8312PolyExtStep::Sub(4357, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8313PolyExtStep::AndEqz(3901, 4383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8314PolyExtStep::Sub(4358, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8315PolyExtStep::AndEqz(3902, 4384), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8316PolyExtStep::Sub(4359, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8317PolyExtStep::AndEqz(3903, 4385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8318PolyExtStep::Sub(4360, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8319PolyExtStep::AndEqz(3904, 4386), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8320PolyExtStep::Sub(4361, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8321PolyExtStep::AndEqz(3905, 4387), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8322PolyExtStep::Sub(4362, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8323PolyExtStep::AndEqz(3906, 4388), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8324PolyExtStep::Sub(4363, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8325PolyExtStep::AndEqz(3907, 4389), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8326PolyExtStep::Sub(4364, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8327PolyExtStep::AndEqz(3908, 4390), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8328PolyExtStep::Sub(4365, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8329PolyExtStep::AndEqz(3909, 4391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8330PolyExtStep::Sub(4366, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8331PolyExtStep::AndEqz(3910, 4392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8332PolyExtStep::Sub(4367, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8333PolyExtStep::AndEqz(3911, 4393), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8334PolyExtStep::Sub(4368, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8335PolyExtStep::AndEqz(3912, 4394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8336PolyExtStep::Sub(4369, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8337PolyExtStep::AndEqz(3913, 4395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8338PolyExtStep::Sub(4370, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8339PolyExtStep::AndEqz(3914, 4396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8340PolyExtStep::Sub(4371, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8341PolyExtStep::AndEqz(3915, 4397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8342PolyExtStep::Sub(4372, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8343PolyExtStep::AndEqz(3916, 4398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8344PolyExtStep::Sub(4373, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8345PolyExtStep::AndEqz(3917, 4399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8346PolyExtStep::Sub(4374, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8347PolyExtStep::AndEqz(3918, 4400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8348PolyExtStep::Sub(4375, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8349PolyExtStep::AndEqz(3919, 4401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8350PolyExtStep::Sub(4376, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8351PolyExtStep::AndEqz(3920, 4402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8352PolyExtStep::Sub(4377, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8353PolyExtStep::AndEqz(3921, 4403), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8354PolyExtStep::Sub(4378, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8355PolyExtStep::AndEqz(3922, 4404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8356PolyExtStep::Sub(4379, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8357PolyExtStep::AndEqz(3923, 4405), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8358PolyExtStep::Sub(4380, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8359PolyExtStep::AndEqz(3924, 4406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8360PolyExtStep::Sub(3798, 4288), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8361PolyExtStep::AndEqz(3925, 4407), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8362PolyExtStep::AndCond(3769, 2683, 3926), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8363PolyExtStep::Mul(4048, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8364PolyExtStep::Add(4408, 4041), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8365PolyExtStep::Mul(4072, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8366PolyExtStep::Add(4410, 4065), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8367PolyExtStep::Mul(4097, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8368PolyExtStep::Add(4412, 4090), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8369PolyExtStep::Mul(4122, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8370PolyExtStep::Add(4414, 4115), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8371PolyExtStep::Mul(4144, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8372PolyExtStep::Add(4416, 4139), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8373PolyExtStep::Mul(4165, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8374PolyExtStep::Add(4418, 4160), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8375PolyExtStep::Mul(4185, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8376PolyExtStep::Add(4420, 4180), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8377PolyExtStep::Mul(4204, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8378PolyExtStep::Add(4422, 4199), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8379PolyExtStep::AndEqz(3896, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8380PolyExtStep::Sub(1, 1122), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8381PolyExtStep::AndEqz(3928, 4424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8382PolyExtStep::AndEqz(3929, 4382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8383PolyExtStep::AndEqz(3930, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8384PolyExtStep::AndEqz(3931, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8385PolyExtStep::Sub(4409, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8386PolyExtStep::AndEqz(3932, 4425), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8387PolyExtStep::Sub(4411, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8388PolyExtStep::AndEqz(3933, 4426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8389PolyExtStep::Sub(4413, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8390PolyExtStep::AndEqz(3934, 4427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8391PolyExtStep::Sub(4415, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8392PolyExtStep::AndEqz(3935, 4428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8393PolyExtStep::Sub(4417, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8394PolyExtStep::AndEqz(3936, 4429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8395PolyExtStep::Sub(4419, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8396PolyExtStep::AndEqz(3937, 4430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8397PolyExtStep::Sub(4421, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8398PolyExtStep::AndEqz(3938, 4431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8399PolyExtStep::Sub(4423, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8400PolyExtStep::AndEqz(3939, 4432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8401PolyExtStep::Sub(3961, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8402PolyExtStep::AndEqz(3940, 4433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8403PolyExtStep::Sub(3962, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8404PolyExtStep::AndEqz(3941, 4434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8405PolyExtStep::Sub(3963, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8406PolyExtStep::AndEqz(3942, 4435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8407PolyExtStep::Sub(3964, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8408PolyExtStep::AndEqz(3943, 4436), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8409PolyExtStep::Sub(3965, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8410PolyExtStep::AndEqz(3944, 4437), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8411PolyExtStep::Sub(3966, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8412PolyExtStep::AndEqz(3945, 4438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8413PolyExtStep::Sub(3967, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8414PolyExtStep::AndEqz(3946, 4439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8415PolyExtStep::Sub(3968, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8416PolyExtStep::AndEqz(3947, 4440), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8417PolyExtStep::Sub(3969, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8418PolyExtStep::AndEqz(3948, 4441), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8419PolyExtStep::Sub(3970, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8420PolyExtStep::AndEqz(3949, 4442), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8421PolyExtStep::Sub(3971, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8422PolyExtStep::AndEqz(3950, 4443), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8423PolyExtStep::Sub(3972, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8424PolyExtStep::AndEqz(3951, 4444), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8425PolyExtStep::Sub(3973, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8426PolyExtStep::AndEqz(3952, 4445), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8427PolyExtStep::Sub(3974, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8428PolyExtStep::AndEqz(3953, 4446), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8429PolyExtStep::Sub(3975, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8430PolyExtStep::AndEqz(3954, 4447), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8431PolyExtStep::Sub(3976, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8432PolyExtStep::AndEqz(3955, 4448), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8433PolyExtStep::AndEqz(3956, 4407), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8434PolyExtStep::AndCond(3927, 2685, 3957), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8435PolyExtStep::Add(3953, 3954), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8436PolyExtStep::Add(3955, 3956), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8437PolyExtStep::Mul(3954, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8438PolyExtStep::Add(4451, 4450), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8439PolyExtStep::Mul(3956, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8440PolyExtStep::Add(4453, 4449), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8441PolyExtStep::Mul(4450, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8442PolyExtStep::Add(4455, 4454), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8443PolyExtStep::Mul(4449, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8444PolyExtStep::Add(4457, 4452), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8445PolyExtStep::Add(4454, 4458), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8446PolyExtStep::Add(4452, 4456), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8447PolyExtStep::Add(3957, 3958), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8448PolyExtStep::Add(3959, 3960), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8449PolyExtStep::Mul(3958, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8450PolyExtStep::Add(4463, 4462), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8451PolyExtStep::Mul(3960, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8452PolyExtStep::Add(4465, 4461), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8453PolyExtStep::Mul(4462, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8454PolyExtStep::Add(4467, 4466), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8455PolyExtStep::Mul(4461, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8456PolyExtStep::Add(4469, 4464), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8457PolyExtStep::Add(4466, 4470), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8458PolyExtStep::Add(4464, 4468), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8459PolyExtStep::Add(4459, 4471), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8460PolyExtStep::Add(4458, 4470), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8461PolyExtStep::Add(4460, 4472), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8462PolyExtStep::Add(4456, 4468), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8463PolyExtStep::Add(4409, 4411), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8464PolyExtStep::Add(4413, 4415), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8465PolyExtStep::Mul(4411, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8466PolyExtStep::Add(4479, 4478), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8467PolyExtStep::Mul(4415, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8468PolyExtStep::Add(4481, 4477), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8469PolyExtStep::Mul(4478, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8470PolyExtStep::Add(4483, 4482), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8471PolyExtStep::Mul(4477, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8472PolyExtStep::Add(4485, 4480), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8473PolyExtStep::Add(4482, 4486), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8474PolyExtStep::Add(4480, 4484), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8475PolyExtStep::Add(4417, 4419), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8476PolyExtStep::Add(4421, 4423), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8477PolyExtStep::Mul(4419, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8478PolyExtStep::Add(4491, 4490), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8479PolyExtStep::Mul(4423, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8480PolyExtStep::Add(4493, 4489), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8481PolyExtStep::Mul(4490, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8482PolyExtStep::Add(4495, 4494), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8483PolyExtStep::Mul(4489, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8484PolyExtStep::Add(4497, 4492), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8485PolyExtStep::Add(4494, 4498), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8486PolyExtStep::Add(4492, 4496), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8487PolyExtStep::Add(4473, 4487), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8488PolyExtStep::Add(4474, 4486), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8489PolyExtStep::Add(4475, 4488), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8490PolyExtStep::Add(4476, 4484), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8491PolyExtStep::Add(4501, 4499), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8492PolyExtStep::Add(4502, 4498), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8493PolyExtStep::Add(4503, 4500), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8494PolyExtStep::Add(4504, 4496), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8495PolyExtStep::Add(4505, 4014), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8496PolyExtStep::Add(4506, 4013), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8497PolyExtStep::Add(4507, 4015), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8498PolyExtStep::Add(4508, 4011), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8499PolyExtStep::Add(4509, 4026), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8500PolyExtStep::Add(4510, 4025), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8501PolyExtStep::Add(4511, 4027), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8502PolyExtStep::Add(4512, 4023), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8503PolyExtStep::Add(4459, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8504PolyExtStep::Add(4458, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8505PolyExtStep::Add(4460, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8506PolyExtStep::Add(4456, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8507PolyExtStep::Add(4471, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8508PolyExtStep::Add(4470, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8509PolyExtStep::Add(4472, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8510PolyExtStep::Add(4468, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8511PolyExtStep::Add(4487, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8512PolyExtStep::Add(4486, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8513PolyExtStep::Add(4488, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8514PolyExtStep::Add(4484, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8515PolyExtStep::Add(4499, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8516PolyExtStep::Add(4498, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8517PolyExtStep::Add(4500, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8518PolyExtStep::Add(4496, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8519PolyExtStep::Add(4014, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8520PolyExtStep::Add(4013, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8521PolyExtStep::Add(4015, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8522PolyExtStep::Add(4011, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8523PolyExtStep::Add(4026, 4513), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8524PolyExtStep::Add(4025, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8525PolyExtStep::Add(4027, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8526PolyExtStep::Add(4023, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8527PolyExtStep::Sub(4517, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8528PolyExtStep::AndEqz(3901, 4541), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8529PolyExtStep::Sub(4518, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8530PolyExtStep::AndEqz(3959, 4542), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8531PolyExtStep::Sub(4519, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8532PolyExtStep::AndEqz(3960, 4543), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8533PolyExtStep::Sub(4520, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8534PolyExtStep::AndEqz(3961, 4544), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8535PolyExtStep::Sub(4521, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8536PolyExtStep::AndEqz(3962, 4545), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8537PolyExtStep::Sub(4522, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8538PolyExtStep::AndEqz(3963, 4546), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8539PolyExtStep::Sub(4523, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8540PolyExtStep::AndEqz(3964, 4547), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8541PolyExtStep::Sub(4524, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8542PolyExtStep::AndEqz(3965, 4548), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8543PolyExtStep::Sub(4525, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8544PolyExtStep::AndEqz(3966, 4549), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8545PolyExtStep::Sub(4526, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8546PolyExtStep::AndEqz(3967, 4550), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8547PolyExtStep::Sub(4527, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8548PolyExtStep::AndEqz(3968, 4551), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8549PolyExtStep::Sub(4528, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8550PolyExtStep::AndEqz(3969, 4552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8551PolyExtStep::Sub(4529, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8552PolyExtStep::AndEqz(3970, 4553), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8553PolyExtStep::Sub(4530, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8554PolyExtStep::AndEqz(3971, 4554), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8555PolyExtStep::Sub(4531, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8556PolyExtStep::AndEqz(3972, 4555), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8557PolyExtStep::Sub(4532, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8558PolyExtStep::AndEqz(3973, 4556), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8559PolyExtStep::Sub(4533, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8560PolyExtStep::AndEqz(3974, 4557), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8561PolyExtStep::Sub(4534, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8562PolyExtStep::AndEqz(3975, 4558), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8563PolyExtStep::Sub(4535, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8564PolyExtStep::AndEqz(3976, 4559), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8565PolyExtStep::Sub(4536, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8566PolyExtStep::AndEqz(3977, 4560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8567PolyExtStep::Sub(4537, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8568PolyExtStep::AndEqz(3978, 4561), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8569PolyExtStep::Sub(4538, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8570PolyExtStep::AndEqz(3979, 4562), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8571PolyExtStep::Sub(4539, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8572PolyExtStep::AndEqz(3980, 4563), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8573PolyExtStep::Sub(4540, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8574PolyExtStep::AndEqz(3981, 4564), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8575PolyExtStep::AndEqz(3982, 4407), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8576PolyExtStep::AndCond(3958, 3852, 3983), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8577PolyExtStep::AndEqz(3984, 900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8578PolyExtStep::AndEqz(3985, 903), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8579PolyExtStep::AndEqz(3986, 906), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8580PolyExtStep::AndEqz(3987, 943), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8581PolyExtStep::AndEqz(3988, 946), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8582PolyExtStep::AndEqz(3989, 949), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8583PolyExtStep::AndEqz(3990, 955), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8584PolyExtStep::AndEqz(3991, 958), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8585PolyExtStep::AndEqz(3992, 961), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8586PolyExtStep::AndEqz(3993, 967), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8587PolyExtStep::AndEqz(3994, 970), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8588PolyExtStep::AndEqz(3995, 973), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8589PolyExtStep::AndEqz(3996, 979), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8590PolyExtStep::AndEqz(3997, 982), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8591PolyExtStep::AndEqz(3998, 985), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8592PolyExtStep::AndEqz(3999, 1022), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8593PolyExtStep::AndEqz(4000, 1025), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8594PolyExtStep::AndEqz(4001, 1028), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8595PolyExtStep::AndEqz(4002, 1034), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8596PolyExtStep::AndEqz(4003, 1037), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8597PolyExtStep::AndEqz(4004, 1040), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8598PolyExtStep::AndEqz(4005, 1046), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8599PolyExtStep::AndEqz(4006, 1049), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8600PolyExtStep::AndEqz(4007, 1052), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8601PolyExtStep::AndEqz(4008, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8602PolyExtStep::AndEqz(4009, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8603PolyExtStep::AndCond(3764, 380, 4010), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8604PolyExtStep::AndEqz(1186, 3758), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8605PolyExtStep::AndEqz(4012, 3759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8606PolyExtStep::Sub(0, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8607PolyExtStep::AndEqz(4013, 4565), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8608PolyExtStep::Sub(0, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8609PolyExtStep::AndEqz(4014, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8610PolyExtStep::Sub(0, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8611PolyExtStep::AndEqz(4015, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8612PolyExtStep::AndEqz(4016, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8613PolyExtStep::Sub(0, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8614PolyExtStep::AndEqz(4017, 4568), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8615PolyExtStep::AndEqz(4018, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8616PolyExtStep::AndEqz(4019, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8617PolyExtStep::AndEqz(4020, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8618PolyExtStep::Sub(0, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8619PolyExtStep::AndEqz(4021, 4569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8620PolyExtStep::AndEqz(4022, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8621PolyExtStep::AndEqz(4023, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8622PolyExtStep::AndEqz(4024, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8623PolyExtStep::AndEqz(4025, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8624PolyExtStep::AndEqz(4026, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8625PolyExtStep::AndEqz(4027, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8626PolyExtStep::AndEqz(4028, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8627PolyExtStep::AndEqz(4029, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8628PolyExtStep::AndEqz(4030, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8629PolyExtStep::AndEqz(4031, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8630PolyExtStep::AndEqz(4032, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8631PolyExtStep::AndEqz(4033, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8632PolyExtStep::AndEqz(4034, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8633PolyExtStep::AndEqz(4035, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8634PolyExtStep::AndEqz(4036, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8635PolyExtStep::AndEqz(4037, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8636PolyExtStep::AndEqz(4038, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8637PolyExtStep::AndEqz(4039, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8638PolyExtStep::AndEqz(4040, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8639PolyExtStep::AndEqz(4041, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8640PolyExtStep::AndEqz(4042, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8641PolyExtStep::AndEqz(4043, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8642PolyExtStep::AndEqz(4044, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8643PolyExtStep::AndEqz(4045, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8644PolyExtStep::AndEqz(4046, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8645PolyExtStep::AndEqz(4047, 536), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8646PolyExtStep::AndEqz(4048, 611), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8647PolyExtStep::AndEqz(4049, 635), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8648PolyExtStep::AndEqz(4050, 662), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8649PolyExtStep::AndEqz(4051, 548), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8650PolyExtStep::AndEqz(4052, 561), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8651PolyExtStep::AndEqz(4053, 570), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8652PolyExtStep::AndEqz(4054, 575), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8653PolyExtStep::AndEqz(4055, 731), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8654PolyExtStep::AndEqz(4056, 737), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8655PolyExtStep::AndEqz(4057, 748), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8656PolyExtStep::AndEqz(4058, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8657PolyExtStep::AndEqz(4059, 761), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8658PolyExtStep::AndEqz(4060, 782), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8659PolyExtStep::AndEqz(4061, 794), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8660PolyExtStep::AndEqz(4062, 809), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8661PolyExtStep::AndEqz(4063, 821), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8662PolyExtStep::AndEqz(4064, 827), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8663PolyExtStep::AndEqz(4065, 864), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8664PolyExtStep::AndEqz(4066, 870), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8665PolyExtStep::AndEqz(4067, 876), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8666PolyExtStep::AndEqz(4068, 882), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8667PolyExtStep::AndEqz(4069, 888), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8668PolyExtStep::AndEqz(4070, 894), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8669PolyExtStep::AndEqz(4071, 900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8670PolyExtStep::AndEqz(4072, 903), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8671PolyExtStep::AndEqz(4073, 906), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8672PolyExtStep::AndEqz(4074, 943), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8673PolyExtStep::AndEqz(4075, 946), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8674PolyExtStep::AndEqz(4076, 949), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8675PolyExtStep::AndEqz(4077, 955), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8676PolyExtStep::AndEqz(4078, 958), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8677PolyExtStep::AndEqz(4079, 961), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8678PolyExtStep::AndEqz(4080, 967), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8679PolyExtStep::AndEqz(4081, 970), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8680PolyExtStep::AndEqz(4082, 973), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8681PolyExtStep::AndEqz(4083, 979), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8682PolyExtStep::AndEqz(4084, 982), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8683PolyExtStep::AndEqz(4085, 985), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8684PolyExtStep::AndEqz(4086, 1022), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8685PolyExtStep::AndEqz(4087, 1025), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8686PolyExtStep::AndEqz(4088, 1028), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8687PolyExtStep::AndEqz(4089, 1034), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8688PolyExtStep::AndEqz(4090, 1037), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8689PolyExtStep::AndEqz(4091, 1040), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8690PolyExtStep::AndEqz(4092, 1046), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8691PolyExtStep::AndEqz(4093, 1049), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8692PolyExtStep::AndEqz(4094, 1052), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8693PolyExtStep::AndEqz(4095, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8694PolyExtStep::AndEqz(4096, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8695PolyExtStep::AndCond(4011, 383, 4097), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8696PolyExtStep::AndCond(4098, 386, 4097), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8697PolyExtStep::Sub(1, 3878), // loc(callsite( builtin Sub at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8698PolyExtStep::Add(3876, 1), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8699PolyExtStep::Add(3876, 7), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8700PolyExtStep::Add(3876, 6), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8701PolyExtStep::Add(3876, 5), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8702PolyExtStep::Add(3876, 4), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8703PolyExtStep::Add(3876, 3), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8704PolyExtStep::Add(3876, 2), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8705PolyExtStep::Mul(3874, 44), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8706PolyExtStep::Sub(1, 3874), // loc(callsite( builtin Sub at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:62) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8707PolyExtStep::Sub(587, 3876), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8708PolyExtStep::AndEqz(3514, 4580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8709PolyExtStep::AndEqz(4100, 3803), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8710PolyExtStep::AndEqz(4101, 3804), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8711PolyExtStep::AndEqz(4102, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8712PolyExtStep::AndEqz(4103, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8713PolyExtStep::Sub(3885, 3953), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8714PolyExtStep::AndEqz(4104, 4581), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8715PolyExtStep::AndEqz(4105, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8716PolyExtStep::AndEqz(4106, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8717PolyExtStep::AndEqz(4107, 3812), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8718PolyExtStep::AndEqz(4108, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8719PolyExtStep::Sub(642, 4571), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8720PolyExtStep::AndEqz(4109, 4582), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8721PolyExtStep::AndEqz(4110, 3814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8722PolyExtStep::AndEqz(4111, 3815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8723PolyExtStep::AndEqz(4112, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8724PolyExtStep::AndEqz(4113, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8725PolyExtStep::Sub(3889, 3954), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8726PolyExtStep::AndEqz(4114, 4583), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8727PolyExtStep::AndEqz(4115, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8728PolyExtStep::AndEqz(4116, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8729PolyExtStep::AndEqz(4117, 3823), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8730PolyExtStep::AndEqz(4118, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8731PolyExtStep::Sub(549, 4572), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8732PolyExtStep::AndEqz(4119, 4584), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8733PolyExtStep::AndEqz(4120, 3825), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8734PolyExtStep::AndEqz(4121, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8735PolyExtStep::AndEqz(4122, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8736PolyExtStep::AndEqz(4123, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8737PolyExtStep::Sub(3893, 3955), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8738PolyExtStep::AndEqz(4124, 4585), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8739PolyExtStep::AndEqz(4125, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8740PolyExtStep::AndEqz(4126, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8741PolyExtStep::AndEqz(4127, 3833), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8742PolyExtStep::AndEqz(4128, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8743PolyExtStep::Sub(571, 4573), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8744PolyExtStep::AndEqz(4129, 4586), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8745PolyExtStep::AndEqz(4130, 1624), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8746PolyExtStep::AndEqz(4131, 3835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8747PolyExtStep::AndEqz(4132, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8748PolyExtStep::AndEqz(4133, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8749PolyExtStep::Sub(3897, 3956), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8750PolyExtStep::AndEqz(4134, 4587), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8751PolyExtStep::AndEqz(4135, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8752PolyExtStep::AndEqz(4136, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8753PolyExtStep::AndEqz(4137, 3899), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8754PolyExtStep::AndEqz(4138, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8755PolyExtStep::Sub(733, 4574), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8756PolyExtStep::AndEqz(4139, 4588), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8757PolyExtStep::AndEqz(4140, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8758PolyExtStep::AndEqz(4141, 1706), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8759PolyExtStep::AndEqz(4142, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8760PolyExtStep::AndEqz(4143, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8761PolyExtStep::Sub(3905, 3957), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8762PolyExtStep::AndEqz(4144, 4589), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8763PolyExtStep::AndEqz(4145, 3907), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8764PolyExtStep::AndEqz(4146, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8765PolyExtStep::AndEqz(4147, 2991), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8766PolyExtStep::AndEqz(4148, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8767PolyExtStep::Sub(729, 4575), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8768PolyExtStep::AndEqz(4149, 4590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8769PolyExtStep::AndEqz(4150, 2993), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8770PolyExtStep::AndEqz(4151, 2031), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8771PolyExtStep::AndEqz(4152, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8772PolyExtStep::AndEqz(4153, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8773PolyExtStep::Sub(3912, 3958), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8774PolyExtStep::AndEqz(4154, 4591), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8775PolyExtStep::AndEqz(4155, 3914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8776PolyExtStep::AndEqz(4156, 2942), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8777PolyExtStep::AndEqz(4157, 3915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8778PolyExtStep::AndEqz(4158, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8779PolyExtStep::Sub(762, 4576), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8780PolyExtStep::AndEqz(4159, 4592), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8781PolyExtStep::AndEqz(4160, 3917), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8782PolyExtStep::AndEqz(4161, 3918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8783PolyExtStep::AndEqz(4162, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8784PolyExtStep::AndEqz(4163, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8785PolyExtStep::Sub(3923, 3959), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8786PolyExtStep::AndEqz(4164, 4593), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8787PolyExtStep::AndEqz(4165, 3925), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8788PolyExtStep::AndEqz(4166, 3926), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8789PolyExtStep::AndEqz(4167, 3927), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8790PolyExtStep::AndEqz(4168, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8791PolyExtStep::Sub(797, 4577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8792PolyExtStep::AndEqz(4169, 4594), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8793PolyExtStep::AndEqz(4170, 3929), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8794PolyExtStep::AndEqz(4171, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8795PolyExtStep::AndEqz(4172, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8796PolyExtStep::AndEqz(4173, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8797PolyExtStep::Sub(3734, 3960), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8798PolyExtStep::AndEqz(4174, 4595), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8799PolyExtStep::AndEqz(4175, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8800PolyExtStep::Mul(3879, 2675), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8801PolyExtStep::Sub(4596, 3838), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8802PolyExtStep::AndEqz(4176, 4597), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8803PolyExtStep::Mul(2673, 3879), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8804PolyExtStep::AndEqz(4177, 4598), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8805PolyExtStep::AndEqz(4178, 3843), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8806PolyExtStep::Mul(2673, 13), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8807PolyExtStep::Mul(3838, 57), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8808PolyExtStep::Add(4599, 4600), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8809PolyExtStep::Mul(4579, 4601), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:80) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8810PolyExtStep::Add(4578, 4602), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:57) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8811PolyExtStep::AndEqz(4179, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8812PolyExtStep::AndEqz(4180, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8813PolyExtStep::AndEqz(4181, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8814PolyExtStep::AndEqz(4182, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8815PolyExtStep::AndEqz(4183, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8816PolyExtStep::AndEqz(4184, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8817PolyExtStep::Sub(4603, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8818PolyExtStep::AndEqz(4185, 4604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8819PolyExtStep::AndEqz(4186, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8820PolyExtStep::AndEqz(4187, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8821PolyExtStep::AndEqz(4188, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8822PolyExtStep::AndEqz(4189, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8823PolyExtStep::Sub(3953, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8824PolyExtStep::AndEqz(4190, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8825PolyExtStep::Sub(3954, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8826PolyExtStep::AndEqz(4191, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8827PolyExtStep::Sub(3955, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8828PolyExtStep::AndEqz(4192, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8829PolyExtStep::Sub(3956, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8830PolyExtStep::AndEqz(4193, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8831PolyExtStep::Sub(3957, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8832PolyExtStep::AndEqz(4194, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8833PolyExtStep::Sub(3958, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8834PolyExtStep::AndEqz(4195, 4610), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8835PolyExtStep::Sub(3959, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8836PolyExtStep::AndEqz(4196, 4611), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8837PolyExtStep::Sub(3960, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8838PolyExtStep::AndEqz(4197, 4612), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8839PolyExtStep::AndEqz(4198, 4433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8840PolyExtStep::AndEqz(4199, 4434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8841PolyExtStep::AndEqz(4200, 4435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8842PolyExtStep::AndEqz(4201, 4436), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8843PolyExtStep::AndEqz(4202, 4437), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8844PolyExtStep::AndEqz(4203, 4438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8845PolyExtStep::AndEqz(4204, 4439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8846PolyExtStep::AndEqz(4205, 4440), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8847PolyExtStep::AndEqz(4206, 4441), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8848PolyExtStep::AndEqz(4207, 4442), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8849PolyExtStep::AndEqz(4208, 4443), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8850PolyExtStep::AndEqz(4209, 4444), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8851PolyExtStep::AndEqz(4210, 4445), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8852PolyExtStep::AndEqz(4211, 4446), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8853PolyExtStep::AndEqz(4212, 4447), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8854PolyExtStep::AndEqz(4213, 4448), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8855PolyExtStep::AndEqz(4214, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8856PolyExtStep::AndEqz(4215, 900), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8857PolyExtStep::AndEqz(4216, 903), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8858PolyExtStep::AndEqz(4217, 906), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8859PolyExtStep::AndEqz(4218, 943), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8860PolyExtStep::AndEqz(4219, 946), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8861PolyExtStep::AndEqz(4220, 949), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8862PolyExtStep::AndEqz(4221, 955), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8863PolyExtStep::AndEqz(4222, 958), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8864PolyExtStep::AndEqz(4223, 961), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8865PolyExtStep::AndEqz(4224, 967), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8866PolyExtStep::AndEqz(4225, 970), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8867PolyExtStep::AndEqz(4226, 973), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8868PolyExtStep::AndEqz(4227, 979), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8869PolyExtStep::AndEqz(4228, 982), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8870PolyExtStep::AndEqz(4229, 985), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8871PolyExtStep::AndEqz(4230, 1022), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8872PolyExtStep::AndEqz(4231, 1025), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8873PolyExtStep::AndEqz(4232, 1028), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8874PolyExtStep::AndEqz(4233, 1034), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8875PolyExtStep::AndEqz(4234, 1037), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8876PolyExtStep::AndEqz(4235, 1040), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8877PolyExtStep::AndEqz(4236, 1046), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8878PolyExtStep::AndEqz(4237, 1049), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8879PolyExtStep::AndEqz(4238, 1052), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8880PolyExtStep::AndCond(0, 3878, 4239), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8881PolyExtStep::AndEqz(0, 1991), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8882PolyExtStep::Sub(3953, 625), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8883PolyExtStep::Mul(4613, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8884PolyExtStep::Sub(903, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8885PolyExtStep::AndEqz(4241, 4615), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8886PolyExtStep::Sub(628, 4614), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8887PolyExtStep::AndEqz(4242, 4616), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8888PolyExtStep::AndEqz(4243, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8889PolyExtStep::Sub(70, 628), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8890PolyExtStep::AndEqz(0, 625), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8891PolyExtStep::Sub(906, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8892PolyExtStep::AndEqz(4245, 4618), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8893PolyExtStep::Sub(940, 4617), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8894PolyExtStep::AndEqz(4246, 4619), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8895PolyExtStep::AndCond(4244, 2673, 4247), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8896PolyExtStep::Sub(69, 628), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8897PolyExtStep::AndEqz(0, 4618), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8898PolyExtStep::Sub(940, 4620), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8899PolyExtStep::AndEqz(4249, 4621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8900PolyExtStep::AndCond(4248, 3838, 4250), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8901PolyExtStep::AndEqz(4251, 3800), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8902PolyExtStep::AndEqz(4252, 2223), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8903PolyExtStep::Sub(618, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8904PolyExtStep::AndEqz(4253, 4622), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8905PolyExtStep::AndEqz(4254, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8906PolyExtStep::AndEqz(4255, 4580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8907PolyExtStep::AndEqz(4256, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8908PolyExtStep::AndEqz(4257, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8909PolyExtStep::AndEqz(4258, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8910PolyExtStep::AndEqz(4259, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8911PolyExtStep::AndEqz(4260, 1995), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8912PolyExtStep::Sub(3954, 672), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8913PolyExtStep::Mul(4623, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8914PolyExtStep::Sub(946, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8915PolyExtStep::AndEqz(4261, 4625), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8916PolyExtStep::Sub(541, 4624), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8917PolyExtStep::AndEqz(4262, 4626), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8918PolyExtStep::AndEqz(4263, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8919PolyExtStep::Sub(70, 541), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8920PolyExtStep::AndEqz(0, 672), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8921PolyExtStep::AndEqz(4265, 1999), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8922PolyExtStep::Sub(952, 4627), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8923PolyExtStep::AndEqz(4266, 4628), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8924PolyExtStep::AndCond(4264, 2675, 4267), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8925PolyExtStep::Sub(69, 541), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8926PolyExtStep::AndEqz(0, 1999), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8927PolyExtStep::Sub(952, 4629), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8928PolyExtStep::AndEqz(4269, 4630), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8929PolyExtStep::AndCond(4268, 2676, 4270), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8930PolyExtStep::AndEqz(4271, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8931PolyExtStep::AndEqz(4272, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8932PolyExtStep::Sub(669, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8933PolyExtStep::AndEqz(4273, 4631), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8934PolyExtStep::AndEqz(4274, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8935PolyExtStep::AndEqz(4275, 4582), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8936PolyExtStep::AndEqz(4276, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8937PolyExtStep::AndEqz(4277, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8938PolyExtStep::AndEqz(4278, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8939PolyExtStep::AndEqz(4279, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8940PolyExtStep::Sub(955, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8941PolyExtStep::AndEqz(4280, 4632), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8942PolyExtStep::Sub(3955, 567), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8943PolyExtStep::Mul(4633, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8944PolyExtStep::AndEqz(4281, 2004), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8945PolyExtStep::Sub(569, 4634), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8946PolyExtStep::AndEqz(4282, 4635), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8947PolyExtStep::AndEqz(4283, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8948PolyExtStep::Sub(70, 569), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8949PolyExtStep::AndEqz(0, 567), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8950PolyExtStep::Sub(961, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8951PolyExtStep::AndEqz(4285, 4637), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8952PolyExtStep::Sub(964, 4636), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8953PolyExtStep::AndEqz(4286, 4638), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8954PolyExtStep::AndCond(4284, 2682, 4287), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8955PolyExtStep::Sub(69, 569), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8956PolyExtStep::AndEqz(0, 4637), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8957PolyExtStep::Sub(964, 4639), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8958PolyExtStep::AndEqz(4289, 4640), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8959PolyExtStep::AndCond(4288, 3844, 4290), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8960PolyExtStep::AndEqz(4291, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8961PolyExtStep::AndEqz(4292, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8962PolyExtStep::Sub(568, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8963PolyExtStep::AndEqz(4293, 4641), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8964PolyExtStep::AndEqz(4294, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8965PolyExtStep::AndEqz(4295, 4584), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8966PolyExtStep::AndEqz(4296, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8967PolyExtStep::AndEqz(4297, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8968PolyExtStep::AndEqz(4298, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8969PolyExtStep::AndEqz(4299, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8970PolyExtStep::Sub(967, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8971PolyExtStep::AndEqz(4300, 4642), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8972PolyExtStep::Sub(3956, 584), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8973PolyExtStep::Mul(4643, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8974PolyExtStep::Sub(970, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8975PolyExtStep::AndEqz(4301, 4645), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8976PolyExtStep::Sub(732, 4644), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8977PolyExtStep::AndEqz(4302, 4646), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8978PolyExtStep::AndEqz(4303, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8979PolyExtStep::Sub(70, 732), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8980PolyExtStep::AndEqz(0, 584), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8981PolyExtStep::Sub(973, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8982PolyExtStep::AndEqz(4305, 4648), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8983PolyExtStep::Sub(976, 4647), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8984PolyExtStep::AndEqz(4306, 4649), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8985PolyExtStep::AndCond(4304, 2683, 4307), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8986PolyExtStep::Sub(69, 732), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8987PolyExtStep::AndEqz(0, 4648), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8988PolyExtStep::Sub(976, 4650), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8989PolyExtStep::AndEqz(4309, 4651), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8990PolyExtStep::AndCond(4308, 3846, 4310), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8991PolyExtStep::AndEqz(4311, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8992PolyExtStep::AndEqz(4312, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8993PolyExtStep::Sub(583, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8994PolyExtStep::AndEqz(4313, 4652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8995PolyExtStep::AndEqz(4314, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8996PolyExtStep::AndEqz(4315, 4586), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8997PolyExtStep::AndEqz(4316, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8998PolyExtStep::AndEqz(4317, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8999PolyExtStep::AndEqz(4318, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9000PolyExtStep::AndEqz(4319, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9001PolyExtStep::Sub(979, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9002PolyExtStep::AndEqz(4320, 4653), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9003PolyExtStep::Sub(3957, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9004PolyExtStep::Mul(4654, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9005PolyExtStep::Sub(982, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9006PolyExtStep::AndEqz(4321, 4656), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9007PolyExtStep::Sub(747, 4655), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9008PolyExtStep::AndEqz(4322, 4657), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9009PolyExtStep::AndEqz(4323, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9010PolyExtStep::Sub(70, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9011PolyExtStep::AndEqz(0, 739), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9012PolyExtStep::Sub(985, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9013PolyExtStep::AndEqz(4325, 4659), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9014PolyExtStep::Sub(1019, 4658), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9015PolyExtStep::AndEqz(4326, 4660), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9016PolyExtStep::AndCond(4324, 2685, 4327), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9017PolyExtStep::Sub(69, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9018PolyExtStep::AndEqz(0, 4659), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9019PolyExtStep::Sub(1019, 4661), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9020PolyExtStep::AndEqz(4329, 4662), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9021PolyExtStep::AndCond(4328, 2686, 4330), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9022PolyExtStep::AndEqz(4331, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9023PolyExtStep::AndEqz(4332, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9024PolyExtStep::Sub(738, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9025PolyExtStep::AndEqz(4333, 4663), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9026PolyExtStep::AndEqz(4334, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9027PolyExtStep::AndEqz(4335, 4588), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9028PolyExtStep::AndEqz(4336, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9029PolyExtStep::AndEqz(4337, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9030PolyExtStep::AndEqz(4338, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9031PolyExtStep::AndEqz(4339, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9032PolyExtStep::Sub(1022, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9033PolyExtStep::AndEqz(4340, 4664), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9034PolyExtStep::Sub(3958, 759), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9035PolyExtStep::Mul(4665, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9036PolyExtStep::Sub(1025, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9037PolyExtStep::AndEqz(4341, 4667), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9038PolyExtStep::Sub(760, 4666), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9039PolyExtStep::AndEqz(4342, 4668), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9040PolyExtStep::AndEqz(4343, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9041PolyExtStep::Sub(70, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9042PolyExtStep::AndEqz(0, 759), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9043PolyExtStep::Sub(1028, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9044PolyExtStep::AndEqz(4345, 4670), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9045PolyExtStep::Sub(1031, 4669), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9046PolyExtStep::AndEqz(4346, 4671), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9047PolyExtStep::AndCond(4344, 3852, 4347), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9048PolyExtStep::Sub(69, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9049PolyExtStep::AndEqz(0, 4670), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9050PolyExtStep::Sub(1031, 4672), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9051PolyExtStep::AndEqz(4349, 4673), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9052PolyExtStep::AndCond(4348, 3988, 4350), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9053PolyExtStep::AndEqz(4351, 3907), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9054PolyExtStep::AndEqz(4352, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9055PolyExtStep::Sub(758, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9056PolyExtStep::AndEqz(4353, 4674), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9057PolyExtStep::AndEqz(4354, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9058PolyExtStep::AndEqz(4355, 4590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9059PolyExtStep::AndEqz(4356, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9060PolyExtStep::AndEqz(4357, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9061PolyExtStep::AndEqz(4358, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9062PolyExtStep::AndEqz(4359, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9063PolyExtStep::Sub(1034, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9064PolyExtStep::AndEqz(4360, 4675), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9065PolyExtStep::Sub(3959, 788), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9066PolyExtStep::Mul(4676, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9067PolyExtStep::Sub(1037, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9068PolyExtStep::AndEqz(4361, 4678), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9069PolyExtStep::Sub(791, 4677), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9070PolyExtStep::AndEqz(4362, 4679), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9071PolyExtStep::AndEqz(4363, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9072PolyExtStep::Sub(70, 791), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9073PolyExtStep::AndEqz(0, 788), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9074PolyExtStep::Sub(1040, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9075PolyExtStep::AndEqz(4365, 4681), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9076PolyExtStep::Sub(1043, 4680), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9077PolyExtStep::AndEqz(4366, 4682), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9078PolyExtStep::AndCond(4364, 3750, 4367), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9079PolyExtStep::Sub(69, 791), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9080PolyExtStep::AndEqz(0, 4681), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9081PolyExtStep::Sub(1043, 4683), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9082PolyExtStep::AndEqz(4369, 4684), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9083PolyExtStep::AndCond(4368, 3752, 4370), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9084PolyExtStep::AndEqz(4371, 3914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9085PolyExtStep::AndEqz(4372, 2942), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9086PolyExtStep::Sub(785, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9087PolyExtStep::AndEqz(4373, 4685), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9088PolyExtStep::AndEqz(4374, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9089PolyExtStep::AndEqz(4375, 4592), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9090PolyExtStep::AndEqz(4376, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9091PolyExtStep::AndEqz(4377, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9092PolyExtStep::AndEqz(4378, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9093PolyExtStep::AndEqz(4379, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9094PolyExtStep::Sub(1046, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9095PolyExtStep::AndEqz(4380, 4686), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9096PolyExtStep::Sub(3960, 815), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9097PolyExtStep::Mul(4687, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9098PolyExtStep::Sub(1049, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9099PolyExtStep::AndEqz(4381, 4689), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9100PolyExtStep::Sub(818, 4688), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9101PolyExtStep::AndEqz(4382, 4690), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9102PolyExtStep::Sub(1, 3751), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9103PolyExtStep::Mul(3751, 4691), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9104PolyExtStep::AndEqz(4383, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9105PolyExtStep::Sub(70, 818), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9106PolyExtStep::AndEqz(0, 815), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9107PolyExtStep::Sub(1052, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9108PolyExtStep::AndEqz(4385, 4694), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9109PolyExtStep::Sub(1055, 4693), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9110PolyExtStep::AndEqz(4386, 4695), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9111PolyExtStep::AndCond(4384, 3751, 4387), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9112PolyExtStep::Sub(69, 818), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9113PolyExtStep::AndEqz(0, 4694), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9114PolyExtStep::Sub(1055, 4696), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9115PolyExtStep::AndEqz(4389, 4697), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9116PolyExtStep::AndCond(4388, 4691, 4390), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9117PolyExtStep::AndEqz(4391, 3925), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9118PolyExtStep::AndEqz(4392, 3926), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9119PolyExtStep::Sub(812, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9120PolyExtStep::AndEqz(4393, 4698), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9121PolyExtStep::AndEqz(4394, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9122PolyExtStep::AndEqz(4395, 4594), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9123PolyExtStep::AndEqz(4396, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9124PolyExtStep::AndEqz(4397, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9125PolyExtStep::AndEqz(4398, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9126PolyExtStep::AndEqz(4399, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9127PolyExtStep::Get(783), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9128PolyExtStep::Get(784), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9129PolyExtStep::Sub(1, 4699), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9130PolyExtStep::Mul(4699, 4701), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9131PolyExtStep::AndEqz(4400, 4702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9132PolyExtStep::Mul(3879, 4700), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9133PolyExtStep::Sub(4703, 4701), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9134PolyExtStep::AndEqz(4401, 4704), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9135PolyExtStep::Mul(4699, 3879), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9136PolyExtStep::AndEqz(4402, 4705), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9137PolyExtStep::Mul(4699, 4700), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9138PolyExtStep::AndEqz(4403, 4706), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9139PolyExtStep::Mul(4699, 13), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9140PolyExtStep::Mul(4701, 57), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9141PolyExtStep::Add(4707, 4708), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9142PolyExtStep::Mul(4579, 4709), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :311:25) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9143PolyExtStep::Add(4578, 4710), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :310:46) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9144PolyExtStep::AndEqz(4404, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9145PolyExtStep::AndEqz(4405, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9146PolyExtStep::AndEqz(4406, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9147PolyExtStep::AndEqz(4407, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9148PolyExtStep::AndEqz(4408, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9149PolyExtStep::AndEqz(4409, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9150PolyExtStep::Sub(4711, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9151PolyExtStep::AndEqz(4410, 4712), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9152PolyExtStep::AndEqz(4411, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9153PolyExtStep::AndEqz(4412, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9154PolyExtStep::AndEqz(4413, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9155PolyExtStep::AndEqz(4414, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9156PolyExtStep::AndEqz(4415, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9157PolyExtStep::AndEqz(4416, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9158PolyExtStep::AndEqz(4417, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9159PolyExtStep::AndEqz(4418, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9160PolyExtStep::AndEqz(4419, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9161PolyExtStep::AndEqz(4420, 4610), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9162PolyExtStep::AndEqz(4421, 4611), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9163PolyExtStep::AndEqz(4422, 4612), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9164PolyExtStep::AndEqz(4423, 4433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9165PolyExtStep::AndEqz(4424, 4434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9166PolyExtStep::AndEqz(4425, 4435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9167PolyExtStep::AndEqz(4426, 4436), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9168PolyExtStep::AndEqz(4427, 4437), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9169PolyExtStep::AndEqz(4428, 4438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9170PolyExtStep::AndEqz(4429, 4439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9171PolyExtStep::AndEqz(4430, 4440), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9172PolyExtStep::AndEqz(4431, 4441), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9173PolyExtStep::AndEqz(4432, 4442), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9174PolyExtStep::AndEqz(4433, 4443), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9175PolyExtStep::AndEqz(4434, 4444), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9176PolyExtStep::AndEqz(4435, 4445), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9177PolyExtStep::AndEqz(4436, 4446), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9178PolyExtStep::AndEqz(4437, 4447), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9179PolyExtStep::AndEqz(4438, 4448), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9180PolyExtStep::AndEqz(4439, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9181PolyExtStep::AndCond(4240, 4570, 4440), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9182PolyExtStep::AndEqz(4441, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9183PolyExtStep::AndEqz(4442, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9184PolyExtStep::AndCond(4099, 389, 4443), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9185PolyExtStep::Sub(54, 3876), // loc(callsite( builtin Sub at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:40) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9186PolyExtStep::Mul(4713, 71), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:57) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9187PolyExtStep::AndEqz(0, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9188PolyExtStep::AndEqz(4445, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9189PolyExtStep::AndEqz(4446, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9190PolyExtStep::AndEqz(4447, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9191PolyExtStep::AndEqz(4448, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9192PolyExtStep::AndEqz(4449, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9193PolyExtStep::Add(2682, 2683), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9194PolyExtStep::Add(4715, 2685), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9195PolyExtStep::Add(4716, 3852), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9196PolyExtStep::Add(4717, 3750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9197PolyExtStep::Add(4718, 3751), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9198PolyExtStep::Sub(4719, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9199PolyExtStep::AndEqz(4450, 4720), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9200PolyExtStep::Mul(2685, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9201PolyExtStep::Mul(3852, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9202PolyExtStep::Mul(3750, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9203PolyExtStep::Mul(3751, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9204PolyExtStep::Add(2683, 4721), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9205PolyExtStep::Add(4725, 4722), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9206PolyExtStep::Add(4726, 4723), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9207PolyExtStep::Add(4727, 4724), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9208PolyExtStep::Sub(4728, 2675), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9209PolyExtStep::AndEqz(4451, 4729), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9210PolyExtStep::AndEqz(4452, 1991), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9211PolyExtStep::Sub(2673, 625), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9212PolyExtStep::Mul(4730, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9213PolyExtStep::Sub(1058, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9214PolyExtStep::AndEqz(4453, 4732), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9215PolyExtStep::Sub(1061, 4731), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9216PolyExtStep::AndEqz(4454, 4733), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9217PolyExtStep::Sub(1, 4716), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9218PolyExtStep::Add(4714, 1), // loc(callsite( builtin Add at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9219PolyExtStep::Sub(2673, 4735), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9220PolyExtStep::AndEqz(0, 4615), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9221PolyExtStep::Sub(4736, 628), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9222PolyExtStep::Mul(4737, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9223PolyExtStep::Sub(1064, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9224PolyExtStep::AndEqz(4456, 4739), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9225PolyExtStep::Sub(2659, 4738), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9226PolyExtStep::AndEqz(4457, 4740), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :450:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9227PolyExtStep::AndCond(4455, 4716, 4458), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9228PolyExtStep::Sub(4714, 1), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9229PolyExtStep::Sub(4741, 2673), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9230PolyExtStep::Sub(4742, 628), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9231PolyExtStep::Mul(4743, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9232PolyExtStep::Sub(2659, 4744), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9233PolyExtStep::AndEqz(4457, 4745), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :452:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9234PolyExtStep::AndCond(4459, 4734, 4460), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9235PolyExtStep::Sub(2675, 371), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :455:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9236PolyExtStep::AndEqz(4461, 4702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :455:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9237PolyExtStep::Sub(4746, 4699), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :455:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9238PolyExtStep::AndEqz(4462, 4747), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :455:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9239PolyExtStep::Mul(2673, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9240PolyExtStep::Sub(54, 4748), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9241PolyExtStep::Mul(2673, 7), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9242PolyExtStep::Add(4750, 1), // loc(callsite( builtin Add at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:38) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9243PolyExtStep::Mul(4751, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9244PolyExtStep::Sub(54, 4752), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9245PolyExtStep::Sub(4749, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9246PolyExtStep::AndEqz(3463, 4754), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9247PolyExtStep::AndEqz(4464, 3761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9248PolyExtStep::AndEqz(4465, 3762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9249PolyExtStep::AndEqz(4466, 3763), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9250PolyExtStep::AndEqz(4467, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9251PolyExtStep::AndEqz(4468, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9252PolyExtStep::Sub(4753, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9253PolyExtStep::AndEqz(4469, 4755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9254PolyExtStep::Sub(1, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9255PolyExtStep::AndEqz(4470, 4756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9256PolyExtStep::AndEqz(4471, 4569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9257PolyExtStep::AndEqz(4472, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9258PolyExtStep::AndEqz(4473, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9259PolyExtStep::AndEqz(4474, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9260PolyExtStep::AndEqz(4475, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9261PolyExtStep::AndEqz(4476, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9262PolyExtStep::AndEqz(4477, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9263PolyExtStep::AndEqz(4478, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9264PolyExtStep::AndEqz(4479, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9265PolyExtStep::AndEqz(4480, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9266PolyExtStep::AndEqz(4481, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9267PolyExtStep::AndEqz(4482, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9268PolyExtStep::AndEqz(4483, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9269PolyExtStep::AndEqz(4484, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9270PolyExtStep::AndEqz(4485, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9271PolyExtStep::AndEqz(4486, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9272PolyExtStep::AndEqz(4487, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9273PolyExtStep::AndEqz(4488, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9274PolyExtStep::AndEqz(4489, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9275PolyExtStep::AndEqz(4490, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9276PolyExtStep::AndEqz(4491, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9277PolyExtStep::AndEqz(4492, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9278PolyExtStep::AndEqz(4493, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9279PolyExtStep::AndEqz(4494, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9280PolyExtStep::AndEqz(4495, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9281PolyExtStep::AndEqz(4496, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9282PolyExtStep::AndCond(4463, 2682, 4497), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9283PolyExtStep::Sub(2673, 72), // loc(callsite( builtin Sub at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :367:13) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9284PolyExtStep::Mul(4757, 20), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :380:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9285PolyExtStep::AndEqz(4464, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9286PolyExtStep::AndEqz(4499, 3762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9287PolyExtStep::AndEqz(4500, 3763), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9288PolyExtStep::AndEqz(4501, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9289PolyExtStep::AndEqz(4502, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9290PolyExtStep::Sub(4758, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9291PolyExtStep::AndEqz(4503, 4759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9292PolyExtStep::Sub(24, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9293PolyExtStep::AndEqz(4504, 4760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9294PolyExtStep::Sub(1, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9295PolyExtStep::AndEqz(4505, 4761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9296PolyExtStep::AndEqz(4506, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9297PolyExtStep::AndEqz(4507, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9298PolyExtStep::AndEqz(4508, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9299PolyExtStep::AndEqz(4509, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9300PolyExtStep::AndEqz(4510, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9301PolyExtStep::AndEqz(4511, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9302PolyExtStep::AndEqz(4512, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9303PolyExtStep::AndEqz(4513, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9304PolyExtStep::AndEqz(4514, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9305PolyExtStep::AndEqz(4515, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9306PolyExtStep::AndEqz(4516, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9307PolyExtStep::AndEqz(4517, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9308PolyExtStep::AndEqz(4518, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9309PolyExtStep::AndEqz(4519, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9310PolyExtStep::AndEqz(4520, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9311PolyExtStep::AndEqz(4521, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9312PolyExtStep::AndEqz(4522, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9313PolyExtStep::AndEqz(4523, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9314PolyExtStep::AndEqz(4524, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9315PolyExtStep::AndEqz(4525, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9316PolyExtStep::AndEqz(4526, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9317PolyExtStep::AndEqz(4527, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9318PolyExtStep::AndEqz(4528, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9319PolyExtStep::AndEqz(4529, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9320PolyExtStep::AndEqz(4530, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9321PolyExtStep::AndCond(4498, 2683, 4531), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9322PolyExtStep::Sub(55, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9323PolyExtStep::AndEqz(3463, 4762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9324PolyExtStep::AndEqz(4533, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9325PolyExtStep::AndEqz(4534, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9326PolyExtStep::AndEqz(4535, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9327PolyExtStep::Sub(1, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9328PolyExtStep::AndEqz(4536, 4763), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9329PolyExtStep::AndEqz(4537, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9330PolyExtStep::AndEqz(4538, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9331PolyExtStep::AndEqz(4539, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9332PolyExtStep::Sub(7, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9333PolyExtStep::AndEqz(4540, 4764), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9334PolyExtStep::AndEqz(4541, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9335PolyExtStep::AndEqz(4542, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9336PolyExtStep::AndEqz(4543, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9337PolyExtStep::AndEqz(4544, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9338PolyExtStep::AndEqz(4545, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9339PolyExtStep::AndEqz(4546, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9340PolyExtStep::AndEqz(4547, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9341PolyExtStep::AndEqz(4548, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9342PolyExtStep::AndEqz(4549, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9343PolyExtStep::AndEqz(4550, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9344PolyExtStep::AndEqz(4551, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9345PolyExtStep::AndEqz(4552, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9346PolyExtStep::AndEqz(4553, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9347PolyExtStep::AndEqz(4554, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9348PolyExtStep::AndEqz(4555, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9349PolyExtStep::AndEqz(4556, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9350PolyExtStep::AndEqz(4557, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9351PolyExtStep::AndEqz(4558, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9352PolyExtStep::AndEqz(4559, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9353PolyExtStep::AndEqz(4560, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9354PolyExtStep::AndEqz(4561, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9355PolyExtStep::AndEqz(4562, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9356PolyExtStep::AndEqz(4563, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9357PolyExtStep::AndEqz(4564, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9358PolyExtStep::AndEqz(4565, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9359PolyExtStep::AndCond(4532, 2685, 4566), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9360PolyExtStep::AndEqz(4499, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9361PolyExtStep::Sub(7, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9362PolyExtStep::AndEqz(4568, 4765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9363PolyExtStep::AndEqz(4569, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9364PolyExtStep::AndEqz(4570, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9365PolyExtStep::AndEqz(4571, 4759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9366PolyExtStep::AndEqz(4572, 4760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9367PolyExtStep::Sub(6, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9368PolyExtStep::AndEqz(4573, 4766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9369PolyExtStep::AndEqz(4574, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9370PolyExtStep::AndEqz(4575, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9371PolyExtStep::AndEqz(4576, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9372PolyExtStep::AndEqz(4577, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9373PolyExtStep::AndEqz(4578, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9374PolyExtStep::AndEqz(4579, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9375PolyExtStep::AndEqz(4580, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9376PolyExtStep::AndEqz(4581, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9377PolyExtStep::AndEqz(4582, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9378PolyExtStep::AndEqz(4583, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9379PolyExtStep::AndEqz(4584, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9380PolyExtStep::AndEqz(4585, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9381PolyExtStep::AndEqz(4586, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9382PolyExtStep::AndEqz(4587, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9383PolyExtStep::AndEqz(4588, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9384PolyExtStep::AndEqz(4589, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9385PolyExtStep::AndEqz(4590, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9386PolyExtStep::AndEqz(4591, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9387PolyExtStep::AndEqz(4592, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9388PolyExtStep::AndEqz(4593, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9389PolyExtStep::AndEqz(4594, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9390PolyExtStep::AndEqz(4595, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9391PolyExtStep::AndEqz(4596, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9392PolyExtStep::AndEqz(4597, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9393PolyExtStep::AndEqz(4598, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9394PolyExtStep::AndCond(4567, 3852, 4599), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9395PolyExtStep::AndEqz(4465, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9396PolyExtStep::AndEqz(4601, 4765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9397PolyExtStep::AndEqz(4602, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9398PolyExtStep::AndEqz(4603, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9399PolyExtStep::AndEqz(4604, 4755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9400PolyExtStep::AndEqz(4605, 4756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9401PolyExtStep::Sub(5, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9402PolyExtStep::AndEqz(4606, 4767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9403PolyExtStep::AndEqz(4607, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9404PolyExtStep::AndEqz(4608, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9405PolyExtStep::AndEqz(4609, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9406PolyExtStep::AndEqz(4610, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9407PolyExtStep::AndEqz(4611, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9408PolyExtStep::AndEqz(4612, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9409PolyExtStep::AndEqz(4613, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9410PolyExtStep::AndEqz(4614, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9411PolyExtStep::AndEqz(4615, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9412PolyExtStep::AndEqz(4616, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9413PolyExtStep::AndEqz(4617, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9414PolyExtStep::AndEqz(4618, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9415PolyExtStep::AndEqz(4619, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9416PolyExtStep::AndEqz(4620, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9417PolyExtStep::AndEqz(4621, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9418PolyExtStep::AndEqz(4622, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9419PolyExtStep::AndEqz(4623, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9420PolyExtStep::AndEqz(4624, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9421PolyExtStep::AndEqz(4625, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9422PolyExtStep::AndEqz(4626, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9423PolyExtStep::AndEqz(4627, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9424PolyExtStep::AndEqz(4628, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9425PolyExtStep::AndEqz(4629, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9426PolyExtStep::AndEqz(4630, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9427PolyExtStep::AndEqz(4631, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9428PolyExtStep::AndCond(4600, 3750, 4632), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9429PolyExtStep::Sub(54, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9430PolyExtStep::AndEqz(3463, 4768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9431PolyExtStep::AndEqz(4634, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9432PolyExtStep::AndEqz(4635, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9433PolyExtStep::AndEqz(4636, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9434PolyExtStep::Sub(4, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9435PolyExtStep::AndEqz(4637, 4769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9436PolyExtStep::AndEqz(4638, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9437PolyExtStep::AndEqz(4639, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9438PolyExtStep::AndEqz(4640, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9439PolyExtStep::Sub(4, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9440PolyExtStep::AndEqz(4641, 4770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9441PolyExtStep::AndEqz(4642, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9442PolyExtStep::AndEqz(4643, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9443PolyExtStep::AndEqz(4644, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9444PolyExtStep::AndEqz(4645, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9445PolyExtStep::AndEqz(4646, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9446PolyExtStep::AndEqz(4647, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9447PolyExtStep::AndEqz(4648, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9448PolyExtStep::AndEqz(4649, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9449PolyExtStep::AndEqz(4650, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9450PolyExtStep::AndEqz(4651, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9451PolyExtStep::AndEqz(4652, 3779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9452PolyExtStep::AndEqz(4653, 3780), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9453PolyExtStep::AndEqz(4654, 3781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9454PolyExtStep::AndEqz(4655, 3782), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9455PolyExtStep::AndEqz(4656, 3783), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9456PolyExtStep::AndEqz(4657, 3784), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9457PolyExtStep::AndEqz(4658, 3785), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9458PolyExtStep::AndEqz(4659, 3786), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9459PolyExtStep::AndEqz(4660, 3787), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9460PolyExtStep::AndEqz(4661, 3788), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9461PolyExtStep::AndEqz(4662, 3789), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9462PolyExtStep::AndEqz(4663, 3790), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9463PolyExtStep::AndEqz(4664, 3791), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9464PolyExtStep::AndEqz(4665, 3792), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9465PolyExtStep::AndEqz(4666, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9466PolyExtStep::AndCond(4633, 3751, 4667), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :456:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :477:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9467PolyExtStep::AndEqz(4668, 536), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9468PolyExtStep::AndEqz(4669, 611), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9469PolyExtStep::AndEqz(4670, 635), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9470PolyExtStep::AndEqz(4671, 662), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9471PolyExtStep::AndEqz(4672, 548), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9472PolyExtStep::AndEqz(4673, 561), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9473PolyExtStep::AndEqz(4674, 570), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9474PolyExtStep::AndEqz(4675, 575), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9475PolyExtStep::AndEqz(4676, 731), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9476PolyExtStep::AndEqz(4677, 737), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9477PolyExtStep::AndEqz(4678, 748), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9478PolyExtStep::AndEqz(4679, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9479PolyExtStep::AndEqz(4680, 761), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9480PolyExtStep::AndEqz(4681, 782), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9481PolyExtStep::AndEqz(4682, 794), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9482PolyExtStep::AndEqz(4683, 809), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9483PolyExtStep::AndEqz(4684, 821), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9484PolyExtStep::AndEqz(4685, 827), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9485PolyExtStep::AndEqz(4686, 864), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9486PolyExtStep::AndEqz(4687, 870), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9487PolyExtStep::AndEqz(4688, 876), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9488PolyExtStep::AndEqz(4689, 882), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9489PolyExtStep::AndEqz(4690, 888), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9490PolyExtStep::AndEqz(4691, 894), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9491PolyExtStep::AndEqz(4692, 906), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9492PolyExtStep::AndEqz(4693, 943), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9493PolyExtStep::AndEqz(4694, 946), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9494PolyExtStep::AndEqz(4695, 949), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9495PolyExtStep::AndEqz(4696, 955), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9496PolyExtStep::AndEqz(4697, 958), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9497PolyExtStep::AndEqz(4698, 961), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9498PolyExtStep::AndEqz(4699, 967), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9499PolyExtStep::AndEqz(4700, 970), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9500PolyExtStep::AndEqz(4701, 973), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9501PolyExtStep::AndEqz(4702, 979), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9502PolyExtStep::AndEqz(4703, 982), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9503PolyExtStep::AndEqz(4704, 985), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9504PolyExtStep::AndEqz(4705, 1022), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9505PolyExtStep::AndEqz(4706, 1025), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9506PolyExtStep::AndEqz(4707, 1028), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9507PolyExtStep::AndEqz(4708, 1034), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9508PolyExtStep::AndEqz(4709, 1037), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9509PolyExtStep::AndEqz(4710, 1040), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9510PolyExtStep::AndEqz(4711, 1046), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9511PolyExtStep::AndEqz(4712, 1049), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9512PolyExtStep::AndEqz(4713, 1052), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9513PolyExtStep::AndCond(4444, 392, 4714), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9514PolyExtStep::Sub(3969, 625), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9515PolyExtStep::Mul(4771, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9516PolyExtStep::Sub(628, 4772), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9517PolyExtStep::AndEqz(4242, 4773), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9518PolyExtStep::AndEqz(4716, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9519PolyExtStep::AndCond(4717, 2673, 4247), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9520PolyExtStep::AndCond(4718, 3838, 4250), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9521PolyExtStep::AndEqz(4719, 3800), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9522PolyExtStep::AndEqz(4720, 2223), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9523PolyExtStep::AndEqz(4721, 4622), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9524PolyExtStep::AndEqz(4722, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9525PolyExtStep::AndEqz(4723, 3883), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9526PolyExtStep::AndEqz(4724, 3737), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9527PolyExtStep::AndEqz(4725, 3806), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9528PolyExtStep::AndEqz(4726, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9529PolyExtStep::AndEqz(4727, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9530PolyExtStep::AndEqz(4728, 1995), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9531PolyExtStep::Sub(3970, 672), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9532PolyExtStep::Mul(4774, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9533PolyExtStep::AndEqz(4729, 4625), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9534PolyExtStep::Sub(541, 4775), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9535PolyExtStep::AndEqz(4730, 4776), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9536PolyExtStep::AndEqz(4731, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9537PolyExtStep::AndCond(4732, 2675, 4267), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9538PolyExtStep::AndCond(4733, 2676, 4270), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9539PolyExtStep::AndEqz(4734, 3810), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9540PolyExtStep::AndEqz(4735, 3811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9541PolyExtStep::AndEqz(4736, 4631), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9542PolyExtStep::AndEqz(4737, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9543PolyExtStep::AndEqz(4738, 3887), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9544PolyExtStep::AndEqz(4739, 2168), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9545PolyExtStep::AndEqz(4740, 3817), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9546PolyExtStep::AndEqz(4741, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9547PolyExtStep::AndEqz(4742, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9548PolyExtStep::AndEqz(4743, 4632), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9549PolyExtStep::Sub(3971, 567), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9550PolyExtStep::Mul(4777, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9551PolyExtStep::AndEqz(4744, 2004), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9552PolyExtStep::Sub(569, 4778), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9553PolyExtStep::AndEqz(4745, 4779), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9554PolyExtStep::AndEqz(4746, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9555PolyExtStep::AndCond(4747, 2682, 4287), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9556PolyExtStep::AndCond(4748, 3844, 4290), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9557PolyExtStep::AndEqz(4749, 3821), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9558PolyExtStep::AndEqz(4750, 3822), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9559PolyExtStep::AndEqz(4751, 4641), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9560PolyExtStep::AndEqz(4752, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9561PolyExtStep::AndEqz(4753, 3891), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9562PolyExtStep::AndEqz(4754, 3827), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9563PolyExtStep::AndEqz(4755, 3828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9564PolyExtStep::AndEqz(4756, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9565PolyExtStep::AndEqz(4757, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9566PolyExtStep::AndEqz(4758, 4642), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9567PolyExtStep::Sub(3972, 584), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9568PolyExtStep::Mul(4780, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9569PolyExtStep::AndEqz(4759, 4645), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9570PolyExtStep::Sub(732, 4781), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9571PolyExtStep::AndEqz(4760, 4782), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9572PolyExtStep::AndEqz(4761, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9573PolyExtStep::AndCond(4762, 2683, 4307), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9574PolyExtStep::AndCond(4763, 3846, 4310), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9575PolyExtStep::AndEqz(4764, 1619), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9576PolyExtStep::AndEqz(4765, 3832), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9577PolyExtStep::AndEqz(4766, 4652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9578PolyExtStep::AndEqz(4767, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9579PolyExtStep::AndEqz(4768, 3895), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9580PolyExtStep::AndEqz(4769, 2174), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9581PolyExtStep::AndEqz(4770, 3837), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9582PolyExtStep::AndEqz(4771, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9583PolyExtStep::AndEqz(4772, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9584PolyExtStep::AndEqz(4773, 4653), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9585PolyExtStep::Sub(3973, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9586PolyExtStep::Mul(4783, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9587PolyExtStep::AndEqz(4774, 4656), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9588PolyExtStep::Sub(747, 4784), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9589PolyExtStep::AndEqz(4775, 4785), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9590PolyExtStep::AndEqz(4776, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9591PolyExtStep::AndCond(4777, 2685, 4327), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9592PolyExtStep::AndCond(4778, 2686, 4330), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9593PolyExtStep::AndEqz(4779, 740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9594PolyExtStep::AndEqz(4780, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9595PolyExtStep::AndEqz(4781, 4663), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9596PolyExtStep::AndEqz(4782, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9597PolyExtStep::AndEqz(4783, 3900), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9598PolyExtStep::AndEqz(4784, 3902), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9599PolyExtStep::AndEqz(4785, 3903), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9600PolyExtStep::AndEqz(4786, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9601PolyExtStep::AndEqz(4787, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9602PolyExtStep::AndEqz(4788, 4664), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9603PolyExtStep::Sub(3974, 759), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9604PolyExtStep::Mul(4786, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9605PolyExtStep::AndEqz(4789, 4667), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9606PolyExtStep::Sub(760, 4787), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9607PolyExtStep::AndEqz(4790, 4788), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9608PolyExtStep::AndEqz(4791, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9609PolyExtStep::AndCond(4792, 3852, 4347), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9610PolyExtStep::AndCond(4793, 3988, 4350), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9611PolyExtStep::AndEqz(4794, 3907), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9612PolyExtStep::AndEqz(4795, 2990), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9613PolyExtStep::AndEqz(4796, 4674), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9614PolyExtStep::AndEqz(4797, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9615PolyExtStep::AndEqz(4798, 3908), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9616PolyExtStep::AndEqz(4799, 3909), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9617PolyExtStep::AndEqz(4800, 3910), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9618PolyExtStep::AndEqz(4801, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9619PolyExtStep::AndEqz(4802, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9620PolyExtStep::AndEqz(4803, 4675), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9621PolyExtStep::Sub(3975, 788), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9622PolyExtStep::Mul(4789, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9623PolyExtStep::AndEqz(4804, 4678), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9624PolyExtStep::Sub(791, 4790), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9625PolyExtStep::AndEqz(4805, 4791), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9626PolyExtStep::AndEqz(4806, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9627PolyExtStep::AndCond(4807, 3750, 4367), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9628PolyExtStep::AndCond(4808, 3752, 4370), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9629PolyExtStep::AndEqz(4809, 3914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9630PolyExtStep::AndEqz(4810, 2942), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9631PolyExtStep::AndEqz(4811, 4685), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9632PolyExtStep::AndEqz(4812, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9633PolyExtStep::AndEqz(4813, 3916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9634PolyExtStep::AndEqz(4814, 3920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9635PolyExtStep::AndEqz(4815, 3921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9636PolyExtStep::AndEqz(4816, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9637PolyExtStep::AndEqz(4817, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9638PolyExtStep::AndEqz(4818, 4686), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9639PolyExtStep::Sub(3976, 815), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9640PolyExtStep::Mul(4792, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9641PolyExtStep::AndEqz(4819, 4689), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9642PolyExtStep::Sub(818, 4793), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9643PolyExtStep::AndEqz(4820, 4794), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9644PolyExtStep::AndEqz(4821, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9645PolyExtStep::AndCond(4822, 3751, 4387), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9646PolyExtStep::AndCond(4823, 4691, 4390), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9647PolyExtStep::AndEqz(4824, 3925), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9648PolyExtStep::AndEqz(4825, 3926), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9649PolyExtStep::AndEqz(4826, 4698), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9650PolyExtStep::AndEqz(4827, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9651PolyExtStep::AndEqz(4828, 3928), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9652PolyExtStep::AndEqz(4829, 3932), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9653PolyExtStep::AndEqz(4830, 3933), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9654PolyExtStep::AndEqz(4831, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9655PolyExtStep::AndEqz(4832, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9656PolyExtStep::AndEqz(4833, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9657PolyExtStep::AndEqz(4834, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9658PolyExtStep::AndEqz(4835, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9659PolyExtStep::AndEqz(4836, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9660PolyExtStep::AndEqz(4837, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9661PolyExtStep::AndEqz(4838, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9662PolyExtStep::Sub(13, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9663PolyExtStep::AndEqz(4839, 4795), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9664PolyExtStep::AndEqz(4840, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9665PolyExtStep::AndEqz(4841, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9666PolyExtStep::AndEqz(4842, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9667PolyExtStep::AndEqz(4843, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9668PolyExtStep::AndEqz(4844, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9669PolyExtStep::AndEqz(4845, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9670PolyExtStep::AndEqz(4846, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9671PolyExtStep::AndEqz(4847, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9672PolyExtStep::AndEqz(4848, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9673PolyExtStep::AndEqz(4849, 4610), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9674PolyExtStep::AndEqz(4850, 4611), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9675PolyExtStep::AndEqz(4851, 4612), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9676PolyExtStep::AndEqz(4852, 4433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9677PolyExtStep::AndEqz(4853, 4434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9678PolyExtStep::AndEqz(4854, 4435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9679PolyExtStep::AndEqz(4855, 4436), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9680PolyExtStep::AndEqz(4856, 4437), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9681PolyExtStep::AndEqz(4857, 4438), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9682PolyExtStep::AndEqz(4858, 4439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9683PolyExtStep::AndEqz(4859, 4440), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9684PolyExtStep::AndEqz(4860, 4441), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9685PolyExtStep::AndEqz(4861, 4442), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9686PolyExtStep::AndEqz(4862, 4443), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9687PolyExtStep::AndEqz(4863, 4444), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9688PolyExtStep::AndEqz(4864, 4445), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9689PolyExtStep::AndEqz(4865, 4446), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9690PolyExtStep::AndEqz(4866, 4447), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9691PolyExtStep::AndEqz(4867, 4448), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9692PolyExtStep::AndEqz(4868, 3799), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9693PolyExtStep::AndEqz(4869, 1058), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9694PolyExtStep::AndEqz(4870, 1064), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9695PolyExtStep::AndCond(4715, 395, 4871), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9696PolyExtStep::AndCond(3454, 446, 4872), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
9697PolyExtStep::Add(373, 68), // loc(callsite( builtin Add at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :485:45) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9698PolyExtStep::Sub(368, 4796), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :485:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9699PolyExtStep::Sub(587, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :484:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9700PolyExtStep::AndEqz(0, 4798), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :484:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9701PolyExtStep::AndEqz(4874, 3168), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :484:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9702PolyExtStep::AndEqz(4875, 4797), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :485:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9703PolyExtStep::Sub(3952, 6), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9704PolyExtStep::AndEqz(0, 606), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9705PolyExtStep::Mul(4799, 611), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9706PolyExtStep::Sub(4800, 605), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9707PolyExtStep::AndEqz(4877, 4801), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9708PolyExtStep::Mul(604, 4799), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9709PolyExtStep::AndEqz(4878, 4802), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9710PolyExtStep::Mul(604, 611), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9711PolyExtStep::AndEqz(4879, 4803), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9712PolyExtStep::Sub(3952, 2), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9713PolyExtStep::AndEqz(4880, 620), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9714PolyExtStep::Mul(4804, 625), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9715PolyExtStep::Sub(4805, 619), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9716PolyExtStep::AndEqz(4881, 4806), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9717PolyExtStep::Mul(618, 4804), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9718PolyExtStep::AndEqz(4882, 4807), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9719PolyExtStep::Mul(618, 625), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9720PolyExtStep::AndEqz(4883, 4808), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9721PolyExtStep::Sub(3881, 1), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :243:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9722PolyExtStep::AndEqz(4884, 630), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9723PolyExtStep::Mul(4809, 635), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9724PolyExtStep::Sub(4810, 629), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9725PolyExtStep::AndEqz(4885, 4811), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9726PolyExtStep::Mul(628, 4809), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9727PolyExtStep::AndEqz(4886, 4812), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9728PolyExtStep::Mul(628, 635), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9729PolyExtStep::AndEqz(4887, 4813), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9730PolyExtStep::Sub(3881, 618), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :245:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9731PolyExtStep::Mul(604, 73), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9732PolyExtStep::Sub(605, 618), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:11) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9733PolyExtStep::Mul(4816, 68), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:30) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9734PolyExtStep::Add(4815, 4817), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:40) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9735PolyExtStep::Mul(618, 629), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9736PolyExtStep::Mul(4819, 60), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:31) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9737PolyExtStep::Add(4818, 4820), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:56) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9738PolyExtStep::Mul(618, 628), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9739PolyExtStep::Mul(4822, 61), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9740PolyExtStep::Add(4821, 4823), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:55) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9741PolyExtStep::Add(3952, 1), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:54) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9742PolyExtStep::Mul(4816, 4825), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:44) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9743PolyExtStep::Sub(1, 752), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9744PolyExtStep::Mul(752, 4827), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9745PolyExtStep::AndEqz(4888, 4828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9746PolyExtStep::AndEqz(4889, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9747PolyExtStep::AndEqz(4890, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9748PolyExtStep::AndEqz(4891, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9749PolyExtStep::AndEqz(4892, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9750PolyExtStep::AndEqz(4893, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9751PolyExtStep::AndEqz(4894, 799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9752PolyExtStep::AndEqz(4895, 802), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9753PolyExtStep::Add(752, 782), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9754PolyExtStep::Add(4829, 785), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9755PolyExtStep::Add(4830, 788), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9756PolyExtStep::Add(4831, 791), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9757PolyExtStep::Add(4832, 794), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9758PolyExtStep::Add(4833, 797), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9759PolyExtStep::Add(4834, 800), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9760PolyExtStep::Sub(4835, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9761PolyExtStep::AndEqz(4896, 4836), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9762PolyExtStep::Mul(788, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9763PolyExtStep::Mul(791, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9764PolyExtStep::Mul(794, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9765PolyExtStep::Mul(797, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9766PolyExtStep::Mul(800, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9767PolyExtStep::Add(845, 4837), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9768PolyExtStep::Add(4842, 4838), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9769PolyExtStep::Add(4843, 4839), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9770PolyExtStep::Add(4844, 4840), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9771PolyExtStep::Add(4845, 4841), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9772PolyExtStep::Sub(4846, 3952), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9773PolyExtStep::AndEqz(4897, 4847), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9774PolyExtStep::Mul(752, 74), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9775PolyExtStep::Mul(752, 75), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9776PolyExtStep::Mul(752, 76), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9777PolyExtStep::Mul(752, 77), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9778PolyExtStep::Mul(752, 78), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9779PolyExtStep::Mul(752, 79), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9780PolyExtStep::Mul(752, 80), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9781PolyExtStep::Mul(752, 81), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9782PolyExtStep::Mul(752, 82), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9783PolyExtStep::Mul(752, 83), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9784PolyExtStep::Mul(752, 84), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9785PolyExtStep::Mul(752, 85), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9786PolyExtStep::Mul(752, 86), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9787PolyExtStep::Mul(752, 87), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9788PolyExtStep::Mul(752, 88), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9789PolyExtStep::Mul(752, 89), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9790PolyExtStep::Mul(752, 90), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9791PolyExtStep::Mul(752, 91), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9792PolyExtStep::Mul(752, 92), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9793PolyExtStep::Mul(752, 93), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9794PolyExtStep::Mul(752, 94), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9795PolyExtStep::Mul(752, 95), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9796PolyExtStep::Mul(752, 96), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9797PolyExtStep::Mul(752, 97), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9798PolyExtStep::Mul(782, 121), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9799PolyExtStep::Mul(782, 120), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9800PolyExtStep::Mul(782, 119), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9801PolyExtStep::Mul(782, 118), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9802PolyExtStep::Mul(782, 117), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9803PolyExtStep::Mul(782, 116), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9804PolyExtStep::Mul(782, 115), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9805PolyExtStep::Mul(782, 114), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9806PolyExtStep::Mul(782, 113), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9807PolyExtStep::Mul(782, 112), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9808PolyExtStep::Mul(782, 111), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9809PolyExtStep::Mul(782, 110), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9810PolyExtStep::Mul(782, 109), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9811PolyExtStep::Mul(782, 108), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9812PolyExtStep::Mul(782, 107), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9813PolyExtStep::Mul(782, 106), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9814PolyExtStep::Mul(782, 105), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9815PolyExtStep::Mul(782, 104), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9816PolyExtStep::Mul(782, 103), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9817PolyExtStep::Mul(782, 102), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9818PolyExtStep::Mul(782, 101), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9819PolyExtStep::Mul(782, 100), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9820PolyExtStep::Mul(782, 99), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9821PolyExtStep::Mul(782, 98), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9822PolyExtStep::Mul(785, 145), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9823PolyExtStep::Mul(785, 144), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9824PolyExtStep::Mul(785, 143), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9825PolyExtStep::Mul(785, 142), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9826PolyExtStep::Mul(785, 141), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9827PolyExtStep::Mul(785, 140), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9828PolyExtStep::Mul(785, 139), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9829PolyExtStep::Mul(785, 138), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9830PolyExtStep::Mul(785, 137), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9831PolyExtStep::Mul(785, 136), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9832PolyExtStep::Mul(785, 135), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9833PolyExtStep::Mul(785, 134), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9834PolyExtStep::Mul(785, 133), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9835PolyExtStep::Mul(785, 132), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9836PolyExtStep::Mul(785, 131), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9837PolyExtStep::Mul(785, 130), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9838PolyExtStep::Mul(785, 129), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9839PolyExtStep::Mul(785, 128), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9840PolyExtStep::Mul(785, 127), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9841PolyExtStep::Mul(785, 126), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9842PolyExtStep::Mul(785, 125), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9843PolyExtStep::Mul(785, 124), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9844PolyExtStep::Mul(785, 123), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9845PolyExtStep::Mul(785, 122), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9846PolyExtStep::Mul(788, 169), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9847PolyExtStep::Mul(788, 168), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9848PolyExtStep::Mul(788, 167), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9849PolyExtStep::Mul(788, 166), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9850PolyExtStep::Mul(788, 165), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9851PolyExtStep::Mul(788, 164), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9852PolyExtStep::Mul(788, 163), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9853PolyExtStep::Mul(788, 162), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9854PolyExtStep::Mul(788, 161), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9855PolyExtStep::Mul(788, 160), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9856PolyExtStep::Mul(788, 159), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9857PolyExtStep::Mul(788, 158), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9858PolyExtStep::Mul(788, 157), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9859PolyExtStep::Mul(788, 156), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9860PolyExtStep::Mul(788, 155), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9861PolyExtStep::Mul(788, 154), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9862PolyExtStep::Mul(788, 153), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9863PolyExtStep::Mul(788, 152), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9864PolyExtStep::Mul(788, 151), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9865PolyExtStep::Mul(788, 150), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9866PolyExtStep::Mul(788, 149), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9867PolyExtStep::Mul(788, 148), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9868PolyExtStep::Mul(788, 147), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9869PolyExtStep::Mul(788, 146), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9870PolyExtStep::Mul(791, 193), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9871PolyExtStep::Mul(791, 192), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9872PolyExtStep::Mul(791, 191), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9873PolyExtStep::Mul(791, 190), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9874PolyExtStep::Mul(791, 189), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9875PolyExtStep::Mul(791, 188), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9876PolyExtStep::Mul(791, 187), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9877PolyExtStep::Mul(791, 186), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9878PolyExtStep::Mul(791, 185), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9879PolyExtStep::Mul(791, 184), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9880PolyExtStep::Mul(791, 183), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9881PolyExtStep::Mul(791, 182), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9882PolyExtStep::Mul(791, 181), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9883PolyExtStep::Mul(791, 180), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9884PolyExtStep::Mul(791, 179), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9885PolyExtStep::Mul(791, 178), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9886PolyExtStep::Mul(791, 177), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9887PolyExtStep::Mul(791, 176), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9888PolyExtStep::Mul(791, 175), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9889PolyExtStep::Mul(791, 174), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9890PolyExtStep::Mul(791, 173), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9891PolyExtStep::Mul(791, 172), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9892PolyExtStep::Mul(791, 171), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9893PolyExtStep::Mul(791, 170), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9894PolyExtStep::Mul(794, 217), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9895PolyExtStep::Mul(794, 216), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9896PolyExtStep::Mul(794, 215), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9897PolyExtStep::Mul(794, 214), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9898PolyExtStep::Mul(794, 213), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9899PolyExtStep::Mul(794, 212), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9900PolyExtStep::Mul(794, 211), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9901PolyExtStep::Mul(794, 210), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9902PolyExtStep::Mul(794, 209), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9903PolyExtStep::Mul(794, 208), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9904PolyExtStep::Mul(794, 207), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9905PolyExtStep::Mul(794, 206), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9906PolyExtStep::Mul(794, 205), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9907PolyExtStep::Mul(794, 204), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9908PolyExtStep::Mul(794, 203), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9909PolyExtStep::Mul(794, 202), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9910PolyExtStep::Mul(794, 201), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9911PolyExtStep::Mul(794, 200), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9912PolyExtStep::Mul(794, 199), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9913PolyExtStep::Mul(794, 198), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9914PolyExtStep::Mul(794, 197), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9915PolyExtStep::Mul(794, 196), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9916PolyExtStep::Mul(794, 195), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9917PolyExtStep::Mul(794, 194), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9918PolyExtStep::Mul(797, 241), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9919PolyExtStep::Mul(797, 240), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9920PolyExtStep::Mul(797, 239), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9921PolyExtStep::Mul(797, 238), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9922PolyExtStep::Mul(797, 237), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9923PolyExtStep::Mul(797, 236), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9924PolyExtStep::Mul(797, 235), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9925PolyExtStep::Mul(797, 234), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9926PolyExtStep::Mul(797, 233), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9927PolyExtStep::Mul(797, 232), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9928PolyExtStep::Mul(797, 231), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9929PolyExtStep::Mul(797, 230), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9930PolyExtStep::Mul(797, 229), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9931PolyExtStep::Mul(797, 228), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9932PolyExtStep::Mul(797, 227), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9933PolyExtStep::Mul(797, 226), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9934PolyExtStep::Mul(797, 225), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9935PolyExtStep::Mul(797, 224), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9936PolyExtStep::Mul(797, 223), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9937PolyExtStep::Mul(797, 222), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9938PolyExtStep::Mul(797, 221), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9939PolyExtStep::Mul(797, 220), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9940PolyExtStep::Mul(797, 219), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9941PolyExtStep::Mul(797, 218), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9942PolyExtStep::Mul(800, 265), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9943PolyExtStep::Mul(800, 264), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9944PolyExtStep::Mul(800, 263), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9945PolyExtStep::Mul(800, 262), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9946PolyExtStep::Mul(800, 261), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9947PolyExtStep::Mul(800, 260), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9948PolyExtStep::Mul(800, 259), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9949PolyExtStep::Mul(800, 258), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9950PolyExtStep::Mul(800, 257), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9951PolyExtStep::Mul(800, 256), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9952PolyExtStep::Mul(800, 255), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9953PolyExtStep::Mul(800, 254), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9954PolyExtStep::Mul(800, 253), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9955PolyExtStep::Mul(800, 252), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9956PolyExtStep::Mul(800, 251), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9957PolyExtStep::Mul(800, 250), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9958PolyExtStep::Mul(800, 249), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9959PolyExtStep::Mul(800, 248), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9960PolyExtStep::Mul(800, 247), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9961PolyExtStep::Mul(800, 246), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9962PolyExtStep::Mul(800, 245), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9963PolyExtStep::Mul(800, 244), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9964PolyExtStep::Mul(800, 243), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9965PolyExtStep::Mul(800, 242), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9966PolyExtStep::Add(4848, 4872), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9967PolyExtStep::Add(4849, 4873), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9968PolyExtStep::Add(4850, 4874), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9969PolyExtStep::Add(4851, 4875), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9970PolyExtStep::Add(4852, 4876), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9971PolyExtStep::Add(4853, 4877), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9972PolyExtStep::Add(4854, 4878), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9973PolyExtStep::Add(4855, 4879), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9974PolyExtStep::Add(4856, 4880), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9975PolyExtStep::Add(4857, 4881), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9976PolyExtStep::Add(4858, 4882), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9977PolyExtStep::Add(4859, 4883), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9978PolyExtStep::Add(4860, 4884), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9979PolyExtStep::Add(4861, 4885), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9980PolyExtStep::Add(4862, 4886), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9981PolyExtStep::Add(4863, 4887), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9982PolyExtStep::Add(4864, 4888), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9983PolyExtStep::Add(4865, 4889), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9984PolyExtStep::Add(4866, 4890), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9985PolyExtStep::Add(4867, 4891), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9986PolyExtStep::Add(4868, 4892), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9987PolyExtStep::Add(4869, 4893), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9988PolyExtStep::Add(4870, 4894), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9989PolyExtStep::Add(4871, 4895), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9990PolyExtStep::Add(5040, 4896), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9991PolyExtStep::Add(5041, 4897), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9992PolyExtStep::Add(5042, 4898), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9993PolyExtStep::Add(5043, 4899), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9994PolyExtStep::Add(5044, 4900), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9995PolyExtStep::Add(5045, 4901), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9996PolyExtStep::Add(5046, 4902), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9997PolyExtStep::Add(5047, 4903), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9998PolyExtStep::Add(5048, 4904), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9999PolyExtStep::Add(5049, 4905), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10000PolyExtStep::Add(5050, 4906), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10001PolyExtStep::Add(5051, 4907), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10002PolyExtStep::Add(5052, 4908), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10003PolyExtStep::Add(5053, 4909), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10004PolyExtStep::Add(5054, 4910), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10005PolyExtStep::Add(5055, 4911), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10006PolyExtStep::Add(5056, 4912), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10007PolyExtStep::Add(5057, 4913), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10008PolyExtStep::Add(5058, 4914), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10009PolyExtStep::Add(5059, 4915), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10010PolyExtStep::Add(5060, 4916), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10011PolyExtStep::Add(5061, 4917), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10012PolyExtStep::Add(5062, 4918), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10013PolyExtStep::Add(5063, 4919), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10014PolyExtStep::Add(5064, 4920), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10015PolyExtStep::Add(5065, 4921), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10016PolyExtStep::Add(5066, 4922), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10017PolyExtStep::Add(5067, 4923), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10018PolyExtStep::Add(5068, 4924), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10019PolyExtStep::Add(5069, 4925), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10020PolyExtStep::Add(5070, 4926), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10021PolyExtStep::Add(5071, 4927), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10022PolyExtStep::Add(5072, 4928), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10023PolyExtStep::Add(5073, 4929), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10024PolyExtStep::Add(5074, 4930), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10025PolyExtStep::Add(5075, 4931), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10026PolyExtStep::Add(5076, 4932), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10027PolyExtStep::Add(5077, 4933), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10028PolyExtStep::Add(5078, 4934), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10029PolyExtStep::Add(5079, 4935), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10030PolyExtStep::Add(5080, 4936), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10031PolyExtStep::Add(5081, 4937), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10032PolyExtStep::Add(5082, 4938), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10033PolyExtStep::Add(5083, 4939), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10034PolyExtStep::Add(5084, 4940), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10035PolyExtStep::Add(5085, 4941), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10036PolyExtStep::Add(5086, 4942), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10037PolyExtStep::Add(5087, 4943), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10038PolyExtStep::Add(5088, 4944), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10039PolyExtStep::Add(5089, 4945), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10040PolyExtStep::Add(5090, 4946), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10041PolyExtStep::Add(5091, 4947), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10042PolyExtStep::Add(5092, 4948), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10043PolyExtStep::Add(5093, 4949), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10044PolyExtStep::Add(5094, 4950), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10045PolyExtStep::Add(5095, 4951), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10046PolyExtStep::Add(5096, 4952), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10047PolyExtStep::Add(5097, 4953), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10048PolyExtStep::Add(5098, 4954), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10049PolyExtStep::Add(5099, 4955), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10050PolyExtStep::Add(5100, 4956), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10051PolyExtStep::Add(5101, 4957), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10052PolyExtStep::Add(5102, 4958), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10053PolyExtStep::Add(5103, 4959), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10054PolyExtStep::Add(5104, 4960), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10055PolyExtStep::Add(5105, 4961), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10056PolyExtStep::Add(5106, 4962), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10057PolyExtStep::Add(5107, 4963), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10058PolyExtStep::Add(5108, 4964), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10059PolyExtStep::Add(5109, 4965), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10060PolyExtStep::Add(5110, 4966), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10061PolyExtStep::Add(5111, 4967), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10062PolyExtStep::Add(5112, 4968), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10063PolyExtStep::Add(5113, 4969), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10064PolyExtStep::Add(5114, 4970), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10065PolyExtStep::Add(5115, 4971), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10066PolyExtStep::Add(5116, 4972), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10067PolyExtStep::Add(5117, 4973), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10068PolyExtStep::Add(5118, 4974), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10069PolyExtStep::Add(5119, 4975), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10070PolyExtStep::Add(5120, 4976), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10071PolyExtStep::Add(5121, 4977), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10072PolyExtStep::Add(5122, 4978), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10073PolyExtStep::Add(5123, 4979), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10074PolyExtStep::Add(5124, 4980), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10075PolyExtStep::Add(5125, 4981), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10076PolyExtStep::Add(5126, 4982), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10077PolyExtStep::Add(5127, 4983), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10078PolyExtStep::Add(5128, 4984), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10079PolyExtStep::Add(5129, 4985), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10080PolyExtStep::Add(5130, 4986), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10081PolyExtStep::Add(5131, 4987), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10082PolyExtStep::Add(5132, 4988), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10083PolyExtStep::Add(5133, 4989), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10084PolyExtStep::Add(5134, 4990), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10085PolyExtStep::Add(5135, 4991), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10086PolyExtStep::Add(5136, 4992), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10087PolyExtStep::Add(5137, 4993), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10088PolyExtStep::Add(5138, 4994), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10089PolyExtStep::Add(5139, 4995), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10090PolyExtStep::Add(5140, 4996), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10091PolyExtStep::Add(5141, 4997), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10092PolyExtStep::Add(5142, 4998), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10093PolyExtStep::Add(5143, 4999), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10094PolyExtStep::Add(5144, 5000), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10095PolyExtStep::Add(5145, 5001), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10096PolyExtStep::Add(5146, 5002), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10097PolyExtStep::Add(5147, 5003), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10098PolyExtStep::Add(5148, 5004), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10099PolyExtStep::Add(5149, 5005), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10100PolyExtStep::Add(5150, 5006), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10101PolyExtStep::Add(5151, 5007), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10102PolyExtStep::Add(5152, 5008), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10103PolyExtStep::Add(5153, 5009), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10104PolyExtStep::Add(5154, 5010), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10105PolyExtStep::Add(5155, 5011), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10106PolyExtStep::Add(5156, 5012), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10107PolyExtStep::Add(5157, 5013), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10108PolyExtStep::Add(5158, 5014), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10109PolyExtStep::Add(5159, 5015), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10110PolyExtStep::Add(5160, 5016), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10111PolyExtStep::Add(5161, 5017), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10112PolyExtStep::Add(5162, 5018), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10113PolyExtStep::Add(5163, 5019), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10114PolyExtStep::Add(5164, 5020), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10115PolyExtStep::Add(5165, 5021), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10116PolyExtStep::Add(5166, 5022), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10117PolyExtStep::Add(5167, 5023), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10118PolyExtStep::Add(5168, 5024), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10119PolyExtStep::Add(5169, 5025), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10120PolyExtStep::Add(5170, 5026), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10121PolyExtStep::Add(5171, 5027), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10122PolyExtStep::Add(5172, 5028), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10123PolyExtStep::Add(5173, 5029), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10124PolyExtStep::Add(5174, 5030), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10125PolyExtStep::Add(5175, 5031), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10126PolyExtStep::Add(5176, 5032), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10127PolyExtStep::Add(5177, 5033), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10128PolyExtStep::Add(5178, 5034), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10129PolyExtStep::Add(5179, 5035), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10130PolyExtStep::Add(5180, 5036), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10131PolyExtStep::Add(5181, 5037), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10132PolyExtStep::Add(5182, 5038), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10133PolyExtStep::Add(5183, 5039), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10134PolyExtStep::Add(3953, 5184), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10135PolyExtStep::Mul(5208, 5208), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10136PolyExtStep::Mul(5209, 5208), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10137PolyExtStep::Sub(5210, 645), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10138PolyExtStep::AndEqz(4898, 5211), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10139PolyExtStep::Mul(645, 645), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10140PolyExtStep::Mul(5212, 5208), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10141PolyExtStep::Sub(5213, 642), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10142PolyExtStep::AndEqz(4899, 5214), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10143PolyExtStep::Add(3954, 5185), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10144PolyExtStep::Mul(5215, 5215), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10145PolyExtStep::Mul(5216, 5215), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10146PolyExtStep::Sub(5217, 655), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10147PolyExtStep::AndEqz(4900, 5218), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10148PolyExtStep::Mul(655, 655), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10149PolyExtStep::Mul(5219, 5215), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10150PolyExtStep::Sub(5220, 648), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10151PolyExtStep::AndEqz(4901, 5221), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10152PolyExtStep::Add(3955, 5186), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10153PolyExtStep::Mul(5222, 5222), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10154PolyExtStep::Mul(5223, 5222), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10155PolyExtStep::Sub(5224, 669), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10156PolyExtStep::AndEqz(4902, 5225), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10157PolyExtStep::Mul(669, 669), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10158PolyExtStep::Mul(5226, 5222), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10159PolyExtStep::Sub(5227, 662), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10160PolyExtStep::AndEqz(4903, 5228), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10161PolyExtStep::Add(3956, 5187), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10162PolyExtStep::Mul(5229, 5229), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10163PolyExtStep::Mul(5230, 5229), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10164PolyExtStep::Sub(5231, 541), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10165PolyExtStep::AndEqz(4904, 5232), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10166PolyExtStep::Mul(541, 541), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10167PolyExtStep::Mul(5233, 5229), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10168PolyExtStep::Sub(5234, 672), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10169PolyExtStep::AndEqz(4905, 5235), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10170PolyExtStep::Add(3957, 5188), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10171PolyExtStep::Mul(5236, 5236), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10172PolyExtStep::Mul(5237, 5236), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10173PolyExtStep::Sub(5238, 549), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10174PolyExtStep::AndEqz(4906, 5239), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10175PolyExtStep::Mul(549, 549), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10176PolyExtStep::Mul(5240, 5236), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10177PolyExtStep::Sub(5241, 548), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10178PolyExtStep::AndEqz(4907, 5242), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10179PolyExtStep::Add(3958, 5189), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10180PolyExtStep::Mul(5243, 5243), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10181PolyExtStep::Mul(5244, 5243), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10182PolyExtStep::Sub(5245, 553), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10183PolyExtStep::AndEqz(4908, 5246), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10184PolyExtStep::Mul(553, 553), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10185PolyExtStep::Mul(5247, 5243), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10186PolyExtStep::Sub(5248, 552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10187PolyExtStep::AndEqz(4909, 5249), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10188PolyExtStep::Add(3959, 5190), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10189PolyExtStep::Mul(5250, 5250), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10190PolyExtStep::Mul(5251, 5250), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10191PolyExtStep::Sub(5252, 561), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10192PolyExtStep::AndEqz(4910, 5253), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10193PolyExtStep::Mul(561, 561), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10194PolyExtStep::Mul(5254, 5250), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10195PolyExtStep::Sub(5255, 560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10196PolyExtStep::AndEqz(4911, 5256), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10197PolyExtStep::Add(3960, 5191), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10198PolyExtStep::Mul(5257, 5257), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10199PolyExtStep::Mul(5258, 5257), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10200PolyExtStep::Sub(5259, 567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10201PolyExtStep::AndEqz(4912, 5260), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10202PolyExtStep::Mul(567, 567), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10203PolyExtStep::Mul(5261, 5257), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10204PolyExtStep::Sub(5262, 568), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10205PolyExtStep::AndEqz(4913, 5263), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10206PolyExtStep::Add(3961, 5192), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10207PolyExtStep::Mul(5264, 5264), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10208PolyExtStep::Mul(5265, 5264), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10209PolyExtStep::Sub(5266, 570), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10210PolyExtStep::AndEqz(4914, 5267), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10211PolyExtStep::Mul(570, 570), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10212PolyExtStep::Mul(5268, 5264), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10213PolyExtStep::Sub(5269, 569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10214PolyExtStep::AndEqz(4915, 5270), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10215PolyExtStep::Add(3962, 5193), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10216PolyExtStep::Mul(5271, 5271), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10217PolyExtStep::Mul(5272, 5271), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10218PolyExtStep::Sub(5273, 572), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10219PolyExtStep::AndEqz(4916, 5274), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10220PolyExtStep::Mul(572, 572), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10221PolyExtStep::Mul(5275, 5271), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10222PolyExtStep::Sub(5276, 571), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10223PolyExtStep::AndEqz(4917, 5277), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10224PolyExtStep::Add(3963, 5194), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10225PolyExtStep::Mul(5278, 5278), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10226PolyExtStep::Mul(5279, 5278), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10227PolyExtStep::Sub(5280, 574), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10228PolyExtStep::AndEqz(4918, 5281), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10229PolyExtStep::Mul(574, 574), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10230PolyExtStep::Mul(5282, 5278), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10231PolyExtStep::Sub(5283, 573), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10232PolyExtStep::AndEqz(4919, 5284), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10233PolyExtStep::Add(3964, 5195), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10234PolyExtStep::Mul(5285, 5285), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10235PolyExtStep::Mul(5286, 5285), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10236PolyExtStep::Sub(5287, 583), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10237PolyExtStep::AndEqz(4920, 5288), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10238PolyExtStep::Mul(583, 583), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10239PolyExtStep::Mul(5289, 5285), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10240PolyExtStep::Sub(5290, 575), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10241PolyExtStep::AndEqz(4921, 5291), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10242PolyExtStep::Add(3965, 5196), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10243PolyExtStep::Mul(5292, 5292), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10244PolyExtStep::Mul(5293, 5292), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10245PolyExtStep::Sub(5294, 732), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10246PolyExtStep::AndEqz(4922, 5295), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10247PolyExtStep::Mul(732, 732), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10248PolyExtStep::Mul(5296, 5292), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10249PolyExtStep::Sub(5297, 584), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10250PolyExtStep::AndEqz(4923, 5298), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10251PolyExtStep::Add(3966, 5197), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10252PolyExtStep::Mul(5299, 5299), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10253PolyExtStep::Mul(5300, 5299), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10254PolyExtStep::Sub(5301, 733), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10255PolyExtStep::AndEqz(4924, 5302), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10256PolyExtStep::Mul(733, 733), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10257PolyExtStep::Mul(5303, 5299), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10258PolyExtStep::Sub(5304, 731), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10259PolyExtStep::AndEqz(4925, 5305), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10260PolyExtStep::Add(3967, 5198), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10261PolyExtStep::Mul(5306, 5306), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10262PolyExtStep::Mul(5307, 5306), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10263PolyExtStep::Sub(5308, 735), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10264PolyExtStep::AndEqz(4926, 5309), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10265PolyExtStep::Mul(735, 735), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10266PolyExtStep::Mul(5310, 5306), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10267PolyExtStep::Sub(5311, 734), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10268PolyExtStep::AndEqz(4927, 5312), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10269PolyExtStep::Add(3968, 5199), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10270PolyExtStep::Mul(5313, 5313), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10271PolyExtStep::Mul(5314, 5313), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10272PolyExtStep::Sub(5315, 737), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10273PolyExtStep::AndEqz(4928, 5316), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10274PolyExtStep::Mul(737, 737), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10275PolyExtStep::Mul(5317, 5313), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10276PolyExtStep::Sub(5318, 736), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10277PolyExtStep::AndEqz(4929, 5319), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10278PolyExtStep::Add(3969, 5200), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10279PolyExtStep::Mul(5320, 5320), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10280PolyExtStep::Mul(5321, 5320), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10281PolyExtStep::Sub(5322, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10282PolyExtStep::AndEqz(4930, 5323), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10283PolyExtStep::Mul(739, 739), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10284PolyExtStep::Mul(5324, 5320), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10285PolyExtStep::Sub(5325, 738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10286PolyExtStep::AndEqz(4931, 5326), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10287PolyExtStep::Add(3970, 5201), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10288PolyExtStep::Mul(5327, 5327), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10289PolyExtStep::Mul(5328, 5327), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10290PolyExtStep::Sub(5329, 748), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10291PolyExtStep::AndEqz(4932, 5330), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10292PolyExtStep::Mul(748, 748), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10293PolyExtStep::Mul(5331, 5327), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10294PolyExtStep::Sub(5332, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10295PolyExtStep::AndEqz(4933, 5333), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10296PolyExtStep::Add(3971, 5202), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10297PolyExtStep::Mul(5334, 5334), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10298PolyExtStep::Mul(5335, 5334), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10299PolyExtStep::Sub(5336, 755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10300PolyExtStep::AndEqz(4934, 5337), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10301PolyExtStep::Mul(755, 755), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10302PolyExtStep::Mul(5338, 5334), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10303PolyExtStep::Sub(5339, 729), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10304PolyExtStep::AndEqz(4935, 5340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10305PolyExtStep::Add(3972, 5203), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10306PolyExtStep::Mul(5341, 5341), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10307PolyExtStep::Mul(5342, 5341), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10308PolyExtStep::Sub(5343, 756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10309PolyExtStep::AndEqz(4936, 5344), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10310PolyExtStep::Mul(756, 756), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10311PolyExtStep::Mul(5345, 5341), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10312PolyExtStep::Sub(5346, 754), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10313PolyExtStep::AndEqz(4937, 5347), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10314PolyExtStep::Add(3973, 5204), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10315PolyExtStep::Mul(5348, 5348), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10316PolyExtStep::Mul(5349, 5348), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10317PolyExtStep::Sub(5350, 758), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10318PolyExtStep::AndEqz(4938, 5351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10319PolyExtStep::Mul(758, 758), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10320PolyExtStep::Mul(5352, 5348), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10321PolyExtStep::Sub(5353, 757), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10322PolyExtStep::AndEqz(4939, 5354), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10323PolyExtStep::Add(3974, 5205), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10324PolyExtStep::Mul(5355, 5355), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10325PolyExtStep::Mul(5356, 5355), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10326PolyExtStep::Sub(5357, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10327PolyExtStep::AndEqz(4940, 5358), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10328PolyExtStep::Mul(760, 760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10329PolyExtStep::Mul(5359, 5355), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10330PolyExtStep::Sub(5360, 759), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10331PolyExtStep::AndEqz(4941, 5361), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10332PolyExtStep::Add(3975, 5206), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10333PolyExtStep::Mul(5362, 5362), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10334PolyExtStep::Mul(5363, 5362), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10335PolyExtStep::Sub(5364, 762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10336PolyExtStep::AndEqz(4942, 5365), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10337PolyExtStep::Mul(762, 762), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10338PolyExtStep::Mul(5366, 5362), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10339PolyExtStep::Sub(5367, 761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10340PolyExtStep::AndEqz(4943, 5368), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10341PolyExtStep::Add(3976, 5207), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10342PolyExtStep::Mul(5369, 5369), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10343PolyExtStep::Mul(5370, 5369), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10344PolyExtStep::Sub(5371, 771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10345PolyExtStep::AndEqz(4944, 5372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10346PolyExtStep::Mul(771, 771), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10347PolyExtStep::Mul(5373, 5369), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10348PolyExtStep::Sub(5374, 770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10349PolyExtStep::AndEqz(4945, 5375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10350PolyExtStep::Add(642, 648), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10351PolyExtStep::Add(662, 672), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10352PolyExtStep::Mul(648, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10353PolyExtStep::Add(5378, 5377), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10354PolyExtStep::Add(1689, 5376), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10355PolyExtStep::Mul(5377, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10356PolyExtStep::Add(5381, 5380), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10357PolyExtStep::Mul(5376, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10358PolyExtStep::Add(5383, 5379), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10359PolyExtStep::Add(5380, 5384), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10360PolyExtStep::Add(5379, 5382), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10361PolyExtStep::Add(548, 552), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10362PolyExtStep::Add(560, 568), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10363PolyExtStep::Mul(552, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10364PolyExtStep::Add(5389, 5388), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10365PolyExtStep::Mul(568, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10366PolyExtStep::Add(5391, 5387), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10367PolyExtStep::Mul(5388, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10368PolyExtStep::Add(5393, 5392), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10369PolyExtStep::Mul(5387, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10370PolyExtStep::Add(5395, 5390), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10371PolyExtStep::Add(5392, 5396), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10372PolyExtStep::Add(5390, 5394), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10373PolyExtStep::Add(569, 571), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10374PolyExtStep::Add(573, 575), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10375PolyExtStep::Add(2140, 5400), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10376PolyExtStep::Mul(575, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10377PolyExtStep::Add(5402, 5399), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10378PolyExtStep::Mul(5400, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10379PolyExtStep::Add(5404, 5403), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10380PolyExtStep::Mul(5399, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10381PolyExtStep::Add(5406, 5401), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10382PolyExtStep::Add(5403, 5407), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10383PolyExtStep::Add(5401, 5405), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10384PolyExtStep::Add(584, 731), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10385PolyExtStep::Add(734, 736), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10386PolyExtStep::Add(2144, 5411), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10387PolyExtStep::Mul(736, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10388PolyExtStep::Add(5413, 5410), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10389PolyExtStep::Mul(5411, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10390PolyExtStep::Add(5415, 5414), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10391PolyExtStep::Mul(5410, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10392PolyExtStep::Add(5417, 5412), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10393PolyExtStep::Add(5414, 5418), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10394PolyExtStep::Add(5412, 5416), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10395PolyExtStep::Add(738, 747), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10396PolyExtStep::Add(729, 754), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10397PolyExtStep::Mul(747, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10398PolyExtStep::Add(5423, 5422), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10399PolyExtStep::Mul(754, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10400PolyExtStep::Add(5425, 5421), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10401PolyExtStep::Mul(5422, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10402PolyExtStep::Add(5427, 5426), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10403PolyExtStep::Mul(5421, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10404PolyExtStep::Add(5429, 5424), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10405PolyExtStep::Add(5426, 5430), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10406PolyExtStep::Add(5424, 5428), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10407PolyExtStep::Add(757, 759), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10408PolyExtStep::Add(761, 770), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10409PolyExtStep::Mul(759, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10410PolyExtStep::Add(5435, 5434), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10411PolyExtStep::Mul(770, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10412PolyExtStep::Add(5437, 5433), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10413PolyExtStep::Mul(5434, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10414PolyExtStep::Add(5439, 5438), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10415PolyExtStep::Mul(5433, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10416PolyExtStep::Add(5441, 5436), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10417PolyExtStep::Add(5438, 5442), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10418PolyExtStep::Add(5436, 5440), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10419PolyExtStep::Add(5385, 5397), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10420PolyExtStep::Add(5384, 5396), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10421PolyExtStep::Add(5386, 5398), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10422PolyExtStep::Add(5382, 5394), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10423PolyExtStep::Add(5445, 5408), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10424PolyExtStep::Add(5446, 5407), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10425PolyExtStep::Add(5447, 5409), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10426PolyExtStep::Add(5448, 5405), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10427PolyExtStep::Add(5449, 5419), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10428PolyExtStep::Add(5450, 5418), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10429PolyExtStep::Add(5451, 5420), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10430PolyExtStep::Add(5452, 5416), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10431PolyExtStep::Add(5453, 5431), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10432PolyExtStep::Add(5454, 5430), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10433PolyExtStep::Add(5455, 5432), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10434PolyExtStep::Add(5456, 5428), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10435PolyExtStep::Add(5457, 5443), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10436PolyExtStep::Add(5458, 5442), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10437PolyExtStep::Add(5459, 5444), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10438PolyExtStep::Add(5460, 5440), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10439PolyExtStep::Add(5385, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10440PolyExtStep::Add(5384, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10441PolyExtStep::Add(5386, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10442PolyExtStep::Add(5382, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10443PolyExtStep::Add(5397, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10444PolyExtStep::Add(5396, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10445PolyExtStep::Add(5398, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10446PolyExtStep::Add(5394, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10447PolyExtStep::Add(5408, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10448PolyExtStep::Add(5407, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10449PolyExtStep::Add(5409, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10450PolyExtStep::Add(5405, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10451PolyExtStep::Add(5419, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10452PolyExtStep::Add(5418, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10453PolyExtStep::Add(5420, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10454PolyExtStep::Add(5416, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10455PolyExtStep::Add(5431, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10456PolyExtStep::Add(5430, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10457PolyExtStep::Add(5432, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10458PolyExtStep::Add(5428, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10459PolyExtStep::Add(5443, 5461), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10460PolyExtStep::Add(5442, 5462), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10461PolyExtStep::Add(5444, 5463), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10462PolyExtStep::Add(5440, 5464), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10463PolyExtStep::AndEqz(4946, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10464PolyExtStep::AndEqz(4947, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10465PolyExtStep::AndEqz(4948, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10466PolyExtStep::AndEqz(4949, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10467PolyExtStep::AndEqz(4950, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10468PolyExtStep::AndEqz(4951, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10469PolyExtStep::Sub(4824, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10470PolyExtStep::AndEqz(4952, 5489), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10471PolyExtStep::Sub(4826, 1122), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10472PolyExtStep::AndEqz(4953, 5490), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10473PolyExtStep::AndEqz(4954, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10474PolyExtStep::Sub(4814, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10475PolyExtStep::AndEqz(4955, 5491), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10476PolyExtStep::AndEqz(4956, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10477PolyExtStep::Sub(5465, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10478PolyExtStep::AndEqz(4957, 5492), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10479PolyExtStep::Sub(5466, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10480PolyExtStep::AndEqz(4958, 5493), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10481PolyExtStep::Sub(5467, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10482PolyExtStep::AndEqz(4959, 5494), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10483PolyExtStep::Sub(5468, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10484PolyExtStep::AndEqz(4960, 5495), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10485PolyExtStep::Sub(5469, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10486PolyExtStep::AndEqz(4961, 5496), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10487PolyExtStep::Sub(5470, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10488PolyExtStep::AndEqz(4962, 5497), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10489PolyExtStep::Sub(5471, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10490PolyExtStep::AndEqz(4963, 5498), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10491PolyExtStep::Sub(5472, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10492PolyExtStep::AndEqz(4964, 5499), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10493PolyExtStep::Sub(5473, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10494PolyExtStep::AndEqz(4965, 5500), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10495PolyExtStep::Sub(5474, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10496PolyExtStep::AndEqz(4966, 5501), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10497PolyExtStep::Sub(5475, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10498PolyExtStep::AndEqz(4967, 5502), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10499PolyExtStep::Sub(5476, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10500PolyExtStep::AndEqz(4968, 5503), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10501PolyExtStep::Sub(5477, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10502PolyExtStep::AndEqz(4969, 5504), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10503PolyExtStep::Sub(5478, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10504PolyExtStep::AndEqz(4970, 5505), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10505PolyExtStep::Sub(5479, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10506PolyExtStep::AndEqz(4971, 5506), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10507PolyExtStep::Sub(5480, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10508PolyExtStep::AndEqz(4972, 5507), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10509PolyExtStep::Sub(5481, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10510PolyExtStep::AndEqz(4973, 5508), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10511PolyExtStep::Sub(5482, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10512PolyExtStep::AndEqz(4974, 5509), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10513PolyExtStep::Sub(5483, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10514PolyExtStep::AndEqz(4975, 5510), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10515PolyExtStep::Sub(5484, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10516PolyExtStep::AndEqz(4976, 5511), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10517PolyExtStep::Sub(5485, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10518PolyExtStep::AndEqz(4977, 5512), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10519PolyExtStep::Sub(5486, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10520PolyExtStep::AndEqz(4978, 5513), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10521PolyExtStep::Sub(5487, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10522PolyExtStep::AndEqz(4979, 5514), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10523PolyExtStep::Sub(5488, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10524PolyExtStep::AndEqz(4980, 5515), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10525PolyExtStep::Sub(3798, 3986), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10526PolyExtStep::AndEqz(4981, 5516), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :488:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10527PolyExtStep::AndCond(4876, 374, 4982), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10528PolyExtStep::Add(3953, 266), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10529PolyExtStep::Mul(5517, 5517), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10530PolyExtStep::Mul(5518, 5517), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10531PolyExtStep::Sub(5519, 611), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10532PolyExtStep::AndEqz(0, 5520), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10533PolyExtStep::Mul(611, 611), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10534PolyExtStep::Mul(5521, 5517), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10535PolyExtStep::Sub(5522, 604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10536PolyExtStep::AndEqz(4984, 5523), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10537PolyExtStep::Add(604, 3954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10538PolyExtStep::Add(5524, 3955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10539PolyExtStep::Add(5525, 3956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10540PolyExtStep::Add(5526, 3957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10541PolyExtStep::Add(5527, 3958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10542PolyExtStep::Add(5528, 3959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10543PolyExtStep::Add(5529, 3960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10544PolyExtStep::Add(5530, 3961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10545PolyExtStep::Add(5531, 3962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10546PolyExtStep::Add(5532, 3963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10547PolyExtStep::Add(5533, 3964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10548PolyExtStep::Add(5534, 3965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10549PolyExtStep::Add(5535, 3966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10550PolyExtStep::Add(5536, 3967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10551PolyExtStep::Add(5537, 3968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10552PolyExtStep::Add(5538, 3969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10553PolyExtStep::Add(5539, 3970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10554PolyExtStep::Add(5540, 3971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10555PolyExtStep::Add(5541, 3972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10556PolyExtStep::Add(5542, 3973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10557PolyExtStep::Add(5543, 3974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10558PolyExtStep::Add(5544, 3975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10559PolyExtStep::Add(5545, 3976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10560PolyExtStep::Mul(604, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10561PolyExtStep::Add(5546, 5547), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10562PolyExtStep::Mul(3954, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10563PolyExtStep::Add(5546, 5549), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10564PolyExtStep::Mul(3955, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10565PolyExtStep::Add(5546, 5551), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10566PolyExtStep::Mul(3956, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10567PolyExtStep::Add(5546, 5553), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10568PolyExtStep::Mul(3957, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10569PolyExtStep::Add(5546, 5555), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10570PolyExtStep::Mul(3958, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10571PolyExtStep::Add(5546, 5557), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10572PolyExtStep::Mul(3959, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10573PolyExtStep::Add(5546, 5559), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10574PolyExtStep::Mul(3960, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10575PolyExtStep::Add(5546, 5561), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10576PolyExtStep::Mul(3961, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10577PolyExtStep::Add(5546, 5563), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10578PolyExtStep::Mul(3962, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10579PolyExtStep::Add(5546, 5565), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10580PolyExtStep::Mul(3963, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10581PolyExtStep::Add(5546, 5567), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10582PolyExtStep::Mul(3964, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10583PolyExtStep::Add(5546, 5569), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10584PolyExtStep::Mul(3965, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10585PolyExtStep::Add(5546, 5571), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10586PolyExtStep::Mul(3966, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10587PolyExtStep::Add(5546, 5573), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10588PolyExtStep::Mul(3967, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10589PolyExtStep::Add(5546, 5575), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10590PolyExtStep::Mul(3968, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10591PolyExtStep::Add(5546, 5577), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10592PolyExtStep::Mul(3969, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10593PolyExtStep::Add(5546, 5579), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10594PolyExtStep::Mul(3970, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10595PolyExtStep::Add(5546, 5581), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10596PolyExtStep::Mul(3971, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10597PolyExtStep::Add(5546, 5583), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10598PolyExtStep::Mul(3972, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10599PolyExtStep::Add(5546, 5585), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10600PolyExtStep::Mul(3973, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10601PolyExtStep::Add(5546, 5587), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10602PolyExtStep::Mul(3974, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10603PolyExtStep::Add(5546, 5589), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10604PolyExtStep::Mul(3975, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10605PolyExtStep::Add(5546, 5591), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10606PolyExtStep::Mul(3976, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10607PolyExtStep::Add(5546, 5593), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10608PolyExtStep::Add(5548, 267), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10609PolyExtStep::Mul(5595, 5595), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10610PolyExtStep::Mul(5596, 5595), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10611PolyExtStep::Sub(5597, 625), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10612PolyExtStep::AndEqz(4985, 5598), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10613PolyExtStep::Mul(625, 625), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10614PolyExtStep::Mul(5599, 5595), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10615PolyExtStep::Sub(5600, 618), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10616PolyExtStep::AndEqz(4986, 5601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10617PolyExtStep::Add(618, 5550), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10618PolyExtStep::Add(5602, 5552), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10619PolyExtStep::Add(5603, 5554), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10620PolyExtStep::Add(5604, 5556), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10621PolyExtStep::Add(5605, 5558), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10622PolyExtStep::Add(5606, 5560), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10623PolyExtStep::Add(5607, 5562), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10624PolyExtStep::Add(5608, 5564), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10625PolyExtStep::Add(5609, 5566), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10626PolyExtStep::Add(5610, 5568), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10627PolyExtStep::Add(5611, 5570), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10628PolyExtStep::Add(5612, 5572), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10629PolyExtStep::Add(5613, 5574), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10630PolyExtStep::Add(5614, 5576), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10631PolyExtStep::Add(5615, 5578), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10632PolyExtStep::Add(5616, 5580), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10633PolyExtStep::Add(5617, 5582), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10634PolyExtStep::Add(5618, 5584), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10635PolyExtStep::Add(5619, 5586), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10636PolyExtStep::Add(5620, 5588), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10637PolyExtStep::Add(5621, 5590), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10638PolyExtStep::Add(5622, 5592), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10639PolyExtStep::Add(5623, 5594), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10640PolyExtStep::Mul(618, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10641PolyExtStep::Add(5624, 5625), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10642PolyExtStep::Mul(5550, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10643PolyExtStep::Add(5624, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10644PolyExtStep::Mul(5552, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10645PolyExtStep::Add(5624, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10646PolyExtStep::Mul(5554, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10647PolyExtStep::Add(5624, 5631), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10648PolyExtStep::Mul(5556, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10649PolyExtStep::Add(5624, 5633), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10650PolyExtStep::Mul(5558, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10651PolyExtStep::Add(5624, 5635), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10652PolyExtStep::Mul(5560, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10653PolyExtStep::Add(5624, 5637), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10654PolyExtStep::Mul(5562, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10655PolyExtStep::Add(5624, 5639), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10656PolyExtStep::Mul(5564, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10657PolyExtStep::Add(5624, 5641), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10658PolyExtStep::Mul(5566, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10659PolyExtStep::Add(5624, 5643), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10660PolyExtStep::Mul(5568, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10661PolyExtStep::Add(5624, 5645), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10662PolyExtStep::Mul(5570, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10663PolyExtStep::Add(5624, 5647), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10664PolyExtStep::Mul(5572, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10665PolyExtStep::Add(5624, 5649), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10666PolyExtStep::Mul(5574, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10667PolyExtStep::Add(5624, 5651), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10668PolyExtStep::Mul(5576, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10669PolyExtStep::Add(5624, 5653), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10670PolyExtStep::Mul(5578, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10671PolyExtStep::Add(5624, 5655), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10672PolyExtStep::Mul(5580, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10673PolyExtStep::Add(5624, 5657), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10674PolyExtStep::Mul(5582, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10675PolyExtStep::Add(5624, 5659), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10676PolyExtStep::Mul(5584, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10677PolyExtStep::Add(5624, 5661), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10678PolyExtStep::Mul(5586, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10679PolyExtStep::Add(5624, 5663), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10680PolyExtStep::Mul(5588, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10681PolyExtStep::Add(5624, 5665), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10682PolyExtStep::Mul(5590, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10683PolyExtStep::Add(5624, 5667), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10684PolyExtStep::Mul(5592, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10685PolyExtStep::Add(5624, 5669), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10686PolyExtStep::Mul(5594, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10687PolyExtStep::Add(5624, 5671), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10688PolyExtStep::Add(5626, 268), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10689PolyExtStep::Mul(5673, 5673), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10690PolyExtStep::Mul(5674, 5673), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10691PolyExtStep::Sub(5675, 635), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10692PolyExtStep::AndEqz(4987, 5676), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10693PolyExtStep::Mul(635, 635), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10694PolyExtStep::Mul(5677, 5673), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10695PolyExtStep::Sub(5678, 628), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10696PolyExtStep::AndEqz(4988, 5679), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10697PolyExtStep::Add(628, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10698PolyExtStep::Add(5680, 5630), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10699PolyExtStep::Add(5681, 5632), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10700PolyExtStep::Add(5682, 5634), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10701PolyExtStep::Add(5683, 5636), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10702PolyExtStep::Add(5684, 5638), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10703PolyExtStep::Add(5685, 5640), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10704PolyExtStep::Add(5686, 5642), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10705PolyExtStep::Add(5687, 5644), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10706PolyExtStep::Add(5688, 5646), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10707PolyExtStep::Add(5689, 5648), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10708PolyExtStep::Add(5690, 5650), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10709PolyExtStep::Add(5691, 5652), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10710PolyExtStep::Add(5692, 5654), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10711PolyExtStep::Add(5693, 5656), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10712PolyExtStep::Add(5694, 5658), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10713PolyExtStep::Add(5695, 5660), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10714PolyExtStep::Add(5696, 5662), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10715PolyExtStep::Add(5697, 5664), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10716PolyExtStep::Add(5698, 5666), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10717PolyExtStep::Add(5699, 5668), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10718PolyExtStep::Add(5700, 5670), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10719PolyExtStep::Add(5701, 5672), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10720PolyExtStep::Mul(628, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10721PolyExtStep::Add(5702, 5703), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10722PolyExtStep::Mul(5628, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10723PolyExtStep::Add(5702, 5705), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10724PolyExtStep::Mul(5630, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10725PolyExtStep::Add(5702, 5707), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10726PolyExtStep::Mul(5632, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10727PolyExtStep::Add(5702, 5709), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10728PolyExtStep::Mul(5634, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10729PolyExtStep::Add(5702, 5711), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10730PolyExtStep::Mul(5636, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10731PolyExtStep::Add(5702, 5713), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10732PolyExtStep::Mul(5638, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10733PolyExtStep::Add(5702, 5715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10734PolyExtStep::Mul(5640, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10735PolyExtStep::Add(5702, 5717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10736PolyExtStep::Mul(5642, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10737PolyExtStep::Add(5702, 5719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10738PolyExtStep::Mul(5644, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10739PolyExtStep::Add(5702, 5721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10740PolyExtStep::Mul(5646, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10741PolyExtStep::Add(5702, 5723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10742PolyExtStep::Mul(5648, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10743PolyExtStep::Add(5702, 5725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10744PolyExtStep::Mul(5650, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10745PolyExtStep::Add(5702, 5727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10746PolyExtStep::Mul(5652, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10747PolyExtStep::Add(5702, 5729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10748PolyExtStep::Mul(5654, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10749PolyExtStep::Add(5702, 5731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10750PolyExtStep::Mul(5656, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10751PolyExtStep::Add(5702, 5733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10752PolyExtStep::Mul(5658, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10753PolyExtStep::Add(5702, 5735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10754PolyExtStep::Mul(5660, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10755PolyExtStep::Add(5702, 5737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10756PolyExtStep::Mul(5662, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10757PolyExtStep::Add(5702, 5739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10758PolyExtStep::Mul(5664, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10759PolyExtStep::Add(5702, 5741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10760PolyExtStep::Mul(5666, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10761PolyExtStep::Add(5702, 5743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10762PolyExtStep::Mul(5668, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10763PolyExtStep::Add(5702, 5745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10764PolyExtStep::Mul(5670, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10765PolyExtStep::Add(5702, 5747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10766PolyExtStep::Mul(5672, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10767PolyExtStep::Add(5702, 5749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10768PolyExtStep::Add(5704, 269), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10769PolyExtStep::Mul(5751, 5751), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10770PolyExtStep::Mul(5752, 5751), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10771PolyExtStep::Sub(5753, 645), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10772PolyExtStep::AndEqz(4989, 5754), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10773PolyExtStep::Mul(5212, 5751), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10774PolyExtStep::Sub(5755, 642), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10775PolyExtStep::AndEqz(4990, 5756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10776PolyExtStep::Add(642, 5706), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10777PolyExtStep::Add(5757, 5708), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10778PolyExtStep::Add(5758, 5710), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10779PolyExtStep::Add(5759, 5712), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10780PolyExtStep::Add(5760, 5714), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10781PolyExtStep::Add(5761, 5716), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10782PolyExtStep::Add(5762, 5718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10783PolyExtStep::Add(5763, 5720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10784PolyExtStep::Add(5764, 5722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10785PolyExtStep::Add(5765, 5724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10786PolyExtStep::Add(5766, 5726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10787PolyExtStep::Add(5767, 5728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10788PolyExtStep::Add(5768, 5730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10789PolyExtStep::Add(5769, 5732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10790PolyExtStep::Add(5770, 5734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10791PolyExtStep::Add(5771, 5736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10792PolyExtStep::Add(5772, 5738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10793PolyExtStep::Add(5773, 5740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10794PolyExtStep::Add(5774, 5742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10795PolyExtStep::Add(5775, 5744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10796PolyExtStep::Add(5776, 5746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10797PolyExtStep::Add(5777, 5748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10798PolyExtStep::Add(5778, 5750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10799PolyExtStep::Mul(642, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10800PolyExtStep::Add(5779, 5780), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10801PolyExtStep::Mul(5706, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10802PolyExtStep::Add(5779, 5782), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10803PolyExtStep::Mul(5708, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10804PolyExtStep::Add(5779, 5784), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10805PolyExtStep::Mul(5710, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10806PolyExtStep::Add(5779, 5786), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10807PolyExtStep::Mul(5712, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10808PolyExtStep::Add(5779, 5788), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10809PolyExtStep::Mul(5714, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10810PolyExtStep::Add(5779, 5790), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10811PolyExtStep::Mul(5716, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10812PolyExtStep::Add(5779, 5792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10813PolyExtStep::Mul(5718, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10814PolyExtStep::Add(5779, 5794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10815PolyExtStep::Mul(5720, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10816PolyExtStep::Add(5779, 5796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10817PolyExtStep::Mul(5722, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10818PolyExtStep::Add(5779, 5798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10819PolyExtStep::Mul(5724, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10820PolyExtStep::Add(5779, 5800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10821PolyExtStep::Mul(5726, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10822PolyExtStep::Add(5779, 5802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10823PolyExtStep::Mul(5728, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10824PolyExtStep::Add(5779, 5804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10825PolyExtStep::Mul(5730, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10826PolyExtStep::Add(5779, 5806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10827PolyExtStep::Mul(5732, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10828PolyExtStep::Add(5779, 5808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10829PolyExtStep::Mul(5734, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10830PolyExtStep::Add(5779, 5810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10831PolyExtStep::Mul(5736, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10832PolyExtStep::Add(5779, 5812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10833PolyExtStep::Mul(5738, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10834PolyExtStep::Add(5779, 5814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10835PolyExtStep::Mul(5740, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10836PolyExtStep::Add(5779, 5816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10837PolyExtStep::Mul(5742, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10838PolyExtStep::Add(5779, 5818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10839PolyExtStep::Mul(5744, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10840PolyExtStep::Add(5779, 5820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10841PolyExtStep::Mul(5746, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10842PolyExtStep::Add(5779, 5822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10843PolyExtStep::Mul(5748, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10844PolyExtStep::Add(5779, 5824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10845PolyExtStep::Mul(5750, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10846PolyExtStep::Add(5779, 5826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10847PolyExtStep::Add(5781, 270), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10848PolyExtStep::Mul(5828, 5828), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10849PolyExtStep::Mul(5829, 5828), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10850PolyExtStep::Sub(5830, 655), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10851PolyExtStep::AndEqz(4991, 5831), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10852PolyExtStep::Mul(5219, 5828), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10853PolyExtStep::Sub(5832, 648), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10854PolyExtStep::AndEqz(4992, 5833), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10855PolyExtStep::Add(648, 5783), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10856PolyExtStep::Add(5834, 5785), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10857PolyExtStep::Add(5835, 5787), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10858PolyExtStep::Add(5836, 5789), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10859PolyExtStep::Add(5837, 5791), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10860PolyExtStep::Add(5838, 5793), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10861PolyExtStep::Add(5839, 5795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10862PolyExtStep::Add(5840, 5797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10863PolyExtStep::Add(5841, 5799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10864PolyExtStep::Add(5842, 5801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10865PolyExtStep::Add(5843, 5803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10866PolyExtStep::Add(5844, 5805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10867PolyExtStep::Add(5845, 5807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10868PolyExtStep::Add(5846, 5809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10869PolyExtStep::Add(5847, 5811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10870PolyExtStep::Add(5848, 5813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10871PolyExtStep::Add(5849, 5815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10872PolyExtStep::Add(5850, 5817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10873PolyExtStep::Add(5851, 5819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10874PolyExtStep::Add(5852, 5821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10875PolyExtStep::Add(5853, 5823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10876PolyExtStep::Add(5854, 5825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10877PolyExtStep::Add(5855, 5827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10878PolyExtStep::Mul(648, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10879PolyExtStep::Add(5856, 5857), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10880PolyExtStep::Mul(5783, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10881PolyExtStep::Add(5856, 5859), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10882PolyExtStep::Mul(5785, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10883PolyExtStep::Add(5856, 5861), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10884PolyExtStep::Mul(5787, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10885PolyExtStep::Add(5856, 5863), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10886PolyExtStep::Mul(5789, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10887PolyExtStep::Add(5856, 5865), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10888PolyExtStep::Mul(5791, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10889PolyExtStep::Add(5856, 5867), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10890PolyExtStep::Mul(5793, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10891PolyExtStep::Add(5856, 5869), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10892PolyExtStep::Mul(5795, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10893PolyExtStep::Add(5856, 5871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10894PolyExtStep::Mul(5797, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10895PolyExtStep::Add(5856, 5873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10896PolyExtStep::Mul(5799, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10897PolyExtStep::Add(5856, 5875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10898PolyExtStep::Mul(5801, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10899PolyExtStep::Add(5856, 5877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10900PolyExtStep::Mul(5803, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10901PolyExtStep::Add(5856, 5879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10902PolyExtStep::Mul(5805, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10903PolyExtStep::Add(5856, 5881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10904PolyExtStep::Mul(5807, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10905PolyExtStep::Add(5856, 5883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10906PolyExtStep::Mul(5809, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10907PolyExtStep::Add(5856, 5885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10908PolyExtStep::Mul(5811, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10909PolyExtStep::Add(5856, 5887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10910PolyExtStep::Mul(5813, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10911PolyExtStep::Add(5856, 5889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10912PolyExtStep::Mul(5815, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10913PolyExtStep::Add(5856, 5891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10914PolyExtStep::Mul(5817, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10915PolyExtStep::Add(5856, 5893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10916PolyExtStep::Mul(5819, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10917PolyExtStep::Add(5856, 5895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10918PolyExtStep::Mul(5821, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10919PolyExtStep::Add(5856, 5897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10920PolyExtStep::Mul(5823, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10921PolyExtStep::Add(5856, 5899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10922PolyExtStep::Mul(5825, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10923PolyExtStep::Add(5856, 5901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10924PolyExtStep::Mul(5827, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10925PolyExtStep::Add(5856, 5903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10926PolyExtStep::Add(5858, 271), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10927PolyExtStep::Mul(5905, 5905), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10928PolyExtStep::Mul(5906, 5905), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10929PolyExtStep::Sub(5907, 669), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10930PolyExtStep::AndEqz(4993, 5908), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10931PolyExtStep::Mul(5226, 5905), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10932PolyExtStep::Sub(5909, 662), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10933PolyExtStep::AndEqz(4994, 5910), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10934PolyExtStep::Add(662, 5860), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10935PolyExtStep::Add(5911, 5862), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10936PolyExtStep::Add(5912, 5864), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10937PolyExtStep::Add(5913, 5866), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10938PolyExtStep::Add(5914, 5868), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10939PolyExtStep::Add(5915, 5870), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10940PolyExtStep::Add(5916, 5872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10941PolyExtStep::Add(5917, 5874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10942PolyExtStep::Add(5918, 5876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10943PolyExtStep::Add(5919, 5878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10944PolyExtStep::Add(5920, 5880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10945PolyExtStep::Add(5921, 5882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10946PolyExtStep::Add(5922, 5884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10947PolyExtStep::Add(5923, 5886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10948PolyExtStep::Add(5924, 5888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10949PolyExtStep::Add(5925, 5890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10950PolyExtStep::Add(5926, 5892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10951PolyExtStep::Add(5927, 5894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10952PolyExtStep::Add(5928, 5896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10953PolyExtStep::Add(5929, 5898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10954PolyExtStep::Add(5930, 5900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10955PolyExtStep::Add(5931, 5902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10956PolyExtStep::Add(5932, 5904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10957PolyExtStep::Mul(662, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10958PolyExtStep::Add(5933, 5934), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10959PolyExtStep::Mul(5860, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10960PolyExtStep::Add(5933, 5936), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10961PolyExtStep::Mul(5862, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10962PolyExtStep::Add(5933, 5938), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10963PolyExtStep::Mul(5864, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10964PolyExtStep::Add(5933, 5940), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10965PolyExtStep::Mul(5866, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10966PolyExtStep::Add(5933, 5942), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10967PolyExtStep::Mul(5868, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10968PolyExtStep::Add(5933, 5944), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10969PolyExtStep::Mul(5870, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10970PolyExtStep::Add(5933, 5946), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10971PolyExtStep::Mul(5872, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10972PolyExtStep::Add(5933, 5948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10973PolyExtStep::Mul(5874, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10974PolyExtStep::Add(5933, 5950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10975PolyExtStep::Mul(5876, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10976PolyExtStep::Add(5933, 5952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10977PolyExtStep::Mul(5878, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10978PolyExtStep::Add(5933, 5954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10979PolyExtStep::Mul(5880, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10980PolyExtStep::Add(5933, 5956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10981PolyExtStep::Mul(5882, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10982PolyExtStep::Add(5933, 5958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10983PolyExtStep::Mul(5884, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10984PolyExtStep::Add(5933, 5960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10985PolyExtStep::Mul(5886, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10986PolyExtStep::Add(5933, 5962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10987PolyExtStep::Mul(5888, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10988PolyExtStep::Add(5933, 5964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10989PolyExtStep::Mul(5890, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10990PolyExtStep::Add(5933, 5966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10991PolyExtStep::Mul(5892, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10992PolyExtStep::Add(5933, 5968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10993PolyExtStep::Mul(5894, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10994PolyExtStep::Add(5933, 5970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10995PolyExtStep::Mul(5896, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10996PolyExtStep::Add(5933, 5972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10997PolyExtStep::Mul(5898, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10998PolyExtStep::Add(5933, 5974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10999PolyExtStep::Mul(5900, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11000PolyExtStep::Add(5933, 5976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11001PolyExtStep::Mul(5902, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11002PolyExtStep::Add(5933, 5978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11003PolyExtStep::Mul(5904, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11004PolyExtStep::Add(5933, 5980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11005PolyExtStep::Add(5935, 272), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11006PolyExtStep::Mul(5982, 5982), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11007PolyExtStep::Mul(5983, 5982), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11008PolyExtStep::Sub(5984, 541), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11009PolyExtStep::AndEqz(4995, 5985), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11010PolyExtStep::Mul(5233, 5982), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11011PolyExtStep::Sub(5986, 672), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11012PolyExtStep::AndEqz(4996, 5987), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11013PolyExtStep::Add(672, 5937), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11014PolyExtStep::Add(5988, 5939), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11015PolyExtStep::Add(5989, 5941), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11016PolyExtStep::Add(5990, 5943), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11017PolyExtStep::Add(5991, 5945), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11018PolyExtStep::Add(5992, 5947), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11019PolyExtStep::Add(5993, 5949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11020PolyExtStep::Add(5994, 5951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11021PolyExtStep::Add(5995, 5953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11022PolyExtStep::Add(5996, 5955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11023PolyExtStep::Add(5997, 5957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11024PolyExtStep::Add(5998, 5959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11025PolyExtStep::Add(5999, 5961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11026PolyExtStep::Add(6000, 5963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11027PolyExtStep::Add(6001, 5965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11028PolyExtStep::Add(6002, 5967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11029PolyExtStep::Add(6003, 5969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11030PolyExtStep::Add(6004, 5971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11031PolyExtStep::Add(6005, 5973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11032PolyExtStep::Add(6006, 5975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11033PolyExtStep::Add(6007, 5977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11034PolyExtStep::Add(6008, 5979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11035PolyExtStep::Add(6009, 5981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11036PolyExtStep::Mul(672, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11037PolyExtStep::Add(6010, 6011), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11038PolyExtStep::Mul(5937, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11039PolyExtStep::Add(6010, 6013), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11040PolyExtStep::Mul(5939, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11041PolyExtStep::Add(6010, 6015), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11042PolyExtStep::Mul(5941, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11043PolyExtStep::Add(6010, 6017), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11044PolyExtStep::Mul(5943, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11045PolyExtStep::Add(6010, 6019), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11046PolyExtStep::Mul(5945, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11047PolyExtStep::Add(6010, 6021), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11048PolyExtStep::Mul(5947, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11049PolyExtStep::Add(6010, 6023), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11050PolyExtStep::Mul(5949, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11051PolyExtStep::Add(6010, 6025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11052PolyExtStep::Mul(5951, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11053PolyExtStep::Add(6010, 6027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11054PolyExtStep::Mul(5953, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11055PolyExtStep::Add(6010, 6029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11056PolyExtStep::Mul(5955, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11057PolyExtStep::Add(6010, 6031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11058PolyExtStep::Mul(5957, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11059PolyExtStep::Add(6010, 6033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11060PolyExtStep::Mul(5959, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11061PolyExtStep::Add(6010, 6035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11062PolyExtStep::Mul(5961, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11063PolyExtStep::Add(6010, 6037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11064PolyExtStep::Mul(5963, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11065PolyExtStep::Add(6010, 6039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11066PolyExtStep::Mul(5965, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11067PolyExtStep::Add(6010, 6041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11068PolyExtStep::Mul(5967, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11069PolyExtStep::Add(6010, 6043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11070PolyExtStep::Mul(5969, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11071PolyExtStep::Add(6010, 6045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11072PolyExtStep::Mul(5971, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11073PolyExtStep::Add(6010, 6047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11074PolyExtStep::Mul(5973, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11075PolyExtStep::Add(6010, 6049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11076PolyExtStep::Mul(5975, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11077PolyExtStep::Add(6010, 6051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11078PolyExtStep::Mul(5977, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11079PolyExtStep::Add(6010, 6053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11080PolyExtStep::Mul(5979, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11081PolyExtStep::Add(6010, 6055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11082PolyExtStep::Mul(5981, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11083PolyExtStep::Add(6010, 6057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11084PolyExtStep::Add(6012, 273), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11085PolyExtStep::Mul(6059, 6059), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11086PolyExtStep::Mul(6060, 6059), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11087PolyExtStep::Sub(6061, 549), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11088PolyExtStep::AndEqz(4997, 6062), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11089PolyExtStep::Mul(5240, 6059), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11090PolyExtStep::Sub(6063, 548), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11091PolyExtStep::AndEqz(4998, 6064), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11092PolyExtStep::Add(548, 6014), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11093PolyExtStep::Add(6065, 6016), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11094PolyExtStep::Add(6066, 6018), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11095PolyExtStep::Add(6067, 6020), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11096PolyExtStep::Add(6068, 6022), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11097PolyExtStep::Add(6069, 6024), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11098PolyExtStep::Add(6070, 6026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11099PolyExtStep::Add(6071, 6028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11100PolyExtStep::Add(6072, 6030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11101PolyExtStep::Add(6073, 6032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11102PolyExtStep::Add(6074, 6034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11103PolyExtStep::Add(6075, 6036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11104PolyExtStep::Add(6076, 6038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11105PolyExtStep::Add(6077, 6040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11106PolyExtStep::Add(6078, 6042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11107PolyExtStep::Add(6079, 6044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11108PolyExtStep::Add(6080, 6046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11109PolyExtStep::Add(6081, 6048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11110PolyExtStep::Add(6082, 6050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11111PolyExtStep::Add(6083, 6052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11112PolyExtStep::Add(6084, 6054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11113PolyExtStep::Add(6085, 6056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11114PolyExtStep::Add(6086, 6058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11115PolyExtStep::Mul(548, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11116PolyExtStep::Add(6087, 6088), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11117PolyExtStep::Mul(6014, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11118PolyExtStep::Add(6087, 6090), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11119PolyExtStep::Mul(6016, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11120PolyExtStep::Add(6087, 6092), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11121PolyExtStep::Mul(6018, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11122PolyExtStep::Add(6087, 6094), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11123PolyExtStep::Mul(6020, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11124PolyExtStep::Add(6087, 6096), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11125PolyExtStep::Mul(6022, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11126PolyExtStep::Add(6087, 6098), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11127PolyExtStep::Mul(6024, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11128PolyExtStep::Add(6087, 6100), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11129PolyExtStep::Mul(6026, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11130PolyExtStep::Add(6087, 6102), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11131PolyExtStep::Mul(6028, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11132PolyExtStep::Add(6087, 6104), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11133PolyExtStep::Mul(6030, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11134PolyExtStep::Add(6087, 6106), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11135PolyExtStep::Mul(6032, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11136PolyExtStep::Add(6087, 6108), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11137PolyExtStep::Mul(6034, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11138PolyExtStep::Add(6087, 6110), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11139PolyExtStep::Mul(6036, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11140PolyExtStep::Add(6087, 6112), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11141PolyExtStep::Mul(6038, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11142PolyExtStep::Add(6087, 6114), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11143PolyExtStep::Mul(6040, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11144PolyExtStep::Add(6087, 6116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11145PolyExtStep::Mul(6042, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11146PolyExtStep::Add(6087, 6118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11147PolyExtStep::Mul(6044, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11148PolyExtStep::Add(6087, 6120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11149PolyExtStep::Mul(6046, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11150PolyExtStep::Add(6087, 6122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11151PolyExtStep::Mul(6048, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11152PolyExtStep::Add(6087, 6124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11153PolyExtStep::Mul(6050, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11154PolyExtStep::Add(6087, 6126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11155PolyExtStep::Mul(6052, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11156PolyExtStep::Add(6087, 6128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11157PolyExtStep::Mul(6054, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11158PolyExtStep::Add(6087, 6130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11159PolyExtStep::Mul(6056, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11160PolyExtStep::Add(6087, 6132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11161PolyExtStep::Mul(6058, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11162PolyExtStep::Add(6087, 6134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11163PolyExtStep::Add(6089, 274), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11164PolyExtStep::Mul(6136, 6136), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11165PolyExtStep::Mul(6137, 6136), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11166PolyExtStep::Sub(6138, 553), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11167PolyExtStep::AndEqz(4999, 6139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11168PolyExtStep::Mul(5247, 6136), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11169PolyExtStep::Sub(6140, 552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11170PolyExtStep::AndEqz(5000, 6141), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11171PolyExtStep::Add(552, 6091), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11172PolyExtStep::Add(6142, 6093), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11173PolyExtStep::Add(6143, 6095), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11174PolyExtStep::Add(6144, 6097), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11175PolyExtStep::Add(6145, 6099), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11176PolyExtStep::Add(6146, 6101), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11177PolyExtStep::Add(6147, 6103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11178PolyExtStep::Add(6148, 6105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11179PolyExtStep::Add(6149, 6107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11180PolyExtStep::Add(6150, 6109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11181PolyExtStep::Add(6151, 6111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11182PolyExtStep::Add(6152, 6113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11183PolyExtStep::Add(6153, 6115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11184PolyExtStep::Add(6154, 6117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11185PolyExtStep::Add(6155, 6119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11186PolyExtStep::Add(6156, 6121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11187PolyExtStep::Add(6157, 6123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11188PolyExtStep::Add(6158, 6125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11189PolyExtStep::Add(6159, 6127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11190PolyExtStep::Add(6160, 6129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11191PolyExtStep::Add(6161, 6131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11192PolyExtStep::Add(6162, 6133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11193PolyExtStep::Add(6163, 6135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11194PolyExtStep::Mul(552, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11195PolyExtStep::Add(6164, 6165), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11196PolyExtStep::Mul(6091, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11197PolyExtStep::Add(6164, 6167), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11198PolyExtStep::Mul(6093, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11199PolyExtStep::Add(6164, 6169), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11200PolyExtStep::Mul(6095, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11201PolyExtStep::Add(6164, 6171), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11202PolyExtStep::Mul(6097, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11203PolyExtStep::Add(6164, 6173), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11204PolyExtStep::Mul(6099, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11205PolyExtStep::Add(6164, 6175), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11206PolyExtStep::Mul(6101, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11207PolyExtStep::Add(6164, 6177), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11208PolyExtStep::Mul(6103, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11209PolyExtStep::Add(6164, 6179), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11210PolyExtStep::Mul(6105, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11211PolyExtStep::Add(6164, 6181), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11212PolyExtStep::Mul(6107, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11213PolyExtStep::Add(6164, 6183), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11214PolyExtStep::Mul(6109, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11215PolyExtStep::Add(6164, 6185), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11216PolyExtStep::Mul(6111, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11217PolyExtStep::Add(6164, 6187), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11218PolyExtStep::Mul(6113, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11219PolyExtStep::Add(6164, 6189), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11220PolyExtStep::Mul(6115, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11221PolyExtStep::Add(6164, 6191), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11222PolyExtStep::Mul(6117, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11223PolyExtStep::Add(6164, 6193), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11224PolyExtStep::Mul(6119, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11225PolyExtStep::Add(6164, 6195), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11226PolyExtStep::Mul(6121, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11227PolyExtStep::Add(6164, 6197), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11228PolyExtStep::Mul(6123, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11229PolyExtStep::Add(6164, 6199), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11230PolyExtStep::Mul(6125, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11231PolyExtStep::Add(6164, 6201), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11232PolyExtStep::Mul(6127, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11233PolyExtStep::Add(6164, 6203), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11234PolyExtStep::Mul(6129, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11235PolyExtStep::Add(6164, 6205), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11236PolyExtStep::Mul(6131, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11237PolyExtStep::Add(6164, 6207), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11238PolyExtStep::Mul(6133, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11239PolyExtStep::Add(6164, 6209), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11240PolyExtStep::Mul(6135, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11241PolyExtStep::Add(6164, 6211), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11242PolyExtStep::Add(6166, 275), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11243PolyExtStep::Mul(6213, 6213), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11244PolyExtStep::Mul(6214, 6213), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11245PolyExtStep::Sub(6215, 561), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11246PolyExtStep::AndEqz(5001, 6216), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11247PolyExtStep::Mul(5254, 6213), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11248PolyExtStep::Sub(6217, 560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11249PolyExtStep::AndEqz(5002, 6218), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11250PolyExtStep::Add(560, 6168), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11251PolyExtStep::Add(6219, 6170), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11252PolyExtStep::Add(6220, 6172), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11253PolyExtStep::Add(6221, 6174), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11254PolyExtStep::Add(6222, 6176), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11255PolyExtStep::Add(6223, 6178), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11256PolyExtStep::Add(6224, 6180), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11257PolyExtStep::Add(6225, 6182), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11258PolyExtStep::Add(6226, 6184), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11259PolyExtStep::Add(6227, 6186), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11260PolyExtStep::Add(6228, 6188), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11261PolyExtStep::Add(6229, 6190), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11262PolyExtStep::Add(6230, 6192), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11263PolyExtStep::Add(6231, 6194), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11264PolyExtStep::Add(6232, 6196), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11265PolyExtStep::Add(6233, 6198), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11266PolyExtStep::Add(6234, 6200), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11267PolyExtStep::Add(6235, 6202), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11268PolyExtStep::Add(6236, 6204), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11269PolyExtStep::Add(6237, 6206), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11270PolyExtStep::Add(6238, 6208), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11271PolyExtStep::Add(6239, 6210), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11272PolyExtStep::Add(6240, 6212), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11273PolyExtStep::Mul(560, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11274PolyExtStep::Add(6241, 6242), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11275PolyExtStep::Mul(6168, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11276PolyExtStep::Add(6241, 6244), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11277PolyExtStep::Mul(6170, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11278PolyExtStep::Add(6241, 6246), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11279PolyExtStep::Mul(6172, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11280PolyExtStep::Add(6241, 6248), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11281PolyExtStep::Mul(6174, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11282PolyExtStep::Add(6241, 6250), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11283PolyExtStep::Mul(6176, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11284PolyExtStep::Add(6241, 6252), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11285PolyExtStep::Mul(6178, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11286PolyExtStep::Add(6241, 6254), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11287PolyExtStep::Mul(6180, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11288PolyExtStep::Add(6241, 6256), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11289PolyExtStep::Mul(6182, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11290PolyExtStep::Add(6241, 6258), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11291PolyExtStep::Mul(6184, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11292PolyExtStep::Add(6241, 6260), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11293PolyExtStep::Mul(6186, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11294PolyExtStep::Add(6241, 6262), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11295PolyExtStep::Mul(6188, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11296PolyExtStep::Add(6241, 6264), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11297PolyExtStep::Mul(6190, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11298PolyExtStep::Add(6241, 6266), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11299PolyExtStep::Mul(6192, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11300PolyExtStep::Add(6241, 6268), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11301PolyExtStep::Mul(6194, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11302PolyExtStep::Add(6241, 6270), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11303PolyExtStep::Mul(6196, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11304PolyExtStep::Add(6241, 6272), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11305PolyExtStep::Mul(6198, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11306PolyExtStep::Add(6241, 6274), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11307PolyExtStep::Mul(6200, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11308PolyExtStep::Add(6241, 6276), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11309PolyExtStep::Mul(6202, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11310PolyExtStep::Add(6241, 6278), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11311PolyExtStep::Mul(6204, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11312PolyExtStep::Add(6241, 6280), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11313PolyExtStep::Mul(6206, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11314PolyExtStep::Add(6241, 6282), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11315PolyExtStep::Mul(6208, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11316PolyExtStep::Add(6241, 6284), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11317PolyExtStep::Mul(6210, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11318PolyExtStep::Add(6241, 6286), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11319PolyExtStep::Mul(6212, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11320PolyExtStep::Add(6241, 6288), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11321PolyExtStep::Add(6243, 276), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11322PolyExtStep::Mul(6290, 6290), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11323PolyExtStep::Mul(6291, 6290), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11324PolyExtStep::Sub(6292, 567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11325PolyExtStep::AndEqz(5003, 6293), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11326PolyExtStep::Mul(5261, 6290), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11327PolyExtStep::Sub(6294, 568), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11328PolyExtStep::AndEqz(5004, 6295), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11329PolyExtStep::Add(568, 6245), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11330PolyExtStep::Add(6296, 6247), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11331PolyExtStep::Add(6297, 6249), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11332PolyExtStep::Add(6298, 6251), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11333PolyExtStep::Add(6299, 6253), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11334PolyExtStep::Add(6300, 6255), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11335PolyExtStep::Add(6301, 6257), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11336PolyExtStep::Add(6302, 6259), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11337PolyExtStep::Add(6303, 6261), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11338PolyExtStep::Add(6304, 6263), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11339PolyExtStep::Add(6305, 6265), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11340PolyExtStep::Add(6306, 6267), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11341PolyExtStep::Add(6307, 6269), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11342PolyExtStep::Add(6308, 6271), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11343PolyExtStep::Add(6309, 6273), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11344PolyExtStep::Add(6310, 6275), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11345PolyExtStep::Add(6311, 6277), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11346PolyExtStep::Add(6312, 6279), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11347PolyExtStep::Add(6313, 6281), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11348PolyExtStep::Add(6314, 6283), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11349PolyExtStep::Add(6315, 6285), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11350PolyExtStep::Add(6316, 6287), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11351PolyExtStep::Add(6317, 6289), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11352PolyExtStep::Mul(568, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11353PolyExtStep::Add(6318, 6319), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11354PolyExtStep::Mul(6245, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11355PolyExtStep::Add(6318, 6321), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11356PolyExtStep::Mul(6247, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11357PolyExtStep::Add(6318, 6323), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11358PolyExtStep::Mul(6249, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11359PolyExtStep::Add(6318, 6325), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11360PolyExtStep::Mul(6251, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11361PolyExtStep::Add(6318, 6327), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11362PolyExtStep::Mul(6253, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11363PolyExtStep::Add(6318, 6329), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11364PolyExtStep::Mul(6255, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11365PolyExtStep::Add(6318, 6331), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11366PolyExtStep::Mul(6257, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11367PolyExtStep::Add(6318, 6333), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11368PolyExtStep::Mul(6259, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11369PolyExtStep::Add(6318, 6335), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11370PolyExtStep::Mul(6261, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11371PolyExtStep::Add(6318, 6337), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11372PolyExtStep::Mul(6263, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11373PolyExtStep::Add(6318, 6339), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11374PolyExtStep::Mul(6265, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11375PolyExtStep::Add(6318, 6341), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11376PolyExtStep::Mul(6267, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11377PolyExtStep::Add(6318, 6343), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11378PolyExtStep::Mul(6269, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11379PolyExtStep::Add(6318, 6345), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11380PolyExtStep::Mul(6271, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11381PolyExtStep::Add(6318, 6347), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11382PolyExtStep::Mul(6273, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11383PolyExtStep::Add(6318, 6349), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11384PolyExtStep::Mul(6275, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11385PolyExtStep::Add(6318, 6351), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11386PolyExtStep::Mul(6277, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11387PolyExtStep::Add(6318, 6353), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11388PolyExtStep::Mul(6279, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11389PolyExtStep::Add(6318, 6355), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11390PolyExtStep::Mul(6281, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11391PolyExtStep::Add(6318, 6357), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11392PolyExtStep::Mul(6283, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11393PolyExtStep::Add(6318, 6359), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11394PolyExtStep::Mul(6285, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11395PolyExtStep::Add(6318, 6361), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11396PolyExtStep::Mul(6287, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11397PolyExtStep::Add(6318, 6363), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11398PolyExtStep::Mul(6289, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11399PolyExtStep::Add(6318, 6365), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11400PolyExtStep::Add(6320, 277), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11401PolyExtStep::Mul(6367, 6367), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11402PolyExtStep::Mul(6368, 6367), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11403PolyExtStep::Sub(6369, 570), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11404PolyExtStep::AndEqz(5005, 6370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11405PolyExtStep::Mul(5268, 6367), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11406PolyExtStep::Sub(6371, 569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11407PolyExtStep::AndEqz(5006, 6372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11408PolyExtStep::Add(569, 6322), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11409PolyExtStep::Add(6373, 6324), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11410PolyExtStep::Add(6374, 6326), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11411PolyExtStep::Add(6375, 6328), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11412PolyExtStep::Add(6376, 6330), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11413PolyExtStep::Add(6377, 6332), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11414PolyExtStep::Add(6378, 6334), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11415PolyExtStep::Add(6379, 6336), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11416PolyExtStep::Add(6380, 6338), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11417PolyExtStep::Add(6381, 6340), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11418PolyExtStep::Add(6382, 6342), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11419PolyExtStep::Add(6383, 6344), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11420PolyExtStep::Add(6384, 6346), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11421PolyExtStep::Add(6385, 6348), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11422PolyExtStep::Add(6386, 6350), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11423PolyExtStep::Add(6387, 6352), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11424PolyExtStep::Add(6388, 6354), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11425PolyExtStep::Add(6389, 6356), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11426PolyExtStep::Add(6390, 6358), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11427PolyExtStep::Add(6391, 6360), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11428PolyExtStep::Add(6392, 6362), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11429PolyExtStep::Add(6393, 6364), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11430PolyExtStep::Add(6394, 6366), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11431PolyExtStep::Mul(569, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11432PolyExtStep::Add(6395, 6396), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11433PolyExtStep::Mul(6322, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11434PolyExtStep::Add(6395, 6398), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11435PolyExtStep::Mul(6324, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11436PolyExtStep::Add(6395, 6400), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11437PolyExtStep::Mul(6326, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11438PolyExtStep::Add(6395, 6402), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11439PolyExtStep::Mul(6328, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11440PolyExtStep::Add(6395, 6404), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11441PolyExtStep::Mul(6330, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11442PolyExtStep::Add(6395, 6406), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11443PolyExtStep::Mul(6332, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11444PolyExtStep::Add(6395, 6408), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11445PolyExtStep::Mul(6334, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11446PolyExtStep::Add(6395, 6410), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11447PolyExtStep::Mul(6336, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11448PolyExtStep::Add(6395, 6412), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11449PolyExtStep::Mul(6338, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11450PolyExtStep::Add(6395, 6414), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11451PolyExtStep::Mul(6340, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11452PolyExtStep::Add(6395, 6416), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11453PolyExtStep::Mul(6342, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11454PolyExtStep::Add(6395, 6418), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11455PolyExtStep::Mul(6344, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11456PolyExtStep::Add(6395, 6420), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11457PolyExtStep::Mul(6346, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11458PolyExtStep::Add(6395, 6422), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11459PolyExtStep::Mul(6348, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11460PolyExtStep::Add(6395, 6424), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11461PolyExtStep::Mul(6350, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11462PolyExtStep::Add(6395, 6426), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11463PolyExtStep::Mul(6352, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11464PolyExtStep::Add(6395, 6428), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11465PolyExtStep::Mul(6354, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11466PolyExtStep::Add(6395, 6430), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11467PolyExtStep::Mul(6356, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11468PolyExtStep::Add(6395, 6432), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11469PolyExtStep::Mul(6358, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11470PolyExtStep::Add(6395, 6434), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11471PolyExtStep::Mul(6360, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11472PolyExtStep::Add(6395, 6436), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11473PolyExtStep::Mul(6362, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11474PolyExtStep::Add(6395, 6438), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11475PolyExtStep::Mul(6364, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11476PolyExtStep::Add(6395, 6440), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11477PolyExtStep::Mul(6366, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11478PolyExtStep::Add(6395, 6442), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11479PolyExtStep::Add(6397, 278), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11480PolyExtStep::Mul(6444, 6444), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11481PolyExtStep::Mul(6445, 6444), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11482PolyExtStep::Sub(6446, 572), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11483PolyExtStep::AndEqz(5007, 6447), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11484PolyExtStep::Mul(5275, 6444), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11485PolyExtStep::Sub(6448, 571), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11486PolyExtStep::AndEqz(5008, 6449), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11487PolyExtStep::Add(571, 6399), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11488PolyExtStep::Add(6450, 6401), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11489PolyExtStep::Add(6451, 6403), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11490PolyExtStep::Add(6452, 6405), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11491PolyExtStep::Add(6453, 6407), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11492PolyExtStep::Add(6454, 6409), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11493PolyExtStep::Add(6455, 6411), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11494PolyExtStep::Add(6456, 6413), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11495PolyExtStep::Add(6457, 6415), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11496PolyExtStep::Add(6458, 6417), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11497PolyExtStep::Add(6459, 6419), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11498PolyExtStep::Add(6460, 6421), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11499PolyExtStep::Add(6461, 6423), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11500PolyExtStep::Add(6462, 6425), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11501PolyExtStep::Add(6463, 6427), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11502PolyExtStep::Add(6464, 6429), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11503PolyExtStep::Add(6465, 6431), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11504PolyExtStep::Add(6466, 6433), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11505PolyExtStep::Add(6467, 6435), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11506PolyExtStep::Add(6468, 6437), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11507PolyExtStep::Add(6469, 6439), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11508PolyExtStep::Add(6470, 6441), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11509PolyExtStep::Add(6471, 6443), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11510PolyExtStep::Mul(571, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11511PolyExtStep::Add(6472, 6473), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11512PolyExtStep::Mul(6399, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11513PolyExtStep::Add(6472, 6475), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11514PolyExtStep::Mul(6401, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11515PolyExtStep::Add(6472, 6477), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11516PolyExtStep::Mul(6403, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11517PolyExtStep::Add(6472, 6479), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11518PolyExtStep::Mul(6405, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11519PolyExtStep::Add(6472, 6481), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11520PolyExtStep::Mul(6407, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11521PolyExtStep::Add(6472, 6483), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11522PolyExtStep::Mul(6409, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11523PolyExtStep::Add(6472, 6485), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11524PolyExtStep::Mul(6411, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11525PolyExtStep::Add(6472, 6487), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11526PolyExtStep::Mul(6413, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11527PolyExtStep::Add(6472, 6489), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11528PolyExtStep::Mul(6415, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11529PolyExtStep::Add(6472, 6491), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11530PolyExtStep::Mul(6417, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11531PolyExtStep::Add(6472, 6493), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11532PolyExtStep::Mul(6419, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11533PolyExtStep::Add(6472, 6495), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11534PolyExtStep::Mul(6421, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11535PolyExtStep::Add(6472, 6497), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11536PolyExtStep::Mul(6423, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11537PolyExtStep::Add(6472, 6499), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11538PolyExtStep::Mul(6425, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11539PolyExtStep::Add(6472, 6501), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11540PolyExtStep::Mul(6427, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11541PolyExtStep::Add(6472, 6503), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11542PolyExtStep::Mul(6429, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11543PolyExtStep::Add(6472, 6505), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11544PolyExtStep::Mul(6431, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11545PolyExtStep::Add(6472, 6507), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11546PolyExtStep::Mul(6433, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11547PolyExtStep::Add(6472, 6509), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11548PolyExtStep::Mul(6435, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11549PolyExtStep::Add(6472, 6511), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11550PolyExtStep::Mul(6437, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11551PolyExtStep::Add(6472, 6513), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11552PolyExtStep::Mul(6439, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11553PolyExtStep::Add(6472, 6515), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11554PolyExtStep::Mul(6441, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11555PolyExtStep::Add(6472, 6517), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11556PolyExtStep::Mul(6443, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11557PolyExtStep::Add(6472, 6519), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11558PolyExtStep::Add(6474, 279), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11559PolyExtStep::Mul(6521, 6521), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11560PolyExtStep::Mul(6522, 6521), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11561PolyExtStep::Sub(6523, 574), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11562PolyExtStep::AndEqz(5009, 6524), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11563PolyExtStep::Mul(5282, 6521), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11564PolyExtStep::Sub(6525, 573), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11565PolyExtStep::AndEqz(5010, 6526), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11566PolyExtStep::Add(573, 6476), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11567PolyExtStep::Add(6527, 6478), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11568PolyExtStep::Add(6528, 6480), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11569PolyExtStep::Add(6529, 6482), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11570PolyExtStep::Add(6530, 6484), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11571PolyExtStep::Add(6531, 6486), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11572PolyExtStep::Add(6532, 6488), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11573PolyExtStep::Add(6533, 6490), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11574PolyExtStep::Add(6534, 6492), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11575PolyExtStep::Add(6535, 6494), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11576PolyExtStep::Add(6536, 6496), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11577PolyExtStep::Add(6537, 6498), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11578PolyExtStep::Add(6538, 6500), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11579PolyExtStep::Add(6539, 6502), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11580PolyExtStep::Add(6540, 6504), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11581PolyExtStep::Add(6541, 6506), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11582PolyExtStep::Add(6542, 6508), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11583PolyExtStep::Add(6543, 6510), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11584PolyExtStep::Add(6544, 6512), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11585PolyExtStep::Add(6545, 6514), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11586PolyExtStep::Add(6546, 6516), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11587PolyExtStep::Add(6547, 6518), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11588PolyExtStep::Add(6548, 6520), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11589PolyExtStep::Mul(573, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11590PolyExtStep::Add(6549, 6550), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11591PolyExtStep::Mul(6476, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11592PolyExtStep::Add(6549, 6552), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11593PolyExtStep::Mul(6478, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11594PolyExtStep::Add(6549, 6554), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11595PolyExtStep::Mul(6480, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11596PolyExtStep::Add(6549, 6556), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11597PolyExtStep::Mul(6482, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11598PolyExtStep::Add(6549, 6558), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11599PolyExtStep::Mul(6484, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11600PolyExtStep::Add(6549, 6560), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11601PolyExtStep::Mul(6486, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11602PolyExtStep::Add(6549, 6562), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11603PolyExtStep::Mul(6488, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11604PolyExtStep::Add(6549, 6564), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11605PolyExtStep::Mul(6490, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11606PolyExtStep::Add(6549, 6566), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11607PolyExtStep::Mul(6492, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11608PolyExtStep::Add(6549, 6568), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11609PolyExtStep::Mul(6494, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11610PolyExtStep::Add(6549, 6570), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11611PolyExtStep::Mul(6496, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11612PolyExtStep::Add(6549, 6572), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11613PolyExtStep::Mul(6498, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11614PolyExtStep::Add(6549, 6574), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11615PolyExtStep::Mul(6500, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11616PolyExtStep::Add(6549, 6576), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11617PolyExtStep::Mul(6502, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11618PolyExtStep::Add(6549, 6578), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11619PolyExtStep::Mul(6504, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11620PolyExtStep::Add(6549, 6580), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11621PolyExtStep::Mul(6506, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11622PolyExtStep::Add(6549, 6582), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11623PolyExtStep::Mul(6508, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11624PolyExtStep::Add(6549, 6584), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11625PolyExtStep::Mul(6510, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11626PolyExtStep::Add(6549, 6586), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11627PolyExtStep::Mul(6512, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11628PolyExtStep::Add(6549, 6588), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11629PolyExtStep::Mul(6514, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11630PolyExtStep::Add(6549, 6590), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11631PolyExtStep::Mul(6516, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11632PolyExtStep::Add(6549, 6592), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11633PolyExtStep::Mul(6518, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11634PolyExtStep::Add(6549, 6594), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11635PolyExtStep::Mul(6520, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11636PolyExtStep::Add(6549, 6596), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11637PolyExtStep::Add(6551, 280), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11638PolyExtStep::Mul(6598, 6598), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11639PolyExtStep::Mul(6599, 6598), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11640PolyExtStep::Sub(6600, 583), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11641PolyExtStep::AndEqz(5011, 6601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11642PolyExtStep::Mul(5289, 6598), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11643PolyExtStep::Sub(6602, 575), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11644PolyExtStep::AndEqz(5012, 6603), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11645PolyExtStep::Add(575, 6553), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11646PolyExtStep::Add(6604, 6555), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11647PolyExtStep::Add(6605, 6557), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11648PolyExtStep::Add(6606, 6559), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11649PolyExtStep::Add(6607, 6561), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11650PolyExtStep::Add(6608, 6563), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11651PolyExtStep::Add(6609, 6565), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11652PolyExtStep::Add(6610, 6567), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11653PolyExtStep::Add(6611, 6569), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11654PolyExtStep::Add(6612, 6571), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11655PolyExtStep::Add(6613, 6573), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11656PolyExtStep::Add(6614, 6575), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11657PolyExtStep::Add(6615, 6577), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11658PolyExtStep::Add(6616, 6579), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11659PolyExtStep::Add(6617, 6581), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11660PolyExtStep::Add(6618, 6583), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11661PolyExtStep::Add(6619, 6585), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11662PolyExtStep::Add(6620, 6587), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11663PolyExtStep::Add(6621, 6589), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11664PolyExtStep::Add(6622, 6591), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11665PolyExtStep::Add(6623, 6593), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11666PolyExtStep::Add(6624, 6595), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11667PolyExtStep::Add(6625, 6597), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11668PolyExtStep::Mul(575, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11669PolyExtStep::Add(6626, 6627), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11670PolyExtStep::Mul(6553, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11671PolyExtStep::Add(6626, 6629), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11672PolyExtStep::Mul(6555, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11673PolyExtStep::Add(6626, 6631), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11674PolyExtStep::Mul(6557, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11675PolyExtStep::Add(6626, 6633), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11676PolyExtStep::Mul(6559, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11677PolyExtStep::Add(6626, 6635), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11678PolyExtStep::Mul(6561, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11679PolyExtStep::Add(6626, 6637), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11680PolyExtStep::Mul(6563, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11681PolyExtStep::Add(6626, 6639), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11682PolyExtStep::Mul(6565, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11683PolyExtStep::Add(6626, 6641), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11684PolyExtStep::Mul(6567, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11685PolyExtStep::Add(6626, 6643), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11686PolyExtStep::Mul(6569, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11687PolyExtStep::Add(6626, 6645), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11688PolyExtStep::Mul(6571, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11689PolyExtStep::Add(6626, 6647), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11690PolyExtStep::Mul(6573, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11691PolyExtStep::Add(6626, 6649), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11692PolyExtStep::Mul(6575, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11693PolyExtStep::Add(6626, 6651), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11694PolyExtStep::Mul(6577, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11695PolyExtStep::Add(6626, 6653), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11696PolyExtStep::Mul(6579, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11697PolyExtStep::Add(6626, 6655), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11698PolyExtStep::Mul(6581, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11699PolyExtStep::Add(6626, 6657), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11700PolyExtStep::Mul(6583, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11701PolyExtStep::Add(6626, 6659), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11702PolyExtStep::Mul(6585, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11703PolyExtStep::Add(6626, 6661), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11704PolyExtStep::Mul(6587, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11705PolyExtStep::Add(6626, 6663), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11706PolyExtStep::Mul(6589, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11707PolyExtStep::Add(6626, 6665), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11708PolyExtStep::Mul(6591, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11709PolyExtStep::Add(6626, 6667), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11710PolyExtStep::Mul(6593, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11711PolyExtStep::Add(6626, 6669), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11712PolyExtStep::Mul(6595, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11713PolyExtStep::Add(6626, 6671), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11714PolyExtStep::Mul(6597, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11715PolyExtStep::Add(6626, 6673), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11716PolyExtStep::Add(6628, 281), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11717PolyExtStep::Mul(6675, 6675), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11718PolyExtStep::Mul(6676, 6675), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11719PolyExtStep::Sub(6677, 732), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11720PolyExtStep::AndEqz(5013, 6678), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11721PolyExtStep::Mul(5296, 6675), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11722PolyExtStep::Sub(6679, 584), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11723PolyExtStep::AndEqz(5014, 6680), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11724PolyExtStep::Add(584, 6630), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11725PolyExtStep::Add(6681, 6632), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11726PolyExtStep::Add(6682, 6634), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11727PolyExtStep::Add(6683, 6636), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11728PolyExtStep::Add(6684, 6638), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11729PolyExtStep::Add(6685, 6640), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11730PolyExtStep::Add(6686, 6642), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11731PolyExtStep::Add(6687, 6644), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11732PolyExtStep::Add(6688, 6646), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11733PolyExtStep::Add(6689, 6648), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11734PolyExtStep::Add(6690, 6650), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11735PolyExtStep::Add(6691, 6652), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11736PolyExtStep::Add(6692, 6654), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11737PolyExtStep::Add(6693, 6656), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11738PolyExtStep::Add(6694, 6658), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11739PolyExtStep::Add(6695, 6660), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11740PolyExtStep::Add(6696, 6662), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11741PolyExtStep::Add(6697, 6664), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11742PolyExtStep::Add(6698, 6666), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11743PolyExtStep::Add(6699, 6668), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11744PolyExtStep::Add(6700, 6670), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11745PolyExtStep::Add(6701, 6672), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11746PolyExtStep::Add(6702, 6674), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11747PolyExtStep::Mul(584, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11748PolyExtStep::Add(6703, 6704), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11749PolyExtStep::Mul(6630, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11750PolyExtStep::Add(6703, 6706), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11751PolyExtStep::Mul(6632, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11752PolyExtStep::Add(6703, 6708), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11753PolyExtStep::Mul(6634, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11754PolyExtStep::Add(6703, 6710), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11755PolyExtStep::Mul(6636, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11756PolyExtStep::Add(6703, 6712), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11757PolyExtStep::Mul(6638, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11758PolyExtStep::Add(6703, 6714), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11759PolyExtStep::Mul(6640, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11760PolyExtStep::Add(6703, 6716), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11761PolyExtStep::Mul(6642, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11762PolyExtStep::Add(6703, 6718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11763PolyExtStep::Mul(6644, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11764PolyExtStep::Add(6703, 6720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11765PolyExtStep::Mul(6646, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11766PolyExtStep::Add(6703, 6722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11767PolyExtStep::Mul(6648, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11768PolyExtStep::Add(6703, 6724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11769PolyExtStep::Mul(6650, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11770PolyExtStep::Add(6703, 6726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11771PolyExtStep::Mul(6652, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11772PolyExtStep::Add(6703, 6728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11773PolyExtStep::Mul(6654, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11774PolyExtStep::Add(6703, 6730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11775PolyExtStep::Mul(6656, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11776PolyExtStep::Add(6703, 6732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11777PolyExtStep::Mul(6658, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11778PolyExtStep::Add(6703, 6734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11779PolyExtStep::Mul(6660, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11780PolyExtStep::Add(6703, 6736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11781PolyExtStep::Mul(6662, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11782PolyExtStep::Add(6703, 6738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11783PolyExtStep::Mul(6664, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11784PolyExtStep::Add(6703, 6740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11785PolyExtStep::Mul(6666, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11786PolyExtStep::Add(6703, 6742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11787PolyExtStep::Mul(6668, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11788PolyExtStep::Add(6703, 6744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11789PolyExtStep::Mul(6670, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11790PolyExtStep::Add(6703, 6746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11791PolyExtStep::Mul(6672, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11792PolyExtStep::Add(6703, 6748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11793PolyExtStep::Mul(6674, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11794PolyExtStep::Add(6703, 6750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11795PolyExtStep::Add(6705, 282), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11796PolyExtStep::Mul(6752, 6752), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11797PolyExtStep::Mul(6753, 6752), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11798PolyExtStep::Sub(6754, 733), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11799PolyExtStep::AndEqz(5015, 6755), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11800PolyExtStep::Mul(5303, 6752), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11801PolyExtStep::Sub(6756, 731), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11802PolyExtStep::AndEqz(5016, 6757), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11803PolyExtStep::Add(731, 6707), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11804PolyExtStep::Add(6758, 6709), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11805PolyExtStep::Add(6759, 6711), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11806PolyExtStep::Add(6760, 6713), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11807PolyExtStep::Add(6761, 6715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11808PolyExtStep::Add(6762, 6717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11809PolyExtStep::Add(6763, 6719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11810PolyExtStep::Add(6764, 6721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11811PolyExtStep::Add(6765, 6723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11812PolyExtStep::Add(6766, 6725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11813PolyExtStep::Add(6767, 6727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11814PolyExtStep::Add(6768, 6729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11815PolyExtStep::Add(6769, 6731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11816PolyExtStep::Add(6770, 6733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11817PolyExtStep::Add(6771, 6735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11818PolyExtStep::Add(6772, 6737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11819PolyExtStep::Add(6773, 6739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11820PolyExtStep::Add(6774, 6741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11821PolyExtStep::Add(6775, 6743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11822PolyExtStep::Add(6776, 6745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11823PolyExtStep::Add(6777, 6747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11824PolyExtStep::Add(6778, 6749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11825PolyExtStep::Add(6779, 6751), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11826PolyExtStep::Mul(731, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11827PolyExtStep::Add(6780, 6781), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11828PolyExtStep::Mul(6707, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11829PolyExtStep::Add(6780, 6783), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11830PolyExtStep::Mul(6709, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11831PolyExtStep::Add(6780, 6785), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11832PolyExtStep::Mul(6711, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11833PolyExtStep::Add(6780, 6787), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11834PolyExtStep::Mul(6713, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11835PolyExtStep::Add(6780, 6789), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11836PolyExtStep::Mul(6715, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11837PolyExtStep::Add(6780, 6791), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11838PolyExtStep::Mul(6717, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11839PolyExtStep::Add(6780, 6793), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11840PolyExtStep::Mul(6719, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11841PolyExtStep::Add(6780, 6795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11842PolyExtStep::Mul(6721, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11843PolyExtStep::Add(6780, 6797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11844PolyExtStep::Mul(6723, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11845PolyExtStep::Add(6780, 6799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11846PolyExtStep::Mul(6725, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11847PolyExtStep::Add(6780, 6801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11848PolyExtStep::Mul(6727, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11849PolyExtStep::Add(6780, 6803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11850PolyExtStep::Mul(6729, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11851PolyExtStep::Add(6780, 6805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11852PolyExtStep::Mul(6731, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11853PolyExtStep::Add(6780, 6807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11854PolyExtStep::Mul(6733, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11855PolyExtStep::Add(6780, 6809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11856PolyExtStep::Mul(6735, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11857PolyExtStep::Add(6780, 6811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11858PolyExtStep::Mul(6737, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11859PolyExtStep::Add(6780, 6813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11860PolyExtStep::Mul(6739, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11861PolyExtStep::Add(6780, 6815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11862PolyExtStep::Mul(6741, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11863PolyExtStep::Add(6780, 6817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11864PolyExtStep::Mul(6743, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11865PolyExtStep::Add(6780, 6819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11866PolyExtStep::Mul(6745, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11867PolyExtStep::Add(6780, 6821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11868PolyExtStep::Mul(6747, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11869PolyExtStep::Add(6780, 6823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11870PolyExtStep::Mul(6749, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11871PolyExtStep::Add(6780, 6825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11872PolyExtStep::Mul(6751, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11873PolyExtStep::Add(6780, 6827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11874PolyExtStep::Add(6782, 283), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11875PolyExtStep::Mul(6829, 6829), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11876PolyExtStep::Mul(6830, 6829), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11877PolyExtStep::Sub(6831, 735), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11878PolyExtStep::AndEqz(5017, 6832), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11879PolyExtStep::Mul(5310, 6829), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11880PolyExtStep::Sub(6833, 734), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11881PolyExtStep::AndEqz(5018, 6834), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11882PolyExtStep::Add(734, 6784), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11883PolyExtStep::Add(6835, 6786), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11884PolyExtStep::Add(6836, 6788), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11885PolyExtStep::Add(6837, 6790), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11886PolyExtStep::Add(6838, 6792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11887PolyExtStep::Add(6839, 6794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11888PolyExtStep::Add(6840, 6796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11889PolyExtStep::Add(6841, 6798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11890PolyExtStep::Add(6842, 6800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11891PolyExtStep::Add(6843, 6802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11892PolyExtStep::Add(6844, 6804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11893PolyExtStep::Add(6845, 6806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11894PolyExtStep::Add(6846, 6808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11895PolyExtStep::Add(6847, 6810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11896PolyExtStep::Add(6848, 6812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11897PolyExtStep::Add(6849, 6814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11898PolyExtStep::Add(6850, 6816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11899PolyExtStep::Add(6851, 6818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11900PolyExtStep::Add(6852, 6820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11901PolyExtStep::Add(6853, 6822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11902PolyExtStep::Add(6854, 6824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11903PolyExtStep::Add(6855, 6826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11904PolyExtStep::Add(6856, 6828), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11905PolyExtStep::Mul(734, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11906PolyExtStep::Add(6857, 6858), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11907PolyExtStep::Mul(6784, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11908PolyExtStep::Add(6857, 6860), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11909PolyExtStep::Mul(6786, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11910PolyExtStep::Add(6857, 6862), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11911PolyExtStep::Mul(6788, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11912PolyExtStep::Add(6857, 6864), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11913PolyExtStep::Mul(6790, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11914PolyExtStep::Add(6857, 6866), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11915PolyExtStep::Mul(6792, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11916PolyExtStep::Add(6857, 6868), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11917PolyExtStep::Mul(6794, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11918PolyExtStep::Add(6857, 6870), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11919PolyExtStep::Mul(6796, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11920PolyExtStep::Add(6857, 6872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11921PolyExtStep::Mul(6798, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11922PolyExtStep::Add(6857, 6874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11923PolyExtStep::Mul(6800, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11924PolyExtStep::Add(6857, 6876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11925PolyExtStep::Mul(6802, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11926PolyExtStep::Add(6857, 6878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11927PolyExtStep::Mul(6804, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11928PolyExtStep::Add(6857, 6880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11929PolyExtStep::Mul(6806, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11930PolyExtStep::Add(6857, 6882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11931PolyExtStep::Mul(6808, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11932PolyExtStep::Add(6857, 6884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11933PolyExtStep::Mul(6810, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11934PolyExtStep::Add(6857, 6886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11935PolyExtStep::Mul(6812, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11936PolyExtStep::Add(6857, 6888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11937PolyExtStep::Mul(6814, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11938PolyExtStep::Add(6857, 6890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11939PolyExtStep::Mul(6816, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11940PolyExtStep::Add(6857, 6892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11941PolyExtStep::Mul(6818, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11942PolyExtStep::Add(6857, 6894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11943PolyExtStep::Mul(6820, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11944PolyExtStep::Add(6857, 6896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11945PolyExtStep::Mul(6822, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11946PolyExtStep::Add(6857, 6898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11947PolyExtStep::Mul(6824, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11948PolyExtStep::Add(6857, 6900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11949PolyExtStep::Mul(6826, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11950PolyExtStep::Add(6857, 6902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11951PolyExtStep::Mul(6828, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11952PolyExtStep::Add(6857, 6904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11953PolyExtStep::Add(6859, 284), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11954PolyExtStep::Mul(6906, 6906), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11955PolyExtStep::Mul(6907, 6906), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11956PolyExtStep::Sub(6908, 737), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11957PolyExtStep::AndEqz(5019, 6909), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11958PolyExtStep::Mul(5317, 6906), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11959PolyExtStep::Sub(6910, 736), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11960PolyExtStep::AndEqz(5020, 6911), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11961PolyExtStep::Add(736, 6861), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11962PolyExtStep::Add(6912, 6863), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11963PolyExtStep::Add(6913, 6865), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11964PolyExtStep::Add(6914, 6867), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11965PolyExtStep::Add(6915, 6869), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11966PolyExtStep::Add(6916, 6871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11967PolyExtStep::Add(6917, 6873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11968PolyExtStep::Add(6918, 6875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11969PolyExtStep::Add(6919, 6877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11970PolyExtStep::Add(6920, 6879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11971PolyExtStep::Add(6921, 6881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11972PolyExtStep::Add(6922, 6883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11973PolyExtStep::Add(6923, 6885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11974PolyExtStep::Add(6924, 6887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11975PolyExtStep::Add(6925, 6889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11976PolyExtStep::Add(6926, 6891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11977PolyExtStep::Add(6927, 6893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11978PolyExtStep::Add(6928, 6895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11979PolyExtStep::Add(6929, 6897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11980PolyExtStep::Add(6930, 6899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11981PolyExtStep::Add(6931, 6901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11982PolyExtStep::Add(6932, 6903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11983PolyExtStep::Add(6933, 6905), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11984PolyExtStep::Mul(736, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11985PolyExtStep::Add(6934, 6935), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11986PolyExtStep::Mul(6861, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11987PolyExtStep::Add(6934, 6937), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11988PolyExtStep::Mul(6863, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11989PolyExtStep::Add(6934, 6939), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11990PolyExtStep::Mul(6865, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11991PolyExtStep::Add(6934, 6941), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11992PolyExtStep::Mul(6867, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11993PolyExtStep::Add(6934, 6943), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11994PolyExtStep::Mul(6869, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11995PolyExtStep::Add(6934, 6945), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11996PolyExtStep::Mul(6871, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11997PolyExtStep::Add(6934, 6947), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11998PolyExtStep::Mul(6873, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11999PolyExtStep::Add(6934, 6949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12000PolyExtStep::Mul(6875, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12001PolyExtStep::Add(6934, 6951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12002PolyExtStep::Mul(6877, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12003PolyExtStep::Add(6934, 6953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12004PolyExtStep::Mul(6879, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12005PolyExtStep::Add(6934, 6955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12006PolyExtStep::Mul(6881, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12007PolyExtStep::Add(6934, 6957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12008PolyExtStep::Mul(6883, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12009PolyExtStep::Add(6934, 6959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12010PolyExtStep::Mul(6885, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12011PolyExtStep::Add(6934, 6961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12012PolyExtStep::Mul(6887, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12013PolyExtStep::Add(6934, 6963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12014PolyExtStep::Mul(6889, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12015PolyExtStep::Add(6934, 6965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12016PolyExtStep::Mul(6891, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12017PolyExtStep::Add(6934, 6967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12018PolyExtStep::Mul(6893, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12019PolyExtStep::Add(6934, 6969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12020PolyExtStep::Mul(6895, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12021PolyExtStep::Add(6934, 6971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12022PolyExtStep::Mul(6897, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12023PolyExtStep::Add(6934, 6973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12024PolyExtStep::Mul(6899, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12025PolyExtStep::Add(6934, 6975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12026PolyExtStep::Mul(6901, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12027PolyExtStep::Add(6934, 6977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12028PolyExtStep::Mul(6903, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12029PolyExtStep::Add(6934, 6979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12030PolyExtStep::Mul(6905, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12031PolyExtStep::Add(6934, 6981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12032PolyExtStep::Add(6936, 285), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12033PolyExtStep::Mul(6983, 6983), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12034PolyExtStep::Mul(6984, 6983), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12035PolyExtStep::Sub(6985, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12036PolyExtStep::AndEqz(5021, 6986), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12037PolyExtStep::Mul(5324, 6983), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12038PolyExtStep::Sub(6987, 738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12039PolyExtStep::AndEqz(5022, 6988), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12040PolyExtStep::Add(738, 6938), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12041PolyExtStep::Add(6989, 6940), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12042PolyExtStep::Add(6990, 6942), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12043PolyExtStep::Add(6991, 6944), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12044PolyExtStep::Add(6992, 6946), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12045PolyExtStep::Add(6993, 6948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12046PolyExtStep::Add(6994, 6950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12047PolyExtStep::Add(6995, 6952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12048PolyExtStep::Add(6996, 6954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12049PolyExtStep::Add(6997, 6956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12050PolyExtStep::Add(6998, 6958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12051PolyExtStep::Add(6999, 6960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12052PolyExtStep::Add(7000, 6962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12053PolyExtStep::Add(7001, 6964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12054PolyExtStep::Add(7002, 6966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12055PolyExtStep::Add(7003, 6968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12056PolyExtStep::Add(7004, 6970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12057PolyExtStep::Add(7005, 6972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12058PolyExtStep::Add(7006, 6974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12059PolyExtStep::Add(7007, 6976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12060PolyExtStep::Add(7008, 6978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12061PolyExtStep::Add(7009, 6980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12062PolyExtStep::Add(7010, 6982), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12063PolyExtStep::Mul(738, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12064PolyExtStep::Add(7011, 7012), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12065PolyExtStep::Mul(6938, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12066PolyExtStep::Add(7011, 7014), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12067PolyExtStep::Mul(6940, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12068PolyExtStep::Add(7011, 7016), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12069PolyExtStep::Mul(6942, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12070PolyExtStep::Add(7011, 7018), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12071PolyExtStep::Mul(6944, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12072PolyExtStep::Add(7011, 7020), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12073PolyExtStep::Mul(6946, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12074PolyExtStep::Add(7011, 7022), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12075PolyExtStep::Mul(6948, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12076PolyExtStep::Add(7011, 7024), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12077PolyExtStep::Mul(6950, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12078PolyExtStep::Add(7011, 7026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12079PolyExtStep::Mul(6952, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12080PolyExtStep::Add(7011, 7028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12081PolyExtStep::Mul(6954, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12082PolyExtStep::Add(7011, 7030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12083PolyExtStep::Mul(6956, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12084PolyExtStep::Add(7011, 7032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12085PolyExtStep::Mul(6958, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12086PolyExtStep::Add(7011, 7034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12087PolyExtStep::Mul(6960, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12088PolyExtStep::Add(7011, 7036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12089PolyExtStep::Mul(6962, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12090PolyExtStep::Add(7011, 7038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12091PolyExtStep::Mul(6964, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12092PolyExtStep::Add(7011, 7040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12093PolyExtStep::Mul(6966, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12094PolyExtStep::Add(7011, 7042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12095PolyExtStep::Mul(6968, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12096PolyExtStep::Add(7011, 7044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12097PolyExtStep::Mul(6970, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12098PolyExtStep::Add(7011, 7046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12099PolyExtStep::Mul(6972, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12100PolyExtStep::Add(7011, 7048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12101PolyExtStep::Mul(6974, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12102PolyExtStep::Add(7011, 7050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12103PolyExtStep::Mul(6976, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12104PolyExtStep::Add(7011, 7052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12105PolyExtStep::Mul(6978, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12106PolyExtStep::Add(7011, 7054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12107PolyExtStep::Mul(6980, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12108PolyExtStep::Add(7011, 7056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12109PolyExtStep::Mul(6982, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12110PolyExtStep::Add(7011, 7058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12111PolyExtStep::Add(7013, 286), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12112PolyExtStep::Mul(7060, 7060), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12113PolyExtStep::Mul(7061, 7060), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12114PolyExtStep::Sub(7062, 748), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12115PolyExtStep::AndEqz(5023, 7063), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12116PolyExtStep::Mul(5331, 7060), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12117PolyExtStep::Sub(7064, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12118PolyExtStep::AndEqz(5024, 7065), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12119PolyExtStep::Add(747, 7015), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12120PolyExtStep::Add(7066, 7017), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12121PolyExtStep::Add(7067, 7019), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12122PolyExtStep::Add(7068, 7021), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12123PolyExtStep::Add(7069, 7023), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12124PolyExtStep::Add(7070, 7025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12125PolyExtStep::Add(7071, 7027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12126PolyExtStep::Add(7072, 7029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12127PolyExtStep::Add(7073, 7031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12128PolyExtStep::Add(7074, 7033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12129PolyExtStep::Add(7075, 7035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12130PolyExtStep::Add(7076, 7037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12131PolyExtStep::Add(7077, 7039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12132PolyExtStep::Add(7078, 7041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12133PolyExtStep::Add(7079, 7043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12134PolyExtStep::Add(7080, 7045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12135PolyExtStep::Add(7081, 7047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12136PolyExtStep::Add(7082, 7049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12137PolyExtStep::Add(7083, 7051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12138PolyExtStep::Add(7084, 7053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12139PolyExtStep::Add(7085, 7055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12140PolyExtStep::Add(7086, 7057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12141PolyExtStep::Add(7087, 7059), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12142PolyExtStep::Mul(747, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12143PolyExtStep::Add(7088, 7089), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12144PolyExtStep::Mul(7015, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12145PolyExtStep::Add(7088, 7091), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12146PolyExtStep::Mul(7017, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12147PolyExtStep::Add(7088, 7093), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12148PolyExtStep::Mul(7019, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12149PolyExtStep::Add(7088, 7095), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12150PolyExtStep::Mul(7021, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12151PolyExtStep::Add(7088, 7097), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12152PolyExtStep::Mul(7023, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12153PolyExtStep::Add(7088, 7099), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12154PolyExtStep::Mul(7025, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12155PolyExtStep::Add(7088, 7101), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12156PolyExtStep::Mul(7027, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12157PolyExtStep::Add(7088, 7103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12158PolyExtStep::Mul(7029, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12159PolyExtStep::Add(7088, 7105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12160PolyExtStep::Mul(7031, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12161PolyExtStep::Add(7088, 7107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12162PolyExtStep::Mul(7033, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12163PolyExtStep::Add(7088, 7109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12164PolyExtStep::Mul(7035, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12165PolyExtStep::Add(7088, 7111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12166PolyExtStep::Mul(7037, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12167PolyExtStep::Add(7088, 7113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12168PolyExtStep::Mul(7039, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12169PolyExtStep::Add(7088, 7115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12170PolyExtStep::Mul(7041, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12171PolyExtStep::Add(7088, 7117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12172PolyExtStep::Mul(7043, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12173PolyExtStep::Add(7088, 7119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12174PolyExtStep::Mul(7045, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12175PolyExtStep::Add(7088, 7121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12176PolyExtStep::Mul(7047, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12177PolyExtStep::Add(7088, 7123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12178PolyExtStep::Mul(7049, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12179PolyExtStep::Add(7088, 7125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12180PolyExtStep::Mul(7051, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12181PolyExtStep::Add(7088, 7127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12182PolyExtStep::Mul(7053, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12183PolyExtStep::Add(7088, 7129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12184PolyExtStep::Mul(7055, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12185PolyExtStep::Add(7088, 7131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12186PolyExtStep::Mul(7057, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12187PolyExtStep::Add(7088, 7133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12188PolyExtStep::Mul(7059, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12189PolyExtStep::Add(7088, 7135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12190PolyExtStep::AndEqz(5025, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12191PolyExtStep::AndEqz(5026, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12192PolyExtStep::AndEqz(5027, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12193PolyExtStep::AndEqz(5028, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12194PolyExtStep::AndEqz(5029, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12195PolyExtStep::AndEqz(5030, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12196PolyExtStep::AndEqz(5031, 4381), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12197PolyExtStep::Sub(5, 1122), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12198PolyExtStep::AndEqz(5032, 7137), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12199PolyExtStep::AndEqz(5033, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12200PolyExtStep::AndEqz(5034, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12201PolyExtStep::AndEqz(5035, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12202PolyExtStep::Sub(7090, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12203PolyExtStep::AndEqz(5036, 7138), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12204PolyExtStep::Sub(7092, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12205PolyExtStep::AndEqz(5037, 7139), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12206PolyExtStep::Sub(7094, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12207PolyExtStep::AndEqz(5038, 7140), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12208PolyExtStep::Sub(7096, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12209PolyExtStep::AndEqz(5039, 7141), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12210PolyExtStep::Sub(7098, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12211PolyExtStep::AndEqz(5040, 7142), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12212PolyExtStep::Sub(7100, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12213PolyExtStep::AndEqz(5041, 7143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12214PolyExtStep::Sub(7102, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12215PolyExtStep::AndEqz(5042, 7144), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12216PolyExtStep::Sub(7104, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12217PolyExtStep::AndEqz(5043, 7145), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12218PolyExtStep::Sub(7106, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12219PolyExtStep::AndEqz(5044, 7146), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12220PolyExtStep::Sub(7108, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12221PolyExtStep::AndEqz(5045, 7147), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12222PolyExtStep::Sub(7110, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12223PolyExtStep::AndEqz(5046, 7148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12224PolyExtStep::Sub(7112, 1378), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12225PolyExtStep::AndEqz(5047, 7149), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12226PolyExtStep::Sub(7114, 1379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12227PolyExtStep::AndEqz(5048, 7150), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12228PolyExtStep::Sub(7116, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12229PolyExtStep::AndEqz(5049, 7151), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12230PolyExtStep::Sub(7118, 1395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12231PolyExtStep::AndEqz(5050, 7152), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12232PolyExtStep::Sub(7120, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12233PolyExtStep::AndEqz(5051, 7153), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12234PolyExtStep::Sub(7122, 1396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12235PolyExtStep::AndEqz(5052, 7154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12236PolyExtStep::Sub(7124, 1773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12237PolyExtStep::AndEqz(5053, 7155), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12238PolyExtStep::Sub(7126, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12239PolyExtStep::AndEqz(5054, 7156), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12240PolyExtStep::Sub(7128, 1397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12241PolyExtStep::AndEqz(5055, 7157), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12242PolyExtStep::Sub(7130, 1398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12243PolyExtStep::AndEqz(5056, 7158), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12244PolyExtStep::Sub(7132, 1399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12245PolyExtStep::AndEqz(5057, 7159), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12246PolyExtStep::Sub(7134, 1400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12247PolyExtStep::AndEqz(5058, 7160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12248PolyExtStep::Sub(7136, 1406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12249PolyExtStep::AndEqz(5059, 7161), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12250PolyExtStep::AndEqz(5060, 5516), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12251PolyExtStep::AndCond(4983, 377, 5061), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12252PolyExtStep::AndCond(5062, 380, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12253PolyExtStep::AndCond(5063, 383, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12254PolyExtStep::AndCond(5064, 386, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12255PolyExtStep::AndCond(5065, 389, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12256PolyExtStep::AndCond(5066, 392, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12257PolyExtStep::AndCond(5067, 395, 4047), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12258PolyExtStep::AndCond(4873, 449, 5068), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
12259PolyExtStep::Add(373, 24), // loc(callsite( builtin Add at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12260PolyExtStep::Sub(368, 7162), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12261PolyExtStep::Sub(1058, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12262PolyExtStep::AndEqz(0, 7164), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12263PolyExtStep::AndEqz(5070, 2663), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12264PolyExtStep::AndEqz(5071, 7163), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12265PolyExtStep::Sub(797, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12266PolyExtStep::AndEqz(0, 7165), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12267PolyExtStep::AndEqz(5073, 3732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12268PolyExtStep::Sub(815, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12269PolyExtStep::AndEqz(5074, 7166), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12270PolyExtStep::AndEqz(5075, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12271PolyExtStep::Sub(800, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12272PolyExtStep::AndEqz(5076, 7167), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12273PolyExtStep::AndEqz(5077, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12274PolyExtStep::Sub(809, 821), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12275PolyExtStep::AndEqz(5078, 7168), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12276PolyExtStep::Sub(815, 803), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12277PolyExtStep::AndEqz(5079, 4667), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12278PolyExtStep::Sub(1028, 7169), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12279PolyExtStep::AndEqz(5080, 7170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12280PolyExtStep::Mul(821, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12281PolyExtStep::Mul(818, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12282PolyExtStep::Add(7171, 7172), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12283PolyExtStep::Sub(824, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12284PolyExtStep::AndEqz(5081, 7174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12285PolyExtStep::AndEqz(5082, 2174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12286PolyExtStep::Sub(873, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12287PolyExtStep::AndEqz(5083, 7175), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12288PolyExtStep::AndEqz(5084, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12289PolyExtStep::Sub(827, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12290PolyExtStep::AndEqz(5085, 7176), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12291PolyExtStep::Sub(864, 876), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12292PolyExtStep::AndEqz(5086, 7177), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12293PolyExtStep::Sub(867, 879), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12294PolyExtStep::AndEqz(5087, 7178), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12295PolyExtStep::Sub(873, 861), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12296PolyExtStep::Sub(1031, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12297PolyExtStep::AndEqz(5088, 7180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12298PolyExtStep::Sub(1034, 7179), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12299PolyExtStep::AndEqz(5089, 7181), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12300PolyExtStep::Mul(879, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12301PolyExtStep::Mul(876, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12302PolyExtStep::Add(7182, 7183), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12303PolyExtStep::Sub(882, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12304PolyExtStep::AndEqz(5090, 7185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12305PolyExtStep::Sub(897, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12306PolyExtStep::AndEqz(5091, 7186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12307PolyExtStep::Sub(900, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12308PolyExtStep::AndEqz(5092, 7187), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12309PolyExtStep::AndEqz(5093, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12310PolyExtStep::Sub(885, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12311PolyExtStep::AndEqz(5094, 7188), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12312PolyExtStep::Sub(891, 903), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12313PolyExtStep::AndEqz(5095, 7189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12314PolyExtStep::Sub(894, 906), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12315PolyExtStep::AndEqz(5096, 7190), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12316PolyExtStep::Sub(900, 888), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12317PolyExtStep::AndEqz(5097, 4678), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12318PolyExtStep::Sub(1040, 7191), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12319PolyExtStep::AndEqz(5098, 7192), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12320PolyExtStep::Mul(906, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12321PolyExtStep::Mul(903, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12322PolyExtStep::Add(7193, 7194), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12323PolyExtStep::Sub(940, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12324PolyExtStep::AndEqz(5099, 7196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12325PolyExtStep::AndEqz(5100, 4632), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12326PolyExtStep::Sub(958, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12327PolyExtStep::AndEqz(5101, 7197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12328PolyExtStep::AndEqz(5102, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12329PolyExtStep::Sub(943, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12330PolyExtStep::AndEqz(5103, 7198), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12331PolyExtStep::Sub(949, 961), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12332PolyExtStep::AndEqz(5104, 7199), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12333PolyExtStep::Sub(952, 964), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12334PolyExtStep::AndEqz(5105, 7200), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12335PolyExtStep::Sub(958, 946), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12336PolyExtStep::Sub(1043, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12337PolyExtStep::AndEqz(5106, 7202), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12338PolyExtStep::Sub(1046, 7201), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12339PolyExtStep::AndEqz(5107, 7203), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12340PolyExtStep::Sub(967, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12341PolyExtStep::AndEqz(5108, 7204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12342PolyExtStep::AndEqz(5109, 4656), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12343PolyExtStep::Sub(985, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12344PolyExtStep::AndEqz(5110, 7205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12345PolyExtStep::AndEqz(5111, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12346PolyExtStep::Sub(970, 311), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12347PolyExtStep::AndEqz(5112, 7206), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12348PolyExtStep::Sub(976, 1019), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12349PolyExtStep::AndEqz(5113, 7207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12350PolyExtStep::Sub(979, 1022), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12351PolyExtStep::AndEqz(5114, 7208), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12352PolyExtStep::Sub(985, 973), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12353PolyExtStep::AndEqz(5115, 4689), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12354PolyExtStep::Sub(1052, 7209), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12355PolyExtStep::AndEqz(5116, 7210), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12356PolyExtStep::Mul(1022, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12357PolyExtStep::Mul(1019, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12358PolyExtStep::Add(7211, 7212), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12359PolyExtStep::Sub(7173, 775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12360PolyExtStep::AndEqz(5117, 7214), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12361PolyExtStep::Sub(7184, 1105), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12362PolyExtStep::AndEqz(5118, 7215), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12363PolyExtStep::Sub(7195, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12364PolyExtStep::AndEqz(5119, 7216), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12365PolyExtStep::Sub(961, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12366PolyExtStep::AndEqz(5120, 7217), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12367PolyExtStep::Sub(7213, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12368PolyExtStep::AndEqz(5121, 7218), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12369PolyExtStep::AndEqz(5122, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12370PolyExtStep::Sub(312, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12371PolyExtStep::AndEqz(5123, 7219), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12372PolyExtStep::AndCond(5072, 374, 5124), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12373PolyExtStep::Sub(6, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12374PolyExtStep::Sub(1, 2659), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12375PolyExtStep::Mul(2659, 7221), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12376PolyExtStep::AndEqz(0, 7222), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12377PolyExtStep::Mul(7220, 2660), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12378PolyExtStep::Sub(7223, 7221), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12379PolyExtStep::AndEqz(5126, 7224), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12380PolyExtStep::Mul(2659, 7220), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12381PolyExtStep::AndEqz(5127, 7225), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12382PolyExtStep::Mul(2659, 2660), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12383PolyExtStep::AndEqz(5128, 7226), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12384PolyExtStep::Sub(1, 2666), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12385PolyExtStep::Mul(2666, 7227), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12386PolyExtStep::AndEqz(5129, 7228), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12387PolyExtStep::Mul(3877, 2667), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12388PolyExtStep::Sub(7229, 7227), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12389PolyExtStep::AndEqz(5130, 7230), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12390PolyExtStep::Mul(2666, 3877), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12391PolyExtStep::AndEqz(5131, 7231), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12392PolyExtStep::Mul(2666, 2667), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12393PolyExtStep::AndEqz(5132, 7232), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12394PolyExtStep::Mul(2666, 13), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12395PolyExtStep::Mul(7227, 313), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12396PolyExtStep::Add(7233, 7234), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12397PolyExtStep::Mul(7235, 2659), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12398PolyExtStep::Mul(7221, 312), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12399PolyExtStep::Add(7236, 7237), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12400PolyExtStep::Add(3874, 6), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12401PolyExtStep::Sub(7239, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12402PolyExtStep::AndEqz(5133, 7165), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12403PolyExtStep::AndEqz(5134, 3732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12404PolyExtStep::AndEqz(5135, 7166), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12405PolyExtStep::AndEqz(5136, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12406PolyExtStep::Sub(800, 7240), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12407PolyExtStep::AndEqz(5137, 7241), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12408PolyExtStep::AndEqz(5138, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12409PolyExtStep::AndEqz(5139, 7168), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12410PolyExtStep::AndEqz(5140, 4667), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12411PolyExtStep::AndEqz(5141, 7170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12412PolyExtStep::Add(3874, 2), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12413PolyExtStep::Sub(7242, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12414PolyExtStep::AndEqz(5142, 7174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12415PolyExtStep::AndEqz(5143, 2174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12416PolyExtStep::AndEqz(5144, 7175), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12417PolyExtStep::AndEqz(5145, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12418PolyExtStep::Sub(827, 7243), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12419PolyExtStep::AndEqz(5146, 7244), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12420PolyExtStep::AndEqz(5147, 7177), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12421PolyExtStep::AndEqz(5148, 7178), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12422PolyExtStep::AndEqz(5149, 7180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12423PolyExtStep::AndEqz(5150, 7181), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12424PolyExtStep::Sub(3894, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12425PolyExtStep::AndEqz(5151, 7185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12426PolyExtStep::AndEqz(5152, 7186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12427PolyExtStep::Sub(900, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12428PolyExtStep::AndEqz(5153, 7246), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12429PolyExtStep::AndEqz(5154, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12430PolyExtStep::Sub(885, 7245), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12431PolyExtStep::AndEqz(5155, 7247), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12432PolyExtStep::AndEqz(5156, 4678), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12433PolyExtStep::AndEqz(5157, 7192), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12434PolyExtStep::Sub(903, 818), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12435PolyExtStep::AndEqz(5158, 7248), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12436PolyExtStep::Sub(906, 821), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12437PolyExtStep::AndEqz(5159, 7249), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12438PolyExtStep::Sub(3924, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12439PolyExtStep::AndEqz(5160, 7196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12440PolyExtStep::AndEqz(5161, 4632), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12441PolyExtStep::Sub(958, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12442PolyExtStep::AndEqz(5162, 7251), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12443PolyExtStep::AndEqz(5163, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12444PolyExtStep::Sub(943, 7250), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12445PolyExtStep::AndEqz(5164, 7252), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12446PolyExtStep::AndEqz(5165, 7202), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12447PolyExtStep::AndEqz(5166, 7203), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12448PolyExtStep::Sub(961, 876), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12449PolyExtStep::AndEqz(5167, 7253), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12450PolyExtStep::Sub(964, 879), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12451PolyExtStep::AndEqz(5168, 7254), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12452PolyExtStep::Add(3879, 1), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12453PolyExtStep::Mul(7221, 7255), // loc(callsite( builtin Mul at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:20) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12454PolyExtStep::AndEqz(5169, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12455PolyExtStep::AndEqz(5170, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12456PolyExtStep::AndEqz(5171, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12457PolyExtStep::AndEqz(5172, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12458PolyExtStep::AndEqz(5173, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12459PolyExtStep::Sub(7256, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12460PolyExtStep::AndEqz(5174, 7257), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12461PolyExtStep::Sub(7238, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12462PolyExtStep::AndEqz(5175, 7258), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12463PolyExtStep::Mul(779, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12464PolyExtStep::Mul(1128, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12465PolyExtStep::Mul(1340, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12466PolyExtStep::Mul(1341, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12467PolyExtStep::Mul(1343, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12468PolyExtStep::Mul(1350, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12469PolyExtStep::Mul(1351, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12470PolyExtStep::Add(1122, 7259), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12471PolyExtStep::Add(7266, 7260), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12472PolyExtStep::Add(7267, 7261), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12473PolyExtStep::Add(7268, 7262), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12474PolyExtStep::Add(7269, 7263), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12475PolyExtStep::Add(7270, 7264), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12476PolyExtStep::Add(7271, 7265), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12477PolyExtStep::Mul(1359, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12478PolyExtStep::Mul(1360, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12479PolyExtStep::Mul(1362, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12480PolyExtStep::Mul(1369, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12481PolyExtStep::Mul(1370, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12482PolyExtStep::Mul(1372, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12483PolyExtStep::Mul(1378, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12484PolyExtStep::Add(1353, 7273), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12485PolyExtStep::Add(7280, 7274), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12486PolyExtStep::Add(7281, 7275), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12487PolyExtStep::Add(7282, 7276), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12488PolyExtStep::Add(7283, 7277), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12489PolyExtStep::Add(7284, 7278), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12490PolyExtStep::Add(7285, 7279), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12491PolyExtStep::Mul(1392, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12492PolyExtStep::Mul(1395, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12493PolyExtStep::Mul(1394, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12494PolyExtStep::Mul(1396, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12495PolyExtStep::Mul(1773, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12496PolyExtStep::Mul(1774, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12497PolyExtStep::Mul(1397, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12498PolyExtStep::Add(1379, 7287), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12499PolyExtStep::Add(7294, 7288), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12500PolyExtStep::Add(7295, 7289), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12501PolyExtStep::Add(7296, 7290), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12502PolyExtStep::Add(7297, 7291), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12503PolyExtStep::Add(7298, 7292), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12504PolyExtStep::Add(7299, 7293), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12505PolyExtStep::Mul(1399, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12506PolyExtStep::Mul(1400, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12507PolyExtStep::Mul(1406, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12508PolyExtStep::Mul(1407, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12509PolyExtStep::Mul(1844, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12510PolyExtStep::Mul(535, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12511PolyExtStep::Mul(2207, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12512PolyExtStep::Add(1398, 7301), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12513PolyExtStep::Add(7308, 7302), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12514PolyExtStep::Add(7309, 7303), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12515PolyExtStep::Add(7310, 7304), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12516PolyExtStep::Add(7311, 7305), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12517PolyExtStep::Add(7312, 7306), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12518PolyExtStep::Add(7313, 7307), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12519PolyExtStep::Mul(1122, 4424), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12520PolyExtStep::AndEqz(5176, 7315), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12521PolyExtStep::Sub(1, 779), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12522PolyExtStep::Mul(779, 7316), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12523PolyExtStep::AndEqz(5177, 7317), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12524PolyExtStep::Mul(1128, 4756), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12525PolyExtStep::AndEqz(5178, 7318), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12526PolyExtStep::Mul(1340, 4761), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12527PolyExtStep::AndEqz(5179, 7319), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12528PolyExtStep::Sub(1, 1341), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12529PolyExtStep::Mul(1341, 7320), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12530PolyExtStep::AndEqz(5180, 7321), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12531PolyExtStep::AndEqz(5181, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12532PolyExtStep::AndEqz(5182, 2720), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12533PolyExtStep::AndEqz(5183, 2726), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12534PolyExtStep::AndEqz(5184, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12535PolyExtStep::AndEqz(5185, 2736), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12536PolyExtStep::AndEqz(5186, 2742), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12537PolyExtStep::AndEqz(5187, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12538PolyExtStep::AndEqz(5188, 2748), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12539PolyExtStep::AndEqz(5189, 2754), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12540PolyExtStep::AndEqz(5190, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12541PolyExtStep::AndEqz(5191, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12542PolyExtStep::AndEqz(5192, 2760), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12543PolyExtStep::AndEqz(5193, 2766), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12544PolyExtStep::AndEqz(5194, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12545PolyExtStep::AndEqz(5195, 2778), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12546PolyExtStep::Sub(1, 1396), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12547PolyExtStep::Mul(1396, 7322), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12548PolyExtStep::AndEqz(5196, 7323), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12549PolyExtStep::AndEqz(5197, 2694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12550PolyExtStep::Sub(1, 1774), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12551PolyExtStep::Mul(1774, 7324), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12552PolyExtStep::AndEqz(5198, 7325), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12553PolyExtStep::Sub(1, 1397), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12554PolyExtStep::Mul(1397, 7326), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12555PolyExtStep::AndEqz(5199, 7327), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12556PolyExtStep::AndEqz(5200, 2702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12557PolyExtStep::Sub(1, 1399), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12558PolyExtStep::Mul(1399, 7328), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12559PolyExtStep::AndEqz(5201, 7329), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12560PolyExtStep::Sub(1, 1400), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12561PolyExtStep::Mul(1400, 7330), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12562PolyExtStep::AndEqz(5202, 7331), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12563PolyExtStep::Sub(1, 1406), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12564PolyExtStep::Mul(1406, 7332), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12565PolyExtStep::AndEqz(5203, 7333), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12566PolyExtStep::Sub(1, 1407), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12567PolyExtStep::Mul(1407, 7334), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12568PolyExtStep::AndEqz(5204, 7335), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12569PolyExtStep::Sub(1, 1844), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12570PolyExtStep::Mul(1844, 7336), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12571PolyExtStep::AndEqz(5205, 7337), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12572PolyExtStep::Sub(1, 535), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12573PolyExtStep::Mul(535, 7338), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12574PolyExtStep::AndEqz(5206, 7339), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12575PolyExtStep::Sub(1, 2207), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12576PolyExtStep::Mul(2207, 7340), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12577PolyExtStep::AndEqz(5207, 7341), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12578PolyExtStep::Mul(7300, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12579PolyExtStep::Add(7342, 7314), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12580PolyExtStep::Sub(818, 7343), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12581PolyExtStep::AndEqz(5208, 7344), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12582PolyExtStep::Mul(7272, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12583PolyExtStep::Add(7345, 7286), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12584PolyExtStep::Sub(821, 7346), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12585PolyExtStep::AndEqz(5209, 7347), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12586PolyExtStep::Mul(587, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12587PolyExtStep::Mul(590, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12588PolyExtStep::Mul(597, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12589PolyExtStep::Mul(611, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12590PolyExtStep::Mul(618, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12591PolyExtStep::Add(536, 7348), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12592PolyExtStep::Add(7353, 7349), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12593PolyExtStep::Add(7354, 7350), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12594PolyExtStep::Add(7355, 1692), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12595PolyExtStep::Add(7356, 7351), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12596PolyExtStep::Add(7357, 7352), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12597PolyExtStep::Add(7358, 1657), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12598PolyExtStep::Mul(645, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12599PolyExtStep::Mul(648, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12600PolyExtStep::Mul(655, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12601PolyExtStep::Mul(662, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12602PolyExtStep::Add(628, 704), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12603PolyExtStep::Add(7364, 1663), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12604PolyExtStep::Add(7365, 7360), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12605PolyExtStep::Add(7366, 7361), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12606PolyExtStep::Add(7367, 7362), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12607PolyExtStep::Add(7368, 7363), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12608PolyExtStep::Add(7369, 699), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12609PolyExtStep::Mul(541, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12610PolyExtStep::Mul(548, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12611PolyExtStep::Mul(549, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12612PolyExtStep::Mul(552, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12613PolyExtStep::Mul(553, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12614PolyExtStep::Mul(560, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12615PolyExtStep::Mul(561, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12616PolyExtStep::Add(672, 7371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12617PolyExtStep::Add(7378, 7372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12618PolyExtStep::Add(7379, 7373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12619PolyExtStep::Add(7380, 7374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12620PolyExtStep::Add(7381, 7375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12621PolyExtStep::Add(7382, 7376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12622PolyExtStep::Add(7383, 7377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12623PolyExtStep::Mul(567, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12624PolyExtStep::Mul(569, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12625PolyExtStep::Mul(571, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12626PolyExtStep::Mul(572, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12627PolyExtStep::Mul(573, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12628PolyExtStep::Mul(574, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12629PolyExtStep::Add(568, 7385), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12630PolyExtStep::Add(7391, 7386), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12631PolyExtStep::Add(7392, 2139), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12632PolyExtStep::Add(7393, 7387), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12633PolyExtStep::Add(7394, 7388), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12634PolyExtStep::Add(7395, 7389), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12635PolyExtStep::Add(7396, 7390), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12636PolyExtStep::Sub(1, 536), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12637PolyExtStep::Mul(536, 7398), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12638PolyExtStep::AndEqz(5210, 7399), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12639PolyExtStep::AndEqz(5211, 589), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12640PolyExtStep::AndEqz(5212, 592), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12641PolyExtStep::AndEqz(5213, 599), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12642PolyExtStep::AndEqz(5214, 606), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12643PolyExtStep::AndEqz(5215, 613), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12644PolyExtStep::AndEqz(5216, 620), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12645PolyExtStep::AndEqz(5217, 627), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12646PolyExtStep::AndEqz(5218, 630), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12647PolyExtStep::AndEqz(5219, 637), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12648PolyExtStep::AndEqz(5220, 644), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12649PolyExtStep::AndEqz(5221, 647), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12650PolyExtStep::AndEqz(5222, 650), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12651PolyExtStep::AndEqz(5223, 657), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12652PolyExtStep::AndEqz(5224, 664), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12653PolyExtStep::AndEqz(5225, 671), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12654PolyExtStep::AndEqz(5226, 1645), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12655PolyExtStep::AndEqz(5227, 543), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12656PolyExtStep::Sub(1, 548), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12657PolyExtStep::Mul(548, 7400), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12658PolyExtStep::AndEqz(5228, 7401), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12659PolyExtStep::AndEqz(5229, 1601), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12660PolyExtStep::AndEqz(5230, 555), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12661PolyExtStep::AndEqz(5231, 2848), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12662PolyExtStep::AndEqz(5232, 1609), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12663PolyExtStep::AndEqz(5233, 2036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12664PolyExtStep::AndEqz(5234, 2038), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12665PolyExtStep::AndEqz(5235, 2044), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12666PolyExtStep::AndEqz(5236, 2050), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12667PolyExtStep::AndEqz(5237, 2056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12668PolyExtStep::AndEqz(5238, 2062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12669PolyExtStep::AndEqz(5239, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12670PolyExtStep::AndEqz(5240, 2070), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12671PolyExtStep::AndEqz(5241, 2076), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12672PolyExtStep::Mul(7384, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12673PolyExtStep::Add(7402, 7397), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12674PolyExtStep::Sub(876, 7403), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12675PolyExtStep::AndEqz(5242, 7404), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12676PolyExtStep::Mul(7359, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12677PolyExtStep::Add(7405, 7370), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12678PolyExtStep::Sub(879, 7406), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12679PolyExtStep::AndEqz(5243, 7407), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12680PolyExtStep::AndEqz(5244, 575), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12681PolyExtStep::AndEqz(5245, 583), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12682PolyExtStep::AndEqz(5246, 584), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12683PolyExtStep::AndEqz(5247, 732), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12684PolyExtStep::AndEqz(5248, 731), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12685PolyExtStep::AndEqz(5249, 733), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12686PolyExtStep::AndEqz(5250, 734), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12687PolyExtStep::AndEqz(5251, 735), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12688PolyExtStep::AndEqz(5252, 736), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12689PolyExtStep::AndEqz(5253, 737), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12690PolyExtStep::AndEqz(5254, 738), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12691PolyExtStep::AndEqz(5255, 739), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12692PolyExtStep::AndEqz(5256, 747), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12693PolyExtStep::AndEqz(5257, 748), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12694PolyExtStep::AndEqz(5258, 729), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12695PolyExtStep::AndEqz(5259, 755), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12696PolyExtStep::AndEqz(5260, 754), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12697PolyExtStep::AndEqz(5261, 756), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12698PolyExtStep::AndEqz(5262, 757), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12699PolyExtStep::AndEqz(5263, 758), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12700PolyExtStep::AndEqz(5264, 759), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12701PolyExtStep::AndEqz(5265, 760), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12702PolyExtStep::AndEqz(5266, 761), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12703PolyExtStep::AndEqz(5267, 762), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12704PolyExtStep::AndEqz(5268, 770), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12705PolyExtStep::AndEqz(5269, 771), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12706PolyExtStep::AndEqz(5270, 752), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12707PolyExtStep::AndEqz(5271, 782), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12708PolyExtStep::AndEqz(5272, 785), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12709PolyExtStep::AndEqz(5273, 788), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12710PolyExtStep::AndEqz(5274, 791), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12711PolyExtStep::AndEqz(5275, 794), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12712PolyExtStep::AndEqz(5276, 967), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12713PolyExtStep::AndEqz(5277, 982), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12714PolyExtStep::AndEqz(5278, 1049), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12715PolyExtStep::AndCond(5125, 377, 5279), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12716PolyExtStep::Get(360), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12717PolyExtStep::Get(366), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12718PolyExtStep::Get(372), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12719PolyExtStep::Get(378), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12720PolyExtStep::Get(384), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12721PolyExtStep::Get(390), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12722PolyExtStep::Get(396), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12723PolyExtStep::Get(402), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12724PolyExtStep::Get(408), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12725PolyExtStep::Get(414), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12726PolyExtStep::Get(420), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12727PolyExtStep::Get(426), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12728PolyExtStep::Get(432), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12729PolyExtStep::Get(438), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12730PolyExtStep::Get(444), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12731PolyExtStep::Get(450), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12732PolyExtStep::Get(456), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12733PolyExtStep::Get(462), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12734PolyExtStep::Get(468), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12735PolyExtStep::Get(474), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12736PolyExtStep::Get(480), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12737PolyExtStep::Get(504), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12738PolyExtStep::Get(510), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12739PolyExtStep::Get(516), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12740PolyExtStep::Get(522), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12741PolyExtStep::Get(528), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12742PolyExtStep::Get(534), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12743PolyExtStep::Get(540), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12744PolyExtStep::Get(546), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12745PolyExtStep::Get(169), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12746PolyExtStep::Get(175), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12747PolyExtStep::Get(181), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12748PolyExtStep::Get(187), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12749PolyExtStep::Get(193), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12750PolyExtStep::Get(199), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12751PolyExtStep::Get(205), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12752PolyExtStep::Get(211), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12753PolyExtStep::Get(217), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12754PolyExtStep::Get(223), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12755PolyExtStep::Get(229), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12756PolyExtStep::Get(235), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12757PolyExtStep::Get(241), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12758PolyExtStep::Get(247), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12759PolyExtStep::Get(253), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12760PolyExtStep::Get(259), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12761PolyExtStep::Get(265), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12762PolyExtStep::Get(271), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12763PolyExtStep::Get(277), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12764PolyExtStep::Get(283), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12765PolyExtStep::Get(289), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12766PolyExtStep::Get(295), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12767PolyExtStep::Get(301), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12768PolyExtStep::Get(307), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12769PolyExtStep::Get(313), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12770PolyExtStep::Get(319), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12771PolyExtStep::Get(325), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12772PolyExtStep::Get(331), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12773PolyExtStep::Get(337), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12774PolyExtStep::Get(343), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12775PolyExtStep::Get(349), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12776PolyExtStep::Get(355), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12777PolyExtStep::Get(361), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12778PolyExtStep::Get(367), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12779PolyExtStep::Get(373), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12780PolyExtStep::Get(379), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12781PolyExtStep::Get(385), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12782PolyExtStep::Get(391), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12783PolyExtStep::Get(397), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12784PolyExtStep::Get(403), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12785PolyExtStep::Get(409), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12786PolyExtStep::Get(415), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12787PolyExtStep::Get(421), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12788PolyExtStep::Get(427), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12789PolyExtStep::Get(433), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12790PolyExtStep::Get(439), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12791PolyExtStep::Get(445), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12792PolyExtStep::Get(451), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12793PolyExtStep::Get(457), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12794PolyExtStep::Get(463), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12795PolyExtStep::Get(469), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12796PolyExtStep::Get(475), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12797PolyExtStep::Get(481), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12798PolyExtStep::Get(487), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12799PolyExtStep::Get(493), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12800PolyExtStep::Get(499), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12801PolyExtStep::Get(505), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12802PolyExtStep::Get(511), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12803PolyExtStep::Get(517), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12804PolyExtStep::Get(523), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12805PolyExtStep::Get(529), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12806PolyExtStep::Get(535), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12807PolyExtStep::Get(541), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12808PolyExtStep::Get(547), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12809PolyExtStep::Get(170), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12810PolyExtStep::Get(176), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12811PolyExtStep::Get(182), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12812PolyExtStep::Get(188), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12813PolyExtStep::Get(194), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12814PolyExtStep::Get(200), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12815PolyExtStep::Get(206), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12816PolyExtStep::Get(212), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12817PolyExtStep::Get(218), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12818PolyExtStep::Get(224), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12819PolyExtStep::Get(230), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12820PolyExtStep::Get(236), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12821PolyExtStep::Get(242), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12822PolyExtStep::Get(248), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12823PolyExtStep::Get(254), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12824PolyExtStep::Get(260), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12825PolyExtStep::Get(266), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12826PolyExtStep::Get(272), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12827PolyExtStep::Get(278), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12828PolyExtStep::Get(284), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12829PolyExtStep::Get(290), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12830PolyExtStep::Get(296), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12831PolyExtStep::Get(302), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12832PolyExtStep::Get(308), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12833PolyExtStep::Get(314), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12834PolyExtStep::Get(320), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12835PolyExtStep::Get(326), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12836PolyExtStep::Get(332), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12837PolyExtStep::Get(338), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12838PolyExtStep::Get(344), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12839PolyExtStep::Get(350), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12840PolyExtStep::Get(356), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12841PolyExtStep::Get(362), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12842PolyExtStep::Get(368), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12843PolyExtStep::Get(374), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12844PolyExtStep::Get(380), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12845PolyExtStep::Get(386), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12846PolyExtStep::Get(392), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12847PolyExtStep::Get(398), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12848PolyExtStep::Get(404), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12849PolyExtStep::Get(410), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12850PolyExtStep::Get(416), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12851PolyExtStep::Get(422), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12852PolyExtStep::Get(428), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12853PolyExtStep::Get(434), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12854PolyExtStep::Get(440), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12855PolyExtStep::Get(446), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12856PolyExtStep::Get(452), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12857PolyExtStep::Get(458), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12858PolyExtStep::Get(464), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12859PolyExtStep::Get(470), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12860PolyExtStep::Get(476), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12861PolyExtStep::Get(482), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12862PolyExtStep::Get(488), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12863PolyExtStep::Get(494), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12864PolyExtStep::Get(500), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12865PolyExtStep::Get(506), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12866PolyExtStep::Get(512), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12867PolyExtStep::Get(518), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12868PolyExtStep::Get(524), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12869PolyExtStep::Get(530), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12870PolyExtStep::Get(536), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12871PolyExtStep::Get(542), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12872PolyExtStep::Get(548), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12873PolyExtStep::Get(171), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12874PolyExtStep::Get(177), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12875PolyExtStep::Get(183), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12876PolyExtStep::Get(189), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12877PolyExtStep::Get(195), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12878PolyExtStep::Get(201), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12879PolyExtStep::Get(207), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12880PolyExtStep::Get(213), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12881PolyExtStep::Get(219), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12882PolyExtStep::Get(225), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12883PolyExtStep::Get(231), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12884PolyExtStep::Get(237), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12885PolyExtStep::Get(243), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12886PolyExtStep::Get(249), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12887PolyExtStep::Get(255), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12888PolyExtStep::Get(261), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12889PolyExtStep::Get(267), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12890PolyExtStep::Get(273), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12891PolyExtStep::Get(279), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12892PolyExtStep::Get(285), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12893PolyExtStep::Get(291), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12894PolyExtStep::Get(297), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12895PolyExtStep::Get(303), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12896PolyExtStep::Get(309), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12897PolyExtStep::Get(315), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12898PolyExtStep::Get(321), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12899PolyExtStep::Get(327), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12900PolyExtStep::Get(333), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12901PolyExtStep::Get(339), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12902PolyExtStep::Get(345), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12903PolyExtStep::Get(351), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12904PolyExtStep::Get(357), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12905PolyExtStep::Get(363), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12906PolyExtStep::Get(369), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12907PolyExtStep::Get(375), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12908PolyExtStep::Get(381), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12909PolyExtStep::Get(387), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12910PolyExtStep::Get(393), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12911PolyExtStep::Get(399), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12912PolyExtStep::Get(405), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12913PolyExtStep::Get(411), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12914PolyExtStep::Get(417), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12915PolyExtStep::Get(423), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12916PolyExtStep::Get(429), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12917PolyExtStep::Get(435), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12918PolyExtStep::Get(441), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12919PolyExtStep::Get(447), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12920PolyExtStep::Get(453), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12921PolyExtStep::Get(459), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12922PolyExtStep::Get(465), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12923PolyExtStep::Get(471), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12924PolyExtStep::Get(477), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12925PolyExtStep::Get(483), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12926PolyExtStep::Get(489), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12927PolyExtStep::Get(495), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12928PolyExtStep::Get(501), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12929PolyExtStep::Get(507), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12930PolyExtStep::Get(513), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12931PolyExtStep::Get(519), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12932PolyExtStep::Get(525), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12933PolyExtStep::Get(531), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12934PolyExtStep::Get(537), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12935PolyExtStep::Get(543), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12936PolyExtStep::Get(549), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12937PolyExtStep::Sub(36, 3879), // loc(callsite( builtin Sub at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12938PolyExtStep::Mul(7629, 2660), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12939PolyExtStep::Sub(7630, 7221), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12940PolyExtStep::AndEqz(5126, 7631), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12941PolyExtStep::Mul(2659, 7629), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12942PolyExtStep::AndEqz(5281, 7632), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12943PolyExtStep::AndEqz(5282, 7226), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12944PolyExtStep::Add(3878, 3879), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12945PolyExtStep::AndEqz(5283, 7165), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12946PolyExtStep::AndEqz(5284, 3732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12947PolyExtStep::AndEqz(5285, 7166), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12948PolyExtStep::AndEqz(5286, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12949PolyExtStep::Sub(800, 7633), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12950PolyExtStep::AndEqz(5287, 7634), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12951PolyExtStep::AndEqz(5288, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12952PolyExtStep::AndEqz(5289, 7168), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12953PolyExtStep::AndEqz(5290, 4667), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12954PolyExtStep::AndEqz(5291, 7170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12955PolyExtStep::AndEqz(5292, 7174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12956PolyExtStep::AndEqz(5293, 2174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12957PolyExtStep::AndEqz(5294, 7175), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12958PolyExtStep::AndEqz(5295, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12959PolyExtStep::Sub(827, 3876), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12960PolyExtStep::AndEqz(5296, 7635), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12961PolyExtStep::AndEqz(5297, 7177), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12962PolyExtStep::AndEqz(5298, 7178), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12963PolyExtStep::AndEqz(5299, 7180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12964PolyExtStep::AndEqz(5300, 7181), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12965PolyExtStep::Mul(583, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12966PolyExtStep::Mul(584, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12967PolyExtStep::Mul(731, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12968PolyExtStep::Mul(733, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12969PolyExtStep::Mul(734, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12970PolyExtStep::Mul(735, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12971PolyExtStep::Add(575, 7636), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12972PolyExtStep::Add(7642, 7637), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12973PolyExtStep::Add(7643, 2143), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12974PolyExtStep::Add(7644, 7638), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12975PolyExtStep::Add(7645, 7639), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12976PolyExtStep::Add(7646, 7640), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12977PolyExtStep::Add(7647, 7641), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12978PolyExtStep::Mul(737, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12979PolyExtStep::Mul(738, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12980PolyExtStep::Mul(739, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12981PolyExtStep::Mul(747, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12982PolyExtStep::Mul(748, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12983PolyExtStep::Mul(729, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12984PolyExtStep::Mul(755, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12985PolyExtStep::Add(736, 7649), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12986PolyExtStep::Add(7656, 7650), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12987PolyExtStep::Add(7657, 7651), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12988PolyExtStep::Add(7658, 7652), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12989PolyExtStep::Add(7659, 7653), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12990PolyExtStep::Add(7660, 7654), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12991PolyExtStep::Add(7661, 7655), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12992PolyExtStep::Mul(756, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12993PolyExtStep::Mul(757, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12994PolyExtStep::Mul(758, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12995PolyExtStep::Mul(759, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12996PolyExtStep::Mul(760, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12997PolyExtStep::Mul(761, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12998PolyExtStep::Mul(762, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12999PolyExtStep::Add(754, 7663), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13000PolyExtStep::Add(7670, 7664), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13001PolyExtStep::Add(7671, 7665), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13002PolyExtStep::Add(7672, 7666), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13003PolyExtStep::Add(7673, 7667), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13004PolyExtStep::Add(7674, 7668), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13005PolyExtStep::Add(7675, 7669), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13006PolyExtStep::Mul(771, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13007PolyExtStep::Mul(752, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13008PolyExtStep::Mul(782, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13009PolyExtStep::Mul(785, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13010PolyExtStep::Mul(788, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13011PolyExtStep::Mul(791, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13012PolyExtStep::Mul(794, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13013PolyExtStep::Add(770, 7677), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13014PolyExtStep::Add(7684, 7678), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13015PolyExtStep::Add(7685, 7679), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13016PolyExtStep::Add(7686, 7680), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13017PolyExtStep::Add(7687, 7681), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13018PolyExtStep::Add(7688, 7682), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13019PolyExtStep::Add(7689, 7683), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13020PolyExtStep::AndEqz(5301, 2082), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13021PolyExtStep::AndEqz(5302, 2084), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13022PolyExtStep::AndEqz(5303, 2086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13023PolyExtStep::AndEqz(5304, 2092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13024PolyExtStep::AndEqz(5305, 2098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13025PolyExtStep::AndEqz(5306, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13026PolyExtStep::AndEqz(5307, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13027PolyExtStep::AndEqz(5308, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13028PolyExtStep::AndEqz(5309, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13029PolyExtStep::AndEqz(5310, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13030PolyExtStep::AndEqz(5311, 2018), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13031PolyExtStep::Sub(1, 739), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13032PolyExtStep::Mul(739, 7691), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13033PolyExtStep::AndEqz(5312, 7692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13034PolyExtStep::AndEqz(5313, 2889), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13035PolyExtStep::AndEqz(5314, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13036PolyExtStep::AndEqz(5315, 3464), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13037PolyExtStep::AndEqz(5316, 3466), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13038PolyExtStep::AndEqz(5317, 3468), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13039PolyExtStep::AndEqz(5318, 3479), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13040PolyExtStep::AndEqz(5319, 3519), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13041PolyExtStep::AndEqz(5320, 3523), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13042PolyExtStep::Sub(1, 759), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13043PolyExtStep::Mul(759, 7693), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13044PolyExtStep::AndEqz(5321, 7694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13045PolyExtStep::Sub(1, 760), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13046PolyExtStep::Mul(760, 7695), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13047PolyExtStep::AndEqz(5322, 7696), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13048PolyExtStep::Sub(1, 761), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13049PolyExtStep::Mul(761, 7697), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13050PolyExtStep::AndEqz(5323, 7698), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13051PolyExtStep::Sub(1, 762), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13052PolyExtStep::Mul(762, 7699), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13053PolyExtStep::AndEqz(5324, 7700), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13054PolyExtStep::AndEqz(5325, 3585), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13055PolyExtStep::Sub(1, 771), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13056PolyExtStep::Mul(771, 7701), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13057PolyExtStep::AndEqz(5326, 7702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13058PolyExtStep::AndEqz(5327, 4828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13059PolyExtStep::AndEqz(5328, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13060PolyExtStep::AndEqz(5329, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13061PolyExtStep::AndEqz(5330, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13062PolyExtStep::AndEqz(5331, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13063PolyExtStep::AndEqz(5332, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13064PolyExtStep::Mul(7676, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13065PolyExtStep::Add(7703, 7690), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13066PolyExtStep::Sub(876, 7704), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13067PolyExtStep::AndEqz(5333, 7705), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13068PolyExtStep::Mul(7648, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13069PolyExtStep::Add(7706, 7662), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13070PolyExtStep::Sub(879, 7707), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13071PolyExtStep::AndEqz(5334, 7708), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13072PolyExtStep::Add(3962, 3971), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13073PolyExtStep::Mul(3962, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13074PolyExtStep::Mul(7710, 3971), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13075PolyExtStep::Sub(7709, 7711), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13076PolyExtStep::Add(3963, 3972), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13077PolyExtStep::Mul(3963, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13078PolyExtStep::Mul(7714, 3972), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13079PolyExtStep::Sub(7713, 7715), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13080PolyExtStep::Add(3964, 3973), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13081PolyExtStep::Mul(3964, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13082PolyExtStep::Mul(7718, 3973), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13083PolyExtStep::Sub(7717, 7719), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13084PolyExtStep::Add(3965, 3974), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13085PolyExtStep::Mul(3965, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13086PolyExtStep::Mul(7722, 3974), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13087PolyExtStep::Sub(7721, 7723), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13088PolyExtStep::Add(3966, 3975), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13089PolyExtStep::Mul(3966, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13090PolyExtStep::Mul(7726, 3975), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13091PolyExtStep::Sub(7725, 7727), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13092PolyExtStep::Add(3967, 3976), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13093PolyExtStep::Mul(3967, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13094PolyExtStep::Mul(7730, 3976), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13095PolyExtStep::Sub(7729, 7731), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13096PolyExtStep::Add(3968, 3984), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13097PolyExtStep::Mul(3968, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13098PolyExtStep::Mul(7734, 3984), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13099PolyExtStep::Sub(7733, 7735), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13100PolyExtStep::Add(3969, 3981), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13101PolyExtStep::Mul(3969, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13102PolyExtStep::Mul(7738, 3981), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13103PolyExtStep::Sub(7737, 7739), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13104PolyExtStep::Add(3970, 3978), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13105PolyExtStep::Mul(4006, 3978), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13106PolyExtStep::Sub(7741, 7742), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13107PolyExtStep::Add(3971, 3977), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13108PolyExtStep::Mul(3971, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13109PolyExtStep::Mul(7745, 3977), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13110PolyExtStep::Sub(7744, 7746), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13111PolyExtStep::Add(3972, 3952), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13112PolyExtStep::Mul(4008, 3952), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13113PolyExtStep::Sub(7748, 7749), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13114PolyExtStep::Add(3973, 3880), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13115PolyExtStep::Mul(3973, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13116PolyExtStep::Mul(7752, 3880), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13117PolyExtStep::Sub(7751, 7753), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13118PolyExtStep::Add(3974, 3881), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13119PolyExtStep::Mul(4018, 3881), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13120PolyExtStep::Sub(7755, 7756), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13121PolyExtStep::Add(3975, 3882), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13122PolyExtStep::Mul(3975, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13123PolyExtStep::Mul(7759, 3882), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13124PolyExtStep::Sub(7758, 7760), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13125PolyExtStep::Add(3976, 3953), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13126PolyExtStep::Mul(4020, 3953), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13127PolyExtStep::Sub(7762, 7763), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13128PolyExtStep::Add(3984, 3954), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13129PolyExtStep::Mul(3984, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13130PolyExtStep::Mul(7766, 3954), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13131PolyExtStep::Sub(7765, 7767), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13132PolyExtStep::Add(3981, 3955), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13133PolyExtStep::Mul(3981, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13134PolyExtStep::Mul(7770, 3955), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13135PolyExtStep::Sub(7769, 7771), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13136PolyExtStep::Add(3978, 3956), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13137PolyExtStep::Mul(3978, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13138PolyExtStep::Mul(7774, 3956), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13139PolyExtStep::Sub(7773, 7775), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13140PolyExtStep::Add(3977, 3957), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13141PolyExtStep::Mul(3977, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13142PolyExtStep::Mul(7778, 3957), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13143PolyExtStep::Sub(7777, 7779), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13144PolyExtStep::Add(3952, 3958), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13145PolyExtStep::Mul(3952, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13146PolyExtStep::Mul(7782, 3958), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13147PolyExtStep::Sub(7781, 7783), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13148PolyExtStep::Add(3880, 3959), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13149PolyExtStep::Mul(3880, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13150PolyExtStep::Mul(7786, 3959), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13151PolyExtStep::Sub(7785, 7787), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13152PolyExtStep::Add(3881, 3960), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13153PolyExtStep::Mul(3881, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13154PolyExtStep::Mul(7790, 3960), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13155PolyExtStep::Sub(7789, 7791), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13156PolyExtStep::Add(3882, 3961), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13157PolyExtStep::Mul(3882, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13158PolyExtStep::Mul(7794, 3961), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13159PolyExtStep::Sub(7793, 7795), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13160PolyExtStep::Add(3953, 3962), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13161PolyExtStep::Mul(3953, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13162PolyExtStep::Mul(7798, 3962), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13163PolyExtStep::Sub(7797, 7799), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13164PolyExtStep::Add(3954, 3963), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13165PolyExtStep::Mul(4451, 3963), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13166PolyExtStep::Sub(7801, 7802), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13167PolyExtStep::Add(3955, 3964), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13168PolyExtStep::Mul(3955, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13169PolyExtStep::Mul(7805, 3964), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13170PolyExtStep::Sub(7804, 7806), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13171PolyExtStep::Add(3956, 3965), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13172PolyExtStep::Mul(4453, 3965), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13173PolyExtStep::Sub(7808, 7809), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13174PolyExtStep::Add(3957, 3966), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13175PolyExtStep::Mul(3957, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13176PolyExtStep::Mul(7812, 3966), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13177PolyExtStep::Sub(7811, 7813), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13178PolyExtStep::Add(3958, 3967), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13179PolyExtStep::Mul(4463, 3967), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13180PolyExtStep::Sub(7815, 7816), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13181PolyExtStep::Add(3959, 3968), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13182PolyExtStep::Mul(3959, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13183PolyExtStep::Mul(7819, 3968), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13184PolyExtStep::Sub(7818, 7820), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13185PolyExtStep::Add(3960, 3969), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13186PolyExtStep::Mul(4465, 3969), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13187PolyExtStep::Sub(7822, 7823), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13188PolyExtStep::Add(3961, 3970), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13189PolyExtStep::Mul(3961, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13190PolyExtStep::Mul(7826, 3970), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13191PolyExtStep::Sub(7825, 7827), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13192PolyExtStep::Add(3881, 7712), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13193PolyExtStep::Mul(7790, 7712), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13194PolyExtStep::Sub(7829, 7830), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13195PolyExtStep::Add(3882, 7716), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13196PolyExtStep::Mul(7794, 7716), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13197PolyExtStep::Sub(7832, 7833), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13198PolyExtStep::Add(3953, 7720), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13199PolyExtStep::Mul(7798, 7720), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13200PolyExtStep::Sub(7835, 7836), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13201PolyExtStep::Add(3954, 7724), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13202PolyExtStep::Mul(4451, 7724), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13203PolyExtStep::Sub(7838, 7839), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13204PolyExtStep::Add(3955, 7728), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13205PolyExtStep::Mul(7805, 7728), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13206PolyExtStep::Sub(7841, 7842), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13207PolyExtStep::Add(3956, 7732), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13208PolyExtStep::Mul(4453, 7732), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13209PolyExtStep::Sub(7844, 7845), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13210PolyExtStep::Add(3957, 7736), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13211PolyExtStep::Mul(7812, 7736), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13212PolyExtStep::Sub(7847, 7848), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13213PolyExtStep::Add(3958, 7740), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13214PolyExtStep::Mul(4463, 7740), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13215PolyExtStep::Sub(7850, 7851), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13216PolyExtStep::Add(3959, 7743), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13217PolyExtStep::Mul(7819, 7743), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13218PolyExtStep::Sub(7853, 7854), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13219PolyExtStep::Add(3960, 7747), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13220PolyExtStep::Mul(4465, 7747), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13221PolyExtStep::Sub(7856, 7857), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13222PolyExtStep::Add(3961, 7750), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13223PolyExtStep::Mul(7826, 7750), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13224PolyExtStep::Sub(7859, 7860), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13225PolyExtStep::Add(3962, 7754), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13226PolyExtStep::Mul(7710, 7754), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13227PolyExtStep::Sub(7862, 7863), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13228PolyExtStep::Add(3963, 7757), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13229PolyExtStep::Mul(7714, 7757), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13230PolyExtStep::Sub(7865, 7866), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13231PolyExtStep::Add(3964, 7761), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13232PolyExtStep::Mul(7718, 7761), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13233PolyExtStep::Sub(7868, 7869), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13234PolyExtStep::Add(3965, 7764), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13235PolyExtStep::Mul(7722, 7764), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13236PolyExtStep::Sub(7871, 7872), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13237PolyExtStep::Add(3966, 7768), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13238PolyExtStep::Mul(7726, 7768), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13239PolyExtStep::Sub(7874, 7875), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13240PolyExtStep::Add(3967, 7772), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13241PolyExtStep::Mul(7730, 7772), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13242PolyExtStep::Sub(7877, 7878), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13243PolyExtStep::Add(3968, 7776), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13244PolyExtStep::Mul(7734, 7776), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13245PolyExtStep::Sub(7880, 7881), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13246PolyExtStep::Add(3969, 7780), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13247PolyExtStep::Mul(7738, 7780), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13248PolyExtStep::Sub(7883, 7884), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13249PolyExtStep::Add(3970, 7784), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13250PolyExtStep::Mul(4006, 7784), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13251PolyExtStep::Sub(7886, 7887), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13252PolyExtStep::Add(3971, 7788), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13253PolyExtStep::Mul(7745, 7788), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13254PolyExtStep::Sub(7889, 7890), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13255PolyExtStep::Add(3972, 7792), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13256PolyExtStep::Mul(4008, 7792), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13257PolyExtStep::Sub(7892, 7893), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13258PolyExtStep::Add(3973, 7796), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13259PolyExtStep::Mul(7752, 7796), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13260PolyExtStep::Sub(7895, 7896), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13261PolyExtStep::Add(3974, 7800), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13262PolyExtStep::Mul(4018, 7800), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13263PolyExtStep::Sub(7898, 7899), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13264PolyExtStep::Add(3975, 7803), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13265PolyExtStep::Mul(7759, 7803), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13266PolyExtStep::Sub(7901, 7902), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13267PolyExtStep::Add(3976, 7807), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13268PolyExtStep::Mul(4020, 7807), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13269PolyExtStep::Sub(7904, 7905), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13270PolyExtStep::Add(3984, 7810), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13271PolyExtStep::Mul(7766, 7810), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13272PolyExtStep::Sub(7907, 7908), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13273PolyExtStep::Add(3981, 7814), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13274PolyExtStep::Mul(7770, 7814), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13275PolyExtStep::Sub(7910, 7911), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13276PolyExtStep::Add(3978, 7817), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13277PolyExtStep::Mul(7774, 7817), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13278PolyExtStep::Sub(7913, 7914), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13279PolyExtStep::Add(3977, 7821), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13280PolyExtStep::Mul(7778, 7821), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13281PolyExtStep::Sub(7916, 7917), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13282PolyExtStep::Add(3952, 7824), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13283PolyExtStep::Mul(7782, 7824), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13284PolyExtStep::Sub(7919, 7920), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13285PolyExtStep::Add(3880, 7828), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13286PolyExtStep::Mul(7786, 7828), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13287PolyExtStep::Sub(7922, 7923), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13288PolyExtStep::Add(7419, 7430), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13289PolyExtStep::Mul(7419, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13290PolyExtStep::Mul(7926, 7430), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13291PolyExtStep::Sub(7925, 7927), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13292PolyExtStep::Add(7420, 7431), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13293PolyExtStep::Mul(7420, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13294PolyExtStep::Mul(7930, 7431), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13295PolyExtStep::Sub(7929, 7931), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13296PolyExtStep::Add(7421, 7432), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13297PolyExtStep::Mul(7421, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13298PolyExtStep::Mul(7934, 7432), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13299PolyExtStep::Sub(7933, 7935), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13300PolyExtStep::Add(7422, 7433), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13301PolyExtStep::Mul(7422, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13302PolyExtStep::Mul(7938, 7433), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13303PolyExtStep::Sub(7937, 7939), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13304PolyExtStep::Add(7423, 7434), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13305PolyExtStep::Mul(7423, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13306PolyExtStep::Mul(7942, 7434), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13307PolyExtStep::Sub(7941, 7943), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13308PolyExtStep::Add(7424, 7435), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13309PolyExtStep::Mul(7424, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13310PolyExtStep::Mul(7946, 7435), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13311PolyExtStep::Sub(7945, 7947), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13312PolyExtStep::Add(7425, 7436), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13313PolyExtStep::Mul(7425, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13314PolyExtStep::Mul(7950, 7436), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13315PolyExtStep::Sub(7949, 7951), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13316PolyExtStep::Add(7426, 7408), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13317PolyExtStep::Mul(7426, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13318PolyExtStep::Mul(7954, 7408), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13319PolyExtStep::Sub(7953, 7955), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13320PolyExtStep::Add(7427, 7409), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13321PolyExtStep::Mul(7427, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13322PolyExtStep::Mul(7958, 7409), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13323PolyExtStep::Sub(7957, 7959), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13324PolyExtStep::Add(7428, 7410), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13325PolyExtStep::Mul(7428, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13326PolyExtStep::Mul(7962, 7410), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13327PolyExtStep::Sub(7961, 7963), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13328PolyExtStep::Add(3494, 7411), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13329PolyExtStep::Mul(3494, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13330PolyExtStep::Mul(7966, 7411), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13331PolyExtStep::Sub(7965, 7967), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13332PolyExtStep::Add(3495, 7412), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13333PolyExtStep::Mul(3495, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13334PolyExtStep::Mul(7970, 7412), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13335PolyExtStep::Sub(7969, 7971), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13336PolyExtStep::Add(3496, 7413), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13337PolyExtStep::Mul(3496, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13338PolyExtStep::Mul(7974, 7413), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13339PolyExtStep::Sub(7973, 7975), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13340PolyExtStep::Add(7429, 7414), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13341PolyExtStep::Mul(7429, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13342PolyExtStep::Mul(7978, 7414), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13343PolyExtStep::Sub(7977, 7979), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13344PolyExtStep::Add(7430, 7415), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13345PolyExtStep::Mul(7430, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13346PolyExtStep::Mul(7982, 7415), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13347PolyExtStep::Sub(7981, 7983), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13348PolyExtStep::Add(7431, 7416), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13349PolyExtStep::Mul(7431, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13350PolyExtStep::Mul(7986, 7416), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13351PolyExtStep::Sub(7985, 7987), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13352PolyExtStep::Add(7432, 7417), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13353PolyExtStep::Mul(7432, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13354PolyExtStep::Mul(7990, 7417), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13355PolyExtStep::Sub(7989, 7991), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13356PolyExtStep::Add(7433, 7418), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13357PolyExtStep::Mul(7433, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13358PolyExtStep::Mul(7994, 7418), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13359PolyExtStep::Sub(7993, 7995), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13360PolyExtStep::Add(7434, 7419), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13361PolyExtStep::Mul(7434, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13362PolyExtStep::Mul(7998, 7419), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13363PolyExtStep::Sub(7997, 7999), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13364PolyExtStep::Add(7435, 7420), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13365PolyExtStep::Mul(7435, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13366PolyExtStep::Mul(8002, 7420), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13367PolyExtStep::Sub(8001, 8003), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13368PolyExtStep::Add(7436, 7421), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13369PolyExtStep::Mul(7436, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13370PolyExtStep::Mul(8006, 7421), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13371PolyExtStep::Sub(8005, 8007), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13372PolyExtStep::Add(7408, 7422), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13373PolyExtStep::Mul(7408, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13374PolyExtStep::Mul(8010, 7422), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13375PolyExtStep::Sub(8009, 8011), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13376PolyExtStep::Add(7409, 7423), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13377PolyExtStep::Mul(7409, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13378PolyExtStep::Mul(8014, 7423), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13379PolyExtStep::Sub(8013, 8015), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13380PolyExtStep::Add(7410, 7424), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13381PolyExtStep::Mul(7410, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13382PolyExtStep::Mul(8018, 7424), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13383PolyExtStep::Sub(8017, 8019), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13384PolyExtStep::Add(7411, 7425), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13385PolyExtStep::Mul(7411, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13386PolyExtStep::Mul(8022, 7425), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13387PolyExtStep::Sub(8021, 8023), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13388PolyExtStep::Add(7412, 7426), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13389PolyExtStep::Mul(7412, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13390PolyExtStep::Mul(8026, 7426), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13391PolyExtStep::Sub(8025, 8027), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13392PolyExtStep::Add(7413, 7427), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13393PolyExtStep::Mul(7413, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13394PolyExtStep::Mul(8030, 7427), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13395PolyExtStep::Sub(8029, 8031), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13396PolyExtStep::Add(7414, 7428), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13397PolyExtStep::Mul(7414, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13398PolyExtStep::Mul(8034, 7428), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13399PolyExtStep::Sub(8033, 8035), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13400PolyExtStep::Add(7415, 3494), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13401PolyExtStep::Mul(7415, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13402PolyExtStep::Mul(8038, 3494), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13403PolyExtStep::Sub(8037, 8039), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13404PolyExtStep::Add(7416, 3495), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13405PolyExtStep::Mul(7416, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13406PolyExtStep::Mul(8042, 3495), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13407PolyExtStep::Sub(8041, 8043), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13408PolyExtStep::Add(7417, 3496), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13409PolyExtStep::Mul(7417, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13410PolyExtStep::Mul(8046, 3496), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13411PolyExtStep::Sub(8045, 8047), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13412PolyExtStep::Add(7418, 7429), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13413PolyExtStep::Mul(7418, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13414PolyExtStep::Mul(8050, 7429), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13415PolyExtStep::Sub(8049, 8051), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13416PolyExtStep::Add(7414, 7928), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13417PolyExtStep::Mul(8034, 7928), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13418PolyExtStep::Sub(8053, 8054), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13419PolyExtStep::Add(7415, 7932), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13420PolyExtStep::Mul(8038, 7932), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13421PolyExtStep::Sub(8056, 8057), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13422PolyExtStep::Add(7416, 7936), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13423PolyExtStep::Mul(8042, 7936), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13424PolyExtStep::Sub(8059, 8060), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13425PolyExtStep::Add(7417, 7940), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13426PolyExtStep::Mul(8046, 7940), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13427PolyExtStep::Sub(8062, 8063), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13428PolyExtStep::Add(7418, 7944), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13429PolyExtStep::Mul(8050, 7944), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13430PolyExtStep::Sub(8065, 8066), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13431PolyExtStep::Add(7419, 7948), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13432PolyExtStep::Mul(7926, 7948), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13433PolyExtStep::Sub(8068, 8069), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13434PolyExtStep::Add(7420, 7952), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13435PolyExtStep::Mul(7930, 7952), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13436PolyExtStep::Sub(8071, 8072), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13437PolyExtStep::Add(7421, 7956), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13438PolyExtStep::Mul(7934, 7956), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13439PolyExtStep::Sub(8074, 8075), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13440PolyExtStep::Add(7422, 7960), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13441PolyExtStep::Mul(7938, 7960), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13442PolyExtStep::Sub(8077, 8078), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13443PolyExtStep::Add(7423, 7964), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13444PolyExtStep::Mul(7942, 7964), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13445PolyExtStep::Sub(8080, 8081), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13446PolyExtStep::Add(7424, 7968), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13447PolyExtStep::Mul(7946, 7968), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13448PolyExtStep::Sub(8083, 8084), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13449PolyExtStep::Add(7425, 7972), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13450PolyExtStep::Mul(7950, 7972), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13451PolyExtStep::Sub(8086, 8087), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13452PolyExtStep::Add(7426, 7976), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13453PolyExtStep::Mul(7954, 7976), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13454PolyExtStep::Sub(8089, 8090), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13455PolyExtStep::Add(7427, 7980), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13456PolyExtStep::Mul(7958, 7980), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13457PolyExtStep::Sub(8092, 8093), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13458PolyExtStep::Add(7428, 7984), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13459PolyExtStep::Mul(7962, 7984), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13460PolyExtStep::Sub(8095, 8096), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13461PolyExtStep::Add(3494, 7988), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13462PolyExtStep::Mul(7966, 7988), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13463PolyExtStep::Sub(8098, 8099), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13464PolyExtStep::Add(3495, 7992), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13465PolyExtStep::Mul(7970, 7992), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13466PolyExtStep::Sub(8101, 8102), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13467PolyExtStep::Add(3496, 7996), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13468PolyExtStep::Mul(7974, 7996), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13469PolyExtStep::Sub(8104, 8105), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13470PolyExtStep::Add(7429, 8000), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13471PolyExtStep::Mul(7978, 8000), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13472PolyExtStep::Sub(8107, 8108), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13473PolyExtStep::Add(7430, 8004), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13474PolyExtStep::Mul(7982, 8004), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13475PolyExtStep::Sub(8110, 8111), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13476PolyExtStep::Add(7431, 8008), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13477PolyExtStep::Mul(7986, 8008), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13478PolyExtStep::Sub(8113, 8114), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13479PolyExtStep::Add(7432, 8012), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13480PolyExtStep::Mul(7990, 8012), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13481PolyExtStep::Sub(8116, 8117), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13482PolyExtStep::Add(7433, 8016), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13483PolyExtStep::Mul(7994, 8016), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13484PolyExtStep::Sub(8119, 8120), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13485PolyExtStep::Add(7434, 8020), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13486PolyExtStep::Mul(7998, 8020), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13487PolyExtStep::Sub(8122, 8123), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13488PolyExtStep::Add(7435, 8024), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13489PolyExtStep::Mul(8002, 8024), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13490PolyExtStep::Sub(8125, 8126), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13491PolyExtStep::Add(7436, 8028), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13492PolyExtStep::Mul(8006, 8028), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13493PolyExtStep::Sub(8128, 8129), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13494PolyExtStep::Add(7408, 8032), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13495PolyExtStep::Mul(8010, 8032), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13496PolyExtStep::Sub(8131, 8132), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13497PolyExtStep::Add(7409, 8036), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13498PolyExtStep::Mul(8014, 8036), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13499PolyExtStep::Sub(8134, 8135), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13500PolyExtStep::Add(7410, 8040), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13501PolyExtStep::Mul(8018, 8040), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13502PolyExtStep::Sub(8137, 8138), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13503PolyExtStep::Add(7411, 8044), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13504PolyExtStep::Mul(8022, 8044), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13505PolyExtStep::Sub(8140, 8141), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13506PolyExtStep::Add(7412, 8048), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13507PolyExtStep::Mul(8026, 8048), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13508PolyExtStep::Sub(8143, 8144), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13509PolyExtStep::Add(7413, 8052), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13510PolyExtStep::Mul(8030, 8052), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13511PolyExtStep::Sub(8146, 8147), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13512PolyExtStep::Mul(736, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13513PolyExtStep::Mul(737, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13514PolyExtStep::Mul(738, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13515PolyExtStep::Mul(739, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13516PolyExtStep::Mul(747, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13517PolyExtStep::Mul(748, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13518PolyExtStep::Mul(729, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13519PolyExtStep::Mul(755, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13520PolyExtStep::Add(7648, 8149), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13521PolyExtStep::Add(8157, 8150), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13522PolyExtStep::Add(8158, 8151), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13523PolyExtStep::Add(8159, 8152), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13524PolyExtStep::Add(8160, 8153), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13525PolyExtStep::Add(8161, 8154), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13526PolyExtStep::Add(8162, 8155), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13527PolyExtStep::Add(8163, 8156), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13528PolyExtStep::Mul(770, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13529PolyExtStep::Mul(771, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13530PolyExtStep::Mul(752, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13531PolyExtStep::Mul(782, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13532PolyExtStep::Mul(785, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13533PolyExtStep::Mul(788, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13534PolyExtStep::Mul(791, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13535PolyExtStep::Add(7676, 8165), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13536PolyExtStep::Add(8172, 8166), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13537PolyExtStep::Add(8173, 8167), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13538PolyExtStep::Add(8174, 8168), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13539PolyExtStep::Add(8175, 8169), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13540PolyExtStep::Add(8176, 8170), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13541PolyExtStep::Add(8177, 8171), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13542PolyExtStep::Add(8178, 1130), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13543PolyExtStep::Mul(7598, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13544PolyExtStep::Mul(7599, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13545PolyExtStep::Mul(7600, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13546PolyExtStep::Mul(7601, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13547PolyExtStep::Mul(7602, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13548PolyExtStep::Mul(7603, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13549PolyExtStep::Mul(7604, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13550PolyExtStep::Mul(7605, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13551PolyExtStep::Mul(7606, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13552PolyExtStep::Mul(7607, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13553PolyExtStep::Mul(7608, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13554PolyExtStep::Mul(7609, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13555PolyExtStep::Mul(7610, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13556PolyExtStep::Mul(7611, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13557PolyExtStep::Mul(7612, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13558PolyExtStep::Add(7597, 8180), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13559PolyExtStep::Add(8195, 8181), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13560PolyExtStep::Add(8196, 8182), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13561PolyExtStep::Add(8197, 8183), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13562PolyExtStep::Add(8198, 8184), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13563PolyExtStep::Add(8199, 8185), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13564PolyExtStep::Add(8200, 8186), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13565PolyExtStep::Add(8201, 8187), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13566PolyExtStep::Add(8202, 8188), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13567PolyExtStep::Add(8203, 8189), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13568PolyExtStep::Add(8204, 8190), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13569PolyExtStep::Add(8205, 8191), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13570PolyExtStep::Add(8206, 8192), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13571PolyExtStep::Add(8207, 8193), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13572PolyExtStep::Add(8208, 8194), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13573PolyExtStep::Mul(7614, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13574PolyExtStep::Mul(7615, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13575PolyExtStep::Mul(7616, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13576PolyExtStep::Mul(7617, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13577PolyExtStep::Mul(7618, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13578PolyExtStep::Mul(7619, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13579PolyExtStep::Mul(7620, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13580PolyExtStep::Mul(7621, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13581PolyExtStep::Mul(7622, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13582PolyExtStep::Mul(7623, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13583PolyExtStep::Mul(7624, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13584PolyExtStep::Mul(7625, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13585PolyExtStep::Mul(7626, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13586PolyExtStep::Mul(7627, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13587PolyExtStep::Mul(7628, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13588PolyExtStep::Add(7613, 8210), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13589PolyExtStep::Add(8225, 8211), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13590PolyExtStep::Add(8226, 8212), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13591PolyExtStep::Add(8227, 8213), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13592PolyExtStep::Add(8228, 8214), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13593PolyExtStep::Add(8229, 8215), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13594PolyExtStep::Add(8230, 8216), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13595PolyExtStep::Add(8231, 8217), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13596PolyExtStep::Add(8232, 8218), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13597PolyExtStep::Add(8233, 8219), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13598PolyExtStep::Add(8234, 8220), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13599PolyExtStep::Add(8235, 8221), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13600PolyExtStep::Add(8236, 8222), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13601PolyExtStep::Add(8237, 8223), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13602PolyExtStep::Add(8238, 8224), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13603PolyExtStep::Mul(7408, 7469), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13604PolyExtStep::Sub(1, 7408), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13605PolyExtStep::Mul(8241, 7533), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13606PolyExtStep::Add(8240, 8242), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13607PolyExtStep::Mul(7409, 7470), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13608PolyExtStep::Sub(1, 7409), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13609PolyExtStep::Mul(8245, 7534), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13610PolyExtStep::Add(8244, 8246), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13611PolyExtStep::Mul(7410, 7471), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13612PolyExtStep::Sub(1, 7410), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13613PolyExtStep::Mul(8249, 7535), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13614PolyExtStep::Add(8248, 8250), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13615PolyExtStep::Mul(7411, 7472), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13616PolyExtStep::Sub(1, 7411), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13617PolyExtStep::Mul(8253, 7536), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13618PolyExtStep::Add(8252, 8254), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13619PolyExtStep::Mul(7412, 7473), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13620PolyExtStep::Sub(1, 7412), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13621PolyExtStep::Mul(8257, 7537), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13622PolyExtStep::Add(8256, 8258), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13623PolyExtStep::Mul(7413, 7474), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13624PolyExtStep::Sub(1, 7413), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13625PolyExtStep::Mul(8261, 7538), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13626PolyExtStep::Add(8260, 8262), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13627PolyExtStep::Mul(7414, 7475), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13628PolyExtStep::Sub(1, 7414), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13629PolyExtStep::Mul(8265, 7539), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13630PolyExtStep::Add(8264, 8266), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13631PolyExtStep::Mul(7415, 7476), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13632PolyExtStep::Sub(1, 7415), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13633PolyExtStep::Mul(8269, 7540), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13634PolyExtStep::Add(8268, 8270), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13635PolyExtStep::Mul(7416, 7477), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13636PolyExtStep::Sub(1, 7416), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13637PolyExtStep::Mul(8273, 7541), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13638PolyExtStep::Add(8272, 8274), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13639PolyExtStep::Mul(7417, 7478), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13640PolyExtStep::Sub(1, 7417), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13641PolyExtStep::Mul(8277, 7542), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13642PolyExtStep::Add(8276, 8278), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13643PolyExtStep::Mul(7418, 7479), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13644PolyExtStep::Sub(1, 7418), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13645PolyExtStep::Mul(8281, 7543), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13646PolyExtStep::Add(8280, 8282), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13647PolyExtStep::Mul(7419, 7480), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13648PolyExtStep::Sub(1, 7419), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13649PolyExtStep::Mul(8285, 7544), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13650PolyExtStep::Add(8284, 8286), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13651PolyExtStep::Mul(7420, 7481), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13652PolyExtStep::Sub(1, 7420), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13653PolyExtStep::Mul(8289, 7545), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13654PolyExtStep::Add(8288, 8290), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13655PolyExtStep::Mul(7421, 7482), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13656PolyExtStep::Sub(1, 7421), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13657PolyExtStep::Mul(8293, 7546), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13658PolyExtStep::Add(8292, 8294), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13659PolyExtStep::Mul(7422, 7483), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13660PolyExtStep::Sub(1, 7422), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13661PolyExtStep::Mul(8297, 7547), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13662PolyExtStep::Add(8296, 8298), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13663PolyExtStep::Mul(7423, 7484), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13664PolyExtStep::Sub(1, 7423), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13665PolyExtStep::Mul(8301, 7548), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13666PolyExtStep::Add(8300, 8302), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13667PolyExtStep::Mul(7424, 7485), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13668PolyExtStep::Sub(1, 7424), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13669PolyExtStep::Mul(8305, 7549), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13670PolyExtStep::Add(8304, 8306), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13671PolyExtStep::Mul(7425, 7486), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13672PolyExtStep::Sub(1, 7425), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13673PolyExtStep::Mul(8309, 7550), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13674PolyExtStep::Add(8308, 8310), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13675PolyExtStep::Mul(7426, 7487), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13676PolyExtStep::Sub(1, 7426), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13677PolyExtStep::Mul(8313, 7551), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13678PolyExtStep::Add(8312, 8314), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13679PolyExtStep::Mul(7427, 7488), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13680PolyExtStep::Sub(1, 7427), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13681PolyExtStep::Mul(8317, 7552), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13682PolyExtStep::Add(8316, 8318), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13683PolyExtStep::Mul(7428, 7489), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13684PolyExtStep::Sub(1, 7428), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13685PolyExtStep::Mul(8321, 7553), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13686PolyExtStep::Add(8320, 8322), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13687PolyExtStep::Mul(3494, 7490), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13688PolyExtStep::Sub(1, 3494), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13689PolyExtStep::Mul(8325, 7554), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13690PolyExtStep::Add(8324, 8326), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13691PolyExtStep::Mul(3495, 7491), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13692PolyExtStep::Sub(1, 3495), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13693PolyExtStep::Mul(8329, 7555), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13694PolyExtStep::Add(8328, 8330), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13695PolyExtStep::Mul(3496, 7492), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13696PolyExtStep::Sub(1, 3496), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13697PolyExtStep::Mul(8333, 7556), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13698PolyExtStep::Add(8332, 8334), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13699PolyExtStep::Mul(7429, 7493), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13700PolyExtStep::Sub(1, 7429), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13701PolyExtStep::Mul(8337, 7557), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13702PolyExtStep::Add(8336, 8338), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13703PolyExtStep::Mul(7430, 7494), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13704PolyExtStep::Sub(1, 7430), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13705PolyExtStep::Mul(8341, 7558), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13706PolyExtStep::Add(8340, 8342), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13707PolyExtStep::Mul(7431, 7495), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13708PolyExtStep::Sub(1, 7431), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13709PolyExtStep::Mul(8345, 7559), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13710PolyExtStep::Add(8344, 8346), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13711PolyExtStep::Mul(7432, 7496), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13712PolyExtStep::Sub(1, 7432), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13713PolyExtStep::Mul(8349, 7560), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13714PolyExtStep::Add(8348, 8350), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13715PolyExtStep::Mul(7433, 7497), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13716PolyExtStep::Sub(1, 7433), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13717PolyExtStep::Mul(8353, 7561), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13718PolyExtStep::Add(8352, 8354), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13719PolyExtStep::Mul(7434, 7498), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13720PolyExtStep::Sub(1, 7434), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13721PolyExtStep::Mul(8357, 7562), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13722PolyExtStep::Add(8356, 8358), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13723PolyExtStep::Mul(7435, 7499), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13724PolyExtStep::Sub(1, 7435), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13725PolyExtStep::Mul(8361, 7563), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13726PolyExtStep::Add(8360, 8362), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13727PolyExtStep::Mul(7436, 7500), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13728PolyExtStep::Sub(1, 7436), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13729PolyExtStep::Mul(8365, 7564), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13730PolyExtStep::Add(8364, 8366), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13731PolyExtStep::Mul(8247, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13732PolyExtStep::Mul(8251, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13733PolyExtStep::Mul(8255, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13734PolyExtStep::Mul(8259, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13735PolyExtStep::Mul(8263, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13736PolyExtStep::Mul(8267, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13737PolyExtStep::Mul(8271, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13738PolyExtStep::Mul(8275, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13739PolyExtStep::Mul(8279, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13740PolyExtStep::Mul(8283, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13741PolyExtStep::Mul(8287, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13742PolyExtStep::Mul(8291, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13743PolyExtStep::Mul(8295, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13744PolyExtStep::Mul(8299, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13745PolyExtStep::Mul(8303, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13746PolyExtStep::Add(8243, 8368), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13747PolyExtStep::Add(8383, 8369), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13748PolyExtStep::Add(8384, 8370), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13749PolyExtStep::Add(8385, 8371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13750PolyExtStep::Add(8386, 8372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13751PolyExtStep::Add(8387, 8373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13752PolyExtStep::Add(8388, 8374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13753PolyExtStep::Add(8389, 8375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13754PolyExtStep::Add(8390, 8376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13755PolyExtStep::Add(8391, 8377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13756PolyExtStep::Add(8392, 8378), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13757PolyExtStep::Add(8393, 8379), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13758PolyExtStep::Add(8394, 8380), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13759PolyExtStep::Add(8395, 8381), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13760PolyExtStep::Add(8396, 8382), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13761PolyExtStep::Mul(8311, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13762PolyExtStep::Mul(8315, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13763PolyExtStep::Mul(8319, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13764PolyExtStep::Mul(8323, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13765PolyExtStep::Mul(8327, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13766PolyExtStep::Mul(8331, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13767PolyExtStep::Mul(8335, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13768PolyExtStep::Mul(8339, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13769PolyExtStep::Mul(8343, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13770PolyExtStep::Mul(8347, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13771PolyExtStep::Mul(8351, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13772PolyExtStep::Mul(8355, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13773PolyExtStep::Mul(8359, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13774PolyExtStep::Mul(8363, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13775PolyExtStep::Mul(8367, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13776PolyExtStep::Add(8307, 8398), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13777PolyExtStep::Add(8413, 8399), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13778PolyExtStep::Add(8414, 8400), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13779PolyExtStep::Add(8415, 8401), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13780PolyExtStep::Add(8416, 8402), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13781PolyExtStep::Add(8417, 8403), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13782PolyExtStep::Add(8418, 8404), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13783PolyExtStep::Add(8419, 8405), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13784PolyExtStep::Add(8420, 8406), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13785PolyExtStep::Add(8421, 8407), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13786PolyExtStep::Add(8422, 8408), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13787PolyExtStep::Add(8423, 8409), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13788PolyExtStep::Add(8424, 8410), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13789PolyExtStep::Add(8425, 8411), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13790PolyExtStep::Add(8426, 8412), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13791PolyExtStep::Mul(8058, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13792PolyExtStep::Mul(8061, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13793PolyExtStep::Mul(8064, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13794PolyExtStep::Mul(8067, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13795PolyExtStep::Mul(8070, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13796PolyExtStep::Mul(8073, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13797PolyExtStep::Mul(8076, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13798PolyExtStep::Mul(8079, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13799PolyExtStep::Mul(8082, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13800PolyExtStep::Mul(8085, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13801PolyExtStep::Mul(8088, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13802PolyExtStep::Mul(8091, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13803PolyExtStep::Mul(8094, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13804PolyExtStep::Mul(8097, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13805PolyExtStep::Mul(8100, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13806PolyExtStep::Add(8055, 8428), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13807PolyExtStep::Add(8443, 8429), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13808PolyExtStep::Add(8444, 8430), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13809PolyExtStep::Add(8445, 8431), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13810PolyExtStep::Add(8446, 8432), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13811PolyExtStep::Add(8447, 8433), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13812PolyExtStep::Add(8448, 8434), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13813PolyExtStep::Add(8449, 8435), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13814PolyExtStep::Add(8450, 8436), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13815PolyExtStep::Add(8451, 8437), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13816PolyExtStep::Add(8452, 8438), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13817PolyExtStep::Add(8453, 8439), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13818PolyExtStep::Add(8454, 8440), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13819PolyExtStep::Add(8455, 8441), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13820PolyExtStep::Add(8456, 8442), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13821PolyExtStep::Mul(8106, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13822PolyExtStep::Mul(8109, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13823PolyExtStep::Mul(8112, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13824PolyExtStep::Mul(8115, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13825PolyExtStep::Mul(8118, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13826PolyExtStep::Mul(8121, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13827PolyExtStep::Mul(8124, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13828PolyExtStep::Mul(8127, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13829PolyExtStep::Mul(8130, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13830PolyExtStep::Mul(8133, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13831PolyExtStep::Mul(8136, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13832PolyExtStep::Mul(8139, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13833PolyExtStep::Mul(8142, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13834PolyExtStep::Mul(8145, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13835PolyExtStep::Mul(8148, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13836PolyExtStep::Add(8103, 8458), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13837PolyExtStep::Add(8473, 8459), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13838PolyExtStep::Add(8474, 8460), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13839PolyExtStep::Add(8475, 8461), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13840PolyExtStep::Add(8476, 8462), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13841PolyExtStep::Add(8477, 8463), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13842PolyExtStep::Add(8478, 8464), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13843PolyExtStep::Add(8479, 8465), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13844PolyExtStep::Add(8480, 8466), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13845PolyExtStep::Add(8481, 8467), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13846PolyExtStep::Add(8482, 8468), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13847PolyExtStep::Add(8483, 8469), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13848PolyExtStep::Add(8484, 8470), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13849PolyExtStep::Add(8485, 8471), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13850PolyExtStep::Add(8486, 8472), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13851PolyExtStep::Add(8397, 8457), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13852PolyExtStep::Add(8427, 8487), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13853PolyExtStep::Add(8209, 8488), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13854PolyExtStep::Add(8239, 8489), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13855PolyExtStep::Add(818, 8490), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13856PolyExtStep::Add(821, 8491), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13857PolyExtStep::Add(8164, 8492), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13858PolyExtStep::Add(8179, 8493), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13859PolyExtStep::Mul(3952, 7437), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13860PolyExtStep::Sub(1, 7501), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13861PolyExtStep::Mul(8496, 8497), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13862PolyExtStep::Sub(1, 7437), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13863PolyExtStep::Mul(3952, 8499), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13864PolyExtStep::Mul(8500, 7501), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13865PolyExtStep::Add(8498, 8501), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13866PolyExtStep::Sub(1, 3952), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13867PolyExtStep::Mul(8503, 7437), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13868PolyExtStep::Mul(8504, 7501), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13869PolyExtStep::Add(8502, 8505), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13870PolyExtStep::Mul(8496, 7501), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13871PolyExtStep::Add(8506, 8507), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13872PolyExtStep::Mul(3880, 7438), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13873PolyExtStep::Sub(1, 7502), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13874PolyExtStep::Mul(8509, 8510), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13875PolyExtStep::Sub(1, 7438), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13876PolyExtStep::Mul(3880, 8512), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13877PolyExtStep::Mul(8513, 7502), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13878PolyExtStep::Add(8511, 8514), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13879PolyExtStep::Sub(1, 3880), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13880PolyExtStep::Mul(8516, 7438), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13881PolyExtStep::Mul(8517, 7502), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13882PolyExtStep::Add(8515, 8518), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13883PolyExtStep::Mul(8509, 7502), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13884PolyExtStep::Add(8519, 8520), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13885PolyExtStep::Mul(3881, 7439), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13886PolyExtStep::Sub(1, 7503), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13887PolyExtStep::Mul(8522, 8523), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13888PolyExtStep::Sub(1, 7439), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13889PolyExtStep::Mul(3881, 8525), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13890PolyExtStep::Mul(8526, 7503), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13891PolyExtStep::Add(8524, 8527), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13892PolyExtStep::Sub(1, 3881), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13893PolyExtStep::Mul(8529, 7439), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13894PolyExtStep::Mul(8530, 7503), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13895PolyExtStep::Add(8528, 8531), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13896PolyExtStep::Mul(8522, 7503), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13897PolyExtStep::Add(8532, 8533), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13898PolyExtStep::Mul(3882, 7440), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13899PolyExtStep::Sub(1, 7504), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13900PolyExtStep::Mul(8535, 8536), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13901PolyExtStep::Sub(1, 7440), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13902PolyExtStep::Mul(3882, 8538), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13903PolyExtStep::Mul(8539, 7504), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13904PolyExtStep::Add(8537, 8540), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13905PolyExtStep::Sub(1, 3882), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13906PolyExtStep::Mul(8542, 7440), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13907PolyExtStep::Mul(8543, 7504), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13908PolyExtStep::Add(8541, 8544), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13909PolyExtStep::Mul(8535, 7504), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13910PolyExtStep::Add(8545, 8546), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13911PolyExtStep::Mul(3953, 7441), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13912PolyExtStep::Sub(1, 7505), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13913PolyExtStep::Mul(8548, 8549), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13914PolyExtStep::Sub(1, 7441), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13915PolyExtStep::Mul(3953, 8551), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13916PolyExtStep::Mul(8552, 7505), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13917PolyExtStep::Add(8550, 8553), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13918PolyExtStep::Sub(1, 3953), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13919PolyExtStep::Mul(8555, 7441), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13920PolyExtStep::Mul(8556, 7505), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13921PolyExtStep::Add(8554, 8557), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13922PolyExtStep::Mul(8548, 7505), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13923PolyExtStep::Add(8558, 8559), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13924PolyExtStep::Mul(3954, 7442), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13925PolyExtStep::Sub(1, 7506), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13926PolyExtStep::Mul(8561, 8562), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13927PolyExtStep::Sub(1, 7442), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13928PolyExtStep::Mul(3954, 8564), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13929PolyExtStep::Mul(8565, 7506), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13930PolyExtStep::Add(8563, 8566), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13931PolyExtStep::Sub(1, 3954), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13932PolyExtStep::Mul(8568, 7442), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13933PolyExtStep::Mul(8569, 7506), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13934PolyExtStep::Add(8567, 8570), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13935PolyExtStep::Mul(8561, 7506), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13936PolyExtStep::Add(8571, 8572), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13937PolyExtStep::Mul(3955, 7443), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13938PolyExtStep::Sub(1, 7507), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13939PolyExtStep::Mul(8574, 8575), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13940PolyExtStep::Sub(1, 7443), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13941PolyExtStep::Mul(3955, 8577), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13942PolyExtStep::Mul(8578, 7507), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13943PolyExtStep::Add(8576, 8579), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13944PolyExtStep::Sub(1, 3955), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13945PolyExtStep::Mul(8581, 7443), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13946PolyExtStep::Mul(8582, 7507), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13947PolyExtStep::Add(8580, 8583), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13948PolyExtStep::Mul(8574, 7507), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13949PolyExtStep::Add(8584, 8585), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13950PolyExtStep::Mul(3956, 7444), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13951PolyExtStep::Sub(1, 7508), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13952PolyExtStep::Mul(8587, 8588), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13953PolyExtStep::Sub(1, 7444), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13954PolyExtStep::Mul(3956, 8590), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13955PolyExtStep::Mul(8591, 7508), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13956PolyExtStep::Add(8589, 8592), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13957PolyExtStep::Sub(1, 3956), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13958PolyExtStep::Mul(8594, 7444), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13959PolyExtStep::Mul(8595, 7508), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13960PolyExtStep::Add(8593, 8596), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13961PolyExtStep::Mul(8587, 7508), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13962PolyExtStep::Add(8597, 8598), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13963PolyExtStep::Mul(3957, 7445), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13964PolyExtStep::Sub(1, 7509), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13965PolyExtStep::Mul(8600, 8601), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13966PolyExtStep::Sub(1, 7445), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13967PolyExtStep::Mul(3957, 8603), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13968PolyExtStep::Mul(8604, 7509), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13969PolyExtStep::Add(8602, 8605), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13970PolyExtStep::Sub(1, 3957), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13971PolyExtStep::Mul(8607, 7445), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13972PolyExtStep::Mul(8608, 7509), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13973PolyExtStep::Add(8606, 8609), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13974PolyExtStep::Mul(8600, 7509), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13975PolyExtStep::Add(8610, 8611), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13976PolyExtStep::Mul(3958, 7446), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13977PolyExtStep::Sub(1, 7510), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13978PolyExtStep::Mul(8613, 8614), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13979PolyExtStep::Sub(1, 7446), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13980PolyExtStep::Mul(3958, 8616), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13981PolyExtStep::Mul(8617, 7510), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13982PolyExtStep::Add(8615, 8618), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13983PolyExtStep::Sub(1, 3958), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13984PolyExtStep::Mul(8620, 7446), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13985PolyExtStep::Mul(8621, 7510), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13986PolyExtStep::Add(8619, 8622), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13987PolyExtStep::Mul(8613, 7510), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13988PolyExtStep::Add(8623, 8624), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13989PolyExtStep::Mul(3959, 7447), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13990PolyExtStep::Sub(1, 7511), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13991PolyExtStep::Mul(8626, 8627), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13992PolyExtStep::Sub(1, 7447), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13993PolyExtStep::Mul(3959, 8629), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13994PolyExtStep::Mul(8630, 7511), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13995PolyExtStep::Add(8628, 8631), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13996PolyExtStep::Sub(1, 3959), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13997PolyExtStep::Mul(8633, 7447), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13998PolyExtStep::Mul(8634, 7511), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13999PolyExtStep::Add(8632, 8635), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14000PolyExtStep::Mul(8626, 7511), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14001PolyExtStep::Add(8636, 8637), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14002PolyExtStep::Mul(3960, 7448), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14003PolyExtStep::Sub(1, 7512), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14004PolyExtStep::Mul(8639, 8640), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14005PolyExtStep::Sub(1, 7448), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14006PolyExtStep::Mul(3960, 8642), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14007PolyExtStep::Mul(8643, 7512), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14008PolyExtStep::Add(8641, 8644), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14009PolyExtStep::Sub(1, 3960), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14010PolyExtStep::Mul(8646, 7448), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14011PolyExtStep::Mul(8647, 7512), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14012PolyExtStep::Add(8645, 8648), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14013PolyExtStep::Mul(8639, 7512), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14014PolyExtStep::Add(8649, 8650), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14015PolyExtStep::Mul(3961, 7449), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14016PolyExtStep::Sub(1, 7513), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14017PolyExtStep::Mul(8652, 8653), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14018PolyExtStep::Sub(1, 7449), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14019PolyExtStep::Mul(3961, 8655), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14020PolyExtStep::Mul(8656, 7513), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14021PolyExtStep::Add(8654, 8657), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14022PolyExtStep::Sub(1, 3961), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14023PolyExtStep::Mul(8659, 7449), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14024PolyExtStep::Mul(8660, 7513), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14025PolyExtStep::Add(8658, 8661), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14026PolyExtStep::Mul(8652, 7513), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14027PolyExtStep::Add(8662, 8663), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14028PolyExtStep::Mul(3962, 7450), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14029PolyExtStep::Sub(1, 7514), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14030PolyExtStep::Mul(8665, 8666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14031PolyExtStep::Sub(1, 7450), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14032PolyExtStep::Mul(3962, 8668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14033PolyExtStep::Mul(8669, 7514), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14034PolyExtStep::Add(8667, 8670), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14035PolyExtStep::Sub(1, 3962), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14036PolyExtStep::Mul(8672, 7450), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14037PolyExtStep::Mul(8673, 7514), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14038PolyExtStep::Add(8671, 8674), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14039PolyExtStep::Mul(8665, 7514), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14040PolyExtStep::Add(8675, 8676), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14041PolyExtStep::Mul(3963, 7451), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14042PolyExtStep::Sub(1, 7515), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14043PolyExtStep::Mul(8678, 8679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14044PolyExtStep::Sub(1, 7451), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14045PolyExtStep::Mul(3963, 8681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14046PolyExtStep::Mul(8682, 7515), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14047PolyExtStep::Add(8680, 8683), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14048PolyExtStep::Sub(1, 3963), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14049PolyExtStep::Mul(8685, 7451), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14050PolyExtStep::Mul(8686, 7515), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14051PolyExtStep::Add(8684, 8687), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14052PolyExtStep::Mul(8678, 7515), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14053PolyExtStep::Add(8688, 8689), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14054PolyExtStep::Mul(3964, 7452), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14055PolyExtStep::Sub(1, 7516), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14056PolyExtStep::Mul(8691, 8692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14057PolyExtStep::Sub(1, 7452), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14058PolyExtStep::Mul(3964, 8694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14059PolyExtStep::Mul(8695, 7516), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14060PolyExtStep::Add(8693, 8696), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14061PolyExtStep::Sub(1, 3964), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14062PolyExtStep::Mul(8698, 7452), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14063PolyExtStep::Mul(8699, 7516), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14064PolyExtStep::Add(8697, 8700), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14065PolyExtStep::Mul(8691, 7516), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14066PolyExtStep::Add(8701, 8702), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14067PolyExtStep::Mul(3965, 7453), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14068PolyExtStep::Sub(1, 7517), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14069PolyExtStep::Mul(8704, 8705), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14070PolyExtStep::Sub(1, 7453), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14071PolyExtStep::Mul(3965, 8707), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14072PolyExtStep::Mul(8708, 7517), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14073PolyExtStep::Add(8706, 8709), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14074PolyExtStep::Sub(1, 3965), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14075PolyExtStep::Mul(8711, 7453), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14076PolyExtStep::Mul(8712, 7517), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14077PolyExtStep::Add(8710, 8713), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14078PolyExtStep::Mul(8704, 7517), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14079PolyExtStep::Add(8714, 8715), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14080PolyExtStep::Mul(3966, 7454), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14081PolyExtStep::Sub(1, 7518), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14082PolyExtStep::Mul(8717, 8718), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14083PolyExtStep::Sub(1, 7454), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14084PolyExtStep::Mul(3966, 8720), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14085PolyExtStep::Mul(8721, 7518), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14086PolyExtStep::Add(8719, 8722), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14087PolyExtStep::Sub(1, 3966), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14088PolyExtStep::Mul(8724, 7454), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14089PolyExtStep::Mul(8725, 7518), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14090PolyExtStep::Add(8723, 8726), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14091PolyExtStep::Mul(8717, 7518), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14092PolyExtStep::Add(8727, 8728), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14093PolyExtStep::Mul(3967, 7455), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14094PolyExtStep::Sub(1, 7519), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14095PolyExtStep::Mul(8730, 8731), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14096PolyExtStep::Sub(1, 7455), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14097PolyExtStep::Mul(3967, 8733), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14098PolyExtStep::Mul(8734, 7519), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14099PolyExtStep::Add(8732, 8735), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14100PolyExtStep::Sub(1, 3967), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14101PolyExtStep::Mul(8737, 7455), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14102PolyExtStep::Mul(8738, 7519), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14103PolyExtStep::Add(8736, 8739), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14104PolyExtStep::Mul(8730, 7519), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14105PolyExtStep::Add(8740, 8741), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14106PolyExtStep::Mul(3968, 7456), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14107PolyExtStep::Sub(1, 7520), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14108PolyExtStep::Mul(8743, 8744), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14109PolyExtStep::Sub(1, 7456), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14110PolyExtStep::Mul(3968, 8746), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14111PolyExtStep::Mul(8747, 7520), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14112PolyExtStep::Add(8745, 8748), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14113PolyExtStep::Sub(1, 3968), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14114PolyExtStep::Mul(8750, 7456), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14115PolyExtStep::Mul(8751, 7520), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14116PolyExtStep::Add(8749, 8752), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14117PolyExtStep::Mul(8743, 7520), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14118PolyExtStep::Add(8753, 8754), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14119PolyExtStep::Mul(3969, 7457), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14120PolyExtStep::Sub(1, 7521), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14121PolyExtStep::Mul(8756, 8757), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14122PolyExtStep::Sub(1, 7457), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14123PolyExtStep::Mul(3969, 8759), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14124PolyExtStep::Mul(8760, 7521), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14125PolyExtStep::Add(8758, 8761), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14126PolyExtStep::Sub(1, 3969), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14127PolyExtStep::Mul(8763, 7457), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14128PolyExtStep::Mul(8764, 7521), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14129PolyExtStep::Add(8762, 8765), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14130PolyExtStep::Mul(8756, 7521), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14131PolyExtStep::Add(8766, 8767), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14132PolyExtStep::Mul(3970, 7458), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14133PolyExtStep::Sub(1, 7522), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14134PolyExtStep::Mul(8769, 8770), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14135PolyExtStep::Sub(1, 7458), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14136PolyExtStep::Mul(3970, 8772), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14137PolyExtStep::Mul(8773, 7522), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14138PolyExtStep::Add(8771, 8774), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14139PolyExtStep::Sub(1, 3970), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14140PolyExtStep::Mul(8776, 7458), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14141PolyExtStep::Mul(8777, 7522), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14142PolyExtStep::Add(8775, 8778), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14143PolyExtStep::Mul(8769, 7522), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14144PolyExtStep::Add(8779, 8780), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14145PolyExtStep::Mul(3971, 7459), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14146PolyExtStep::Sub(1, 7523), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14147PolyExtStep::Mul(8782, 8783), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14148PolyExtStep::Sub(1, 7459), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14149PolyExtStep::Mul(3971, 8785), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14150PolyExtStep::Mul(8786, 7523), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14151PolyExtStep::Add(8784, 8787), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14152PolyExtStep::Sub(1, 3971), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14153PolyExtStep::Mul(8789, 7459), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14154PolyExtStep::Mul(8790, 7523), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14155PolyExtStep::Add(8788, 8791), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14156PolyExtStep::Mul(8782, 7523), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14157PolyExtStep::Add(8792, 8793), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14158PolyExtStep::Mul(3972, 7460), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14159PolyExtStep::Sub(1, 7524), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14160PolyExtStep::Mul(8795, 8796), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14161PolyExtStep::Sub(1, 7460), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14162PolyExtStep::Mul(3972, 8798), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14163PolyExtStep::Mul(8799, 7524), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14164PolyExtStep::Add(8797, 8800), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14165PolyExtStep::Sub(1, 3972), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14166PolyExtStep::Mul(8802, 7460), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14167PolyExtStep::Mul(8803, 7524), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14168PolyExtStep::Add(8801, 8804), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14169PolyExtStep::Mul(8795, 7524), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14170PolyExtStep::Add(8805, 8806), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14171PolyExtStep::Mul(3973, 7461), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14172PolyExtStep::Sub(1, 7525), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14173PolyExtStep::Mul(8808, 8809), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14174PolyExtStep::Sub(1, 7461), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14175PolyExtStep::Mul(3973, 8811), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14176PolyExtStep::Mul(8812, 7525), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14177PolyExtStep::Add(8810, 8813), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14178PolyExtStep::Sub(1, 3973), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14179PolyExtStep::Mul(8815, 7461), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14180PolyExtStep::Mul(8816, 7525), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14181PolyExtStep::Add(8814, 8817), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14182PolyExtStep::Mul(8808, 7525), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14183PolyExtStep::Add(8818, 8819), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14184PolyExtStep::Mul(3974, 7462), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14185PolyExtStep::Sub(1, 7526), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14186PolyExtStep::Mul(8821, 8822), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14187PolyExtStep::Sub(1, 7462), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14188PolyExtStep::Mul(3974, 8824), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14189PolyExtStep::Mul(8825, 7526), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14190PolyExtStep::Add(8823, 8826), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14191PolyExtStep::Sub(1, 3974), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14192PolyExtStep::Mul(8828, 7462), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14193PolyExtStep::Mul(8829, 7526), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14194PolyExtStep::Add(8827, 8830), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14195PolyExtStep::Mul(8821, 7526), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14196PolyExtStep::Add(8831, 8832), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14197PolyExtStep::Mul(3975, 7463), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14198PolyExtStep::Sub(1, 7527), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14199PolyExtStep::Mul(8834, 8835), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14200PolyExtStep::Sub(1, 7463), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14201PolyExtStep::Mul(3975, 8837), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14202PolyExtStep::Mul(8838, 7527), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14203PolyExtStep::Add(8836, 8839), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14204PolyExtStep::Sub(1, 3975), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14205PolyExtStep::Mul(8841, 7463), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14206PolyExtStep::Mul(8842, 7527), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14207PolyExtStep::Add(8840, 8843), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14208PolyExtStep::Mul(8834, 7527), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14209PolyExtStep::Add(8844, 8845), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14210PolyExtStep::Mul(3976, 7464), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14211PolyExtStep::Sub(1, 7528), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14212PolyExtStep::Mul(8847, 8848), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14213PolyExtStep::Sub(1, 7464), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14214PolyExtStep::Mul(3976, 8850), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14215PolyExtStep::Mul(8851, 7528), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14216PolyExtStep::Add(8849, 8852), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14217PolyExtStep::Sub(1, 3976), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14218PolyExtStep::Mul(8854, 7464), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14219PolyExtStep::Mul(8855, 7528), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14220PolyExtStep::Add(8853, 8856), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14221PolyExtStep::Mul(8847, 7528), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14222PolyExtStep::Add(8857, 8858), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14223PolyExtStep::Mul(3984, 7465), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14224PolyExtStep::Sub(1, 7529), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14225PolyExtStep::Mul(8860, 8861), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14226PolyExtStep::Sub(1, 7465), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14227PolyExtStep::Mul(3984, 8863), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14228PolyExtStep::Mul(8864, 7529), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14229PolyExtStep::Add(8862, 8865), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14230PolyExtStep::Sub(1, 3984), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14231PolyExtStep::Mul(8867, 7465), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14232PolyExtStep::Mul(8868, 7529), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14233PolyExtStep::Add(8866, 8869), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14234PolyExtStep::Mul(8860, 7529), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14235PolyExtStep::Add(8870, 8871), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14236PolyExtStep::Mul(3981, 7466), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14237PolyExtStep::Sub(1, 7530), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14238PolyExtStep::Mul(8873, 8874), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14239PolyExtStep::Sub(1, 7466), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14240PolyExtStep::Mul(3981, 8876), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14241PolyExtStep::Mul(8877, 7530), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14242PolyExtStep::Add(8875, 8878), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14243PolyExtStep::Sub(1, 3981), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14244PolyExtStep::Mul(8880, 7466), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14245PolyExtStep::Mul(8881, 7530), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14246PolyExtStep::Add(8879, 8882), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14247PolyExtStep::Mul(8873, 7530), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14248PolyExtStep::Add(8883, 8884), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14249PolyExtStep::Mul(3978, 7467), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14250PolyExtStep::Sub(1, 7531), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14251PolyExtStep::Mul(8886, 8887), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14252PolyExtStep::Sub(1, 7467), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14253PolyExtStep::Mul(3978, 8889), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14254PolyExtStep::Mul(8890, 7531), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14255PolyExtStep::Add(8888, 8891), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14256PolyExtStep::Sub(1, 3978), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14257PolyExtStep::Mul(8893, 7467), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14258PolyExtStep::Mul(8894, 7531), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14259PolyExtStep::Add(8892, 8895), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14260PolyExtStep::Mul(8886, 7531), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14261PolyExtStep::Add(8896, 8897), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14262PolyExtStep::Mul(3977, 7468), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14263PolyExtStep::Sub(1, 7532), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14264PolyExtStep::Mul(8899, 8900), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14265PolyExtStep::Sub(1, 7468), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14266PolyExtStep::Mul(3977, 8902), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14267PolyExtStep::Mul(8903, 7532), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14268PolyExtStep::Add(8901, 8904), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14269PolyExtStep::Sub(1, 3977), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14270PolyExtStep::Mul(8906, 7468), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14271PolyExtStep::Mul(8907, 7532), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14272PolyExtStep::Add(8905, 8908), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14273PolyExtStep::Mul(8899, 7532), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14274PolyExtStep::Add(8909, 8910), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14275PolyExtStep::Mul(8521, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14276PolyExtStep::Mul(8534, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14277PolyExtStep::Mul(8547, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14278PolyExtStep::Mul(8560, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14279PolyExtStep::Mul(8573, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14280PolyExtStep::Mul(8586, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14281PolyExtStep::Mul(8599, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14282PolyExtStep::Mul(8612, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14283PolyExtStep::Mul(8625, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14284PolyExtStep::Mul(8638, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14285PolyExtStep::Mul(8651, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14286PolyExtStep::Mul(8664, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14287PolyExtStep::Mul(8677, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14288PolyExtStep::Mul(8690, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14289PolyExtStep::Mul(8703, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14290PolyExtStep::Add(8508, 8912), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14291PolyExtStep::Add(8927, 8913), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14292PolyExtStep::Add(8928, 8914), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14293PolyExtStep::Add(8929, 8915), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14294PolyExtStep::Add(8930, 8916), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14295PolyExtStep::Add(8931, 8917), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14296PolyExtStep::Add(8932, 8918), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14297PolyExtStep::Add(8933, 8919), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14298PolyExtStep::Add(8934, 8920), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14299PolyExtStep::Add(8935, 8921), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14300PolyExtStep::Add(8936, 8922), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14301PolyExtStep::Add(8937, 8923), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14302PolyExtStep::Add(8938, 8924), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14303PolyExtStep::Add(8939, 8925), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14304PolyExtStep::Add(8940, 8926), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14305PolyExtStep::Mul(8729, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14306PolyExtStep::Mul(8742, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14307PolyExtStep::Mul(8755, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14308PolyExtStep::Mul(8768, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14309PolyExtStep::Mul(8781, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14310PolyExtStep::Mul(8794, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14311PolyExtStep::Mul(8807, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14312PolyExtStep::Mul(8820, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14313PolyExtStep::Mul(8833, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14314PolyExtStep::Mul(8846, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14315PolyExtStep::Mul(8859, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14316PolyExtStep::Mul(8872, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14317PolyExtStep::Mul(8885, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14318PolyExtStep::Mul(8898, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14319PolyExtStep::Mul(8911, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14320PolyExtStep::Add(8716, 8942), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14321PolyExtStep::Add(8957, 8943), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14322PolyExtStep::Add(8958, 8944), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14323PolyExtStep::Add(8959, 8945), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14324PolyExtStep::Add(8960, 8946), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14325PolyExtStep::Add(8961, 8947), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14326PolyExtStep::Add(8962, 8948), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14327PolyExtStep::Add(8963, 8949), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14328PolyExtStep::Add(8964, 8950), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14329PolyExtStep::Add(8965, 8951), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14330PolyExtStep::Add(8966, 8952), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14331PolyExtStep::Add(8967, 8953), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14332PolyExtStep::Add(8968, 8954), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14333PolyExtStep::Add(8969, 8955), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14334PolyExtStep::Add(8970, 8956), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14335PolyExtStep::Mul(7834, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14336PolyExtStep::Mul(7837, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14337PolyExtStep::Mul(7840, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14338PolyExtStep::Mul(7843, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14339PolyExtStep::Mul(7846, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14340PolyExtStep::Mul(7849, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14341PolyExtStep::Mul(7852, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14342PolyExtStep::Mul(7855, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14343PolyExtStep::Mul(7858, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14344PolyExtStep::Mul(7861, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14345PolyExtStep::Mul(7864, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14346PolyExtStep::Mul(7867, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14347PolyExtStep::Mul(7870, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14348PolyExtStep::Mul(7873, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14349PolyExtStep::Mul(7876, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14350PolyExtStep::Add(7831, 8972), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14351PolyExtStep::Add(8987, 8973), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14352PolyExtStep::Add(8988, 8974), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14353PolyExtStep::Add(8989, 8975), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14354PolyExtStep::Add(8990, 8976), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14355PolyExtStep::Add(8991, 8977), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14356PolyExtStep::Add(8992, 8978), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14357PolyExtStep::Add(8993, 8979), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14358PolyExtStep::Add(8994, 8980), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14359PolyExtStep::Add(8995, 8981), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14360PolyExtStep::Add(8996, 8982), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14361PolyExtStep::Add(8997, 8983), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14362PolyExtStep::Add(8998, 8984), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14363PolyExtStep::Add(8999, 8985), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14364PolyExtStep::Add(9000, 8986), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14365PolyExtStep::Mul(7882, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14366PolyExtStep::Mul(7885, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14367PolyExtStep::Mul(7888, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14368PolyExtStep::Mul(7891, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14369PolyExtStep::Mul(7894, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14370PolyExtStep::Mul(7897, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14371PolyExtStep::Mul(7900, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14372PolyExtStep::Mul(7903, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14373PolyExtStep::Mul(7906, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14374PolyExtStep::Mul(7909, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14375PolyExtStep::Mul(7912, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14376PolyExtStep::Mul(7915, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14377PolyExtStep::Mul(7918, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14378PolyExtStep::Mul(7921, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14379PolyExtStep::Mul(7924, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14380PolyExtStep::Add(7879, 9002), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14381PolyExtStep::Add(9017, 9003), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14382PolyExtStep::Add(9018, 9004), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14383PolyExtStep::Add(9019, 9005), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14384PolyExtStep::Add(9020, 9006), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14385PolyExtStep::Add(9021, 9007), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14386PolyExtStep::Add(9022, 9008), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14387PolyExtStep::Add(9023, 9009), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14388PolyExtStep::Add(9024, 9010), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14389PolyExtStep::Add(9025, 9011), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14390PolyExtStep::Add(9026, 9012), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14391PolyExtStep::Add(9027, 9013), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14392PolyExtStep::Add(9028, 9014), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14393PolyExtStep::Add(9029, 9015), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14394PolyExtStep::Add(9030, 9016), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14395PolyExtStep::Add(8941, 9001), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14396PolyExtStep::Add(8971, 9031), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14397PolyExtStep::Add(8494, 9032), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14398PolyExtStep::Add(8495, 9033), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14399PolyExtStep::Mul(7566, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14400PolyExtStep::Mul(7567, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14401PolyExtStep::Mul(7568, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14402PolyExtStep::Mul(7569, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14403PolyExtStep::Mul(7570, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14404PolyExtStep::Mul(7571, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14405PolyExtStep::Mul(7572, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14406PolyExtStep::Mul(7573, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14407PolyExtStep::Mul(7574, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14408PolyExtStep::Mul(7575, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14409PolyExtStep::Mul(7576, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14410PolyExtStep::Mul(7577, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14411PolyExtStep::Mul(7578, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14412PolyExtStep::Mul(7579, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14413PolyExtStep::Mul(7580, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14414PolyExtStep::Add(7565, 9036), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14415PolyExtStep::Add(9051, 9037), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14416PolyExtStep::Add(9052, 9038), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14417PolyExtStep::Add(9053, 9039), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14418PolyExtStep::Add(9054, 9040), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14419PolyExtStep::Add(9055, 9041), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14420PolyExtStep::Add(9056, 9042), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14421PolyExtStep::Add(9057, 9043), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14422PolyExtStep::Add(9058, 9044), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14423PolyExtStep::Add(9059, 9045), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14424PolyExtStep::Add(9060, 9046), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14425PolyExtStep::Add(9061, 9047), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14426PolyExtStep::Add(9062, 9048), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14427PolyExtStep::Add(9063, 9049), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14428PolyExtStep::Add(9064, 9050), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14429PolyExtStep::Mul(7582, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14430PolyExtStep::Mul(7583, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14431PolyExtStep::Mul(7584, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14432PolyExtStep::Mul(7585, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14433PolyExtStep::Mul(7586, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14434PolyExtStep::Mul(7587, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14435PolyExtStep::Mul(7588, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14436PolyExtStep::Mul(7589, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14437PolyExtStep::Mul(7590, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14438PolyExtStep::Mul(7591, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14439PolyExtStep::Mul(7592, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14440PolyExtStep::Mul(7593, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14441PolyExtStep::Mul(7594, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14442PolyExtStep::Mul(7595, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14443PolyExtStep::Mul(7596, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14444PolyExtStep::Add(7581, 9066), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14445PolyExtStep::Add(9081, 9067), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14446PolyExtStep::Add(9082, 9068), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14447PolyExtStep::Add(9083, 9069), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14448PolyExtStep::Add(9084, 9070), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14449PolyExtStep::Add(9085, 9071), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14450PolyExtStep::Add(9086, 9072), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14451PolyExtStep::Add(9087, 9073), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14452PolyExtStep::Add(9088, 9074), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14453PolyExtStep::Add(9089, 9075), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14454PolyExtStep::Add(9090, 9076), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14455PolyExtStep::Add(9091, 9077), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14456PolyExtStep::Add(9092, 9078), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14457PolyExtStep::Add(9093, 9079), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14458PolyExtStep::Add(9094, 9080), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14459PolyExtStep::Add(8494, 9065), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14460PolyExtStep::Add(8495, 9095), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14461PolyExtStep::AndEqz(5335, 7228), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14462PolyExtStep::Sub(1, 2667), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
14463PolyExtStep::Mul(2667, 9098), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
14464PolyExtStep::AndEqz(5336, 9099), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14465PolyExtStep::Sub(1, 2672), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
14466PolyExtStep::Mul(2672, 9100), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
14467PolyExtStep::AndEqz(5337, 9101), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14468PolyExtStep::Mul(2672, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14469PolyExtStep::Mul(2667, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14470PolyExtStep::Add(9102, 9103), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14471PolyExtStep::Add(9104, 2666), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14472PolyExtStep::Mul(9105, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14473PolyExtStep::Sub(9034, 9106), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14474PolyExtStep::Add(9035, 9105), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14475PolyExtStep::AndEqz(5338, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14476PolyExtStep::AndEqz(5339, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14477PolyExtStep::AndEqz(5340, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14478PolyExtStep::Mul(2682, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14479PolyExtStep::Mul(2675, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14480PolyExtStep::Add(9109, 9110), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14481PolyExtStep::Add(9111, 2673), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14482PolyExtStep::Mul(9112, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14483PolyExtStep::Sub(9108, 9113), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14484PolyExtStep::AndEqz(5341, 7315), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14485PolyExtStep::AndEqz(5342, 7317), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14486PolyExtStep::AndEqz(5343, 7318), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14487PolyExtStep::AndEqz(5344, 7319), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14488PolyExtStep::AndEqz(5345, 7321), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14489PolyExtStep::AndEqz(5346, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14490PolyExtStep::AndEqz(5347, 2720), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14491PolyExtStep::AndEqz(5348, 2726), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14492PolyExtStep::AndEqz(5349, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14493PolyExtStep::AndEqz(5350, 2736), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14494PolyExtStep::AndEqz(5351, 2742), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14495PolyExtStep::AndEqz(5352, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14496PolyExtStep::AndEqz(5353, 2748), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14497PolyExtStep::AndEqz(5354, 2754), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14498PolyExtStep::AndEqz(5355, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14499PolyExtStep::AndEqz(5356, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14500PolyExtStep::AndEqz(5357, 2760), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14501PolyExtStep::AndEqz(5358, 2766), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14502PolyExtStep::AndEqz(5359, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14503PolyExtStep::AndEqz(5360, 2778), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14504PolyExtStep::AndEqz(5361, 7323), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14505PolyExtStep::AndEqz(5362, 2694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14506PolyExtStep::AndEqz(5363, 7325), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14507PolyExtStep::AndEqz(5364, 7327), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14508PolyExtStep::AndEqz(5365, 2702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14509PolyExtStep::AndEqz(5366, 7329), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14510PolyExtStep::AndEqz(5367, 7331), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14511PolyExtStep::AndEqz(5368, 7333), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14512PolyExtStep::AndEqz(5369, 7335), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14513PolyExtStep::AndEqz(5370, 7337), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14514PolyExtStep::AndEqz(5371, 7339), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14515PolyExtStep::AndEqz(5372, 7341), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14516PolyExtStep::Mul(1359, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14517PolyExtStep::Mul(1360, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14518PolyExtStep::Mul(1362, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14519PolyExtStep::Mul(1369, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14520PolyExtStep::Mul(1370, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14521PolyExtStep::Mul(1372, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14522PolyExtStep::Mul(1378, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14523PolyExtStep::Add(7272, 1758), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14524PolyExtStep::Add(9122, 9115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14525PolyExtStep::Add(9123, 9116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14526PolyExtStep::Add(9124, 9117), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14527PolyExtStep::Add(9125, 9118), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14528PolyExtStep::Add(9126, 9119), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14529PolyExtStep::Add(9127, 9120), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14530PolyExtStep::Add(9128, 9121), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14531PolyExtStep::Mul(1398, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14532PolyExtStep::Mul(1399, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14533PolyExtStep::Mul(1400, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14534PolyExtStep::Mul(1406, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14535PolyExtStep::Mul(1407, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14536PolyExtStep::Mul(1844, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14537PolyExtStep::Mul(535, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14538PolyExtStep::Mul(2207, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14539PolyExtStep::Add(7300, 9130), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14540PolyExtStep::Add(9138, 9131), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14541PolyExtStep::Add(9139, 9132), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14542PolyExtStep::Add(9140, 9133), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14543PolyExtStep::Add(9141, 9134), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14544PolyExtStep::Add(9142, 9135), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14545PolyExtStep::Add(9143, 9136), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14546PolyExtStep::Add(9144, 9137), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14547PolyExtStep::Sub(9129, 9107), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14548PolyExtStep::AndEqz(5373, 9146), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14549PolyExtStep::Sub(9145, 9114), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14550PolyExtStep::AndEqz(5374, 9147), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14551PolyExtStep::AndEqz(5375, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14552PolyExtStep::AndEqz(5376, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14553PolyExtStep::AndEqz(5377, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14554PolyExtStep::Mul(3852, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14555PolyExtStep::Add(9148, 4721), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14556PolyExtStep::Add(9149, 2683), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14557PolyExtStep::Mul(9150, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14558PolyExtStep::Sub(9096, 9151), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14559PolyExtStep::Add(9097, 9150), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14560PolyExtStep::AndEqz(5378, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14561PolyExtStep::AndEqz(5379, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14562PolyExtStep::AndEqz(5380, 4702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14563PolyExtStep::Mul(4699, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14564PolyExtStep::Mul(3751, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14565PolyExtStep::Add(9154, 9155), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14566PolyExtStep::Add(9156, 3750), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14567PolyExtStep::Mul(9157, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14568PolyExtStep::Sub(9153, 9158), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14569PolyExtStep::AndEqz(5381, 7399), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14570PolyExtStep::AndEqz(5382, 589), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14571PolyExtStep::AndEqz(5383, 592), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14572PolyExtStep::AndEqz(5384, 599), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14573PolyExtStep::AndEqz(5385, 606), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14574PolyExtStep::AndEqz(5386, 613), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14575PolyExtStep::AndEqz(5387, 620), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14576PolyExtStep::AndEqz(5388, 627), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14577PolyExtStep::AndEqz(5389, 630), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14578PolyExtStep::AndEqz(5390, 637), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14579PolyExtStep::AndEqz(5391, 644), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14580PolyExtStep::AndEqz(5392, 647), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14581PolyExtStep::AndEqz(5393, 650), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14582PolyExtStep::AndEqz(5394, 657), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14583PolyExtStep::AndEqz(5395, 664), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14584PolyExtStep::AndEqz(5396, 671), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14585PolyExtStep::AndEqz(5397, 1645), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14586PolyExtStep::AndEqz(5398, 543), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14587PolyExtStep::AndEqz(5399, 7401), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14588PolyExtStep::AndEqz(5400, 1601), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14589PolyExtStep::AndEqz(5401, 555), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14590PolyExtStep::AndEqz(5402, 2848), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14591PolyExtStep::AndEqz(5403, 1609), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14592PolyExtStep::AndEqz(5404, 2036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14593PolyExtStep::AndEqz(5405, 2038), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14594PolyExtStep::AndEqz(5406, 2044), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14595PolyExtStep::AndEqz(5407, 2050), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14596PolyExtStep::AndEqz(5408, 2056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14597PolyExtStep::AndEqz(5409, 2062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14598PolyExtStep::AndEqz(5410, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14599PolyExtStep::AndEqz(5411, 2070), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14600PolyExtStep::AndEqz(5412, 2076), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14601PolyExtStep::Mul(628, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14602PolyExtStep::Mul(635, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14603PolyExtStep::Mul(642, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14604PolyExtStep::Mul(645, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14605PolyExtStep::Mul(655, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14606PolyExtStep::Mul(662, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14607PolyExtStep::Mul(669, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14608PolyExtStep::Add(7359, 9160), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14609PolyExtStep::Add(9167, 9161), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14610PolyExtStep::Add(9168, 9162), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14611PolyExtStep::Add(9169, 9163), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14612PolyExtStep::Add(9170, 693), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14613PolyExtStep::Add(9171, 9164), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14614PolyExtStep::Add(9172, 9165), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14615PolyExtStep::Add(9173, 9166), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14616PolyExtStep::Mul(568, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14617PolyExtStep::Mul(567, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14618PolyExtStep::Mul(569, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14619PolyExtStep::Mul(570, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14620PolyExtStep::Mul(571, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14621PolyExtStep::Mul(572, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14622PolyExtStep::Mul(573, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14623PolyExtStep::Mul(574, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14624PolyExtStep::Add(7384, 9175), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14625PolyExtStep::Add(9183, 9176), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14626PolyExtStep::Add(9184, 9177), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14627PolyExtStep::Add(9185, 9178), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14628PolyExtStep::Add(9186, 9179), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14629PolyExtStep::Add(9187, 9180), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14630PolyExtStep::Add(9188, 9181), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14631PolyExtStep::Add(9189, 9182), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14632PolyExtStep::Sub(9174, 9152), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14633PolyExtStep::AndEqz(5413, 9191), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14634PolyExtStep::Sub(9190, 9159), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14635PolyExtStep::AndEqz(5414, 9192), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14636PolyExtStep::Mul(2659, 51), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14637PolyExtStep::Mul(7221, 313), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14638PolyExtStep::Add(9193, 9194), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14639PolyExtStep::AndEqz(5415, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14640PolyExtStep::AndEqz(5416, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14641PolyExtStep::Sub(4571, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14642PolyExtStep::AndEqz(5417, 9196), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14643PolyExtStep::AndEqz(5418, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14644PolyExtStep::AndEqz(5419, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14645PolyExtStep::AndEqz(5420, 7257), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14646PolyExtStep::Sub(9195, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14647PolyExtStep::AndEqz(5421, 9197), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14648PolyExtStep::AndEqz(5422, 882), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14649PolyExtStep::AndEqz(5423, 897), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14650PolyExtStep::AndEqz(5424, 940), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14651PolyExtStep::AndEqz(5425, 955), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14652PolyExtStep::AndEqz(5426, 967), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14653PolyExtStep::AndEqz(5427, 982), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14654PolyExtStep::AndEqz(5428, 1037), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14655PolyExtStep::AndEqz(5429, 1043), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14656PolyExtStep::AndEqz(5430, 1049), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14657PolyExtStep::AndCond(5280, 380, 5431), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14658PolyExtStep::Get(552), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14659PolyExtStep::Get(557), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14660PolyExtStep::Get(562), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14661PolyExtStep::Get(567), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14662PolyExtStep::Get(572), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14663PolyExtStep::Get(577), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14664PolyExtStep::Get(582), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14665PolyExtStep::Get(587), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14666PolyExtStep::Get(592), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14667PolyExtStep::Get(597), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14668PolyExtStep::Get(602), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14669PolyExtStep::Get(607), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14670PolyExtStep::Get(612), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14671PolyExtStep::Get(617), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14672PolyExtStep::Get(622), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14673PolyExtStep::Get(627), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14674PolyExtStep::Get(632), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14675PolyExtStep::Get(637), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14676PolyExtStep::Get(642), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14677PolyExtStep::Get(647), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14678PolyExtStep::Get(652), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14679PolyExtStep::Get(657), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14680PolyExtStep::Get(662), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14681PolyExtStep::Get(667), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14682PolyExtStep::Get(672), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14683PolyExtStep::Get(677), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14684PolyExtStep::Get(682), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14685PolyExtStep::Get(687), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14686PolyExtStep::Get(692), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14687PolyExtStep::Get(697), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14688PolyExtStep::Get(702), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14689PolyExtStep::Get(707), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14690PolyExtStep::Get(553), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14691PolyExtStep::Get(558), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14692PolyExtStep::Get(563), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14693PolyExtStep::Get(568), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14694PolyExtStep::Get(573), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14695PolyExtStep::Get(578), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14696PolyExtStep::Get(583), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14697PolyExtStep::Get(588), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14698PolyExtStep::Get(593), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14699PolyExtStep::Get(598), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14700PolyExtStep::Get(603), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14701PolyExtStep::Get(608), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14702PolyExtStep::Get(613), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14703PolyExtStep::Get(618), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14704PolyExtStep::Get(623), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14705PolyExtStep::Get(628), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14706PolyExtStep::Get(633), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14707PolyExtStep::Get(638), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14708PolyExtStep::Get(643), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14709PolyExtStep::Get(648), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14710PolyExtStep::Get(653), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14711PolyExtStep::Get(658), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14712PolyExtStep::Get(663), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14713PolyExtStep::Get(668), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14714PolyExtStep::Get(673), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14715PolyExtStep::Get(678), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14716PolyExtStep::Get(683), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14717PolyExtStep::Get(688), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14718PolyExtStep::Get(693), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14719PolyExtStep::Get(698), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14720PolyExtStep::Get(703), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14721PolyExtStep::Get(708), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14722PolyExtStep::Get(554), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14723PolyExtStep::Get(559), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14724PolyExtStep::Get(564), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14725PolyExtStep::Get(569), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14726PolyExtStep::Get(574), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14727PolyExtStep::Get(579), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14728PolyExtStep::Get(584), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14729PolyExtStep::Get(589), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14730PolyExtStep::Get(594), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14731PolyExtStep::Get(599), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14732PolyExtStep::Get(604), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14733PolyExtStep::Get(609), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14734PolyExtStep::Get(614), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14735PolyExtStep::Get(619), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14736PolyExtStep::Get(624), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14737PolyExtStep::Get(629), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14738PolyExtStep::Get(634), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14739PolyExtStep::Get(639), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14740PolyExtStep::Get(644), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14741PolyExtStep::Get(649), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14742PolyExtStep::Get(654), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14743PolyExtStep::Get(659), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14744PolyExtStep::Get(664), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14745PolyExtStep::Get(669), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14746PolyExtStep::Get(674), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14747PolyExtStep::Get(679), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14748PolyExtStep::Get(684), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14749PolyExtStep::Get(689), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14750PolyExtStep::Get(694), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14751PolyExtStep::Get(699), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14752PolyExtStep::Get(704), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14753PolyExtStep::Get(709), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14754PolyExtStep::Get(555), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14755PolyExtStep::Get(560), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14756PolyExtStep::Get(565), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14757PolyExtStep::Get(570), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14758PolyExtStep::Get(575), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14759PolyExtStep::Get(580), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14760PolyExtStep::Get(585), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14761PolyExtStep::Get(590), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14762PolyExtStep::Get(595), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14763PolyExtStep::Get(600), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14764PolyExtStep::Get(605), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14765PolyExtStep::Get(610), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14766PolyExtStep::Get(615), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14767PolyExtStep::Get(620), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14768PolyExtStep::Get(625), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14769PolyExtStep::Get(630), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14770PolyExtStep::Get(635), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14771PolyExtStep::Get(640), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14772PolyExtStep::Get(645), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14773PolyExtStep::Get(650), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14774PolyExtStep::Get(655), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14775PolyExtStep::Get(660), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14776PolyExtStep::Get(665), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14777PolyExtStep::Get(670), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14778PolyExtStep::Get(675), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14779PolyExtStep::Get(680), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14780PolyExtStep::Get(685), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14781PolyExtStep::Get(690), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14782PolyExtStep::Get(695), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14783PolyExtStep::Get(700), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14784PolyExtStep::Get(705), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14785PolyExtStep::Get(710), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14786PolyExtStep::Sub(314, 3879), // loc(callsite( builtin Sub at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14787PolyExtStep::Mul(9326, 2660), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14788PolyExtStep::Sub(9327, 7221), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14789PolyExtStep::AndEqz(5126, 9328), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14790PolyExtStep::Mul(2659, 9326), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14791PolyExtStep::AndEqz(5433, 9329), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14792PolyExtStep::AndEqz(5434, 7226), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14793PolyExtStep::Add(3878, 23), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14794PolyExtStep::Add(9330, 3879), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:40) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14795PolyExtStep::AndEqz(5435, 7165), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14796PolyExtStep::AndEqz(5436, 3732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14797PolyExtStep::AndEqz(5437, 7166), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14798PolyExtStep::AndEqz(5438, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14799PolyExtStep::Sub(800, 9331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14800PolyExtStep::AndEqz(5439, 9332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14801PolyExtStep::AndEqz(5440, 3930), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14802PolyExtStep::AndEqz(5441, 7168), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14803PolyExtStep::AndEqz(5442, 4667), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14804PolyExtStep::AndEqz(5443, 7170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14805PolyExtStep::Add(9280, 9265), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14806PolyExtStep::Mul(9280, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14807PolyExtStep::Mul(9334, 9265), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14808PolyExtStep::Sub(9333, 9335), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14809PolyExtStep::Add(9281, 9266), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14810PolyExtStep::Mul(9281, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14811PolyExtStep::Mul(9338, 9266), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14812PolyExtStep::Sub(9337, 9339), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14813PolyExtStep::Add(9282, 9267), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14814PolyExtStep::Mul(9282, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14815PolyExtStep::Mul(9342, 9267), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14816PolyExtStep::Sub(9341, 9343), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14817PolyExtStep::Add(9283, 9268), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14818PolyExtStep::Mul(9283, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14819PolyExtStep::Mul(9346, 9268), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14820PolyExtStep::Sub(9345, 9347), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14821PolyExtStep::Add(9284, 9269), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14822PolyExtStep::Mul(9284, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14823PolyExtStep::Mul(9350, 9269), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14824PolyExtStep::Sub(9349, 9351), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14825PolyExtStep::Add(9285, 9270), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14826PolyExtStep::Mul(9285, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14827PolyExtStep::Mul(9354, 9270), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14828PolyExtStep::Sub(9353, 9355), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14829PolyExtStep::Add(9286, 9271), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14830PolyExtStep::Mul(9286, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14831PolyExtStep::Mul(9358, 9271), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14832PolyExtStep::Sub(9357, 9359), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14833PolyExtStep::Add(9287, 9272), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14834PolyExtStep::Mul(9287, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14835PolyExtStep::Mul(9362, 9272), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14836PolyExtStep::Sub(9361, 9363), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14837PolyExtStep::Add(9288, 9273), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14838PolyExtStep::Mul(9288, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14839PolyExtStep::Mul(9366, 9273), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14840PolyExtStep::Sub(9365, 9367), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14841PolyExtStep::Add(9289, 9274), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14842PolyExtStep::Mul(9289, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14843PolyExtStep::Mul(9370, 9274), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14844PolyExtStep::Sub(9369, 9371), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14845PolyExtStep::Add(9290, 9275), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14846PolyExtStep::Mul(9290, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14847PolyExtStep::Mul(9374, 9275), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14848PolyExtStep::Sub(9373, 9375), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14849PolyExtStep::Add(9291, 9276), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14850PolyExtStep::Mul(9291, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14851PolyExtStep::Mul(9378, 9276), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14852PolyExtStep::Sub(9377, 9379), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14853PolyExtStep::Add(9292, 9277), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14854PolyExtStep::Mul(9292, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14855PolyExtStep::Mul(9382, 9277), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14856PolyExtStep::Sub(9381, 9383), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14857PolyExtStep::Add(9293, 9278), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14858PolyExtStep::Mul(9293, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14859PolyExtStep::Mul(9386, 9278), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14860PolyExtStep::Sub(9385, 9387), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14861PolyExtStep::Add(9262, 9279), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14862PolyExtStep::Mul(9262, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14863PolyExtStep::Mul(9390, 9279), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14864PolyExtStep::Sub(9389, 9391), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14865PolyExtStep::Add(9263, 9280), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14866PolyExtStep::Mul(9263, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14867PolyExtStep::Mul(9394, 9280), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14868PolyExtStep::Sub(9393, 9395), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14869PolyExtStep::Add(9264, 9281), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14870PolyExtStep::Mul(9264, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14871PolyExtStep::Mul(9398, 9281), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14872PolyExtStep::Sub(9397, 9399), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14873PolyExtStep::Add(9265, 9282), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14874PolyExtStep::Mul(9265, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14875PolyExtStep::Mul(9402, 9282), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14876PolyExtStep::Sub(9401, 9403), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14877PolyExtStep::Add(9266, 9283), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14878PolyExtStep::Mul(9266, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14879PolyExtStep::Mul(9406, 9283), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14880PolyExtStep::Sub(9405, 9407), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14881PolyExtStep::Add(9267, 9284), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14882PolyExtStep::Mul(9267, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14883PolyExtStep::Mul(9410, 9284), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14884PolyExtStep::Sub(9409, 9411), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14885PolyExtStep::Add(9268, 9285), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14886PolyExtStep::Mul(9268, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14887PolyExtStep::Mul(9414, 9285), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14888PolyExtStep::Sub(9413, 9415), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14889PolyExtStep::Add(9269, 9286), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14890PolyExtStep::Mul(9269, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14891PolyExtStep::Mul(9418, 9286), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14892PolyExtStep::Sub(9417, 9419), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14893PolyExtStep::Add(9270, 9287), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14894PolyExtStep::Mul(9270, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14895PolyExtStep::Mul(9422, 9287), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14896PolyExtStep::Sub(9421, 9423), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14897PolyExtStep::Add(9271, 9288), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14898PolyExtStep::Mul(9271, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14899PolyExtStep::Mul(9426, 9288), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14900PolyExtStep::Sub(9425, 9427), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14901PolyExtStep::Add(9272, 9289), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14902PolyExtStep::Mul(9272, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14903PolyExtStep::Mul(9430, 9289), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14904PolyExtStep::Sub(9429, 9431), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14905PolyExtStep::Add(9273, 9290), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14906PolyExtStep::Mul(9273, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14907PolyExtStep::Mul(9434, 9290), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14908PolyExtStep::Sub(9433, 9435), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14909PolyExtStep::Add(9274, 9291), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14910PolyExtStep::Mul(9274, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14911PolyExtStep::Mul(9438, 9291), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14912PolyExtStep::Sub(9437, 9439), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14913PolyExtStep::Add(9275, 9292), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14914PolyExtStep::Mul(9275, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14915PolyExtStep::Mul(9442, 9292), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14916PolyExtStep::Sub(9441, 9443), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14917PolyExtStep::Add(9276, 9293), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14918PolyExtStep::Mul(9276, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14919PolyExtStep::Mul(9446, 9293), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14920PolyExtStep::Sub(9445, 9447), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14921PolyExtStep::Add(9269, 9336), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14922PolyExtStep::Mul(9418, 9336), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14923PolyExtStep::Sub(9449, 9450), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14924PolyExtStep::Add(9270, 9340), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14925PolyExtStep::Mul(9422, 9340), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14926PolyExtStep::Sub(9452, 9453), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14927PolyExtStep::Add(9271, 9344), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14928PolyExtStep::Mul(9426, 9344), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14929PolyExtStep::Sub(9455, 9456), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14930PolyExtStep::Add(9272, 9348), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14931PolyExtStep::Mul(9430, 9348), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14932PolyExtStep::Sub(9458, 9459), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14933PolyExtStep::Add(9273, 9352), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14934PolyExtStep::Mul(9434, 9352), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14935PolyExtStep::Sub(9461, 9462), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14936PolyExtStep::Add(9274, 9356), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14937PolyExtStep::Mul(9438, 9356), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14938PolyExtStep::Sub(9464, 9465), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14939PolyExtStep::Add(9275, 9360), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14940PolyExtStep::Mul(9442, 9360), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14941PolyExtStep::Sub(9467, 9468), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14942PolyExtStep::Add(9276, 9364), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14943PolyExtStep::Mul(9446, 9364), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14944PolyExtStep::Sub(9470, 9471), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14945PolyExtStep::Add(9277, 9368), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14946PolyExtStep::Mul(9277, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14947PolyExtStep::Mul(9474, 9368), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14948PolyExtStep::Sub(9473, 9475), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14949PolyExtStep::Add(9278, 9372), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14950PolyExtStep::Mul(9278, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14951PolyExtStep::Mul(9478, 9372), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14952PolyExtStep::Sub(9477, 9479), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14953PolyExtStep::Add(9279, 9376), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14954PolyExtStep::Mul(9279, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14955PolyExtStep::Mul(9482, 9376), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14956PolyExtStep::Sub(9481, 9483), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14957PolyExtStep::Add(9280, 9380), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14958PolyExtStep::Mul(9334, 9380), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14959PolyExtStep::Sub(9485, 9486), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14960PolyExtStep::Add(9281, 9384), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14961PolyExtStep::Mul(9338, 9384), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14962PolyExtStep::Sub(9488, 9489), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14963PolyExtStep::Add(9282, 9388), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14964PolyExtStep::Mul(9342, 9388), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14965PolyExtStep::Sub(9491, 9492), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14966PolyExtStep::Add(9283, 9392), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14967PolyExtStep::Mul(9346, 9392), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14968PolyExtStep::Sub(9494, 9495), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14969PolyExtStep::Add(9284, 9396), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14970PolyExtStep::Mul(9350, 9396), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14971PolyExtStep::Sub(9497, 9498), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14972PolyExtStep::Add(9285, 9400), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14973PolyExtStep::Mul(9354, 9400), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14974PolyExtStep::Sub(9500, 9501), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14975PolyExtStep::Add(9286, 9404), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14976PolyExtStep::Mul(9358, 9404), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14977PolyExtStep::Sub(9503, 9504), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14978PolyExtStep::Add(9287, 9408), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14979PolyExtStep::Mul(9362, 9408), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14980PolyExtStep::Sub(9506, 9507), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14981PolyExtStep::Add(9288, 9412), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14982PolyExtStep::Mul(9366, 9412), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14983PolyExtStep::Sub(9509, 9510), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14984PolyExtStep::Add(9289, 9416), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14985PolyExtStep::Mul(9370, 9416), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14986PolyExtStep::Sub(9512, 9513), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14987PolyExtStep::Add(9290, 9420), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14988PolyExtStep::Mul(9374, 9420), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14989PolyExtStep::Sub(9515, 9516), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14990PolyExtStep::Add(9291, 9424), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14991PolyExtStep::Mul(9378, 9424), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14992PolyExtStep::Sub(9518, 9519), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14993PolyExtStep::Add(9292, 9428), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14994PolyExtStep::Mul(9382, 9428), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14995PolyExtStep::Sub(9521, 9522), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14996PolyExtStep::Add(9293, 9432), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14997PolyExtStep::Mul(9386, 9432), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14998PolyExtStep::Sub(9524, 9525), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14999PolyExtStep::Add(9262, 9436), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15000PolyExtStep::Mul(9390, 9436), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15001PolyExtStep::Sub(9527, 9528), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15002PolyExtStep::Add(9263, 9440), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15003PolyExtStep::Mul(9394, 9440), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15004PolyExtStep::Sub(9530, 9531), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15005PolyExtStep::Add(9264, 9444), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15006PolyExtStep::Mul(9398, 9444), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15007PolyExtStep::Sub(9533, 9534), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15008PolyExtStep::Add(9265, 9448), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15009PolyExtStep::Mul(9402, 9448), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15010PolyExtStep::Sub(9536, 9537), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15011PolyExtStep::Add(9266, 9277), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15012PolyExtStep::Mul(9406, 9277), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15013PolyExtStep::Sub(9539, 9540), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15014PolyExtStep::Add(9267, 9278), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15015PolyExtStep::Mul(9410, 9278), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15016PolyExtStep::Sub(9542, 9543), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15017PolyExtStep::Add(9268, 9279), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15018PolyExtStep::Mul(9414, 9279), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15019PolyExtStep::Sub(9545, 9546), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15020PolyExtStep::Add(9217, 9208), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15021PolyExtStep::Mul(9217, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15022PolyExtStep::Mul(9549, 9208), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15023PolyExtStep::Sub(9548, 9550), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15024PolyExtStep::Add(9218, 9209), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15025PolyExtStep::Mul(9218, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15026PolyExtStep::Mul(9553, 9209), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15027PolyExtStep::Sub(9552, 9554), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15028PolyExtStep::Add(9219, 9210), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15029PolyExtStep::Mul(9219, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15030PolyExtStep::Mul(9557, 9210), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15031PolyExtStep::Sub(9556, 9558), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15032PolyExtStep::Add(9220, 9211), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15033PolyExtStep::Mul(9220, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15034PolyExtStep::Mul(9561, 9211), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15035PolyExtStep::Sub(9560, 9562), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15036PolyExtStep::Add(9221, 9212), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15037PolyExtStep::Mul(9221, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15038PolyExtStep::Mul(9565, 9212), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15039PolyExtStep::Sub(9564, 9566), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15040PolyExtStep::Add(9222, 9213), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15041PolyExtStep::Mul(9222, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15042PolyExtStep::Mul(9569, 9213), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15043PolyExtStep::Sub(9568, 9570), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15044PolyExtStep::Add(9223, 9214), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15045PolyExtStep::Mul(9223, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15046PolyExtStep::Mul(9573, 9214), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15047PolyExtStep::Sub(9572, 9574), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15048PolyExtStep::Add(9224, 9215), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15049PolyExtStep::Mul(9224, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15050PolyExtStep::Mul(9577, 9215), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15051PolyExtStep::Sub(9576, 9578), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15052PolyExtStep::Add(9225, 9216), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15053PolyExtStep::Mul(9225, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15054PolyExtStep::Mul(9581, 9216), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15055PolyExtStep::Sub(9580, 9582), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15056PolyExtStep::Add(9226, 9217), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15057PolyExtStep::Mul(9226, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15058PolyExtStep::Mul(9585, 9217), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15059PolyExtStep::Sub(9584, 9586), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15060PolyExtStep::Add(9227, 9218), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15061PolyExtStep::Mul(9227, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15062PolyExtStep::Mul(9589, 9218), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15063PolyExtStep::Sub(9588, 9590), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15064PolyExtStep::Add(9228, 9219), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15065PolyExtStep::Mul(9228, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15066PolyExtStep::Mul(9593, 9219), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15067PolyExtStep::Sub(9592, 9594), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15068PolyExtStep::Add(9229, 9220), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15069PolyExtStep::Mul(9229, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15070PolyExtStep::Mul(9597, 9220), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15071PolyExtStep::Sub(9596, 9598), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15072PolyExtStep::Add(9198, 9221), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15073PolyExtStep::Mul(9198, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15074PolyExtStep::Mul(9601, 9221), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15075PolyExtStep::Sub(9600, 9602), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15076PolyExtStep::Add(9199, 9222), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15077PolyExtStep::Mul(9199, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15078PolyExtStep::Mul(9605, 9222), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15079PolyExtStep::Sub(9604, 9606), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15080PolyExtStep::Add(9200, 9223), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15081PolyExtStep::Mul(9200, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15082PolyExtStep::Mul(9609, 9223), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15083PolyExtStep::Sub(9608, 9610), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15084PolyExtStep::Add(9201, 9224), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15085PolyExtStep::Mul(9201, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15086PolyExtStep::Mul(9613, 9224), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15087PolyExtStep::Sub(9612, 9614), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15088PolyExtStep::Add(9202, 9225), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15089PolyExtStep::Mul(9202, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15090PolyExtStep::Mul(9617, 9225), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15091PolyExtStep::Sub(9616, 9618), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15092PolyExtStep::Add(9203, 9226), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15093PolyExtStep::Mul(9203, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15094PolyExtStep::Mul(9621, 9226), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15095PolyExtStep::Sub(9620, 9622), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15096PolyExtStep::Add(9204, 9227), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15097PolyExtStep::Mul(9204, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15098PolyExtStep::Mul(9625, 9227), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15099PolyExtStep::Sub(9624, 9626), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15100PolyExtStep::Add(9205, 9228), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15101PolyExtStep::Mul(9205, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15102PolyExtStep::Mul(9629, 9228), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15103PolyExtStep::Sub(9628, 9630), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15104PolyExtStep::Add(9206, 9229), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15105PolyExtStep::Mul(9206, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15106PolyExtStep::Mul(9633, 9229), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15107PolyExtStep::Sub(9632, 9634), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15108PolyExtStep::Add(9215, 9551), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15109PolyExtStep::Mul(9215, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15110PolyExtStep::Mul(9637, 9551), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15111PolyExtStep::Sub(9636, 9638), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15112PolyExtStep::Add(9216, 9555), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15113PolyExtStep::Mul(9216, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15114PolyExtStep::Mul(9641, 9555), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15115PolyExtStep::Sub(9640, 9642), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15116PolyExtStep::Add(9217, 9559), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15117PolyExtStep::Mul(9549, 9559), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15118PolyExtStep::Sub(9644, 9645), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15119PolyExtStep::Add(9218, 9563), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15120PolyExtStep::Mul(9553, 9563), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15121PolyExtStep::Sub(9647, 9648), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15122PolyExtStep::Add(9219, 9567), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15123PolyExtStep::Mul(9557, 9567), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15124PolyExtStep::Sub(9650, 9651), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15125PolyExtStep::Add(9220, 9571), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15126PolyExtStep::Mul(9561, 9571), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15127PolyExtStep::Sub(9653, 9654), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15128PolyExtStep::Add(9221, 9575), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15129PolyExtStep::Mul(9565, 9575), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15130PolyExtStep::Sub(9656, 9657), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15131PolyExtStep::Add(9222, 9579), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15132PolyExtStep::Mul(9569, 9579), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15133PolyExtStep::Sub(9659, 9660), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15134PolyExtStep::Add(9223, 9583), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15135PolyExtStep::Mul(9573, 9583), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15136PolyExtStep::Sub(9662, 9663), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15137PolyExtStep::Add(9224, 9587), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15138PolyExtStep::Mul(9577, 9587), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15139PolyExtStep::Sub(9665, 9666), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15140PolyExtStep::Add(9225, 9591), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15141PolyExtStep::Mul(9581, 9591), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15142PolyExtStep::Sub(9668, 9669), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15143PolyExtStep::Add(9226, 9595), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15144PolyExtStep::Mul(9585, 9595), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15145PolyExtStep::Sub(9671, 9672), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15146PolyExtStep::Add(9227, 9599), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15147PolyExtStep::Mul(9589, 9599), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15148PolyExtStep::Sub(9674, 9675), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15149PolyExtStep::Add(9228, 9603), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15150PolyExtStep::Mul(9593, 9603), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15151PolyExtStep::Sub(9677, 9678), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15152PolyExtStep::Add(9229, 9607), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15153PolyExtStep::Mul(9597, 9607), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15154PolyExtStep::Sub(9680, 9681), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15155PolyExtStep::Add(9198, 9611), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15156PolyExtStep::Mul(9601, 9611), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15157PolyExtStep::Sub(9683, 9684), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15158PolyExtStep::Add(9199, 9615), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15159PolyExtStep::Mul(9605, 9615), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15160PolyExtStep::Sub(9686, 9687), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15161PolyExtStep::Add(9200, 9619), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15162PolyExtStep::Mul(9609, 9619), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15163PolyExtStep::Sub(9689, 9690), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15164PolyExtStep::Add(9201, 9623), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15165PolyExtStep::Mul(9613, 9623), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15166PolyExtStep::Sub(9692, 9693), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15167PolyExtStep::Add(9202, 9627), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15168PolyExtStep::Mul(9617, 9627), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15169PolyExtStep::Sub(9695, 9696), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15170PolyExtStep::Add(9203, 9631), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15171PolyExtStep::Mul(9621, 9631), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15172PolyExtStep::Sub(9698, 9699), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15173PolyExtStep::Add(9204, 9635), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15174PolyExtStep::Mul(9625, 9635), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15175PolyExtStep::Sub(9701, 9702), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15176PolyExtStep::Add(9205, 9207), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15177PolyExtStep::Mul(9629, 9207), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15178PolyExtStep::Sub(9704, 9705), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15179PolyExtStep::Add(9206, 9208), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15180PolyExtStep::Mul(9633, 9208), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15181PolyExtStep::Sub(9707, 9708), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15182PolyExtStep::Add(9207, 9209), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15183PolyExtStep::Mul(9207, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15184PolyExtStep::Mul(9711, 9209), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15185PolyExtStep::Sub(9710, 9712), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15186PolyExtStep::Add(9208, 9210), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15187PolyExtStep::Mul(9208, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15188PolyExtStep::Mul(9715, 9210), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15189PolyExtStep::Sub(9714, 9716), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15190PolyExtStep::Add(9209, 9211), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15191PolyExtStep::Mul(9209, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15192PolyExtStep::Mul(9719, 9211), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15193PolyExtStep::Sub(9718, 9720), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15194PolyExtStep::Add(9210, 9212), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15195PolyExtStep::Mul(9210, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15196PolyExtStep::Mul(9723, 9212), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15197PolyExtStep::Sub(9722, 9724), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15198PolyExtStep::Add(9211, 9213), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15199PolyExtStep::Mul(9211, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15200PolyExtStep::Mul(9727, 9213), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15201PolyExtStep::Sub(9726, 9728), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15202PolyExtStep::Add(9212, 9214), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15203PolyExtStep::Mul(9212, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15204PolyExtStep::Mul(9731, 9214), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15205PolyExtStep::Sub(9730, 9732), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15206PolyExtStep::Add(9213, 9215), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15207PolyExtStep::Mul(9213, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15208PolyExtStep::Mul(9735, 9215), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15209PolyExtStep::Sub(9734, 9736), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15210PolyExtStep::Add(9214, 9216), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15211PolyExtStep::Mul(9214, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15212PolyExtStep::Mul(9739, 9216), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15213PolyExtStep::Sub(9738, 9740), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15214PolyExtStep::Mul(9454, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15215PolyExtStep::Mul(9457, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15216PolyExtStep::Mul(9460, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15217PolyExtStep::Mul(9463, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15218PolyExtStep::Mul(9466, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15219PolyExtStep::Mul(9469, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15220PolyExtStep::Mul(9472, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15221PolyExtStep::Mul(9476, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15222PolyExtStep::Mul(9480, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15223PolyExtStep::Mul(9484, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15224PolyExtStep::Mul(9487, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15225PolyExtStep::Mul(9490, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15226PolyExtStep::Mul(9493, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15227PolyExtStep::Mul(9496, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15228PolyExtStep::Mul(9499, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15229PolyExtStep::Add(9451, 9742), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15230PolyExtStep::Add(9757, 9743), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15231PolyExtStep::Add(9758, 9744), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15232PolyExtStep::Add(9759, 9745), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15233PolyExtStep::Add(9760, 9746), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15234PolyExtStep::Add(9761, 9747), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15235PolyExtStep::Add(9762, 9748), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15236PolyExtStep::Add(9763, 9749), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15237PolyExtStep::Add(9764, 9750), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15238PolyExtStep::Add(9765, 9751), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15239PolyExtStep::Add(9766, 9752), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15240PolyExtStep::Add(9767, 9753), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15241PolyExtStep::Add(9768, 9754), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15242PolyExtStep::Add(9769, 9755), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15243PolyExtStep::Add(9770, 9756), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15244PolyExtStep::Mul(9505, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15245PolyExtStep::Mul(9508, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15246PolyExtStep::Mul(9511, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15247PolyExtStep::Mul(9514, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15248PolyExtStep::Mul(9517, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15249PolyExtStep::Mul(9520, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15250PolyExtStep::Mul(9523, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15251PolyExtStep::Mul(9526, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15252PolyExtStep::Mul(9529, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15253PolyExtStep::Mul(9532, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15254PolyExtStep::Mul(9535, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15255PolyExtStep::Mul(9538, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15256PolyExtStep::Mul(9541, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15257PolyExtStep::Mul(9544, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15258PolyExtStep::Mul(9547, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15259PolyExtStep::Add(9502, 9772), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15260PolyExtStep::Add(9787, 9773), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15261PolyExtStep::Add(9788, 9774), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15262PolyExtStep::Add(9789, 9775), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15263PolyExtStep::Add(9790, 9776), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15264PolyExtStep::Add(9791, 9777), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15265PolyExtStep::Add(9792, 9778), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15266PolyExtStep::Add(9793, 9779), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15267PolyExtStep::Add(9794, 9780), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15268PolyExtStep::Add(9795, 9781), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15269PolyExtStep::Add(9796, 9782), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15270PolyExtStep::Add(9797, 9783), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15271PolyExtStep::Add(9798, 9784), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15272PolyExtStep::Add(9799, 9785), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15273PolyExtStep::Add(9800, 9786), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15274PolyExtStep::Mul(9643, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15275PolyExtStep::Mul(9646, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15276PolyExtStep::Mul(9649, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15277PolyExtStep::Mul(9652, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15278PolyExtStep::Mul(9655, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15279PolyExtStep::Mul(9658, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15280PolyExtStep::Mul(9661, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15281PolyExtStep::Mul(9664, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15282PolyExtStep::Mul(9667, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15283PolyExtStep::Mul(9670, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15284PolyExtStep::Mul(9673, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15285PolyExtStep::Mul(9676, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15286PolyExtStep::Mul(9679, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15287PolyExtStep::Mul(9682, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15288PolyExtStep::Mul(9685, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15289PolyExtStep::Add(9639, 9802), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15290PolyExtStep::Add(9817, 9803), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15291PolyExtStep::Add(9818, 9804), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15292PolyExtStep::Add(9819, 9805), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15293PolyExtStep::Add(9820, 9806), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15294PolyExtStep::Add(9821, 9807), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15295PolyExtStep::Add(9822, 9808), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15296PolyExtStep::Add(9823, 9809), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15297PolyExtStep::Add(9824, 9810), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15298PolyExtStep::Add(9825, 9811), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15299PolyExtStep::Add(9826, 9812), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15300PolyExtStep::Add(9827, 9813), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15301PolyExtStep::Add(9828, 9814), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15302PolyExtStep::Add(9829, 9815), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15303PolyExtStep::Add(9830, 9816), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15304PolyExtStep::Mul(9691, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15305PolyExtStep::Mul(9694, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15306PolyExtStep::Mul(9697, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15307PolyExtStep::Mul(9700, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15308PolyExtStep::Mul(9703, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15309PolyExtStep::Mul(9706, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15310PolyExtStep::Mul(9709, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15311PolyExtStep::Mul(9713, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15312PolyExtStep::Mul(9717, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15313PolyExtStep::Mul(9721, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15314PolyExtStep::Mul(9725, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15315PolyExtStep::Mul(9729, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15316PolyExtStep::Mul(9733, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15317PolyExtStep::Mul(9737, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15318PolyExtStep::Mul(9741, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15319PolyExtStep::Add(9688, 9832), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15320PolyExtStep::Add(9847, 9833), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15321PolyExtStep::Add(9848, 9834), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15322PolyExtStep::Add(9849, 9835), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15323PolyExtStep::Add(9850, 9836), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15324PolyExtStep::Add(9851, 9837), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15325PolyExtStep::Add(9852, 9838), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15326PolyExtStep::Add(9853, 9839), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15327PolyExtStep::Add(9854, 9840), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15328PolyExtStep::Add(9855, 9841), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15329PolyExtStep::Add(9856, 9842), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15330PolyExtStep::Add(9857, 9843), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15331PolyExtStep::Add(9858, 9844), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15332PolyExtStep::Add(9859, 9845), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15333PolyExtStep::Add(9860, 9846), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15334PolyExtStep::Mul(9295, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15335PolyExtStep::Mul(9296, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15336PolyExtStep::Mul(9297, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15337PolyExtStep::Mul(9298, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15338PolyExtStep::Mul(9299, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15339PolyExtStep::Mul(9300, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15340PolyExtStep::Mul(9301, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15341PolyExtStep::Mul(9302, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15342PolyExtStep::Mul(9303, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15343PolyExtStep::Mul(9304, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15344PolyExtStep::Mul(9305, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15345PolyExtStep::Mul(9306, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15346PolyExtStep::Mul(9307, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15347PolyExtStep::Mul(9308, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15348PolyExtStep::Mul(9309, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15349PolyExtStep::Add(9294, 9862), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15350PolyExtStep::Add(9877, 9863), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15351PolyExtStep::Add(9878, 9864), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15352PolyExtStep::Add(9879, 9865), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15353PolyExtStep::Add(9880, 9866), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15354PolyExtStep::Add(9881, 9867), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15355PolyExtStep::Add(9882, 9868), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15356PolyExtStep::Add(9883, 9869), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15357PolyExtStep::Add(9884, 9870), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15358PolyExtStep::Add(9885, 9871), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15359PolyExtStep::Add(9886, 9872), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15360PolyExtStep::Add(9887, 9873), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15361PolyExtStep::Add(9888, 9874), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15362PolyExtStep::Add(9889, 9875), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15363PolyExtStep::Add(9890, 9876), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15364PolyExtStep::Mul(9311, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15365PolyExtStep::Mul(9312, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15366PolyExtStep::Mul(9313, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15367PolyExtStep::Mul(9314, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15368PolyExtStep::Mul(9315, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15369PolyExtStep::Mul(9316, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15370PolyExtStep::Mul(9317, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15371PolyExtStep::Mul(9318, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15372PolyExtStep::Mul(9319, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15373PolyExtStep::Mul(9320, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15374PolyExtStep::Mul(9321, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15375PolyExtStep::Mul(9322, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15376PolyExtStep::Mul(9323, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15377PolyExtStep::Mul(9324, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15378PolyExtStep::Mul(9325, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15379PolyExtStep::Add(9310, 9892), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15380PolyExtStep::Add(9907, 9893), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15381PolyExtStep::Add(9908, 9894), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15382PolyExtStep::Add(9909, 9895), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15383PolyExtStep::Add(9910, 9896), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15384PolyExtStep::Add(9911, 9897), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15385PolyExtStep::Add(9912, 9898), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15386PolyExtStep::Add(9913, 9899), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15387PolyExtStep::Add(9914, 9900), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15388PolyExtStep::Add(9915, 9901), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15389PolyExtStep::Add(9916, 9902), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15390PolyExtStep::Add(9917, 9903), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15391PolyExtStep::Add(9918, 9904), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15392PolyExtStep::Add(9919, 9905), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15393PolyExtStep::Add(9920, 9906), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15394PolyExtStep::Mul(9231, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15395PolyExtStep::Mul(9232, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15396PolyExtStep::Mul(9233, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15397PolyExtStep::Mul(9234, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15398PolyExtStep::Mul(9235, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15399PolyExtStep::Mul(9236, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15400PolyExtStep::Mul(9237, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15401PolyExtStep::Mul(9238, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15402PolyExtStep::Mul(9239, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15403PolyExtStep::Mul(9240, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15404PolyExtStep::Mul(9241, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15405PolyExtStep::Mul(9242, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15406PolyExtStep::Mul(9243, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15407PolyExtStep::Mul(9244, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15408PolyExtStep::Mul(9245, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15409PolyExtStep::Add(9230, 9922), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15410PolyExtStep::Add(9937, 9923), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15411PolyExtStep::Add(9938, 9924), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15412PolyExtStep::Add(9939, 9925), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15413PolyExtStep::Add(9940, 9926), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15414PolyExtStep::Add(9941, 9927), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15415PolyExtStep::Add(9942, 9928), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15416PolyExtStep::Add(9943, 9929), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15417PolyExtStep::Add(9944, 9930), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15418PolyExtStep::Add(9945, 9931), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15419PolyExtStep::Add(9946, 9932), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15420PolyExtStep::Add(9947, 9933), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15421PolyExtStep::Add(9948, 9934), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15422PolyExtStep::Add(9949, 9935), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15423PolyExtStep::Add(9950, 9936), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15424PolyExtStep::Mul(9247, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15425PolyExtStep::Mul(9248, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15426PolyExtStep::Mul(9249, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15427PolyExtStep::Mul(9250, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15428PolyExtStep::Mul(9251, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15429PolyExtStep::Mul(9252, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15430PolyExtStep::Mul(9253, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15431PolyExtStep::Mul(9254, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15432PolyExtStep::Mul(9255, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15433PolyExtStep::Mul(9256, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15434PolyExtStep::Mul(9257, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15435PolyExtStep::Mul(9258, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15436PolyExtStep::Mul(9259, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15437PolyExtStep::Mul(9260, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15438PolyExtStep::Mul(9261, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15439PolyExtStep::Add(9246, 9952), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15440PolyExtStep::Add(9967, 9953), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15441PolyExtStep::Add(9968, 9954), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15442PolyExtStep::Add(9969, 9955), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15443PolyExtStep::Add(9970, 9956), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15444PolyExtStep::Add(9971, 9957), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15445PolyExtStep::Add(9972, 9958), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15446PolyExtStep::Add(9973, 9959), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15447PolyExtStep::Add(9974, 9960), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15448PolyExtStep::Add(9975, 9961), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15449PolyExtStep::Add(9976, 9962), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15450PolyExtStep::Add(9977, 9963), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15451PolyExtStep::Add(9978, 9964), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15452PolyExtStep::Add(9979, 9965), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15453PolyExtStep::Add(9980, 9966), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15454PolyExtStep::Add(9891, 9951), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15455PolyExtStep::Add(9921, 9981), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15456PolyExtStep::Add(9831, 9982), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15457PolyExtStep::Add(9861, 9983), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15458PolyExtStep::Add(9771, 9984), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15459PolyExtStep::Add(9801, 9985), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15460PolyExtStep::AndEqz(5444, 7228), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15461PolyExtStep::AndEqz(5445, 9099), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15462PolyExtStep::AndEqz(5446, 9101), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15463PolyExtStep::Sub(9986, 9106), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15464PolyExtStep::Add(9987, 9105), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15465PolyExtStep::AndEqz(5447, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15466PolyExtStep::AndEqz(5448, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15467PolyExtStep::AndEqz(5449, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15468PolyExtStep::Sub(9989, 9113), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15469PolyExtStep::AndEqz(5450, 2082), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15470PolyExtStep::AndEqz(5451, 2084), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15471PolyExtStep::AndEqz(5452, 2086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15472PolyExtStep::AndEqz(5453, 2092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15473PolyExtStep::AndEqz(5454, 2098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15474PolyExtStep::AndEqz(5455, 2104), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15475PolyExtStep::AndEqz(5456, 2971), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15476PolyExtStep::AndEqz(5457, 2011), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15477PolyExtStep::AndEqz(5458, 3415), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15478PolyExtStep::AndEqz(5459, 2978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15479PolyExtStep::AndEqz(5460, 2018), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15480PolyExtStep::AndEqz(5461, 7692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15481PolyExtStep::AndEqz(5462, 2889), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15482PolyExtStep::AndEqz(5463, 2922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15483PolyExtStep::AndEqz(5464, 3464), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15484PolyExtStep::AndEqz(5465, 3466), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15485PolyExtStep::AndEqz(5466, 3468), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15486PolyExtStep::AndEqz(5467, 3479), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15487PolyExtStep::AndEqz(5468, 3519), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15488PolyExtStep::AndEqz(5469, 3523), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15489PolyExtStep::AndEqz(5470, 7694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15490PolyExtStep::AndEqz(5471, 7696), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15491PolyExtStep::AndEqz(5472, 7698), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15492PolyExtStep::AndEqz(5473, 7700), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15493PolyExtStep::AndEqz(5474, 3585), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15494PolyExtStep::AndEqz(5475, 7702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15495PolyExtStep::AndEqz(5476, 4828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15496PolyExtStep::AndEqz(5477, 784), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15497PolyExtStep::AndEqz(5478, 787), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15498PolyExtStep::AndEqz(5479, 790), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15499PolyExtStep::AndEqz(5480, 793), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15500PolyExtStep::AndEqz(5481, 796), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15501PolyExtStep::Sub(8164, 9988), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15502PolyExtStep::AndEqz(5482, 9991), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15503PolyExtStep::Sub(8179, 9990), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15504PolyExtStep::AndEqz(5483, 9992), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15505PolyExtStep::AndEqz(5484, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15506PolyExtStep::AndEqz(5485, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15507PolyExtStep::AndEqz(5486, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15508PolyExtStep::Sub(9034, 9151), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15509PolyExtStep::Add(9035, 9150), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15510PolyExtStep::AndEqz(5487, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15511PolyExtStep::AndEqz(5488, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15512PolyExtStep::AndEqz(5489, 4702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15513PolyExtStep::Sub(9994, 9158), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15514PolyExtStep::AndEqz(5490, 7315), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15515PolyExtStep::AndEqz(5491, 7317), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15516PolyExtStep::AndEqz(5492, 7318), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15517PolyExtStep::AndEqz(5493, 7319), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15518PolyExtStep::AndEqz(5494, 7321), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15519PolyExtStep::AndEqz(5495, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15520PolyExtStep::AndEqz(5496, 2720), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15521PolyExtStep::AndEqz(5497, 2726), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15522PolyExtStep::AndEqz(5498, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15523PolyExtStep::AndEqz(5499, 2736), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15524PolyExtStep::AndEqz(5500, 2742), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15525PolyExtStep::AndEqz(5501, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15526PolyExtStep::AndEqz(5502, 2748), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15527PolyExtStep::AndEqz(5503, 2754), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15528PolyExtStep::AndEqz(5504, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15529PolyExtStep::AndEqz(5505, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15530PolyExtStep::AndEqz(5506, 2760), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15531PolyExtStep::AndEqz(5507, 2766), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15532PolyExtStep::AndEqz(5508, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15533PolyExtStep::AndEqz(5509, 2778), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15534PolyExtStep::AndEqz(5510, 7323), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15535PolyExtStep::AndEqz(5511, 2694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15536PolyExtStep::AndEqz(5512, 7325), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15537PolyExtStep::AndEqz(5513, 7327), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15538PolyExtStep::AndEqz(5514, 2702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15539PolyExtStep::AndEqz(5515, 7329), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15540PolyExtStep::AndEqz(5516, 7331), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15541PolyExtStep::AndEqz(5517, 7333), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15542PolyExtStep::AndEqz(5518, 7335), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15543PolyExtStep::AndEqz(5519, 7337), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15544PolyExtStep::AndEqz(5520, 7339), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15545PolyExtStep::AndEqz(5521, 7341), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15546PolyExtStep::Sub(9129, 9993), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15547PolyExtStep::AndEqz(5522, 9996), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15548PolyExtStep::Sub(9145, 9995), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15549PolyExtStep::AndEqz(5523, 9997), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15550PolyExtStep::Sub(1, 4700), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15551PolyExtStep::Mul(4700, 9998), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15552PolyExtStep::AndEqz(5524, 9999), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15553PolyExtStep::Get(785), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15554PolyExtStep::Sub(1, 10000), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15555PolyExtStep::Mul(10000, 10001), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15556PolyExtStep::AndEqz(5525, 10002), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15557PolyExtStep::Get(786), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15558PolyExtStep::Sub(1, 10003), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15559PolyExtStep::Mul(10003, 10004), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15560PolyExtStep::AndEqz(5526, 10005), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15561PolyExtStep::Mul(10003, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15562PolyExtStep::Mul(10000, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15563PolyExtStep::Add(10006, 10007), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15564PolyExtStep::Add(10008, 4700), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15565PolyExtStep::Mul(10009, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15566PolyExtStep::Sub(9096, 10010), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15567PolyExtStep::Add(9097, 10009), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15568PolyExtStep::Get(787), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15569PolyExtStep::Sub(1, 10013), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15570PolyExtStep::Mul(10013, 10014), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15571PolyExtStep::AndEqz(5527, 10015), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15572PolyExtStep::Get(788), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15573PolyExtStep::Sub(1, 10016), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15574PolyExtStep::Mul(10016, 10017), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15575PolyExtStep::AndEqz(5528, 10018), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15576PolyExtStep::Get(789), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15577PolyExtStep::Sub(1, 10019), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15578PolyExtStep::Mul(10019, 10020), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15579PolyExtStep::AndEqz(5529, 10021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15580PolyExtStep::Mul(10019, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15581PolyExtStep::Mul(10016, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15582PolyExtStep::Add(10022, 10023), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15583PolyExtStep::Add(10024, 10013), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15584PolyExtStep::Mul(10025, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15585PolyExtStep::Sub(10012, 10026), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15586PolyExtStep::AndEqz(5530, 7399), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15587PolyExtStep::AndEqz(5531, 589), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15588PolyExtStep::AndEqz(5532, 592), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15589PolyExtStep::AndEqz(5533, 599), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15590PolyExtStep::AndEqz(5534, 606), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15591PolyExtStep::AndEqz(5535, 613), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15592PolyExtStep::AndEqz(5536, 620), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15593PolyExtStep::AndEqz(5537, 627), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15594PolyExtStep::AndEqz(5538, 630), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15595PolyExtStep::AndEqz(5539, 637), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15596PolyExtStep::AndEqz(5540, 644), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15597PolyExtStep::AndEqz(5541, 647), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15598PolyExtStep::AndEqz(5542, 650), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15599PolyExtStep::AndEqz(5543, 657), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15600PolyExtStep::AndEqz(5544, 664), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15601PolyExtStep::AndEqz(5545, 671), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15602PolyExtStep::AndEqz(5546, 1645), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15603PolyExtStep::AndEqz(5547, 543), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15604PolyExtStep::AndEqz(5548, 7401), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15605PolyExtStep::AndEqz(5549, 1601), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15606PolyExtStep::AndEqz(5550, 555), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15607PolyExtStep::AndEqz(5551, 2848), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15608PolyExtStep::AndEqz(5552, 1609), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15609PolyExtStep::AndEqz(5553, 2036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15610PolyExtStep::AndEqz(5554, 2038), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15611PolyExtStep::AndEqz(5555, 2044), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15612PolyExtStep::AndEqz(5556, 2050), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15613PolyExtStep::AndEqz(5557, 2056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15614PolyExtStep::AndEqz(5558, 2062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15615PolyExtStep::AndEqz(5559, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15616PolyExtStep::AndEqz(5560, 2070), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15617PolyExtStep::AndEqz(5561, 2076), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15618PolyExtStep::Sub(9174, 10011), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15619PolyExtStep::AndEqz(5562, 10028), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15620PolyExtStep::Sub(9190, 10027), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15621PolyExtStep::AndEqz(5563, 10029), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15622PolyExtStep::Mul(2659, 315), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15623PolyExtStep::Mul(7221, 51), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:55) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15624PolyExtStep::Add(10030, 10031), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15625PolyExtStep::AndEqz(5564, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15626PolyExtStep::AndEqz(5565, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15627PolyExtStep::AndEqz(5566, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15628PolyExtStep::AndEqz(5567, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15629PolyExtStep::AndEqz(5568, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15630PolyExtStep::AndEqz(5569, 7257), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15631PolyExtStep::Sub(10032, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15632PolyExtStep::AndEqz(5570, 10033), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15633PolyExtStep::AndEqz(5571, 824), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15634PolyExtStep::AndEqz(5572, 870), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15635PolyExtStep::AndEqz(5573, 882), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15636PolyExtStep::AndEqz(5574, 897), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15637PolyExtStep::AndEqz(5575, 940), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15638PolyExtStep::AndEqz(5576, 955), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15639PolyExtStep::AndEqz(5577, 967), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15640PolyExtStep::AndEqz(5578, 982), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15641PolyExtStep::AndEqz(5579, 1031), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15642PolyExtStep::AndEqz(5580, 1037), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15643PolyExtStep::AndEqz(5581, 1043), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15644PolyExtStep::AndEqz(5582, 1049), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15645PolyExtStep::AndCond(5432, 383, 5583), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15646PolyExtStep::Get(172), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15647PolyExtStep::Get(178), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15648PolyExtStep::Get(184), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15649PolyExtStep::Get(190), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15650PolyExtStep::Get(196), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15651PolyExtStep::Get(202), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15652PolyExtStep::Get(208), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15653PolyExtStep::Get(214), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15654PolyExtStep::Get(220), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15655PolyExtStep::Get(226), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15656PolyExtStep::Get(232), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15657PolyExtStep::Get(238), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15658PolyExtStep::Get(244), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15659PolyExtStep::Get(250), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15660PolyExtStep::Get(256), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15661PolyExtStep::Get(262), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15662PolyExtStep::Get(268), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15663PolyExtStep::Get(274), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15664PolyExtStep::Get(280), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15665PolyExtStep::Get(286), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15666PolyExtStep::Get(292), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15667PolyExtStep::Get(298), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15668PolyExtStep::Get(304), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15669PolyExtStep::Get(310), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15670PolyExtStep::Get(316), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15671PolyExtStep::Get(322), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15672PolyExtStep::Get(328), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15673PolyExtStep::Get(334), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15674PolyExtStep::Get(340), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15675PolyExtStep::Get(346), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15676PolyExtStep::Get(352), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15677PolyExtStep::Get(358), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15678PolyExtStep::Get(364), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15679PolyExtStep::Get(370), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15680PolyExtStep::Get(376), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15681PolyExtStep::Get(382), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15682PolyExtStep::Get(388), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15683PolyExtStep::Get(394), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15684PolyExtStep::Get(400), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15685PolyExtStep::Get(406), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15686PolyExtStep::Get(412), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15687PolyExtStep::Get(418), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15688PolyExtStep::Get(424), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15689PolyExtStep::Get(430), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15690PolyExtStep::Get(436), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15691PolyExtStep::Get(442), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15692PolyExtStep::Get(448), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15693PolyExtStep::Get(454), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15694PolyExtStep::Get(460), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15695PolyExtStep::Get(466), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15696PolyExtStep::Get(472), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15697PolyExtStep::Get(478), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15698PolyExtStep::Get(484), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15699PolyExtStep::Get(490), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15700PolyExtStep::Get(496), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15701PolyExtStep::Get(502), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15702PolyExtStep::Get(508), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15703PolyExtStep::Get(514), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15704PolyExtStep::Get(520), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15705PolyExtStep::Get(526), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15706PolyExtStep::Get(532), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15707PolyExtStep::Get(538), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15708PolyExtStep::Get(544), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15709PolyExtStep::Get(550), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15710PolyExtStep::Sub(3877, 2659), // loc(callsite( builtin Sub at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :192:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15711PolyExtStep::Mul(10098, 2667), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15712PolyExtStep::Sub(10099, 7227), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15713PolyExtStep::AndEqz(5130, 10100), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15714PolyExtStep::Mul(2666, 10098), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15715PolyExtStep::AndEqz(5585, 10101), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15716PolyExtStep::AndEqz(5586, 7232), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15717PolyExtStep::Mul(2659, 313), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
15718PolyExtStep::Mul(7221, 315), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
15719PolyExtStep::Add(10102, 10103), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
15720PolyExtStep::Mul(10104, 7227), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
15721PolyExtStep::Add(7233, 10105), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
15722PolyExtStep::Mul(10035, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15723PolyExtStep::Mul(10036, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15724PolyExtStep::Mul(10037, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15725PolyExtStep::Mul(10038, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15726PolyExtStep::Mul(10039, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15727PolyExtStep::Mul(10040, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15728PolyExtStep::Mul(10041, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15729PolyExtStep::Mul(10042, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15730PolyExtStep::Mul(10043, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15731PolyExtStep::Mul(10044, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15732PolyExtStep::Mul(10045, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15733PolyExtStep::Mul(10046, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15734PolyExtStep::Mul(10047, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15735PolyExtStep::Mul(10048, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15736PolyExtStep::Mul(10049, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15737PolyExtStep::Add(10034, 10107), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15738PolyExtStep::Add(10122, 10108), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15739PolyExtStep::Add(10123, 10109), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15740PolyExtStep::Add(10124, 10110), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15741PolyExtStep::Add(10125, 10111), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15742PolyExtStep::Add(10126, 10112), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15743PolyExtStep::Add(10127, 10113), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15744PolyExtStep::Add(10128, 10114), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15745PolyExtStep::Add(10129, 10115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15746PolyExtStep::Add(10130, 10116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15747PolyExtStep::Add(10131, 10117), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15748PolyExtStep::Add(10132, 10118), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15749PolyExtStep::Add(10133, 10119), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15750PolyExtStep::Add(10134, 10120), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15751PolyExtStep::Add(10135, 10121), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15752PolyExtStep::Mul(10051, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15753PolyExtStep::Mul(10052, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15754PolyExtStep::Mul(10053, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15755PolyExtStep::Mul(10054, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15756PolyExtStep::Mul(10055, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15757PolyExtStep::Mul(10056, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15758PolyExtStep::Mul(10057, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15759PolyExtStep::Mul(10058, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15760PolyExtStep::Mul(10059, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15761PolyExtStep::Mul(10060, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15762PolyExtStep::Mul(10061, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15763PolyExtStep::Mul(10062, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15764PolyExtStep::Mul(10063, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15765PolyExtStep::Mul(10064, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15766PolyExtStep::Mul(10065, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15767PolyExtStep::Add(10050, 10137), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15768PolyExtStep::Add(10152, 10138), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15769PolyExtStep::Add(10153, 10139), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15770PolyExtStep::Add(10154, 10140), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15771PolyExtStep::Add(10155, 10141), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15772PolyExtStep::Add(10156, 10142), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15773PolyExtStep::Add(10157, 10143), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15774PolyExtStep::Add(10158, 10144), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15775PolyExtStep::Add(10159, 10145), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15776PolyExtStep::Add(10160, 10146), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15777PolyExtStep::Add(10161, 10147), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15778PolyExtStep::Add(10162, 10148), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15779PolyExtStep::Add(10163, 10149), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15780PolyExtStep::Add(10164, 10150), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15781PolyExtStep::Add(10165, 10151), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15782PolyExtStep::Add(9065, 10136), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15783PolyExtStep::Add(9095, 10166), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15784PolyExtStep::AndEqz(5587, 9101), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15785PolyExtStep::AndEqz(5588, 3839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15786PolyExtStep::AndEqz(5589, 2677), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15787PolyExtStep::Mul(2675, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15788PolyExtStep::Add(10169, 4750), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15789PolyExtStep::Add(10170, 2672), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15790PolyExtStep::Mul(10171, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15791PolyExtStep::Sub(10167, 10172), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15792PolyExtStep::Add(10168, 10171), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15793PolyExtStep::AndEqz(5590, 3845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15794PolyExtStep::AndEqz(5591, 3847), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15795PolyExtStep::AndEqz(5592, 2687), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15796PolyExtStep::Mul(2685, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15797PolyExtStep::Mul(2683, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15798PolyExtStep::Add(10175, 10176), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15799PolyExtStep::Add(10177, 2682), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15800PolyExtStep::Mul(10178, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15801PolyExtStep::Sub(10174, 10179), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15802PolyExtStep::AndEqz(5593, 7315), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15803PolyExtStep::AndEqz(5594, 7317), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15804PolyExtStep::AndEqz(5595, 7318), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15805PolyExtStep::AndEqz(5596, 7319), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15806PolyExtStep::AndEqz(5597, 7321), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15807PolyExtStep::AndEqz(5598, 1345), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15808PolyExtStep::AndEqz(5599, 2720), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15809PolyExtStep::AndEqz(5600, 2726), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15810PolyExtStep::AndEqz(5601, 1355), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15811PolyExtStep::AndEqz(5602, 2736), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15812PolyExtStep::AndEqz(5603, 2742), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15813PolyExtStep::AndEqz(5604, 1364), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15814PolyExtStep::AndEqz(5605, 2748), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15815PolyExtStep::AndEqz(5606, 2754), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15816PolyExtStep::AndEqz(5607, 1374), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15817PolyExtStep::AndEqz(5608, 1381), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15818PolyExtStep::AndEqz(5609, 2760), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15819PolyExtStep::AndEqz(5610, 2766), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15820PolyExtStep::AndEqz(5611, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15821PolyExtStep::AndEqz(5612, 2778), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15822PolyExtStep::AndEqz(5613, 7323), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15823PolyExtStep::AndEqz(5614, 2694), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15824PolyExtStep::AndEqz(5615, 7325), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15825PolyExtStep::AndEqz(5616, 7327), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15826PolyExtStep::AndEqz(5617, 2702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15827PolyExtStep::AndEqz(5618, 7329), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15828PolyExtStep::AndEqz(5619, 7331), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15829PolyExtStep::AndEqz(5620, 7333), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15830PolyExtStep::AndEqz(5621, 7335), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15831PolyExtStep::AndEqz(5622, 7337), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15832PolyExtStep::AndEqz(5623, 7339), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15833PolyExtStep::AndEqz(5624, 7341), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15834PolyExtStep::Sub(9129, 10173), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15835PolyExtStep::AndEqz(5625, 10181), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15836PolyExtStep::Sub(9145, 10180), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15837PolyExtStep::AndEqz(5626, 10182), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15838PolyExtStep::Mul(10067, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15839PolyExtStep::Mul(10068, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15840PolyExtStep::Mul(10069, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15841PolyExtStep::Mul(10070, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15842PolyExtStep::Mul(10071, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15843PolyExtStep::Mul(10072, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15844PolyExtStep::Mul(10073, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15845PolyExtStep::Mul(10074, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15846PolyExtStep::Mul(10075, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15847PolyExtStep::Mul(10076, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15848PolyExtStep::Mul(10077, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15849PolyExtStep::Mul(10078, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15850PolyExtStep::Mul(10079, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15851PolyExtStep::Mul(10080, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15852PolyExtStep::Mul(10081, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15853PolyExtStep::Add(10066, 10183), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15854PolyExtStep::Add(10198, 10184), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15855PolyExtStep::Add(10199, 10185), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15856PolyExtStep::Add(10200, 10186), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15857PolyExtStep::Add(10201, 10187), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15858PolyExtStep::Add(10202, 10188), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15859PolyExtStep::Add(10203, 10189), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15860PolyExtStep::Add(10204, 10190), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15861PolyExtStep::Add(10205, 10191), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15862PolyExtStep::Add(10206, 10192), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15863PolyExtStep::Add(10207, 10193), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15864PolyExtStep::Add(10208, 10194), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15865PolyExtStep::Add(10209, 10195), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15866PolyExtStep::Add(10210, 10196), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15867PolyExtStep::Add(10211, 10197), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15868PolyExtStep::Mul(10083, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15869PolyExtStep::Mul(10084, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15870PolyExtStep::Mul(10085, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15871PolyExtStep::Mul(10086, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15872PolyExtStep::Mul(10087, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15873PolyExtStep::Mul(10088, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15874PolyExtStep::Mul(10089, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15875PolyExtStep::Mul(10090, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15876PolyExtStep::Mul(10091, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15877PolyExtStep::Mul(10092, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15878PolyExtStep::Mul(10093, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15879PolyExtStep::Mul(10094, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15880PolyExtStep::Mul(10095, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15881PolyExtStep::Mul(10096, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15882PolyExtStep::Mul(10097, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15883PolyExtStep::Add(10082, 10213), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15884PolyExtStep::Add(10228, 10214), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15885PolyExtStep::Add(10229, 10215), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15886PolyExtStep::Add(10230, 10216), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15887PolyExtStep::Add(10231, 10217), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15888PolyExtStep::Add(10232, 10218), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15889PolyExtStep::Add(10233, 10219), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15890PolyExtStep::Add(10234, 10220), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15891PolyExtStep::Add(10235, 10221), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15892PolyExtStep::Add(10236, 10222), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15893PolyExtStep::Add(10237, 10223), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15894PolyExtStep::Add(10238, 10224), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15895PolyExtStep::Add(10239, 10225), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15896PolyExtStep::Add(10240, 10226), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15897PolyExtStep::Add(10241, 10227), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15898PolyExtStep::Add(8209, 10212), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15899PolyExtStep::Add(8239, 10242), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15900PolyExtStep::AndEqz(5627, 3989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15901PolyExtStep::AndEqz(5628, 3753), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15902PolyExtStep::AndEqz(5629, 4692), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15903PolyExtStep::Mul(3751, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15904PolyExtStep::Mul(3750, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15905PolyExtStep::Add(10245, 10246), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15906PolyExtStep::Add(10247, 3852), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15907PolyExtStep::Mul(10248, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15908PolyExtStep::Sub(10243, 10249), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15909PolyExtStep::Add(10244, 10248), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15910PolyExtStep::AndEqz(5630, 4702), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15911PolyExtStep::AndEqz(5631, 9999), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15912PolyExtStep::AndEqz(5632, 10002), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15913PolyExtStep::Mul(10000, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15914PolyExtStep::Mul(4700, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15915PolyExtStep::Add(10252, 10253), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15916PolyExtStep::Add(10254, 4699), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15917PolyExtStep::Mul(10255, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15918PolyExtStep::Sub(10251, 10256), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15919PolyExtStep::AndEqz(5633, 7399), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15920PolyExtStep::AndEqz(5634, 589), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15921PolyExtStep::AndEqz(5635, 592), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15922PolyExtStep::AndEqz(5636, 599), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15923PolyExtStep::AndEqz(5637, 606), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15924PolyExtStep::AndEqz(5638, 613), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15925PolyExtStep::AndEqz(5639, 620), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15926PolyExtStep::AndEqz(5640, 627), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15927PolyExtStep::AndEqz(5641, 630), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15928PolyExtStep::AndEqz(5642, 637), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15929PolyExtStep::AndEqz(5643, 644), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15930PolyExtStep::AndEqz(5644, 647), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15931PolyExtStep::AndEqz(5645, 650), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15932PolyExtStep::AndEqz(5646, 657), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15933PolyExtStep::AndEqz(5647, 664), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15934PolyExtStep::AndEqz(5648, 671), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15935PolyExtStep::AndEqz(5649, 1645), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15936PolyExtStep::AndEqz(5650, 543), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15937PolyExtStep::AndEqz(5651, 7401), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15938PolyExtStep::AndEqz(5652, 1601), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15939PolyExtStep::AndEqz(5653, 555), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15940PolyExtStep::AndEqz(5654, 2848), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15941PolyExtStep::AndEqz(5655, 1609), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15942PolyExtStep::AndEqz(5656, 2036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15943PolyExtStep::AndEqz(5657, 2038), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15944PolyExtStep::AndEqz(5658, 2044), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15945PolyExtStep::AndEqz(5659, 2050), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15946PolyExtStep::AndEqz(5660, 2056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15947PolyExtStep::AndEqz(5661, 2062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15948PolyExtStep::AndEqz(5662, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15949PolyExtStep::AndEqz(5663, 2070), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15950PolyExtStep::AndEqz(5664, 2076), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15951PolyExtStep::Sub(9174, 10250), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15952PolyExtStep::AndEqz(5665, 10258), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15953PolyExtStep::Sub(9190, 10257), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15954PolyExtStep::AndEqz(5666, 10259), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15955PolyExtStep::AndEqz(5667, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15956PolyExtStep::AndEqz(5668, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15957PolyExtStep::AndEqz(5669, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15958PolyExtStep::Sub(10098, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15959PolyExtStep::AndEqz(5670, 10260), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15960PolyExtStep::AndEqz(5671, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15961PolyExtStep::AndEqz(5672, 7257), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15962PolyExtStep::Sub(10106, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15963PolyExtStep::AndEqz(5673, 10261), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15964PolyExtStep::AndEqz(5674, 7165), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15965PolyExtStep::AndEqz(5675, 3732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15966PolyExtStep::Sub(815, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15967PolyExtStep::AndEqz(5676, 10262), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15968PolyExtStep::AndEqz(5677, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15969PolyExtStep::Sub(800, 7245), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15970PolyExtStep::AndEqz(5678, 10263), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15971PolyExtStep::AndEqz(5679, 4667), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15972PolyExtStep::AndEqz(5680, 7170), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15973PolyExtStep::AndEqz(5681, 7344), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15974PolyExtStep::AndEqz(5682, 7347), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15975PolyExtStep::AndEqz(5683, 7174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15976PolyExtStep::AndEqz(5684, 2174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15977PolyExtStep::Sub(873, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15978PolyExtStep::AndEqz(5685, 10264), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15979PolyExtStep::AndEqz(5686, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15980PolyExtStep::Sub(827, 7250), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15981PolyExtStep::AndEqz(5687, 10265), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15982PolyExtStep::AndEqz(5688, 7180), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15983PolyExtStep::AndEqz(5689, 7181), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15984PolyExtStep::AndEqz(5690, 7404), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15985PolyExtStep::AndEqz(5691, 7407), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15986PolyExtStep::AndEqz(5692, 882), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15987PolyExtStep::AndEqz(5693, 897), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15988PolyExtStep::AndEqz(5694, 940), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15989PolyExtStep::AndEqz(5695, 955), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15990PolyExtStep::AndEqz(5696, 967), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15991PolyExtStep::AndEqz(5697, 982), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15992PolyExtStep::AndEqz(5698, 1037), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15993PolyExtStep::AndEqz(5699, 1043), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15994PolyExtStep::AndEqz(5700, 1049), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15995PolyExtStep::AndCond(5584, 386, 5701), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15996PolyExtStep::AndEqz(4017, 4795), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :34:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :234:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15997PolyExtStep::AndEqz(5703, 797), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15998PolyExtStep::AndEqz(5704, 812), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15999PolyExtStep::AndEqz(5705, 824), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16000PolyExtStep::AndEqz(5706, 870), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16001PolyExtStep::AndEqz(5707, 882), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16002PolyExtStep::AndEqz(5708, 897), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16003PolyExtStep::AndEqz(5709, 940), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16004PolyExtStep::AndEqz(5710, 955), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16005PolyExtStep::AndEqz(5711, 967), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16006PolyExtStep::AndEqz(5712, 982), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16007PolyExtStep::AndEqz(5713, 1025), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16008PolyExtStep::AndEqz(5714, 1031), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16009PolyExtStep::AndEqz(5715, 1037), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16010PolyExtStep::AndEqz(5716, 1043), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16011PolyExtStep::AndEqz(5717, 1049), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16012PolyExtStep::AndCond(5702, 389, 5718), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16013PolyExtStep::AndCond(5719, 392, 5718), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16014PolyExtStep::AndCond(5720, 395, 5718), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16015PolyExtStep::AndCond(5069, 452, 5721), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16016PolyExtStep::Add(373, 53), // loc(callsite( builtin Add at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:40) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16017PolyExtStep::Sub(368, 10266), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16018PolyExtStep::Sub(949, 537), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16019PolyExtStep::AndEqz(0, 10268), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16020PolyExtStep::Sub(955, 539), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16021PolyExtStep::AndEqz(5723, 10269), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16022PolyExtStep::AndEqz(5724, 10267), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16023PolyExtStep::Sub(1378, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16024PolyExtStep::AndEqz(0, 10270), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16025PolyExtStep::Sub(1396, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16026PolyExtStep::AndEqz(5726, 10271), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16027PolyExtStep::Sub(1773, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16028PolyExtStep::AndEqz(5727, 10272), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16029PolyExtStep::AndEqz(5728, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16030PolyExtStep::Sub(1379, 316), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16031PolyExtStep::AndEqz(5729, 10273), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16032PolyExtStep::Sub(1395, 1774), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16033PolyExtStep::AndEqz(5730, 10274), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16034PolyExtStep::Sub(1394, 1397), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16035PolyExtStep::AndEqz(5731, 10275), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16036PolyExtStep::Sub(1773, 1392), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16037PolyExtStep::AndEqz(5732, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16038PolyExtStep::Sub(734, 10276), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16039PolyExtStep::AndEqz(5733, 10277), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16040PolyExtStep::AndEqz(5734, 1397), // loc(callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :42:14) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16041PolyExtStep::Sub(1398, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16042PolyExtStep::AndEqz(5735, 10278), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16043PolyExtStep::AndEqz(5736, 1845), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16044PolyExtStep::AndEqz(5737, 538), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16045PolyExtStep::AndEqz(5738, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16046PolyExtStep::Sub(1399, 317), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16047PolyExtStep::AndEqz(5739, 10279), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16048PolyExtStep::Sub(1406, 2207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16049PolyExtStep::AndEqz(5740, 10280), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16050PolyExtStep::Sub(1407, 536), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16051PolyExtStep::AndEqz(5741, 10281), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16052PolyExtStep::Sub(535, 1400), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16053PolyExtStep::AndEqz(5742, 2975), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16054PolyExtStep::Sub(736, 10282), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16055PolyExtStep::AndEqz(5743, 10283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16056PolyExtStep::Mul(536, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16057PolyExtStep::Mul(2207, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :22:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16058PolyExtStep::Add(10284, 10285), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16059PolyExtStep::Sub(10286, 1), // loc(callsite( builtin Sub at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :49:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16060PolyExtStep::Sub(1, 775), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16061PolyExtStep::Mul(775, 10288), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16062PolyExtStep::AndEqz(5744, 10289), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16063PolyExtStep::AndEqz(5745, 10288), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16064PolyExtStep::Sub(1, 1105), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16065PolyExtStep::Mul(1105, 10290), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16066PolyExtStep::AndEqz(5746, 10291), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16067PolyExtStep::Sub(1774, 1105), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16068PolyExtStep::AndEqz(5747, 10292), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16069PolyExtStep::Sub(10287, 776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16070PolyExtStep::AndEqz(5748, 10293), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16071PolyExtStep::AndEqz(5749, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16072PolyExtStep::AndEqz(5750, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16073PolyExtStep::AndEqz(5751, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16074PolyExtStep::AndEqz(5752, 4568), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16075PolyExtStep::AndEqz(5753, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16076PolyExtStep::AndEqz(5754, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16077PolyExtStep::AndEqz(5755, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16078PolyExtStep::AndEqz(5756, 4569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16079PolyExtStep::AndEqz(5757, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16080PolyExtStep::AndEqz(5758, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16081PolyExtStep::AndEqz(5759, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16082PolyExtStep::AndEqz(5760, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16083PolyExtStep::AndEqz(5761, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16084PolyExtStep::AndEqz(5762, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16085PolyExtStep::AndEqz(5763, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16086PolyExtStep::AndEqz(5764, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16087PolyExtStep::AndEqz(5765, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16088PolyExtStep::AndEqz(5766, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16089PolyExtStep::Sub(318, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16090PolyExtStep::AndEqz(5767, 10294), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16091PolyExtStep::AndEqz(5768, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16092PolyExtStep::AndEqz(5769, 618), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16093PolyExtStep::AndEqz(5770, 642), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16094PolyExtStep::AndEqz(5771, 669), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16095PolyExtStep::AndEqz(5772, 549), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16096PolyExtStep::AndEqz(5773, 568), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16097PolyExtStep::AndEqz(5774, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16098PolyExtStep::AndEqz(5775, 583), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16099PolyExtStep::AndEqz(5776, 737), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16100PolyExtStep::AndEqz(5777, 739), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16101PolyExtStep::AndEqz(5778, 748), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16102PolyExtStep::AndEqz(5779, 755), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16103PolyExtStep::AndEqz(5780, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16104PolyExtStep::AndEqz(5781, 758), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16105PolyExtStep::AndEqz(5782, 760), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16106PolyExtStep::AndEqz(5783, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16107PolyExtStep::AndEqz(5784, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16108PolyExtStep::AndEqz(5785, 782), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16109PolyExtStep::AndEqz(5786, 788), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16110PolyExtStep::AndEqz(5787, 794), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16111PolyExtStep::AndEqz(5788, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16112PolyExtStep::AndEqz(5789, 806), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16113PolyExtStep::AndEqz(5790, 812), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16114PolyExtStep::AndEqz(5791, 818), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16115PolyExtStep::AndEqz(5792, 824), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16116PolyExtStep::AndEqz(5793, 861), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16117PolyExtStep::AndEqz(5794, 867), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16118PolyExtStep::AndEqz(5795, 873), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16119PolyExtStep::AndEqz(5796, 879), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16120PolyExtStep::AndEqz(5797, 885), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16121PolyExtStep::AndEqz(5798, 891), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16122PolyExtStep::AndEqz(5799, 897), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16123PolyExtStep::AndEqz(5800, 903), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16124PolyExtStep::AndEqz(5801, 940), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16125PolyExtStep::AndCond(5725, 374, 5802), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16126PolyExtStep::Sub(1379, 4571), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16127PolyExtStep::AndEqz(5729, 10295), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16128PolyExtStep::AndEqz(5804, 10274), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16129PolyExtStep::AndEqz(5805, 10275), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16130PolyExtStep::AndEqz(5806, 3154), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16131PolyExtStep::AndEqz(5807, 10277), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16132PolyExtStep::AndEqz(5808, 3207), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16133PolyExtStep::AndEqz(5809, 2028), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16134PolyExtStep::Mul(759, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16135PolyExtStep::Add(10296, 757), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16136PolyExtStep::Sub(1397, 10297), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16137PolyExtStep::AndEqz(5810, 10298), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16138PolyExtStep::Mul(961, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16139PolyExtStep::Add(10299, 958), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:12) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16140PolyExtStep::Sub(10300, 759), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16141PolyExtStep::AndEqz(5811, 10301), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16142PolyExtStep::AndEqz(5812, 966), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16143PolyExtStep::AndEqz(5813, 969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16144PolyExtStep::AndEqz(5814, 972), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16145PolyExtStep::AndEqz(5815, 975), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16146PolyExtStep::AndEqz(5816, 978), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16147PolyExtStep::Mul(970, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16148PolyExtStep::Mul(973, 12), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16149PolyExtStep::Mul(976, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16150PolyExtStep::Add(2411, 10302), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16151PolyExtStep::Add(10305, 10303), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16152PolyExtStep::Add(10306, 10304), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16153PolyExtStep::AndEqz(5817, 981), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16154PolyExtStep::AndEqz(5818, 984), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16155PolyExtStep::AndEqz(5819, 987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16156PolyExtStep::Mul(982, 7), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:46) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16157PolyExtStep::Mul(985, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:46) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16158PolyExtStep::Add(979, 10308), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16159PolyExtStep::Add(10310, 10309), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16160PolyExtStep::Mul(10311, 24), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16161PolyExtStep::Add(10312, 10307), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:9) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16162PolyExtStep::Sub(10313, 757), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16163PolyExtStep::AndEqz(5820, 10314), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16164PolyExtStep::Add(10307, 30), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:52) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16165PolyExtStep::AndEqz(5821, 10278), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16166PolyExtStep::AndEqz(5822, 1845), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16167PolyExtStep::AndEqz(5823, 538), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16168PolyExtStep::AndEqz(5824, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16169PolyExtStep::Sub(1399, 10315), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16170PolyExtStep::AndEqz(5825, 10316), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16171PolyExtStep::AndEqz(5826, 10280), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16172PolyExtStep::AndEqz(5827, 10281), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16173PolyExtStep::AndEqz(5828, 2975), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16174PolyExtStep::AndEqz(5829, 10283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16175PolyExtStep::Mul(1774, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:59) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16176PolyExtStep::Mul(10317, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:68) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16177PolyExtStep::Add(2207, 10318), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:38) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16178PolyExtStep::Sub(891, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16179PolyExtStep::AndEqz(5830, 10320), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16180PolyExtStep::AndEqz(5831, 1021), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16181PolyExtStep::Add(2333, 894), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16182PolyExtStep::Sub(10319, 10321), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16183PolyExtStep::AndEqz(5832, 10322), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16184PolyExtStep::Add(536, 1019), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16185PolyExtStep::AndEqz(5833, 7186), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16186PolyExtStep::AndEqz(5834, 1024), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16187PolyExtStep::Add(2336, 900), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16188PolyExtStep::Sub(10323, 10324), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16189PolyExtStep::AndEqz(5835, 10325), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16190PolyExtStep::AndEqz(5836, 1027), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16191PolyExtStep::AndEqz(5837, 1030), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16192PolyExtStep::AndEqz(5838, 1033), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16193PolyExtStep::Add(1025, 1028), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16194PolyExtStep::Add(10326, 1031), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16195PolyExtStep::Sub(10327, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16196PolyExtStep::AndEqz(5839, 10328), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16197PolyExtStep::Mul(1031, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16198PolyExtStep::Add(1028, 10329), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16199PolyExtStep::Sub(10330, 961), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16200PolyExtStep::AndEqz(5840, 10331), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16201PolyExtStep::Sub(900, 15), // loc(callsite( builtin Sub at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:19) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16202PolyExtStep::Mul(3875, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16203PolyExtStep::Sub(1, 3875), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:41) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16204PolyExtStep::Mul(10334, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16205PolyExtStep::Add(10333, 10335), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16206PolyExtStep::Sub(10336, 900), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16207PolyExtStep::Mul(900, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16208PolyExtStep::AndEqz(0, 1048), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16209PolyExtStep::Mul(10332, 1049), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16210PolyExtStep::Sub(10339, 1047), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16211PolyExtStep::AndEqz(5842, 10340), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16212PolyExtStep::Mul(1046, 10332), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16213PolyExtStep::AndEqz(5843, 10341), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16214PolyExtStep::AndEqz(5844, 3212), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16215PolyExtStep::AndEqz(5845, 1046), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:34) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16216PolyExtStep::AndEqz(5846, 1036), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16217PolyExtStep::AndEqz(5847, 1039), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16218PolyExtStep::Mul(1037, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16219PolyExtStep::Add(10342, 1034), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16220PolyExtStep::AndEqz(5848, 4615), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16221PolyExtStep::Sub(906, 10337), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16222PolyExtStep::AndEqz(5849, 10344), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16223PolyExtStep::AndEqz(5850, 1042), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16224PolyExtStep::Mul(900, 1043), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16225PolyExtStep::Sub(10345, 1041), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16226PolyExtStep::AndEqz(5851, 10346), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16227PolyExtStep::Mul(1040, 900), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16228PolyExtStep::AndEqz(5852, 10347), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16229PolyExtStep::AndEqz(5853, 3235), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16230PolyExtStep::AndEqz(5854, 1040), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16231PolyExtStep::Sub(940, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16232PolyExtStep::AndEqz(5855, 10348), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16233PolyExtStep::Mul(943, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16234PolyExtStep::Add(10349, 10343), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16235PolyExtStep::Sub(10350, 894), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16236PolyExtStep::AndEqz(5856, 10351), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16237PolyExtStep::Add(10338, 943), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16238PolyExtStep::AndEqz(5857, 10343), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :67:14) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16239PolyExtStep::Sub(587, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16240PolyExtStep::AndEqz(5858, 10353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16241PolyExtStep::Sub(618, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16242PolyExtStep::AndEqz(5859, 10354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16243PolyExtStep::Sub(625, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16244PolyExtStep::AndEqz(5860, 10355), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16245PolyExtStep::AndEqz(5861, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16246PolyExtStep::Sub(590, 10352), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16247PolyExtStep::AndEqz(5862, 10356), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16248PolyExtStep::AndEqz(5863, 3804), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16249PolyExtStep::Sub(611, 635), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16250PolyExtStep::AndEqz(5864, 10357), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16251PolyExtStep::Sub(625, 597), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16252PolyExtStep::AndEqz(5865, 3171), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16253PolyExtStep::Sub(738, 10358), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16254PolyExtStep::AndEqz(5866, 10359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16255PolyExtStep::AndEqz(5867, 2934), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16256PolyExtStep::AndEqz(5868, 2033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16257PolyExtStep::Add(8165, 761), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16258PolyExtStep::Sub(628, 10360), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16259PolyExtStep::AndEqz(5869, 10361), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16260PolyExtStep::AndEqz(5870, 2938), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16261PolyExtStep::AndEqz(5871, 2942), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16262PolyExtStep::Mul(785, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16263PolyExtStep::Add(10362, 752), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16264PolyExtStep::Sub(635, 10363), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16265PolyExtStep::AndEqz(5872, 10364), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16266PolyExtStep::Add(10352, 1), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16267PolyExtStep::Sub(642, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16268PolyExtStep::AndEqz(5873, 10366), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16269PolyExtStep::AndEqz(5874, 2275), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16270PolyExtStep::Sub(672, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16271PolyExtStep::AndEqz(5875, 10367), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16272PolyExtStep::AndEqz(5876, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16273PolyExtStep::Sub(645, 10365), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16274PolyExtStep::AndEqz(5877, 10368), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16275PolyExtStep::AndEqz(5878, 3815), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16276PolyExtStep::AndEqz(5879, 3540), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16277PolyExtStep::Sub(672, 648), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16278PolyExtStep::AndEqz(5880, 2983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16279PolyExtStep::Sub(747, 10369), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16280PolyExtStep::AndEqz(5881, 10370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16281PolyExtStep::AndEqz(5882, 3033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16282PolyExtStep::Sub(794, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16283PolyExtStep::AndEqz(5883, 10371), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16284PolyExtStep::Mul(797, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16285PolyExtStep::Add(10372, 791), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16286PolyExtStep::Sub(541, 10373), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16287PolyExtStep::AndEqz(5884, 10374), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16288PolyExtStep::AndEqz(5885, 3037), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16289PolyExtStep::AndEqz(5886, 3041), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16290PolyExtStep::Mul(809, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16291PolyExtStep::Add(10375, 803), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16292PolyExtStep::Sub(548, 10376), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16293PolyExtStep::AndEqz(5887, 10377), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16294PolyExtStep::Add(10352, 7), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16295PolyExtStep::Sub(549, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16296PolyExtStep::AndEqz(5888, 10379), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16297PolyExtStep::AndEqz(5889, 1614), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16298PolyExtStep::AndEqz(5890, 2954), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16299PolyExtStep::AndEqz(5891, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16300PolyExtStep::Sub(552, 10378), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16301PolyExtStep::AndEqz(5892, 10380), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16302PolyExtStep::AndEqz(5893, 2956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16303PolyExtStep::AndEqz(5894, 2957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16304PolyExtStep::AndEqz(5895, 3188), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16305PolyExtStep::Sub(729, 2958), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16306PolyExtStep::AndEqz(5896, 10381), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16307PolyExtStep::AndEqz(5897, 3732), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16308PolyExtStep::Sub(818, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16309PolyExtStep::AndEqz(5898, 10382), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16310PolyExtStep::Mul(821, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16311PolyExtStep::Add(10383, 815), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16312PolyExtStep::Sub(569, 10384), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16313PolyExtStep::AndEqz(5899, 10385), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16314PolyExtStep::Sub(824, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16315PolyExtStep::AndEqz(5900, 10386), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16316PolyExtStep::Sub(861, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16317PolyExtStep::AndEqz(5901, 10387), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16318PolyExtStep::Mul(864, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16319PolyExtStep::Add(10388, 827), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16320PolyExtStep::Sub(570, 10389), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16321PolyExtStep::AndEqz(5902, 10390), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16322PolyExtStep::Add(10352, 6), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16323PolyExtStep::Sub(571, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16324PolyExtStep::AndEqz(5903, 10392), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16325PolyExtStep::AndEqz(5904, 585), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16326PolyExtStep::Sub(584, 537), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16327PolyExtStep::AndEqz(5905, 10393), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16328PolyExtStep::AndEqz(5906, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16329PolyExtStep::Sub(572, 10391), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16330PolyExtStep::AndEqz(5907, 10394), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16331PolyExtStep::AndEqz(5908, 3835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16332PolyExtStep::Sub(575, 731), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16333PolyExtStep::AndEqz(5909, 10395), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16334PolyExtStep::Sub(584, 573), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16335PolyExtStep::AndEqz(5910, 3196), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16336PolyExtStep::Sub(754, 10396), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16337PolyExtStep::AndEqz(5911, 10397), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16338PolyExtStep::Sub(867, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16339PolyExtStep::AndEqz(5912, 10398), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16340PolyExtStep::Sub(873, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16341PolyExtStep::AndEqz(5913, 10399), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16342PolyExtStep::Mul(876, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16343PolyExtStep::Add(10400, 870), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16344PolyExtStep::Sub(732, 10401), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16345PolyExtStep::AndEqz(5914, 10402), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16346PolyExtStep::Sub(879, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16347PolyExtStep::AndEqz(5915, 10403), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16348PolyExtStep::Sub(885, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16349PolyExtStep::AndEqz(5916, 10404), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16350PolyExtStep::Mul(888, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16351PolyExtStep::Add(10405, 882), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16352PolyExtStep::Sub(731, 10406), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16353PolyExtStep::AndEqz(5917, 10407), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16354PolyExtStep::AndCond(5841, 1025, 5918), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16355PolyExtStep::AndEqz(5858, 2934), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16356PolyExtStep::AndEqz(5920, 2033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16357PolyExtStep::AndEqz(5921, 2938), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16358PolyExtStep::AndEqz(5922, 2942), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16359PolyExtStep::AndEqz(5923, 3033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16360PolyExtStep::AndEqz(5924, 10371), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16361PolyExtStep::AndEqz(5925, 3037), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16362PolyExtStep::AndEqz(5926, 3041), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16363PolyExtStep::AndEqz(5927, 3732), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16364PolyExtStep::AndEqz(5928, 10382), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16365PolyExtStep::AndEqz(5929, 10386), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16366PolyExtStep::AndEqz(5930, 10387), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16367PolyExtStep::AndEqz(5931, 10398), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16368PolyExtStep::AndEqz(5932, 10399), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16369PolyExtStep::AndEqz(5933, 10403), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16370PolyExtStep::AndEqz(5934, 10404), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16371PolyExtStep::AndEqz(5935, 10353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16372PolyExtStep::AndEqz(5936, 10354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16373PolyExtStep::Sub(625, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16374PolyExtStep::AndEqz(5937, 10408), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16375PolyExtStep::AndEqz(5938, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16376PolyExtStep::AndEqz(5939, 10356), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16377PolyExtStep::AndEqz(5940, 3171), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16378PolyExtStep::AndEqz(5941, 10359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16379PolyExtStep::AndEqz(5942, 10361), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16380PolyExtStep::AndEqz(5943, 10364), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16381PolyExtStep::AndEqz(5944, 10366), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16382PolyExtStep::AndEqz(5945, 2275), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16383PolyExtStep::Sub(672, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16384PolyExtStep::AndEqz(5946, 10409), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16385PolyExtStep::AndEqz(5947, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16386PolyExtStep::AndEqz(5948, 10368), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16387PolyExtStep::AndEqz(5949, 2983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16388PolyExtStep::AndEqz(5950, 10370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16389PolyExtStep::AndEqz(5951, 10374), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16390PolyExtStep::AndEqz(5952, 10377), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16391PolyExtStep::AndEqz(5953, 10379), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16392PolyExtStep::AndEqz(5954, 1614), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16393PolyExtStep::Sub(567, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16394PolyExtStep::AndEqz(5955, 10410), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16395PolyExtStep::AndEqz(5956, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16396PolyExtStep::AndEqz(5957, 10380), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16397PolyExtStep::AndEqz(5958, 3188), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16398PolyExtStep::AndEqz(5959, 10381), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16399PolyExtStep::AndEqz(5960, 10385), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16400PolyExtStep::AndEqz(5961, 10390), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16401PolyExtStep::AndEqz(5962, 10392), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16402PolyExtStep::AndEqz(5963, 585), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16403PolyExtStep::Sub(584, 539), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16404PolyExtStep::AndEqz(5964, 10411), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16405PolyExtStep::AndEqz(5965, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16406PolyExtStep::AndEqz(5966, 10394), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16407PolyExtStep::AndEqz(5967, 3196), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16408PolyExtStep::AndEqz(5968, 10397), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16409PolyExtStep::AndEqz(5969, 10402), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16410PolyExtStep::AndEqz(5970, 10407), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16411PolyExtStep::AndCond(5919, 1028, 5971), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16412PolyExtStep::AndEqz(0, 2934), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16413PolyExtStep::AndEqz(5973, 2033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16414PolyExtStep::AndEqz(5974, 2938), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16415PolyExtStep::AndEqz(5975, 2942), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16416PolyExtStep::AndEqz(5976, 3033), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16417PolyExtStep::AndEqz(5977, 10371), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16418PolyExtStep::AndEqz(5978, 3037), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16419PolyExtStep::AndEqz(5979, 3041), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16420PolyExtStep::AndEqz(5980, 3732), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16421PolyExtStep::AndEqz(5981, 10382), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16422PolyExtStep::AndEqz(5982, 10386), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16423PolyExtStep::AndEqz(5983, 10387), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16424PolyExtStep::AndEqz(5984, 10398), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16425PolyExtStep::AndEqz(5985, 10399), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16426PolyExtStep::AndEqz(5986, 10403), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16427PolyExtStep::AndEqz(5987, 10404), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16428PolyExtStep::AndEqz(5988, 903), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16429PolyExtStep::AndEqz(5989, 940), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16430PolyExtStep::AndEqz(5990, 587), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16431PolyExtStep::AndEqz(5991, 618), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16432PolyExtStep::AndEqz(5992, 642), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16433PolyExtStep::AndEqz(5993, 669), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16434PolyExtStep::AndEqz(5994, 549), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16435PolyExtStep::AndEqz(5995, 568), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16436PolyExtStep::AndEqz(5996, 571), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16437PolyExtStep::AndEqz(5997, 583), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16438PolyExtStep::AndEqz(5998, 737), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16439PolyExtStep::AndEqz(5999, 739), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16440PolyExtStep::AndEqz(6000, 748), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16441PolyExtStep::AndEqz(6001, 755), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16442PolyExtStep::AndCond(5972, 1031, 6002), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16443PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :10:27) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :33:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
16444PolyExtStep::Mul(10412, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16445PolyExtStep::Mul(10412, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16446PolyExtStep::Mul(10412, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16447PolyExtStep::Add(10413, 10414), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16448PolyExtStep::Add(10416, 10415), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16449PolyExtStep::Mul(3635, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16450PolyExtStep::Mul(3635, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16451PolyExtStep::Mul(3635, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16452PolyExtStep::Add(10418, 10419), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16453PolyExtStep::Add(10421, 10420), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16454PolyExtStep::Mul(3636, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16455PolyExtStep::Mul(3636, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16456PolyExtStep::Mul(3636, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16457PolyExtStep::Add(10423, 10424), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16458PolyExtStep::Add(10426, 10425), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16459PolyExtStep::Mul(1151, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16460PolyExtStep::Mul(1151, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16461PolyExtStep::Mul(1151, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16462PolyExtStep::Add(10428, 10429), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16463PolyExtStep::Add(10431, 10430), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16464PolyExtStep::Mul(1153, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16465PolyExtStep::Mul(1153, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16466PolyExtStep::Mul(1153, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16467PolyExtStep::Add(10433, 10434), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16468PolyExtStep::Add(10436, 10435), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16469PolyExtStep::Mul(1155, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16470PolyExtStep::Mul(1155, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16471PolyExtStep::Mul(1155, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16472PolyExtStep::Add(10438, 10439), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16473PolyExtStep::Add(10441, 10440), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16474PolyExtStep::Mul(1157, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16475PolyExtStep::Mul(1157, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16476PolyExtStep::Mul(1157, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16477PolyExtStep::Add(10443, 10444), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16478PolyExtStep::Add(10446, 10445), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16479PolyExtStep::Mul(1159, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16480PolyExtStep::Mul(1159, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16481PolyExtStep::Mul(1159, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16482PolyExtStep::Add(10448, 10449), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16483PolyExtStep::Add(10451, 10450), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16484PolyExtStep::Mul(1161, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16485PolyExtStep::Mul(1161, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16486PolyExtStep::Mul(1161, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16487PolyExtStep::Add(10453, 10454), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16488PolyExtStep::Add(10456, 10455), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16489PolyExtStep::Mul(1163, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16490PolyExtStep::Mul(1163, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16491PolyExtStep::Mul(1163, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16492PolyExtStep::Add(10458, 10459), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16493PolyExtStep::Add(10461, 10460), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16494PolyExtStep::Mul(1165, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16495PolyExtStep::Mul(1165, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16496PolyExtStep::Mul(1165, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16497PolyExtStep::Add(10463, 10464), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16498PolyExtStep::Add(10466, 10465), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16499PolyExtStep::Mul(1167, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16500PolyExtStep::Mul(1167, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16501PolyExtStep::Mul(1167, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16502PolyExtStep::Add(10468, 10469), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16503PolyExtStep::Add(10471, 10470), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16504PolyExtStep::Mul(1169, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16505PolyExtStep::Mul(1169, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16506PolyExtStep::Mul(1169, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16507PolyExtStep::Add(10473, 10474), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16508PolyExtStep::Add(10476, 10475), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16509PolyExtStep::Mul(1171, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16510PolyExtStep::Mul(1171, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16511PolyExtStep::Mul(1171, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16512PolyExtStep::Add(10478, 10479), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16513PolyExtStep::Add(10481, 10480), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16514PolyExtStep::Mul(1173, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16515PolyExtStep::Mul(1173, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16516PolyExtStep::Mul(1173, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16517PolyExtStep::Add(10483, 10484), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16518PolyExtStep::Add(10486, 10485), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16519PolyExtStep::Mul(1175, 1025), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16520PolyExtStep::Mul(1175, 1028), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16521PolyExtStep::Mul(1175, 1031), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16522PolyExtStep::Add(10488, 10489), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16523PolyExtStep::Add(10491, 10490), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16524PolyExtStep::AndEqz(6003, 1054), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16525PolyExtStep::Mul(958, 1055), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16526PolyExtStep::Sub(10493, 1053), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16527PolyExtStep::AndEqz(6004, 10494), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16528PolyExtStep::Mul(1052, 958), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16529PolyExtStep::AndEqz(6005, 10495), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16530PolyExtStep::Mul(1052, 1055), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16531PolyExtStep::AndEqz(6006, 10496), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16532PolyExtStep::Mul(1052, 4579), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16533PolyExtStep::Sub(1, 10497), // loc(callsite( builtin Sub at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16534PolyExtStep::Mul(10497, 13), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16535PolyExtStep::Mul(10498, 318), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16536PolyExtStep::Add(10499, 10500), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16537PolyExtStep::AndEqz(6007, 10289), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16538PolyExtStep::AndEqz(6008, 3758), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16539PolyExtStep::AndEqz(6009, 10291), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16540PolyExtStep::AndEqz(6010, 3935), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16541PolyExtStep::AndEqz(6011, 9196), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16542PolyExtStep::Sub(958, 1111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16543PolyExtStep::AndEqz(6012, 10502), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16544PolyExtStep::Sub(10311, 777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16545PolyExtStep::AndEqz(6013, 10503), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16546PolyExtStep::Sub(10417, 1116), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16547PolyExtStep::AndEqz(6014, 10504), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16548PolyExtStep::Sub(10422, 778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16549PolyExtStep::AndEqz(6015, 10505), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16550PolyExtStep::Sub(10427, 1122), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16551PolyExtStep::AndEqz(6016, 10506), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16552PolyExtStep::Sub(10432, 779), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16553PolyExtStep::AndEqz(6017, 10507), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16554PolyExtStep::Sub(10437, 1128), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16555PolyExtStep::AndEqz(6018, 10508), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16556PolyExtStep::Sub(10442, 1340), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16557PolyExtStep::AndEqz(6019, 10509), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16558PolyExtStep::Sub(10447, 1341), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16559PolyExtStep::AndEqz(6020, 10510), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16560PolyExtStep::Sub(10452, 1343), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16561PolyExtStep::AndEqz(6021, 10511), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16562PolyExtStep::Sub(10457, 1350), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16563PolyExtStep::AndEqz(6022, 10512), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16564PolyExtStep::Sub(10462, 1351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16565PolyExtStep::AndEqz(6023, 10513), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16566PolyExtStep::Sub(10467, 1353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16567PolyExtStep::AndEqz(6024, 10514), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16568PolyExtStep::Sub(10472, 1359), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16569PolyExtStep::AndEqz(6025, 10515), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16570PolyExtStep::Sub(10477, 1360), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16571PolyExtStep::AndEqz(6026, 10516), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16572PolyExtStep::Sub(10482, 1362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16573PolyExtStep::AndEqz(6027, 10517), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16574PolyExtStep::Sub(10487, 1369), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16575PolyExtStep::AndEqz(6028, 10518), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16576PolyExtStep::Sub(10492, 1370), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16577PolyExtStep::AndEqz(6029, 10519), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16578PolyExtStep::Sub(10501, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16579PolyExtStep::AndEqz(6030, 10520), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16580PolyExtStep::AndCond(5803, 377, 6031), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16581PolyExtStep::AndEqz(1186, 10289), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16582PolyExtStep::AndEqz(6033, 3758), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16583PolyExtStep::AndEqz(6034, 10291), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16584PolyExtStep::AndEqz(6035, 3759), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16585PolyExtStep::AndEqz(6036, 4565), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16586PolyExtStep::AndEqz(6037, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16587PolyExtStep::AndEqz(6038, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16588PolyExtStep::AndEqz(6039, 3870), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16589PolyExtStep::AndEqz(6040, 4568), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16590PolyExtStep::AndEqz(6041, 3765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16591PolyExtStep::AndEqz(6042, 3766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16592PolyExtStep::AndEqz(6043, 3767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16593PolyExtStep::AndEqz(6044, 4569), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16594PolyExtStep::AndEqz(6045, 3769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16595PolyExtStep::AndEqz(6046, 3770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16596PolyExtStep::AndEqz(6047, 3771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16597PolyExtStep::AndEqz(6048, 3772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16598PolyExtStep::AndEqz(6049, 3773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16599PolyExtStep::AndEqz(6050, 3774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16600PolyExtStep::AndEqz(6051, 3775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16601PolyExtStep::AndEqz(6052, 3776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16602PolyExtStep::AndEqz(6053, 3777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16603PolyExtStep::AndEqz(6054, 3778), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16604PolyExtStep::Sub(13, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16605PolyExtStep::AndEqz(6055, 10521), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16606PolyExtStep::AndEqz(6056, 1378), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16607PolyExtStep::AndEqz(6057, 1396), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16608PolyExtStep::AndEqz(6058, 1398), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16609PolyExtStep::AndEqz(6059, 1844), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16610PolyExtStep::AndEqz(6060, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16611PolyExtStep::AndEqz(6061, 618), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16612PolyExtStep::AndEqz(6062, 642), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16613PolyExtStep::AndEqz(6063, 669), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16614PolyExtStep::AndEqz(6064, 549), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16615PolyExtStep::AndEqz(6065, 568), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16616PolyExtStep::AndEqz(6066, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16617PolyExtStep::AndEqz(6067, 583), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16618PolyExtStep::AndEqz(6068, 733), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16619PolyExtStep::AndEqz(6069, 735), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16620PolyExtStep::AndEqz(6070, 737), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16621PolyExtStep::AndEqz(6071, 739), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16622PolyExtStep::AndEqz(6072, 748), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16623PolyExtStep::AndEqz(6073, 755), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16624PolyExtStep::AndEqz(6074, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16625PolyExtStep::AndEqz(6075, 758), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16626PolyExtStep::AndEqz(6076, 760), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16627PolyExtStep::AndEqz(6077, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16628PolyExtStep::AndEqz(6078, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16629PolyExtStep::AndEqz(6079, 782), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16630PolyExtStep::AndEqz(6080, 788), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16631PolyExtStep::AndEqz(6081, 794), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16632PolyExtStep::AndEqz(6082, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16633PolyExtStep::AndEqz(6083, 806), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16634PolyExtStep::AndEqz(6084, 812), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16635PolyExtStep::AndEqz(6085, 818), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16636PolyExtStep::AndEqz(6086, 824), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16637PolyExtStep::AndEqz(6087, 861), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16638PolyExtStep::AndEqz(6088, 867), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16639PolyExtStep::AndEqz(6089, 873), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16640PolyExtStep::AndEqz(6090, 879), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16641PolyExtStep::AndEqz(6091, 885), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16642PolyExtStep::AndEqz(6092, 891), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16643PolyExtStep::AndEqz(6093, 897), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16644PolyExtStep::AndEqz(6094, 903), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16645PolyExtStep::AndEqz(6095, 940), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16646PolyExtStep::AndCond(6032, 380, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16647PolyExtStep::AndCond(6097, 383, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16648PolyExtStep::AndCond(6098, 386, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16649PolyExtStep::AndCond(6099, 389, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16650PolyExtStep::AndCond(6100, 392, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16651PolyExtStep::AndCond(6101, 395, 6096), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16652PolyExtStep::AndCond(5722, 455, 6102), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16653PolyExtStep::Mul(3652, 419), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16654PolyExtStep::Mul(3652, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16655PolyExtStep::Mul(3652, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16656PolyExtStep::Mul(1253, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16657PolyExtStep::Get(775), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16658PolyExtStep::Mul(10526, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16659PolyExtStep::Mul(1151, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16660PolyExtStep::Mul(1159, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16661PolyExtStep::Sub(1, 1271), // loc(callsite( builtin Sub at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16662PolyExtStep::Mul(1959, 1271), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16663PolyExtStep::Mul(365, 10530), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16664PolyExtStep::Add(10531, 10532), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16665PolyExtStep::Mul(10533, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16666PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :58:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :177:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16667PolyExtStep::Mul(10535, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16668PolyExtStep::Mul(10412, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16669PolyExtStep::Sub(1, 1274), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16670PolyExtStep::Add(1273, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :135:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16671PolyExtStep::Mul(10539, 10530), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16672PolyExtStep::Mul(10540, 1274), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16673PolyExtStep::Mul(10540, 10538), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16674PolyExtStep::Add(10541, 10542), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16675PolyExtStep::Mul(10543, 392), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16676PolyExtStep::Add(10534, 10536), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16677PolyExtStep::Add(10545, 10537), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16678PolyExtStep::Add(10546, 10544), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16679PolyExtStep::Mul(10547, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16680PolyExtStep::Mul(1161, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16681PolyExtStep::Mul(365, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16682PolyExtStep::Mul(365, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16683PolyExtStep::Mul(365, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16684PolyExtStep::Mul(365, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16685PolyExtStep::Add(10522, 10523), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16686PolyExtStep::Add(10554, 10524), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16687PolyExtStep::Add(10555, 10525), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16688PolyExtStep::Add(10556, 10527), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16689PolyExtStep::Add(10557, 10528), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16690PolyExtStep::Add(10558, 10529), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16691PolyExtStep::Add(10559, 10548), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16692PolyExtStep::Add(10560, 10549), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16693PolyExtStep::Add(10561, 10550), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16694PolyExtStep::Add(10562, 10551), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16695PolyExtStep::Add(10563, 10552), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16696PolyExtStep::Add(10564, 10553), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16697PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :41:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16698PolyExtStep::Mul(10566, 419), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16699PolyExtStep::Mul(10566, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16700PolyExtStep::Mul(10566, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16701PolyExtStep::Mul(1256, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16702PolyExtStep::Get(778), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16703PolyExtStep::Mul(10571, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16704PolyExtStep::Mul(1154, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16705PolyExtStep::Mul(1162, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16706PolyExtStep::Get(173), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16707PolyExtStep::Mul(10575, 1271), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16708PolyExtStep::Mul(367, 10530), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16709PolyExtStep::Add(10576, 10577), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16710PolyExtStep::Mul(10578, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16711PolyExtStep::Mul(3652, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16712PolyExtStep::Mul(3635, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16713PolyExtStep::Add(10579, 10580), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16714PolyExtStep::Add(10582, 10581), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16715PolyExtStep::Mul(10583, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16716PolyExtStep::Mul(1164, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16717PolyExtStep::Mul(367, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16718PolyExtStep::Mul(367, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16719PolyExtStep::Mul(367, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16720PolyExtStep::Mul(367, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16721PolyExtStep::Add(10567, 10568), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16722PolyExtStep::Add(10590, 10569), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16723PolyExtStep::Add(10591, 10570), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16724PolyExtStep::Add(10592, 10572), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16725PolyExtStep::Add(10593, 10573), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16726PolyExtStep::Add(10594, 10574), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16727PolyExtStep::Add(10595, 10584), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16728PolyExtStep::Add(10596, 10585), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16729PolyExtStep::Add(10597, 10586), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16730PolyExtStep::Add(10598, 10587), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16731PolyExtStep::Add(10599, 10588), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16732PolyExtStep::Add(10600, 10589), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16733PolyExtStep::Mul(419, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16734PolyExtStep::Mul(422, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16735PolyExtStep::Mul(425, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16736PolyExtStep::Mul(428, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16737PolyExtStep::Mul(431, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16738PolyExtStep::Mul(434, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16739PolyExtStep::Mul(437, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16740PolyExtStep::Mul(374, 23), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16741PolyExtStep::Mul(10530, 13), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16742PolyExtStep::Add(1271, 10610), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16743PolyExtStep::Mul(10611, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16744PolyExtStep::Mul(380, 13), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16745PolyExtStep::Sub(1, 1272), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16746PolyExtStep::Mul(1272, 23), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16747PolyExtStep::Mul(10614, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16748PolyExtStep::Add(10615, 10616), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16749PolyExtStep::Mul(10617, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16750PolyExtStep::Mul(389, 3), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16751PolyExtStep::Mul(1271, 2), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16752PolyExtStep::Mul(10530, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16753PolyExtStep::Add(10620, 10621), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16754PolyExtStep::Mul(10622, 1274), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16755PolyExtStep::Mul(1271, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16756PolyExtStep::Add(10624, 10621), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16757PolyExtStep::Mul(10625, 10538), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16758PolyExtStep::Add(10623, 10626), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16759PolyExtStep::Mul(10627, 392), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16760PolyExtStep::Add(10609, 10612), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16761PolyExtStep::Add(10629, 10613), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16762PolyExtStep::Add(10630, 3396), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16763PolyExtStep::Add(10631, 10618), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16764PolyExtStep::Add(10632, 10619), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16765PolyExtStep::Add(10633, 10628), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16766PolyExtStep::Add(10634, 411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16767PolyExtStep::Mul(10635, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16768PolyExtStep::Mul(3651, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16769PolyExtStep::Get(166), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16770PolyExtStep::Mul(10638, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16771PolyExtStep::Mul(10638, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16772PolyExtStep::Mul(10638, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16773PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16774PolyExtStep::Mul(10642, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16775PolyExtStep::Add(10602, 10603), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16776PolyExtStep::Add(10644, 10604), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16777PolyExtStep::Add(10645, 10605), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16778PolyExtStep::Add(10646, 10606), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16779PolyExtStep::Add(10647, 10607), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16780PolyExtStep::Add(10648, 10608), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16781PolyExtStep::Add(10649, 10636), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16782PolyExtStep::Add(10650, 10637), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16783PolyExtStep::Add(10651, 10639), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16784PolyExtStep::Add(10652, 10640), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16785PolyExtStep::Add(10653, 10641), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16786PolyExtStep::Add(10654, 10643), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16787PolyExtStep::Mul(371, 419), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16788PolyExtStep::Mul(371, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16789PolyExtStep::Mul(371, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16790PolyExtStep::Mul(371, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16791PolyExtStep::Mul(371, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16792PolyExtStep::Mul(371, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16793PolyExtStep::Mul(371, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16794PolyExtStep::Mul(10535, 1271), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16795PolyExtStep::Mul(371, 10530), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16796PolyExtStep::Add(10663, 10664), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :34:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :176:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16797PolyExtStep::Mul(10665, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16798PolyExtStep::Mul(1272, 6), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16799PolyExtStep::Mul(371, 10614), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16800PolyExtStep::Add(10667, 10668), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :179:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16801PolyExtStep::Mul(10669, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16802PolyExtStep::Mul(10530, 1274), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16803PolyExtStep::Mul(1271, 10538), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16804PolyExtStep::Add(10671, 10672), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :128:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :181:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16805PolyExtStep::Mul(10673, 392), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16806PolyExtStep::Add(10666, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16807PolyExtStep::Add(10675, 10670), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16808PolyExtStep::Add(10676, 10674), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16809PolyExtStep::Add(10677, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16810PolyExtStep::Mul(10678, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16811PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16812PolyExtStep::Mul(10680, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16813PolyExtStep::Mul(10680, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16814PolyExtStep::Mul(371, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16815PolyExtStep::Mul(371, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16816PolyExtStep::Add(10656, 10657), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16817PolyExtStep::Add(10685, 10658), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16818PolyExtStep::Add(10686, 10659), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16819PolyExtStep::Add(10687, 10660), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16820PolyExtStep::Add(10688, 10661), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16821PolyExtStep::Add(10689, 10662), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16822PolyExtStep::Add(10690, 10679), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16823PolyExtStep::Add(10691, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16824PolyExtStep::Add(10692, 10681), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16825PolyExtStep::Add(10693, 10682), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16826PolyExtStep::Add(10694, 10683), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16827PolyExtStep::Add(10695, 10684), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16828PolyExtStep::Get(135), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :90:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16829PolyExtStep::Sub(10565, 10697), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :90:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16830PolyExtStep::AndEqz(6103, 10698), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :90:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16831PolyExtStep::Get(137), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16832PolyExtStep::Sub(10601, 10699), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16833PolyExtStep::AndEqz(6104, 10700), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16834PolyExtStep::Get(139), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16835PolyExtStep::Sub(10655, 10701), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16836PolyExtStep::AndEqz(6105, 10702), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16837PolyExtStep::Get(141), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16838PolyExtStep::Sub(10696, 10703), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16839PolyExtStep::AndEqz(6106, 10704), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16840PolyExtStep::GetGlobal(1, 35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16841PolyExtStep::GetGlobal(1, 34), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16842PolyExtStep::Mul(10705, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16843PolyExtStep::Add(10706, 10707), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16844PolyExtStep::GetGlobal(1, 33), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16845PolyExtStep::Mul(10708, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16846PolyExtStep::Add(10709, 10710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16847PolyExtStep::GetGlobal(1, 32), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16848PolyExtStep::Mul(10711, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16849PolyExtStep::Add(10712, 10713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
16850PolyExtStep::Mul(1957, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16851PolyExtStep::Get(162), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16852PolyExtStep::Mul(10716, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16853PolyExtStep::Mul(1954, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16854PolyExtStep::Mul(10638, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16855PolyExtStep::Mul(1959, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16856PolyExtStep::Mul(10575, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16857PolyExtStep::Mul(1971, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16858PolyExtStep::Mul(10680, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16859PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16860PolyExtStep::Mul(10724, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16861PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16862PolyExtStep::Mul(10726, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16863PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16864PolyExtStep::Mul(10728, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16865PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16866PolyExtStep::Mul(10730, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16867PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16868PolyExtStep::Mul(10732, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16869PolyExtStep::Mul(10535, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16870PolyExtStep::Mul(3652, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16871PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16872PolyExtStep::Mul(10736, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16873PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16874PolyExtStep::Mul(10738, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16875PolyExtStep::Mul(10566, 455), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))
16876PolyExtStep::Get(24), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16877PolyExtStep::Sub(1, 10741), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16878PolyExtStep::Mul(10741, 10742), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16879PolyExtStep::AndEqz(6107, 10743), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16880PolyExtStep::Get(25), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16881PolyExtStep::Sub(1, 10744), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16882PolyExtStep::Mul(10744, 10745), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16883PolyExtStep::AndEqz(6108, 10746), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16884PolyExtStep::Get(26), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16885PolyExtStep::Sub(1, 10747), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16886PolyExtStep::Mul(10747, 10748), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16887PolyExtStep::AndEqz(6109, 10749), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16888PolyExtStep::Get(27), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16889PolyExtStep::Sub(1, 10750), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16890PolyExtStep::Mul(10750, 10751), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16891PolyExtStep::AndEqz(6110, 10752), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16892PolyExtStep::Get(28), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16893PolyExtStep::Sub(1, 10753), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16894PolyExtStep::Mul(10753, 10754), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16895PolyExtStep::AndEqz(6111, 10755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16896PolyExtStep::Get(29), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16897PolyExtStep::Sub(1, 10756), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16898PolyExtStep::Mul(10756, 10757), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16899PolyExtStep::AndEqz(6112, 10758), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16900PolyExtStep::Get(30), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16901PolyExtStep::Sub(1, 10759), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16902PolyExtStep::Mul(10759, 10760), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16903PolyExtStep::AndEqz(6113, 10761), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16904PolyExtStep::Add(10741, 10744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16905PolyExtStep::Add(10762, 10747), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16906PolyExtStep::Add(10763, 10750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16907PolyExtStep::Add(10764, 10753), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16908PolyExtStep::Add(10765, 10756), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16909PolyExtStep::Add(10766, 10759), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16910PolyExtStep::Sub(10767, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))
16911PolyExtStep::AndEqz(6114, 10768), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))
16912PolyExtStep::Mul(10747, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16913PolyExtStep::Mul(10750, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16914PolyExtStep::Mul(10753, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16915PolyExtStep::Mul(10756, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16916PolyExtStep::Mul(10759, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16917PolyExtStep::Add(10744, 10769), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16918PolyExtStep::Add(10774, 10770), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16919PolyExtStep::Add(10775, 10771), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16920PolyExtStep::Add(10776, 10772), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16921PolyExtStep::Add(10777, 10773), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
16922PolyExtStep::Sub(10778, 10715), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))
16923PolyExtStep::AndEqz(6115, 10779), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))
16924PolyExtStep::Get(6), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16925PolyExtStep::Get(4), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16926PolyExtStep::Mul(10780, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16927PolyExtStep::Add(10781, 10782), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16928PolyExtStep::Get(2), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16929PolyExtStep::Mul(10783, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16930PolyExtStep::Add(10784, 10785), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16931PolyExtStep::Get(0), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16932PolyExtStep::Mul(10786, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16933PolyExtStep::Add(10787, 10788), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16934PolyExtStep::Sub(10789, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16935PolyExtStep::AndEqz(0, 10790), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16936PolyExtStep::Get(14), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16937PolyExtStep::Get(12), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16938PolyExtStep::Mul(10791, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16939PolyExtStep::Add(10792, 10793), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16940PolyExtStep::Get(10), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16941PolyExtStep::Mul(10794, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16942PolyExtStep::Add(10795, 10796), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16943PolyExtStep::Get(8), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16944PolyExtStep::Mul(10797, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16945PolyExtStep::Add(10798, 10799), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16946PolyExtStep::Sub(10800, 67), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16947PolyExtStep::AndEqz(6117, 10801), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16948PolyExtStep::Get(22), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16949PolyExtStep::Get(20), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16950PolyExtStep::Mul(10802, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16951PolyExtStep::Add(10803, 10804), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16952PolyExtStep::Get(18), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16953PolyExtStep::Mul(10805, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16954PolyExtStep::Add(10806, 10807), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16955PolyExtStep::Get(16), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16956PolyExtStep::Mul(10808, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16957PolyExtStep::Add(10809, 10810), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16958PolyExtStep::Sub(10811, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16959PolyExtStep::AndEqz(6118, 10812), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16960PolyExtStep::AndCond(6116, 10741, 6119), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
16961PolyExtStep::Mul(10714, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :210:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16962PolyExtStep::Mul(10813, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :211:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16963PolyExtStep::Mul(10814, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :212:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16964PolyExtStep::Mul(10815, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :213:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16965PolyExtStep::Mul(10816, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :214:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16966PolyExtStep::Mul(10817, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :215:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16967PolyExtStep::Mul(10818, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :216:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16968PolyExtStep::Mul(10819, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :217:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16969PolyExtStep::Mul(10820, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :218:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16970PolyExtStep::Mul(10821, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :219:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16971PolyExtStep::Mul(10822, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :220:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16972PolyExtStep::Mul(10823, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :221:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16973PolyExtStep::Mul(10824, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :222:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16974PolyExtStep::Mul(10825, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :223:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16975PolyExtStep::Mul(10826, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :224:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16976PolyExtStep::Mul(10827, 10714), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :225:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
16977PolyExtStep::Add(10718, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16978PolyExtStep::Mul(10829, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16979PolyExtStep::Add(10719, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16980PolyExtStep::Mul(10813, 10831), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16981PolyExtStep::Add(10720, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16982PolyExtStep::Mul(10814, 10833), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16983PolyExtStep::Add(10721, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16984PolyExtStep::Mul(10815, 10835), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16985PolyExtStep::Add(10722, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16986PolyExtStep::Mul(10816, 10837), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16987PolyExtStep::Add(10723, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16988PolyExtStep::Mul(10817, 10839), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16989PolyExtStep::Add(10725, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16990PolyExtStep::Mul(10818, 10841), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16991PolyExtStep::Add(10727, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16992PolyExtStep::Mul(10819, 10843), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16993PolyExtStep::Add(10729, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16994PolyExtStep::Mul(10820, 10845), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16995PolyExtStep::Add(10731, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16996PolyExtStep::Mul(10821, 10847), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16997PolyExtStep::Add(10733, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16998PolyExtStep::Mul(10822, 10849), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
16999PolyExtStep::Add(10734, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17000PolyExtStep::Mul(10823, 10851), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17001PolyExtStep::Add(10735, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17002PolyExtStep::Mul(10824, 10853), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17003PolyExtStep::Add(10737, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17004PolyExtStep::Mul(10825, 10855), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17005PolyExtStep::Add(10739, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17006PolyExtStep::Mul(10826, 10857), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17007PolyExtStep::Add(10740, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17008PolyExtStep::Mul(10827, 10859), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17009PolyExtStep::Add(10830, 58), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17010PolyExtStep::Add(10861, 10832), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17011PolyExtStep::Add(10862, 10834), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17012PolyExtStep::Add(10863, 10836), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17013PolyExtStep::Add(10864, 10838), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17014PolyExtStep::Add(10865, 10840), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17015PolyExtStep::Add(10866, 10842), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17016PolyExtStep::Add(10867, 10844), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17017PolyExtStep::Add(10868, 10846), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17018PolyExtStep::Add(10869, 10848), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17019PolyExtStep::Add(10870, 10850), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17020PolyExtStep::Add(10871, 10852), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17021PolyExtStep::Add(10872, 10854), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17022PolyExtStep::Add(10873, 10856), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17023PolyExtStep::Add(10874, 10858), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17024PolyExtStep::Add(10875, 10860), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17025PolyExtStep::Get(7), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17026PolyExtStep::Get(5), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17027PolyExtStep::Mul(10877, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17028PolyExtStep::Add(10878, 10879), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17029PolyExtStep::Get(3), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17030PolyExtStep::Mul(10880, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17031PolyExtStep::Add(10881, 10882), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17032PolyExtStep::Get(1), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17033PolyExtStep::Mul(10883, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17034PolyExtStep::Add(10884, 10885), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17035PolyExtStep::Get(15), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17036PolyExtStep::Get(13), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17037PolyExtStep::Mul(10887, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17038PolyExtStep::Add(10888, 10889), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17039PolyExtStep::Get(11), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17040PolyExtStep::Mul(10890, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17041PolyExtStep::Add(10891, 10892), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17042PolyExtStep::Get(9), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17043PolyExtStep::Mul(10893, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17044PolyExtStep::Add(10894, 10895), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17045PolyExtStep::Get(23), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17046PolyExtStep::Get(21), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17047PolyExtStep::Mul(10897, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17048PolyExtStep::Add(10898, 10899), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17049PolyExtStep::Get(19), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17050PolyExtStep::Mul(10900, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17051PolyExtStep::Add(10901, 10902), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17052PolyExtStep::Get(17), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17053PolyExtStep::Mul(10903, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17054PolyExtStep::Add(10904, 10905), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17055PolyExtStep::Add(10886, 10876), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :246:28) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17056PolyExtStep::Mul(10907, 10828), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :262:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17057PolyExtStep::Sub(10789, 10908), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17058PolyExtStep::AndEqz(0, 10909), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17059PolyExtStep::Sub(10800, 10896), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17060PolyExtStep::AndEqz(6121, 10910), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17061PolyExtStep::Sub(10811, 10906), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17062PolyExtStep::AndEqz(6122, 10911), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17063PolyExtStep::AndCond(6120, 10744, 6123), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17064PolyExtStep::Sub(10800, 10907), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17065PolyExtStep::AndEqz(6117, 10912), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17066PolyExtStep::AndEqz(6125, 10911), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17067PolyExtStep::AndCond(6124, 10747, 6126), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17068PolyExtStep::Sub(10717, 5), // loc(callsite( builtin Sub at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:30) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17069PolyExtStep::Add(10913, 58), // loc(callsite( builtin MakeExt at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17070PolyExtStep::Mul(10914, 10896), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:24) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17071PolyExtStep::Get(34), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17072PolyExtStep::Get(33), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17073PolyExtStep::Mul(10916, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17074PolyExtStep::Add(10917, 10918), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17075PolyExtStep::Get(32), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17076PolyExtStep::Mul(10919, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17077PolyExtStep::Add(10920, 10921), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17078PolyExtStep::Get(31), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17079PolyExtStep::Mul(10922, 353), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17080PolyExtStep::Add(10923, 10924), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17081PolyExtStep::Sub(10925, 10915), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17082PolyExtStep::AndEqz(0, 10926), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17083PolyExtStep::Mul(10925, 10907), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17084PolyExtStep::Add(10906, 10927), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17085PolyExtStep::AndEqz(6128, 10790), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17086PolyExtStep::AndEqz(6129, 10801), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17087PolyExtStep::Sub(10811, 10928), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17088PolyExtStep::AndEqz(6130, 10929), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17089PolyExtStep::AndCond(6127, 10750, 6131), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17090PolyExtStep::Mul(10813, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17091PolyExtStep::Mul(10814, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17092PolyExtStep::Mul(10815, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17093PolyExtStep::Mul(10816, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17094PolyExtStep::Mul(10817, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17095PolyExtStep::Mul(10818, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17096PolyExtStep::Mul(10819, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17097PolyExtStep::Mul(10820, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17098PolyExtStep::Mul(10821, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17099PolyExtStep::Mul(10822, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17100PolyExtStep::Mul(10823, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17101PolyExtStep::Mul(10824, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17102PolyExtStep::Mul(10825, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17103PolyExtStep::Mul(10826, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17104PolyExtStep::Mul(10827, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17105PolyExtStep::Add(10930, 319), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17106PolyExtStep::Add(10945, 10931), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17107PolyExtStep::Add(10946, 10932), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17108PolyExtStep::Add(10947, 10933), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17109PolyExtStep::Add(10948, 10934), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17110PolyExtStep::Add(10949, 10935), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17111PolyExtStep::Add(10950, 10936), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17112PolyExtStep::Add(10951, 10937), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17113PolyExtStep::Add(10952, 10938), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17114PolyExtStep::Add(10953, 10939), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17115PolyExtStep::Add(10954, 10940), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17116PolyExtStep::Add(10955, 10941), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17117PolyExtStep::Add(10956, 10942), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17118PolyExtStep::Add(10957, 10943), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17119PolyExtStep::Add(10958, 10944), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))))))))
17120PolyExtStep::Sub(10876, 10959), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17121PolyExtStep::Mul(10960, 320), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17122PolyExtStep::Add(10886, 10961), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17123PolyExtStep::Sub(10789, 10962), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17124PolyExtStep::AndEqz(0, 10963), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17125PolyExtStep::AndEqz(6133, 10910), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17126PolyExtStep::AndEqz(6134, 10911), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17127PolyExtStep::AndCond(6132, 10753, 6135), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17128PolyExtStep::Mul(10876, 321), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17129PolyExtStep::Add(10886, 10964), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17130PolyExtStep::Sub(10789, 10965), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17131PolyExtStep::AndEqz(0, 10966), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17132PolyExtStep::AndEqz(6137, 10910), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17133PolyExtStep::AndEqz(6138, 10911), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17134PolyExtStep::AndCond(6136, 10756, 6139), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17135PolyExtStep::Sub(10813, 321), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :313:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17136PolyExtStep::Mul(10907, 10967), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17137PolyExtStep::Add(10906, 10968), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17138PolyExtStep::AndEqz(0, 10969), // loc(callsite( builtin EqzExt at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :315:10) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))
17139PolyExtStep::AndEqz(6141, 10790), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17140PolyExtStep::AndEqz(6142, 10801), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17141PolyExtStep::AndEqz(6143, 10812), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))))))
17142PolyExtStep::AndCond(6140, 10759, 6144), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :99:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :555:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints ))))))
17143PolyExtStep::GetGlobal(1, 7), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17144PolyExtStep::GetGlobal(1, 6), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17145PolyExtStep::Mul(10970, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17146PolyExtStep::Add(10971, 10972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17147PolyExtStep::GetGlobal(1, 5), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17148PolyExtStep::Mul(10973, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17149PolyExtStep::Add(10974, 10975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17150PolyExtStep::GetGlobal(1, 4), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17151PolyExtStep::Mul(10976, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17152PolyExtStep::Add(10977, 10978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17153PolyExtStep::GetGlobal(1, 11), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17154PolyExtStep::GetGlobal(1, 10), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17155PolyExtStep::Mul(10980, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17156PolyExtStep::Add(10981, 10982), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17157PolyExtStep::GetGlobal(1, 9), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17158PolyExtStep::Mul(10983, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17159PolyExtStep::Add(10984, 10985), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17160PolyExtStep::GetGlobal(1, 8), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17161PolyExtStep::Mul(10986, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17162PolyExtStep::Add(10987, 10988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17163PolyExtStep::GetGlobal(1, 15), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17164PolyExtStep::GetGlobal(1, 14), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17165PolyExtStep::Mul(10990, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17166PolyExtStep::Add(10991, 10992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17167PolyExtStep::GetGlobal(1, 13), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17168PolyExtStep::Mul(10993, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17169PolyExtStep::Add(10994, 10995), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17170PolyExtStep::GetGlobal(1, 12), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17171PolyExtStep::Mul(10996, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17172PolyExtStep::Add(10997, 10998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17173PolyExtStep::GetGlobal(1, 19), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17174PolyExtStep::GetGlobal(1, 18), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17175PolyExtStep::Mul(11000, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17176PolyExtStep::Add(11001, 11002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17177PolyExtStep::GetGlobal(1, 17), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17178PolyExtStep::Mul(11003, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17179PolyExtStep::Add(11004, 11005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17180PolyExtStep::GetGlobal(1, 16), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17181PolyExtStep::Mul(11006, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17182PolyExtStep::Add(11007, 11008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17183PolyExtStep::GetGlobal(1, 23), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17184PolyExtStep::GetGlobal(1, 22), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17185PolyExtStep::Mul(11010, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17186PolyExtStep::Add(11011, 11012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17187PolyExtStep::GetGlobal(1, 21), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17188PolyExtStep::Mul(11013, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17189PolyExtStep::Add(11014, 11015), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17190PolyExtStep::GetGlobal(1, 20), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17191PolyExtStep::Mul(11016, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17192PolyExtStep::Add(11017, 11018), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17193PolyExtStep::GetGlobal(1, 27), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17194PolyExtStep::GetGlobal(1, 26), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17195PolyExtStep::Mul(11020, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17196PolyExtStep::Add(11021, 11022), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17197PolyExtStep::GetGlobal(1, 25), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17198PolyExtStep::Mul(11023, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17199PolyExtStep::Add(11024, 11025), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17200PolyExtStep::GetGlobal(1, 24), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17201PolyExtStep::Mul(11026, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17202PolyExtStep::Add(11027, 11028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17203PolyExtStep::GetGlobal(1, 31), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17204PolyExtStep::GetGlobal(1, 30), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17205PolyExtStep::Mul(11030, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17206PolyExtStep::Add(11031, 11032), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17207PolyExtStep::GetGlobal(1, 29), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17208PolyExtStep::Mul(11033, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17209PolyExtStep::Add(11034, 11035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17210PolyExtStep::GetGlobal(1, 28), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17211PolyExtStep::Mul(11036, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17212PolyExtStep::Add(11037, 11038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17213PolyExtStep::Get(118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17214PolyExtStep::Get(116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17215PolyExtStep::Mul(11040, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17216PolyExtStep::Add(11041, 11042), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17217PolyExtStep::Get(114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17218PolyExtStep::Mul(11043, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17219PolyExtStep::Add(11044, 11045), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17220PolyExtStep::Get(112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17221PolyExtStep::Mul(11046, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17222PolyExtStep::Add(11047, 11048), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17223PolyExtStep::Mul(10979, 1341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17224PolyExtStep::Add(11050, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17225PolyExtStep::Mul(10979, 1351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17226PolyExtStep::Add(11052, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17227PolyExtStep::Mul(11051, 11053), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17228PolyExtStep::Mul(11051, 1350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17229PolyExtStep::Mul(1340, 11053), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17230PolyExtStep::Mul(10979, 1360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17231PolyExtStep::Add(11057, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17232PolyExtStep::Mul(11054, 11058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17233PolyExtStep::Mul(11054, 1359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17234PolyExtStep::Mul(11056, 11058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17235PolyExtStep::Mul(11055, 11058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17236PolyExtStep::Get(38), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17237PolyExtStep::Get(37), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17238PolyExtStep::Mul(11063, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17239PolyExtStep::Add(11064, 11065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17240PolyExtStep::Get(36), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17241PolyExtStep::Mul(11066, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17242PolyExtStep::Add(11067, 11068), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17243PolyExtStep::Get(35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17244PolyExtStep::Mul(11069, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17245PolyExtStep::Add(11070, 11071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17246PolyExtStep::Sub(11072, 11049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17247PolyExtStep::Mul(11073, 11059), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17248PolyExtStep::Sub(11074, 11061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17249PolyExtStep::Sub(11075, 11062), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17250PolyExtStep::Sub(11076, 11060), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17251PolyExtStep::AndEqz(0, 11077), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17252PolyExtStep::Mul(10979, 1370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17253PolyExtStep::Add(11078, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17254PolyExtStep::Mul(10989, 1395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17255PolyExtStep::Mul(10999, 1396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17256PolyExtStep::Add(11080, 11081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17257PolyExtStep::Mul(11009, 1773), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17258PolyExtStep::Add(11082, 11083), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17259PolyExtStep::Mul(11019, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17260PolyExtStep::Add(11084, 11085), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17261PolyExtStep::Add(11086, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17262PolyExtStep::Mul(11079, 11087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17263PolyExtStep::Mul(11079, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17264PolyExtStep::Mul(1369, 11087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17265PolyExtStep::Mul(10999, 1398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17266PolyExtStep::Add(11080, 11091), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17267PolyExtStep::Mul(11009, 1399), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17268PolyExtStep::Add(11092, 11093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17269PolyExtStep::Mul(11019, 1400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17270PolyExtStep::Add(11094, 11095), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17271PolyExtStep::Add(11096, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17272PolyExtStep::Mul(11088, 11097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17273PolyExtStep::Mul(11088, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17274PolyExtStep::Mul(11090, 11097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17275PolyExtStep::Mul(11089, 11097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17276PolyExtStep::Get(42), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17277PolyExtStep::Get(41), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17278PolyExtStep::Mul(11102, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17279PolyExtStep::Add(11103, 11104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17280PolyExtStep::Get(40), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17281PolyExtStep::Mul(11105, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17282PolyExtStep::Add(11106, 11107), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17283PolyExtStep::Get(39), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17284PolyExtStep::Mul(11108, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17285PolyExtStep::Add(11109, 11110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17286PolyExtStep::Sub(11111, 11072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17287PolyExtStep::Mul(11112, 11098), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17288PolyExtStep::Sub(11113, 11100), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17289PolyExtStep::Sub(11114, 11101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17290PolyExtStep::Sub(11115, 11099), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17291PolyExtStep::AndEqz(6146, 11116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17292PolyExtStep::Mul(11029, 1407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17293PolyExtStep::Add(11117, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17294PolyExtStep::Mul(11029, 535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17295PolyExtStep::Add(11119, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17296PolyExtStep::Mul(11118, 11120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17297PolyExtStep::Mul(11118, 1844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17298PolyExtStep::Mul(1406, 11120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17299PolyExtStep::Mul(11029, 536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17300PolyExtStep::Add(11124, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17301PolyExtStep::Mul(11121, 11125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17302PolyExtStep::Mul(11121, 2207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17303PolyExtStep::Mul(11123, 11125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17304PolyExtStep::Mul(11122, 11125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17305PolyExtStep::Get(46), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17306PolyExtStep::Get(45), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17307PolyExtStep::Mul(11130, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17308PolyExtStep::Add(11131, 11132), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17309PolyExtStep::Get(44), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17310PolyExtStep::Mul(11133, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17311PolyExtStep::Add(11134, 11135), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17312PolyExtStep::Get(43), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17313PolyExtStep::Mul(11136, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17314PolyExtStep::Add(11137, 11138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17315PolyExtStep::Sub(11139, 11111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17316PolyExtStep::Mul(11140, 11126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17317PolyExtStep::Sub(11141, 11128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17318PolyExtStep::Sub(11142, 11129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17319PolyExtStep::Sub(11143, 11127), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17320PolyExtStep::AndEqz(6147, 11144), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17321PolyExtStep::Mul(10979, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17322PolyExtStep::Add(11145, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17323PolyExtStep::Mul(10979, 561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17324PolyExtStep::Add(11147, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17325PolyExtStep::Mul(11146, 11148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17326PolyExtStep::Mul(11146, 560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17327PolyExtStep::Mul(548, 11148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17328PolyExtStep::Mul(10989, 568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17329PolyExtStep::Mul(10999, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17330PolyExtStep::Add(11152, 11153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17331PolyExtStep::Mul(11009, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17332PolyExtStep::Add(11154, 11155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17333PolyExtStep::Mul(11019, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17334PolyExtStep::Add(11156, 11157), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17335PolyExtStep::Add(11158, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17336PolyExtStep::Mul(11149, 11159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17337PolyExtStep::Mul(11149, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17338PolyExtStep::Mul(11151, 11159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17339PolyExtStep::Mul(11150, 11159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17340PolyExtStep::Get(50), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17341PolyExtStep::Get(49), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17342PolyExtStep::Mul(11164, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17343PolyExtStep::Add(11165, 11166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17344PolyExtStep::Get(48), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17345PolyExtStep::Mul(11167, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17346PolyExtStep::Add(11168, 11169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17347PolyExtStep::Get(47), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17348PolyExtStep::Mul(11170, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17349PolyExtStep::Add(11171, 11172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17350PolyExtStep::Sub(11173, 11139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17351PolyExtStep::Mul(11174, 11160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17352PolyExtStep::Sub(11175, 11162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17353PolyExtStep::Sub(11176, 11163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17354PolyExtStep::Sub(11177, 11161), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17355PolyExtStep::AndEqz(6148, 11178), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17356PolyExtStep::Mul(10999, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17357PolyExtStep::Add(11152, 11179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17358PolyExtStep::Mul(11009, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17359PolyExtStep::Add(11180, 11181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17360PolyExtStep::Mul(11019, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17361PolyExtStep::Add(11182, 11183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17362PolyExtStep::Add(11184, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17363PolyExtStep::Mul(11029, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17364PolyExtStep::Add(11186, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17365PolyExtStep::Mul(11185, 11187), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17366PolyExtStep::Mul(11185, 583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17367PolyExtStep::Mul(572, 11187), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17368PolyExtStep::Mul(10989, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17369PolyExtStep::Mul(10999, 733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17370PolyExtStep::Add(11191, 11192), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17371PolyExtStep::Mul(11009, 734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17372PolyExtStep::Add(11193, 11194), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17373PolyExtStep::Mul(11019, 735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17374PolyExtStep::Add(11195, 11196), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17375PolyExtStep::Add(11197, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17376PolyExtStep::Mul(11188, 11198), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17377PolyExtStep::Mul(11188, 731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17378PolyExtStep::Mul(11190, 11198), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17379PolyExtStep::Mul(11189, 11198), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17380PolyExtStep::Get(54), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17381PolyExtStep::Get(53), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17382PolyExtStep::Mul(11203, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17383PolyExtStep::Add(11204, 11205), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17384PolyExtStep::Get(52), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17385PolyExtStep::Mul(11206, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17386PolyExtStep::Add(11207, 11208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17387PolyExtStep::Get(51), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17388PolyExtStep::Mul(11209, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17389PolyExtStep::Add(11210, 11211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17390PolyExtStep::Sub(11212, 11173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17391PolyExtStep::Mul(11213, 11199), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17392PolyExtStep::Sub(11214, 11201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17393PolyExtStep::Sub(11215, 11202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17394PolyExtStep::Sub(11216, 11200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17395PolyExtStep::AndEqz(6149, 11217), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17396PolyExtStep::Mul(10999, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17397PolyExtStep::Add(11191, 11218), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17398PolyExtStep::Mul(11009, 738), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17399PolyExtStep::Add(11219, 11220), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17400PolyExtStep::Mul(11019, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17401PolyExtStep::Add(11221, 11222), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17402PolyExtStep::Add(11223, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17403PolyExtStep::Mul(11029, 748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17404PolyExtStep::Add(11225, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17405PolyExtStep::Mul(11224, 11226), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17406PolyExtStep::Mul(11224, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17407PolyExtStep::Mul(736, 11226), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17408PolyExtStep::Mul(10989, 755), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17409PolyExtStep::Mul(10999, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17410PolyExtStep::Add(11230, 11231), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17411PolyExtStep::Mul(11009, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17412PolyExtStep::Add(11232, 11233), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17413PolyExtStep::Mul(11019, 758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17414PolyExtStep::Add(11234, 11235), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17415PolyExtStep::Add(11236, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17416PolyExtStep::Mul(11227, 11237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17417PolyExtStep::Mul(11227, 754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17418PolyExtStep::Mul(11229, 11237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17419PolyExtStep::Mul(11228, 11237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17420PolyExtStep::Get(58), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17421PolyExtStep::Get(57), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17422PolyExtStep::Mul(11242, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17423PolyExtStep::Add(11243, 11244), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17424PolyExtStep::Get(56), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17425PolyExtStep::Mul(11245, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17426PolyExtStep::Add(11246, 11247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17427PolyExtStep::Get(55), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17428PolyExtStep::Mul(11248, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17429PolyExtStep::Add(11249, 11250), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17430PolyExtStep::Sub(11251, 11212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17431PolyExtStep::Mul(11252, 11238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17432PolyExtStep::Sub(11253, 11240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17433PolyExtStep::Sub(11254, 11241), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17434PolyExtStep::Sub(11255, 11239), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17435PolyExtStep::AndEqz(6150, 11256), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17436PolyExtStep::Mul(10999, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17437PolyExtStep::Add(11230, 11257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17438PolyExtStep::Mul(11009, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17439PolyExtStep::Add(11258, 11259), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17440PolyExtStep::Mul(11019, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17441PolyExtStep::Add(11260, 11261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17442PolyExtStep::Add(11262, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17443PolyExtStep::Mul(11029, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17444PolyExtStep::Add(11264, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17445PolyExtStep::Mul(11263, 11265), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17446PolyExtStep::Mul(11263, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17447PolyExtStep::Mul(759, 11265), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17448PolyExtStep::Mul(10979, 1105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17449PolyExtStep::Add(11269, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17450PolyExtStep::Mul(11266, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17451PolyExtStep::Mul(11266, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17452PolyExtStep::Mul(11268, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17453PolyExtStep::Mul(11267, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17454PolyExtStep::Get(62), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17455PolyExtStep::Get(61), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17456PolyExtStep::Mul(11275, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17457PolyExtStep::Add(11276, 11277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17458PolyExtStep::Get(60), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17459PolyExtStep::Mul(11278, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17460PolyExtStep::Add(11279, 11280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17461PolyExtStep::Get(59), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17462PolyExtStep::Mul(11281, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17463PolyExtStep::Add(11282, 11283), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17464PolyExtStep::Sub(11284, 11251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17465PolyExtStep::Mul(11285, 11271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17466PolyExtStep::Sub(11286, 11273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17467PolyExtStep::Sub(11287, 11274), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17468PolyExtStep::Sub(11288, 11272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17469PolyExtStep::AndEqz(6151, 11289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17470PolyExtStep::Mul(10979, 1111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17471PolyExtStep::Add(11290, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17472PolyExtStep::Mul(10979, 1116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17473PolyExtStep::Add(11292, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17474PolyExtStep::Mul(11291, 11293), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17475PolyExtStep::Mul(11291, 777), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17476PolyExtStep::Mul(776, 11293), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17477PolyExtStep::Mul(10979, 1122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17478PolyExtStep::Add(11297, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17479PolyExtStep::Mul(11294, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17480PolyExtStep::Mul(11294, 778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17481PolyExtStep::Mul(11296, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17482PolyExtStep::Mul(11295, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17483PolyExtStep::Get(66), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17484PolyExtStep::Get(65), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17485PolyExtStep::Mul(11303, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17486PolyExtStep::Add(11304, 11305), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17487PolyExtStep::Get(64), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17488PolyExtStep::Mul(11306, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17489PolyExtStep::Add(11307, 11308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17490PolyExtStep::Get(63), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17491PolyExtStep::Mul(11309, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17492PolyExtStep::Add(11310, 11311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17493PolyExtStep::Sub(11312, 11284), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17494PolyExtStep::Mul(11313, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17495PolyExtStep::Sub(11314, 11301), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17496PolyExtStep::Sub(11315, 11302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17497PolyExtStep::Sub(11316, 11300), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17498PolyExtStep::AndEqz(6152, 11317), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17499PolyExtStep::Mul(10979, 1128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17500PolyExtStep::Add(11318, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17501PolyExtStep::Get(70), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17502PolyExtStep::Get(69), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17503PolyExtStep::Mul(11320, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17504PolyExtStep::Add(11321, 11322), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17505PolyExtStep::Get(68), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17506PolyExtStep::Mul(11323, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17507PolyExtStep::Add(11324, 11325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17508PolyExtStep::Get(67), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17509PolyExtStep::Mul(11326, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17510PolyExtStep::Add(11327, 11328), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17511PolyExtStep::Sub(11329, 11312), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17512PolyExtStep::Mul(11330, 11319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17513PolyExtStep::Sub(11331, 779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17514PolyExtStep::AndEqz(6153, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17515PolyExtStep::Get(117), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17516PolyExtStep::Get(115), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17517PolyExtStep::Mul(11333, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17518PolyExtStep::Add(11334, 11335), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17519PolyExtStep::Get(113), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17520PolyExtStep::Mul(11336, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17521PolyExtStep::Add(11337, 11338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17522PolyExtStep::Get(111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17523PolyExtStep::Mul(11339, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17524PolyExtStep::Add(11340, 11341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17525PolyExtStep::Sub(11342, 11329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17526PolyExtStep::AndEqz(6154, 11343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17527PolyExtStep::AndCond(6145, 419, 6155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17528PolyExtStep::AndCond(6156, 422, 6155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17529PolyExtStep::AndCond(6157, 425, 6155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17530PolyExtStep::GetGlobal(1, 3), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17531PolyExtStep::GetGlobal(1, 2), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17532PolyExtStep::Mul(11344, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17533PolyExtStep::Add(11345, 11346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17534PolyExtStep::GetGlobal(1, 1), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17535PolyExtStep::Mul(11347, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17536PolyExtStep::Add(11348, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17537PolyExtStep::GetGlobal(1, 0), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17538PolyExtStep::Mul(11350, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17539PolyExtStep::Add(11351, 11352), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17540PolyExtStep::Mul(11029, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17541PolyExtStep::Add(11354, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17542PolyExtStep::Mul(11125, 11355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17543PolyExtStep::Mul(11125, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17544PolyExtStep::Mul(2207, 11355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17545PolyExtStep::Mul(10979, 553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17546PolyExtStep::Add(11359, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17547PolyExtStep::Mul(11356, 11360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17548PolyExtStep::Mul(11356, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17549PolyExtStep::Mul(11358, 11360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17550PolyExtStep::Mul(11357, 11360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17551PolyExtStep::Mul(11073, 11361), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17552PolyExtStep::Sub(11365, 11363), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17553PolyExtStep::Sub(11366, 11364), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17554PolyExtStep::Sub(11367, 11362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17555PolyExtStep::AndEqz(0, 11368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17556PolyExtStep::Mul(10979, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17557PolyExtStep::Add(11369, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17558PolyExtStep::Mul(10989, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17559PolyExtStep::Mul(10999, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17560PolyExtStep::Add(11371, 11372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17561PolyExtStep::Mul(11009, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17562PolyExtStep::Add(11373, 11374), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17563PolyExtStep::Mul(11019, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17564PolyExtStep::Add(11375, 11376), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17565PolyExtStep::Add(11377, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17566PolyExtStep::Mul(11370, 11378), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17567PolyExtStep::Mul(11370, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17568PolyExtStep::Mul(568, 11378), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17569PolyExtStep::Mul(10999, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17570PolyExtStep::Add(11371, 11382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17571PolyExtStep::Mul(11009, 583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17572PolyExtStep::Add(11383, 11384), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17573PolyExtStep::Mul(11019, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17574PolyExtStep::Add(11385, 11386), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17575PolyExtStep::Add(11387, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17576PolyExtStep::Mul(11379, 11388), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17577PolyExtStep::Mul(11379, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17578PolyExtStep::Mul(11381, 11388), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17579PolyExtStep::Mul(11380, 11388), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17580PolyExtStep::Mul(11112, 11389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17581PolyExtStep::Sub(11393, 11391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17582PolyExtStep::Sub(11394, 11392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17583PolyExtStep::Sub(11395, 11390), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17584PolyExtStep::AndEqz(6159, 11396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17585PolyExtStep::Mul(11029, 731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17586PolyExtStep::Add(11397, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17587PolyExtStep::Mul(10989, 733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17588PolyExtStep::Mul(10999, 735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17589PolyExtStep::Add(11399, 11400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17590PolyExtStep::Mul(11009, 736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17591PolyExtStep::Add(11401, 11402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17592PolyExtStep::Mul(11019, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17593PolyExtStep::Add(11403, 11404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17594PolyExtStep::Add(11405, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17595PolyExtStep::Mul(11398, 11406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17596PolyExtStep::Mul(11398, 734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17597PolyExtStep::Mul(732, 11406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17598PolyExtStep::Mul(10999, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17599PolyExtStep::Add(11399, 11410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17600PolyExtStep::Mul(11009, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17601PolyExtStep::Add(11411, 11412), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17602PolyExtStep::Mul(11019, 748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17603PolyExtStep::Add(11413, 11414), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17604PolyExtStep::Add(11415, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17605PolyExtStep::Mul(11407, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17606PolyExtStep::Mul(11407, 738), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17607PolyExtStep::Mul(11409, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17608PolyExtStep::Mul(11408, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17609PolyExtStep::Mul(11140, 11417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17610PolyExtStep::Sub(11421, 11419), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17611PolyExtStep::Sub(11422, 11420), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17612PolyExtStep::Sub(11423, 11418), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17613PolyExtStep::AndEqz(6160, 11424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17614PolyExtStep::Mul(11029, 755), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17615PolyExtStep::Add(11425, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17616PolyExtStep::Mul(10989, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17617PolyExtStep::Mul(10999, 758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17618PolyExtStep::Add(11427, 11428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17619PolyExtStep::Mul(11009, 759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17620PolyExtStep::Add(11429, 11430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17621PolyExtStep::Mul(11019, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17622PolyExtStep::Add(11431, 11432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17623PolyExtStep::Add(11433, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17624PolyExtStep::Mul(11426, 11434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17625PolyExtStep::Mul(11426, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17626PolyExtStep::Mul(729, 11434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17627PolyExtStep::Mul(10999, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17628PolyExtStep::Add(11427, 11438), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17629PolyExtStep::Mul(11009, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17630PolyExtStep::Add(11439, 11440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17631PolyExtStep::Mul(11019, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17632PolyExtStep::Add(11441, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17633PolyExtStep::Add(11443, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17634PolyExtStep::Mul(11435, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17635PolyExtStep::Mul(11435, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17636PolyExtStep::Mul(11437, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17637PolyExtStep::Mul(11436, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17638PolyExtStep::Mul(11174, 11445), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17639PolyExtStep::Sub(11449, 11447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17640PolyExtStep::Sub(11450, 11448), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17641PolyExtStep::Sub(11451, 11446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17642PolyExtStep::AndEqz(6161, 11452), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17643PolyExtStep::Mul(11029, 782), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17644PolyExtStep::Add(11453, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17645PolyExtStep::Mul(11454, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17646PolyExtStep::Mul(11454, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17647PolyExtStep::Mul(752, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17648PolyExtStep::Mul(11455, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17649PolyExtStep::Mul(11455, 776), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17650PolyExtStep::Mul(11457, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17651PolyExtStep::Mul(11456, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17652PolyExtStep::Mul(11213, 11458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17653PolyExtStep::Sub(11462, 11460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17654PolyExtStep::Sub(11463, 11461), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17655PolyExtStep::Sub(11464, 11459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17656PolyExtStep::AndEqz(6162, 11465), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17657PolyExtStep::Mul(11293, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17658PolyExtStep::Mul(11293, 778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17659PolyExtStep::Mul(777, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17660PolyExtStep::Mul(11466, 11319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17661PolyExtStep::Mul(11466, 779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17662PolyExtStep::Mul(11468, 11319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17663PolyExtStep::Mul(11467, 11319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17664PolyExtStep::Mul(11252, 11469), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17665PolyExtStep::Sub(11473, 11471), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17666PolyExtStep::Sub(11474, 11472), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17667PolyExtStep::Sub(11475, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17668PolyExtStep::AndEqz(6163, 11476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17669PolyExtStep::Mul(11353, 1350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17670PolyExtStep::Add(11477, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17671PolyExtStep::Mul(11051, 11478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17672PolyExtStep::Mul(11051, 1343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17673PolyExtStep::Mul(1340, 11478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17674PolyExtStep::Mul(11353, 1353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17675PolyExtStep::Add(11482, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17676PolyExtStep::Mul(11479, 11483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17677PolyExtStep::Mul(11479, 1351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17678PolyExtStep::Mul(11481, 11483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17679PolyExtStep::Mul(11480, 11483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17680PolyExtStep::Mul(11285, 11484), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17681PolyExtStep::Sub(11488, 11486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17682PolyExtStep::Sub(11489, 11487), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17683PolyExtStep::Sub(11490, 11485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17684PolyExtStep::AndEqz(6164, 11491), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17685PolyExtStep::Mul(11353, 1360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17686PolyExtStep::Add(11492, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17687PolyExtStep::Mul(11353, 1369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17688PolyExtStep::Add(11494, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17689PolyExtStep::Mul(11493, 11495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17690PolyExtStep::Mul(11493, 1362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17691PolyExtStep::Mul(1359, 11495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17692PolyExtStep::Mul(11353, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17693PolyExtStep::Add(11499, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17694PolyExtStep::Mul(11496, 11500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17695PolyExtStep::Mul(11496, 1370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17696PolyExtStep::Mul(11498, 11500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17697PolyExtStep::Mul(11497, 11500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17698PolyExtStep::Mul(11313, 11501), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17699PolyExtStep::Sub(11505, 11503), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17700PolyExtStep::Sub(11506, 11504), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17701PolyExtStep::Sub(11507, 11502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17702PolyExtStep::AndEqz(6165, 11508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17703PolyExtStep::Mul(11353, 1379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17704PolyExtStep::Add(11509, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17705PolyExtStep::Mul(11353, 1395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17706PolyExtStep::Add(11511, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17707PolyExtStep::Mul(11510, 11512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17708PolyExtStep::Mul(11510, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17709PolyExtStep::Mul(1378, 11512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17710PolyExtStep::Mul(11353, 1396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17711PolyExtStep::Add(11516, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17712PolyExtStep::Mul(11513, 11517), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17713PolyExtStep::Mul(11513, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17714PolyExtStep::Mul(11515, 11517), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17715PolyExtStep::Mul(11514, 11517), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17716PolyExtStep::Mul(11330, 11518), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17717PolyExtStep::Sub(11522, 11520), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17718PolyExtStep::Sub(11523, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17719PolyExtStep::Sub(11524, 11519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17720PolyExtStep::AndEqz(6166, 11525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17721PolyExtStep::Mul(11353, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17722PolyExtStep::Add(11526, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17723PolyExtStep::Mul(11353, 1398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17724PolyExtStep::Add(11528, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17725PolyExtStep::Mul(11527, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17726PolyExtStep::Mul(11527, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17727PolyExtStep::Mul(1773, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17728PolyExtStep::Mul(11353, 1400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17729PolyExtStep::Add(11533, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17730PolyExtStep::Mul(11530, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17731PolyExtStep::Mul(11530, 1399), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17732PolyExtStep::Mul(11532, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17733PolyExtStep::Mul(11531, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17734PolyExtStep::Get(74), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17735PolyExtStep::Get(73), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17736PolyExtStep::Mul(11539, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17737PolyExtStep::Add(11540, 11541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17738PolyExtStep::Get(72), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17739PolyExtStep::Mul(11542, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17740PolyExtStep::Add(11543, 11544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17741PolyExtStep::Get(71), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17742PolyExtStep::Mul(11545, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17743PolyExtStep::Add(11546, 11547), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17744PolyExtStep::Sub(11548, 11329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17745PolyExtStep::Mul(11549, 11535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17746PolyExtStep::Sub(11550, 11537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17747PolyExtStep::Sub(11551, 11538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17748PolyExtStep::Sub(11552, 11536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17749PolyExtStep::AndEqz(6167, 11553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17750PolyExtStep::Mul(11353, 1407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17751PolyExtStep::Add(11554, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17752PolyExtStep::Mul(11353, 535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17753PolyExtStep::Add(11556, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17754PolyExtStep::Mul(11555, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17755PolyExtStep::Mul(11555, 1844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17756PolyExtStep::Mul(1406, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17757PolyExtStep::Mul(10989, 885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17758PolyExtStep::Mul(10999, 891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17759PolyExtStep::Add(11561, 11562), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17760PolyExtStep::Mul(11009, 894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17761PolyExtStep::Add(11563, 11564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17762PolyExtStep::Mul(11019, 897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17763PolyExtStep::Add(11565, 11566), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17764PolyExtStep::Add(11567, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17765PolyExtStep::Mul(11558, 11568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17766PolyExtStep::Mul(11558, 888), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17767PolyExtStep::Mul(11560, 11568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17768PolyExtStep::Mul(11559, 11568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17769PolyExtStep::Get(78), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17770PolyExtStep::Get(77), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17771PolyExtStep::Mul(11573, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17772PolyExtStep::Add(11574, 11575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17773PolyExtStep::Get(76), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17774PolyExtStep::Mul(11576, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17775PolyExtStep::Add(11577, 11578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17776PolyExtStep::Get(75), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17777PolyExtStep::Mul(11579, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17778PolyExtStep::Add(11580, 11581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17779PolyExtStep::Sub(11582, 11548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17780PolyExtStep::Mul(11583, 11569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17781PolyExtStep::Sub(11584, 11571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17782PolyExtStep::Sub(11585, 11572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17783PolyExtStep::Sub(11586, 11570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17784PolyExtStep::AndEqz(6168, 11587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17785PolyExtStep::Mul(10999, 903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17786PolyExtStep::Add(11561, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17787PolyExtStep::Mul(11009, 906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17788PolyExtStep::Add(11589, 11590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17789PolyExtStep::Mul(11019, 940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17790PolyExtStep::Add(11591, 11592), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17791PolyExtStep::Add(11593, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17792PolyExtStep::Mul(11029, 946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17793PolyExtStep::Add(11595, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17794PolyExtStep::Mul(11594, 11596), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17795PolyExtStep::Mul(11594, 943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17796PolyExtStep::Mul(900, 11596), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17797PolyExtStep::Mul(10979, 952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17798PolyExtStep::Add(11600, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17799PolyExtStep::Mul(11597, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17800PolyExtStep::Mul(11597, 949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17801PolyExtStep::Mul(11599, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17802PolyExtStep::Mul(11598, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17803PolyExtStep::Get(82), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17804PolyExtStep::Get(81), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17805PolyExtStep::Mul(11606, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17806PolyExtStep::Add(11607, 11608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17807PolyExtStep::Get(80), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17808PolyExtStep::Mul(11609, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17809PolyExtStep::Add(11610, 11611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17810PolyExtStep::Get(79), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17811PolyExtStep::Mul(11612, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17812PolyExtStep::Add(11613, 11614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17813PolyExtStep::Sub(11615, 11582), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17814PolyExtStep::Mul(11616, 11602), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17815PolyExtStep::Sub(11617, 11604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17816PolyExtStep::Sub(11618, 11605), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17817PolyExtStep::Sub(11619, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17818PolyExtStep::AndEqz(6169, 11620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17819PolyExtStep::Mul(10979, 961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17820PolyExtStep::Add(11621, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17821PolyExtStep::Get(86), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17822PolyExtStep::Get(85), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17823PolyExtStep::Mul(11623, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17824PolyExtStep::Add(11624, 11625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17825PolyExtStep::Get(84), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17826PolyExtStep::Mul(11626, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17827PolyExtStep::Add(11627, 11628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17828PolyExtStep::Get(83), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17829PolyExtStep::Mul(11629, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17830PolyExtStep::Add(11630, 11631), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17831PolyExtStep::Sub(11632, 11615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17832PolyExtStep::Mul(11633, 11622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17833PolyExtStep::Sub(11634, 958), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17834PolyExtStep::AndEqz(6170, 11635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17835PolyExtStep::Sub(11342, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17836PolyExtStep::AndEqz(6171, 11636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17837PolyExtStep::AndCond(6158, 428, 6172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17838PolyExtStep::Mul(11029, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17839PolyExtStep::Add(11637, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17840PolyExtStep::Mul(11029, 560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17841PolyExtStep::Add(11639, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17842PolyExtStep::Mul(11638, 11640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17843PolyExtStep::Mul(11638, 553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17844PolyExtStep::Mul(549, 11640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17845PolyExtStep::Mul(10979, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17846PolyExtStep::Add(11644, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17847PolyExtStep::Mul(11641, 11645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17848PolyExtStep::Mul(11641, 736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17849PolyExtStep::Mul(11643, 11645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17850PolyExtStep::Mul(11642, 11645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17851PolyExtStep::Mul(11073, 11646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17852PolyExtStep::Sub(11650, 11648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17853PolyExtStep::Sub(11651, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17854PolyExtStep::Sub(11652, 11647), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17855PolyExtStep::AndEqz(0, 11653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17856PolyExtStep::Mul(10979, 748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17857PolyExtStep::Add(11654, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17858PolyExtStep::Mul(10989, 729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17859PolyExtStep::Mul(10999, 754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17860PolyExtStep::Add(11656, 11657), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17861PolyExtStep::Mul(11009, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17862PolyExtStep::Add(11658, 11659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17863PolyExtStep::Mul(11019, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17864PolyExtStep::Add(11660, 11661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17865PolyExtStep::Add(11662, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17866PolyExtStep::Mul(11655, 11663), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17867PolyExtStep::Mul(11655, 755), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17868PolyExtStep::Mul(747, 11663), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17869PolyExtStep::Mul(10999, 759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17870PolyExtStep::Add(11656, 11667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17871PolyExtStep::Mul(11009, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17872PolyExtStep::Add(11668, 11669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17873PolyExtStep::Mul(11019, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17874PolyExtStep::Add(11670, 11671), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17875PolyExtStep::Add(11672, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17876PolyExtStep::Mul(11664, 11673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17877PolyExtStep::Mul(11664, 758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17878PolyExtStep::Mul(11666, 11673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17879PolyExtStep::Mul(11665, 11673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17880PolyExtStep::Mul(11112, 11674), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17881PolyExtStep::Sub(11678, 11676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17882PolyExtStep::Sub(11679, 11677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17883PolyExtStep::Sub(11680, 11675), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17884PolyExtStep::AndEqz(6174, 11681), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17885PolyExtStep::Mul(11029, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17886PolyExtStep::Add(11682, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17887PolyExtStep::Mul(10989, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17888PolyExtStep::Mul(10999, 782), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17889PolyExtStep::Add(11684, 11685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17890PolyExtStep::Mul(11009, 785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17891PolyExtStep::Add(11686, 11687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17892PolyExtStep::Mul(11019, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17893PolyExtStep::Add(11688, 11689), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17894PolyExtStep::Add(11690, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17895PolyExtStep::Mul(11683, 11691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17896PolyExtStep::Mul(11683, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17897PolyExtStep::Mul(762, 11691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17898PolyExtStep::Mul(10999, 794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17899PolyExtStep::Add(11684, 11695), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17900PolyExtStep::Mul(11009, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17901PolyExtStep::Add(11696, 11697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17902PolyExtStep::Mul(11019, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17903PolyExtStep::Add(11698, 11699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17904PolyExtStep::Add(11700, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17905PolyExtStep::Mul(11692, 11701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17906PolyExtStep::Mul(11692, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17907PolyExtStep::Mul(11694, 11701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17908PolyExtStep::Mul(11693, 11701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17909PolyExtStep::Mul(11140, 11702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17910PolyExtStep::Sub(11706, 11704), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17911PolyExtStep::Sub(11707, 11705), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17912PolyExtStep::Sub(11708, 11703), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17913PolyExtStep::AndEqz(6175, 11709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17914PolyExtStep::Mul(11029, 806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17915PolyExtStep::Add(11710, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17916PolyExtStep::Mul(10989, 812), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17917PolyExtStep::Mul(10999, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17918PolyExtStep::Add(11712, 11713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17919PolyExtStep::Mul(11009, 821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17920PolyExtStep::Add(11714, 11715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17921PolyExtStep::Mul(11019, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17922PolyExtStep::Add(11716, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17923PolyExtStep::Add(11718, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17924PolyExtStep::Mul(11711, 11719), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17925PolyExtStep::Mul(11711, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17926PolyExtStep::Mul(803, 11719), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17927PolyExtStep::Mul(10999, 861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17928PolyExtStep::Add(11712, 11723), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17929PolyExtStep::Mul(11009, 864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17930PolyExtStep::Add(11724, 11725), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17931PolyExtStep::Mul(11019, 867), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17932PolyExtStep::Add(11726, 11727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17933PolyExtStep::Add(11728, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17934PolyExtStep::Mul(11720, 11729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17935PolyExtStep::Mul(11720, 827), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17936PolyExtStep::Mul(11722, 11729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17937PolyExtStep::Mul(11721, 11729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17938PolyExtStep::Mul(11174, 11730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17939PolyExtStep::Sub(11734, 11732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17940PolyExtStep::Sub(11735, 11733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17941PolyExtStep::Sub(11736, 11731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17942PolyExtStep::AndEqz(6176, 11737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17943PolyExtStep::Mul(11029, 873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17944PolyExtStep::Add(11738, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17945PolyExtStep::Mul(11739, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17946PolyExtStep::Mul(11739, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17947PolyExtStep::Mul(870, 11270), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17948PolyExtStep::Mul(11740, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17949PolyExtStep::Mul(11740, 776), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17950PolyExtStep::Mul(11742, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17951PolyExtStep::Mul(11741, 11291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17952PolyExtStep::Mul(11213, 11743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17953PolyExtStep::Sub(11747, 11745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17954PolyExtStep::Sub(11748, 11746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17955PolyExtStep::Sub(11749, 11744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17956PolyExtStep::AndEqz(6177, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17957PolyExtStep::AndEqz(6178, 11476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17958PolyExtStep::Mul(10979, 1350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17959PolyExtStep::Add(11751, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17960PolyExtStep::Mul(11051, 11752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17961PolyExtStep::Mul(1340, 11752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17962PolyExtStep::Mul(10979, 1353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17963PolyExtStep::Add(11755, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17964PolyExtStep::Mul(11753, 11756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17965PolyExtStep::Mul(11753, 1351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17966PolyExtStep::Mul(11754, 11756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17967PolyExtStep::Mul(11480, 11756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17968PolyExtStep::Mul(11285, 11757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17969PolyExtStep::Sub(11761, 11759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17970PolyExtStep::Sub(11762, 11760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17971PolyExtStep::Sub(11763, 11758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17972PolyExtStep::AndEqz(6179, 11764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17973PolyExtStep::Mul(10979, 1369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17974PolyExtStep::Add(11765, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17975PolyExtStep::Mul(11058, 11766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17976PolyExtStep::Mul(11058, 1362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17977PolyExtStep::Mul(1359, 11766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17978PolyExtStep::Mul(10979, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17979PolyExtStep::Add(11770, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17980PolyExtStep::Mul(11767, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17981PolyExtStep::Mul(11767, 1370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17982PolyExtStep::Mul(11769, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17983PolyExtStep::Mul(11768, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17984PolyExtStep::Mul(11313, 11772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17985PolyExtStep::Sub(11776, 11774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17986PolyExtStep::Sub(11777, 11775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17987PolyExtStep::Sub(11778, 11773), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17988PolyExtStep::AndEqz(6180, 11779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17989PolyExtStep::Mul(10979, 1379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17990PolyExtStep::Add(11780, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17991PolyExtStep::Mul(10979, 1395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17992PolyExtStep::Add(11782, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17993PolyExtStep::Mul(11781, 11783), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17994PolyExtStep::Mul(11781, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17995PolyExtStep::Mul(1378, 11783), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17996PolyExtStep::Mul(10979, 1396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17997PolyExtStep::Add(11787, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17998PolyExtStep::Mul(11784, 11788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
17999PolyExtStep::Mul(11784, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18000PolyExtStep::Mul(11786, 11788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18001PolyExtStep::Mul(11785, 11788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18002PolyExtStep::Mul(11330, 11789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18003PolyExtStep::Sub(11793, 11791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18004PolyExtStep::Sub(11794, 11792), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18005PolyExtStep::Sub(11795, 11790), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18006PolyExtStep::AndEqz(6181, 11796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18007PolyExtStep::Mul(10979, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18008PolyExtStep::Add(11797, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18009PolyExtStep::Mul(10979, 1398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18010PolyExtStep::Add(11799, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18011PolyExtStep::Mul(11798, 11800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18012PolyExtStep::Mul(11798, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18013PolyExtStep::Mul(1773, 11800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18014PolyExtStep::Mul(11801, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18015PolyExtStep::Mul(11801, 1399), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18016PolyExtStep::Mul(11803, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18017PolyExtStep::Mul(11802, 11534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18018PolyExtStep::Mul(11549, 11804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18019PolyExtStep::Sub(11808, 11806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18020PolyExtStep::Sub(11809, 11807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18021PolyExtStep::Sub(11810, 11805), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18022PolyExtStep::AndEqz(6182, 11811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18023PolyExtStep::Mul(11353, 536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18024PolyExtStep::Add(11812, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18025PolyExtStep::Mul(11558, 11813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18026PolyExtStep::Mul(11558, 2207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18027PolyExtStep::Mul(11560, 11813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18028PolyExtStep::Mul(11559, 11813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18029PolyExtStep::Mul(11583, 11814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18030PolyExtStep::Sub(11818, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18031PolyExtStep::Sub(11819, 11817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18032PolyExtStep::Sub(11820, 11815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18033PolyExtStep::AndEqz(6183, 11821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18034PolyExtStep::Mul(11353, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18035PolyExtStep::Add(11822, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18036PolyExtStep::Mul(11353, 604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18037PolyExtStep::Add(11824, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18038PolyExtStep::Mul(11823, 11825), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18039PolyExtStep::Mul(11823, 597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18040PolyExtStep::Mul(587, 11825), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18041PolyExtStep::Mul(11353, 618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18042PolyExtStep::Add(11829, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18043PolyExtStep::Mul(11826, 11830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18044PolyExtStep::Mul(11826, 611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18045PolyExtStep::Mul(11828, 11830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18046PolyExtStep::Mul(11827, 11830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18047PolyExtStep::Mul(11616, 11831), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18048PolyExtStep::Sub(11835, 11833), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18049PolyExtStep::Sub(11836, 11834), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18050PolyExtStep::Sub(11837, 11832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18051PolyExtStep::AndEqz(6184, 11838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18052PolyExtStep::Mul(11353, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18053PolyExtStep::Add(11839, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18054PolyExtStep::Mul(11353, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18055PolyExtStep::Add(11841, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18056PolyExtStep::Mul(11840, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18057PolyExtStep::Mul(11840, 635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18058PolyExtStep::Mul(625, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18059PolyExtStep::Mul(11353, 648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18060PolyExtStep::Add(11846, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18061PolyExtStep::Mul(11843, 11847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18062PolyExtStep::Mul(11843, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18063PolyExtStep::Mul(11845, 11847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18064PolyExtStep::Mul(11844, 11847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18065PolyExtStep::Mul(11633, 11848), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18066PolyExtStep::Sub(11852, 11850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18067PolyExtStep::Sub(11853, 11851), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18068PolyExtStep::Sub(11854, 11849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18069PolyExtStep::AndEqz(6185, 11855), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18070PolyExtStep::Mul(11353, 662), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18071PolyExtStep::Add(11856, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18072PolyExtStep::Mul(11353, 672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18073PolyExtStep::Add(11858, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18074PolyExtStep::Mul(11857, 11859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18075PolyExtStep::Mul(11857, 669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18076PolyExtStep::Mul(655, 11859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18077PolyExtStep::Mul(11353, 548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18078PolyExtStep::Add(11863, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18079PolyExtStep::Mul(11860, 11864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18080PolyExtStep::Mul(11860, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18081PolyExtStep::Mul(11862, 11864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18082PolyExtStep::Mul(11861, 11864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18083PolyExtStep::Get(90), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18084PolyExtStep::Get(89), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18085PolyExtStep::Mul(11869, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18086PolyExtStep::Add(11870, 11871), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18087PolyExtStep::Get(88), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18088PolyExtStep::Mul(11872, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18089PolyExtStep::Add(11873, 11874), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18090PolyExtStep::Get(87), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18091PolyExtStep::Mul(11875, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18092PolyExtStep::Add(11876, 11877), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18093PolyExtStep::Sub(11878, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18094PolyExtStep::Mul(11879, 11865), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18095PolyExtStep::Sub(11880, 11867), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18096PolyExtStep::Sub(11881, 11868), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18097PolyExtStep::Sub(11882, 11866), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18098PolyExtStep::AndEqz(6186, 11883), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18099PolyExtStep::Mul(10989, 1046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18100PolyExtStep::Mul(10999, 1052), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18101PolyExtStep::Add(11884, 11885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18102PolyExtStep::Mul(11009, 1055), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18103PolyExtStep::Add(11886, 11887), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18104PolyExtStep::Mul(11019, 1058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18105PolyExtStep::Add(11888, 11889), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18106PolyExtStep::Add(11890, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18107PolyExtStep::Mul(10999, 1064), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18108PolyExtStep::Add(11884, 11892), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18109PolyExtStep::Mul(11009, 2659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18110PolyExtStep::Add(11893, 11894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18111PolyExtStep::Mul(11019, 2660), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18112PolyExtStep::Add(11895, 11896), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18113PolyExtStep::Add(11897, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18114PolyExtStep::Mul(11891, 11898), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18115PolyExtStep::Mul(11891, 1061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18116PolyExtStep::Mul(1049, 11898), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18117PolyExtStep::Mul(11029, 2667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18118PolyExtStep::Add(11902, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18119PolyExtStep::Mul(11899, 11903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18120PolyExtStep::Mul(11899, 2666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18121PolyExtStep::Mul(11901, 11903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18122PolyExtStep::Mul(11900, 11903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18123PolyExtStep::Get(94), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18124PolyExtStep::Get(93), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18125PolyExtStep::Mul(11908, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18126PolyExtStep::Add(11909, 11910), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18127PolyExtStep::Get(92), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18128PolyExtStep::Mul(11911, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18129PolyExtStep::Add(11912, 11913), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18130PolyExtStep::Get(91), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18131PolyExtStep::Mul(11914, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18132PolyExtStep::Add(11915, 11916), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18133PolyExtStep::Sub(11917, 11878), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18134PolyExtStep::Mul(11918, 11904), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18135PolyExtStep::Sub(11919, 11906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18136PolyExtStep::Sub(11920, 11907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18137PolyExtStep::Sub(11921, 11905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18138PolyExtStep::AndEqz(6187, 11922), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18139PolyExtStep::Mul(10979, 2673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18140PolyExtStep::Add(11923, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18141PolyExtStep::Mul(10979, 2683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18142PolyExtStep::Add(11925, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18143PolyExtStep::Mul(11924, 11926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18144PolyExtStep::Mul(11924, 2682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18145PolyExtStep::Mul(2672, 11926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18146PolyExtStep::Get(98), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18147PolyExtStep::Get(97), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18148PolyExtStep::Mul(11930, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18149PolyExtStep::Add(11931, 11932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18150PolyExtStep::Get(96), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18151PolyExtStep::Mul(11933, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18152PolyExtStep::Add(11934, 11935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18153PolyExtStep::Get(95), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18154PolyExtStep::Mul(11936, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18155PolyExtStep::Add(11937, 11938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18156PolyExtStep::Sub(11939, 11917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18157PolyExtStep::Mul(11940, 11927), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18158PolyExtStep::Sub(11941, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18159PolyExtStep::Sub(11942, 11928), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18160PolyExtStep::AndEqz(6188, 11943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18161PolyExtStep::Sub(11342, 11939), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18162PolyExtStep::AndEqz(6189, 11944), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18163PolyExtStep::AndCond(6173, 431, 6190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18164PolyExtStep::Mul(11029, 1128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18165PolyExtStep::Add(11945, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18166PolyExtStep::Mul(11029, 1341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18167PolyExtStep::Add(11947, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18168PolyExtStep::Mul(11946, 11948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18169PolyExtStep::Mul(11946, 1340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18170PolyExtStep::Mul(779, 11948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18171PolyExtStep::Mul(10979, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18172PolyExtStep::Add(11952, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18173PolyExtStep::Mul(11949, 11953), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18174PolyExtStep::Mul(11949, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18175PolyExtStep::Mul(11951, 11953), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18176PolyExtStep::Mul(11950, 11953), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18177PolyExtStep::Mul(11073, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18178PolyExtStep::Sub(11958, 11956), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18179PolyExtStep::Sub(11959, 11957), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18180PolyExtStep::Sub(11960, 11955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18181PolyExtStep::AndEqz(0, 11961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18182PolyExtStep::Mul(10979, 1406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18183PolyExtStep::Add(11962, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18184PolyExtStep::Mul(10989, 1407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18185PolyExtStep::Mul(10999, 535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18186PolyExtStep::Add(11964, 11965), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18187PolyExtStep::Mul(11009, 2207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18188PolyExtStep::Add(11966, 11967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18189PolyExtStep::Mul(11019, 536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18190PolyExtStep::Add(11968, 11969), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18191PolyExtStep::Add(11970, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18192PolyExtStep::Mul(11963, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18193PolyExtStep::Mul(11963, 1844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18194PolyExtStep::Mul(1400, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18195PolyExtStep::Mul(10999, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18196PolyExtStep::Add(11964, 11975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18197PolyExtStep::Mul(11009, 597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18198PolyExtStep::Add(11976, 11977), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18199PolyExtStep::Mul(11019, 604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18200PolyExtStep::Add(11978, 11979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18201PolyExtStep::Add(11980, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18202PolyExtStep::Mul(11972, 11981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18203PolyExtStep::Mul(11972, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18204PolyExtStep::Mul(11974, 11981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18205PolyExtStep::Mul(11973, 11981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18206PolyExtStep::Mul(11112, 11982), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18207PolyExtStep::Sub(11986, 11984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18208PolyExtStep::Sub(11987, 11985), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18209PolyExtStep::Sub(11988, 11983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18210PolyExtStep::AndEqz(6192, 11989), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18211PolyExtStep::Mul(11029, 618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18212PolyExtStep::Add(11990, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18213PolyExtStep::Mul(10989, 625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18214PolyExtStep::Mul(10999, 635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18215PolyExtStep::Add(11992, 11993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18216PolyExtStep::Mul(11009, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18217PolyExtStep::Add(11994, 11995), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18218PolyExtStep::Mul(11019, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18219PolyExtStep::Add(11996, 11997), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18220PolyExtStep::Add(11998, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18221PolyExtStep::Mul(11991, 11999), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18222PolyExtStep::Mul(11991, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18223PolyExtStep::Mul(611, 11999), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18224PolyExtStep::Mul(10999, 655), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18225PolyExtStep::Add(11992, 12003), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18226PolyExtStep::Mul(11009, 662), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18227PolyExtStep::Add(12004, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18228PolyExtStep::Mul(11019, 669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18229PolyExtStep::Add(12006, 12007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18230PolyExtStep::Add(12008, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18231PolyExtStep::Mul(12000, 12009), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18232PolyExtStep::Mul(12000, 648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18233PolyExtStep::Mul(12002, 12009), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18234PolyExtStep::Mul(12001, 12009), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18235PolyExtStep::Mul(11140, 12010), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18236PolyExtStep::Sub(12014, 12012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18237PolyExtStep::Sub(12015, 12013), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18238PolyExtStep::Sub(12016, 12011), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18239PolyExtStep::AndEqz(6193, 12017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18240PolyExtStep::Mul(11029, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18241PolyExtStep::Add(12018, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18242PolyExtStep::Mul(10979, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18243PolyExtStep::Add(12020, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18244PolyExtStep::Mul(12019, 12021), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18245PolyExtStep::Mul(12019, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18246PolyExtStep::Mul(672, 12021), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18247PolyExtStep::Mul(12022, 11148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18248PolyExtStep::Mul(12022, 560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18249PolyExtStep::Mul(12024, 11148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18250PolyExtStep::Mul(12023, 11148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18251PolyExtStep::Mul(11174, 12025), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18252PolyExtStep::Sub(12029, 12027), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18253PolyExtStep::Sub(12030, 12028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18254PolyExtStep::Sub(12031, 12026), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18255PolyExtStep::AndEqz(6194, 12032), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18256PolyExtStep::Mul(10979, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18257PolyExtStep::Add(12033, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18258PolyExtStep::Mul(10979, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18259PolyExtStep::Add(12035, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18260PolyExtStep::Mul(12034, 12036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18261PolyExtStep::Mul(12034, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18262PolyExtStep::Mul(570, 12036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18263PolyExtStep::Mul(10989, 583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18264PolyExtStep::Mul(10999, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18265PolyExtStep::Add(12040, 12041), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18266PolyExtStep::Mul(11009, 731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18267PolyExtStep::Add(12042, 12043), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18268PolyExtStep::Mul(11019, 733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18269PolyExtStep::Add(12044, 12045), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18270PolyExtStep::Add(12046, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18271PolyExtStep::Mul(12037, 12047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18272PolyExtStep::Mul(12037, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18273PolyExtStep::Mul(12039, 12047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18274PolyExtStep::Mul(12038, 12047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18275PolyExtStep::Mul(11213, 12048), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18276PolyExtStep::Sub(12052, 12050), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18277PolyExtStep::Sub(12053, 12051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18278PolyExtStep::Sub(12054, 12049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18279PolyExtStep::AndEqz(6195, 12055), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18280PolyExtStep::Add(12040, 11400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18281PolyExtStep::Add(12056, 11402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18282PolyExtStep::Add(12057, 11404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18283PolyExtStep::Add(12058, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18284PolyExtStep::Mul(11029, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18285PolyExtStep::Add(12060, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18286PolyExtStep::Mul(12059, 12061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18287PolyExtStep::Mul(12059, 738), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18288PolyExtStep::Mul(734, 12061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18289PolyExtStep::Mul(11353, 1105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18290PolyExtStep::Add(12065, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18291PolyExtStep::Mul(12062, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18292PolyExtStep::Mul(12062, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18293PolyExtStep::Mul(12064, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18294PolyExtStep::Mul(12063, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18295PolyExtStep::Mul(11252, 12067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18296PolyExtStep::Sub(12071, 12069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18297PolyExtStep::Sub(12072, 12070), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18298PolyExtStep::Sub(12073, 12068), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18299PolyExtStep::AndEqz(6196, 12074), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18300PolyExtStep::Mul(11353, 1111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18301PolyExtStep::Add(12075, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18302PolyExtStep::Mul(11353, 1116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18303PolyExtStep::Add(12077, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18304PolyExtStep::Mul(12076, 12078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18305PolyExtStep::Mul(12076, 777), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18306PolyExtStep::Mul(776, 12078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18307PolyExtStep::Mul(12079, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18308PolyExtStep::Mul(12079, 778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18309PolyExtStep::Mul(12081, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18310PolyExtStep::Mul(12080, 11298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18311PolyExtStep::Mul(11285, 12082), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18312PolyExtStep::Sub(12086, 12084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18313PolyExtStep::Sub(12087, 12085), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18314PolyExtStep::Sub(12088, 12083), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18315PolyExtStep::AndEqz(6197, 12089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18316PolyExtStep::Mul(10989, 754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18317PolyExtStep::Mul(10999, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18318PolyExtStep::Add(12090, 12091), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18319PolyExtStep::Mul(11009, 758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18320PolyExtStep::Add(12092, 12093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18321PolyExtStep::Mul(11019, 759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18322PolyExtStep::Add(12094, 12095), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18323PolyExtStep::Add(12096, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18324PolyExtStep::Mul(10999, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18325PolyExtStep::Add(12090, 12098), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18326PolyExtStep::Mul(11009, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18327PolyExtStep::Add(12099, 12100), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18328PolyExtStep::Mul(11019, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18329PolyExtStep::Add(12101, 12102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18330PolyExtStep::Add(12103, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18331PolyExtStep::Mul(12097, 12104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18332PolyExtStep::Mul(12097, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18333PolyExtStep::Mul(756, 12104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18334PolyExtStep::Mul(11029, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18335PolyExtStep::Add(12108, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18336PolyExtStep::Mul(12105, 12109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18337PolyExtStep::Mul(12105, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18338PolyExtStep::Mul(12107, 12109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18339PolyExtStep::Mul(12106, 12109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18340PolyExtStep::Mul(11313, 12110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18341PolyExtStep::Sub(12114, 12112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18342PolyExtStep::Sub(12115, 12113), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18343PolyExtStep::Sub(12116, 12111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18344PolyExtStep::AndEqz(6198, 12117), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18345PolyExtStep::Mul(10979, 785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18346PolyExtStep::Add(12118, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18347PolyExtStep::Mul(10979, 794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18348PolyExtStep::Add(12120, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18349PolyExtStep::Mul(12119, 12121), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18350PolyExtStep::Mul(12119, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18351PolyExtStep::Mul(782, 12121), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18352PolyExtStep::Mul(11330, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18353PolyExtStep::Sub(12125, 12124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18354PolyExtStep::Sub(12126, 12123), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18355PolyExtStep::AndEqz(6199, 12127), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18356PolyExtStep::AndEqz(6200, 11343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18357PolyExtStep::AndCond(6191, 434, 6201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18358PolyExtStep::Mul(10989, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18359PolyExtStep::Mul(10999, 553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18360PolyExtStep::Add(12128, 12129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18361PolyExtStep::Mul(11009, 560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18362PolyExtStep::Add(12130, 12131), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18363PolyExtStep::Mul(11019, 561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18364PolyExtStep::Add(12132, 12133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18365PolyExtStep::Add(12134, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18366PolyExtStep::Mul(12019, 12135), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18367PolyExtStep::Mul(12019, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18368PolyExtStep::Mul(672, 12135), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18369PolyExtStep::Mul(10999, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18370PolyExtStep::Add(12128, 12139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18371PolyExtStep::Mul(11009, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18372PolyExtStep::Add(12140, 12141), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18373PolyExtStep::Mul(11019, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18374PolyExtStep::Add(12142, 12143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18375PolyExtStep::Add(12144, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18376PolyExtStep::Mul(12136, 12145), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18377PolyExtStep::Mul(12136, 568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18378PolyExtStep::Mul(12138, 12145), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18379PolyExtStep::Mul(12137, 12145), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18380PolyExtStep::Mul(11174, 12146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18381PolyExtStep::Sub(12150, 12148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18382PolyExtStep::Sub(12151, 12149), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18383PolyExtStep::Sub(12152, 12147), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18384PolyExtStep::AndEqz(6194, 12153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18385PolyExtStep::Mul(11029, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18386PolyExtStep::Add(12154, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18387PolyExtStep::Mul(12155, 12036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18388PolyExtStep::Mul(12155, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18389PolyExtStep::Mul(571, 12036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18390PolyExtStep::Mul(10979, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18391PolyExtStep::Add(12159, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18392PolyExtStep::Mul(12156, 12160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18393PolyExtStep::Mul(12156, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18394PolyExtStep::Mul(12158, 12160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18395PolyExtStep::Mul(12157, 12160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18396PolyExtStep::Mul(11213, 12161), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18397PolyExtStep::Sub(12165, 12163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18398PolyExtStep::Sub(12166, 12164), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18399PolyExtStep::Sub(12167, 12162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18400PolyExtStep::AndEqz(6203, 12168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18401PolyExtStep::Mul(10979, 736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18402PolyExtStep::Add(12169, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18403PolyExtStep::Mul(10979, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18404PolyExtStep::Add(12171, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18405PolyExtStep::Mul(12170, 12172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18406PolyExtStep::Mul(12170, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18407PolyExtStep::Mul(735, 12172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18408PolyExtStep::Mul(10989, 748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18409PolyExtStep::Mul(10999, 755), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18410PolyExtStep::Add(12176, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18411PolyExtStep::Mul(11009, 754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18412PolyExtStep::Add(12178, 12179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18413PolyExtStep::Mul(11019, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18414PolyExtStep::Add(12180, 12181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18415PolyExtStep::Add(12182, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18416PolyExtStep::Mul(12173, 12183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18417PolyExtStep::Mul(12173, 729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18418PolyExtStep::Mul(12175, 12183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18419PolyExtStep::Mul(12174, 12183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18420PolyExtStep::Mul(11252, 12184), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18421PolyExtStep::Sub(12188, 12186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18422PolyExtStep::Sub(12189, 12187), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18423PolyExtStep::Sub(12190, 12185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18424PolyExtStep::AndEqz(6204, 12191), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18425PolyExtStep::Add(12176, 11428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18426PolyExtStep::Add(12192, 11430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18427PolyExtStep::Add(12193, 11432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18428PolyExtStep::Add(12194, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18429PolyExtStep::Mul(11029, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18430PolyExtStep::Add(12196, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18431PolyExtStep::Mul(12195, 12197), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18432PolyExtStep::Mul(12195, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18433PolyExtStep::Mul(757, 12197), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18434PolyExtStep::Mul(12198, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18435PolyExtStep::Mul(12198, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18436PolyExtStep::Mul(12200, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18437PolyExtStep::Mul(12199, 12066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18438PolyExtStep::Mul(11285, 12201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18439PolyExtStep::Sub(12205, 12203), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18440PolyExtStep::Sub(12206, 12204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18441PolyExtStep::Sub(12207, 12202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18442PolyExtStep::AndEqz(6205, 12208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18443PolyExtStep::Mul(11353, 1122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18444PolyExtStep::Add(12209, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18445PolyExtStep::Mul(12079, 12210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18446PolyExtStep::Mul(12081, 12210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18447PolyExtStep::Mul(12080, 12210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18448PolyExtStep::Mul(11313, 12211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18449PolyExtStep::Sub(12214, 12212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18450PolyExtStep::Sub(12215, 12213), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18451PolyExtStep::Sub(12216, 12083), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18452PolyExtStep::AndEqz(6206, 12217), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18453PolyExtStep::Mul(10989, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18454PolyExtStep::Mul(10999, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18455PolyExtStep::Add(12218, 12219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18456PolyExtStep::Mul(11009, 782), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18457PolyExtStep::Add(12220, 12221), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18458PolyExtStep::Mul(11019, 785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18459PolyExtStep::Add(12222, 12223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18460PolyExtStep::Add(12224, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18461PolyExtStep::Mul(10999, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18462PolyExtStep::Add(12218, 12226), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18463PolyExtStep::Mul(11009, 794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18464PolyExtStep::Add(12227, 12228), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18465PolyExtStep::Mul(11019, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18466PolyExtStep::Add(12229, 12230), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18467PolyExtStep::Add(12231, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18468PolyExtStep::Mul(12225, 12232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18469PolyExtStep::Mul(12225, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18470PolyExtStep::Mul(771, 12232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18471PolyExtStep::Mul(11029, 803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18472PolyExtStep::Add(12236, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18473PolyExtStep::Mul(12233, 12237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18474PolyExtStep::Mul(12233, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18475PolyExtStep::Mul(12235, 12237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18476PolyExtStep::Mul(12234, 12237), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18477PolyExtStep::Mul(11330, 12238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18478PolyExtStep::Sub(12242, 12240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18479PolyExtStep::Sub(12243, 12241), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18480PolyExtStep::Sub(12244, 12239), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18481PolyExtStep::AndEqz(6207, 12245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18482PolyExtStep::Mul(10979, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18483PolyExtStep::Add(12246, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18484PolyExtStep::Mul(10979, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18485PolyExtStep::Add(12248, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18486PolyExtStep::Mul(12247, 12249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18487PolyExtStep::Mul(12247, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18488PolyExtStep::Mul(806, 12249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18489PolyExtStep::Mul(11549, 12250), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18490PolyExtStep::Sub(12253, 12252), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18491PolyExtStep::Sub(12254, 12251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18492PolyExtStep::AndEqz(6208, 12255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18493PolyExtStep::Sub(11342, 11548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18494PolyExtStep::AndEqz(6209, 12256), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18495PolyExtStep::AndCond(6202, 437, 6210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18496PolyExtStep::Mul(11029, 1061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18497PolyExtStep::Add(12257, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18498PolyExtStep::Mul(11029, 2659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18499PolyExtStep::Add(12259, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18500PolyExtStep::Mul(12258, 12260), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18501PolyExtStep::Mul(12258, 1064), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18502PolyExtStep::Mul(1058, 12260), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18503PolyExtStep::Mul(10989, 1105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18504PolyExtStep::Mul(10999, 776), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18505PolyExtStep::Add(12264, 12265), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18506PolyExtStep::Mul(11009, 1111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18507PolyExtStep::Add(12266, 12267), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18508PolyExtStep::Mul(11019, 777), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18509PolyExtStep::Add(12268, 12269), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18510PolyExtStep::Add(12270, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18511PolyExtStep::Mul(12261, 12271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18512PolyExtStep::Mul(12261, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18513PolyExtStep::Mul(12263, 12271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18514PolyExtStep::Mul(12262, 12271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18515PolyExtStep::Mul(11073, 12272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18516PolyExtStep::Sub(12276, 12274), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18517PolyExtStep::Sub(12277, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18518PolyExtStep::Sub(12278, 12273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18519PolyExtStep::AndEqz(0, 12279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18520PolyExtStep::Mul(10999, 778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18521PolyExtStep::Add(12264, 12280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18522PolyExtStep::Mul(11009, 1122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18523PolyExtStep::Add(12281, 12282), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18524PolyExtStep::Mul(11019, 779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18525PolyExtStep::Add(12283, 12284), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18526PolyExtStep::Add(12285, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18527PolyExtStep::Mul(10989, 1340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18528PolyExtStep::Mul(10999, 1341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18529PolyExtStep::Add(12287, 12288), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18530PolyExtStep::Mul(11009, 1343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18531PolyExtStep::Add(12289, 12290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18532PolyExtStep::Mul(11019, 1350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18533PolyExtStep::Add(12291, 12292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18534PolyExtStep::Add(12293, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18535PolyExtStep::Mul(12286, 12294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18536PolyExtStep::Mul(12286, 1128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18537PolyExtStep::Mul(1116, 12294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18538PolyExtStep::Mul(10999, 1353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18539PolyExtStep::Add(12287, 12298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18540PolyExtStep::Mul(11009, 1359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18541PolyExtStep::Add(12299, 12300), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18542PolyExtStep::Mul(11019, 1360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18543PolyExtStep::Add(12301, 12302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18544PolyExtStep::Add(12303, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18545PolyExtStep::Mul(12295, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18546PolyExtStep::Mul(12295, 1351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18547PolyExtStep::Mul(12297, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18548PolyExtStep::Mul(12296, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18549PolyExtStep::Mul(11112, 12305), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18550PolyExtStep::Sub(12309, 12307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18551PolyExtStep::Sub(12310, 12308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18552PolyExtStep::Sub(12311, 12306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18553PolyExtStep::AndEqz(6212, 12312), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18554PolyExtStep::Mul(10989, 1369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18555PolyExtStep::Mul(10999, 1370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18556PolyExtStep::Add(12313, 12314), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18557PolyExtStep::Mul(11009, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18558PolyExtStep::Add(12315, 12316), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18559PolyExtStep::Mul(11019, 1378), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18560PolyExtStep::Add(12317, 12318), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18561PolyExtStep::Add(12319, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18562PolyExtStep::Mul(10999, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18563PolyExtStep::Add(12313, 12321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18564PolyExtStep::Mul(11009, 1395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18565PolyExtStep::Add(12322, 12323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18566PolyExtStep::Mul(11019, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18567PolyExtStep::Add(12324, 12325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18568PolyExtStep::Add(12326, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18569PolyExtStep::Mul(12320, 12327), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18570PolyExtStep::Mul(12320, 1379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18571PolyExtStep::Mul(1362, 12327), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18572PolyExtStep::Mul(10989, 1773), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18573PolyExtStep::Mul(10999, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18574PolyExtStep::Add(12331, 12332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18575PolyExtStep::Mul(11009, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18576PolyExtStep::Add(12333, 12334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18577PolyExtStep::Mul(11019, 1398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18578PolyExtStep::Add(12335, 12336), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18579PolyExtStep::Add(12337, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18580PolyExtStep::Mul(12328, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18581PolyExtStep::Mul(12328, 1396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18582PolyExtStep::Mul(12330, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18583PolyExtStep::Mul(12329, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18584PolyExtStep::Mul(11140, 12339), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18585PolyExtStep::Sub(12343, 12341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18586PolyExtStep::Sub(12344, 12342), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18587PolyExtStep::Sub(12345, 12340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18588PolyExtStep::AndEqz(6213, 12346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18589PolyExtStep::Mul(10999, 1400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18590PolyExtStep::Add(12331, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18591PolyExtStep::Mul(11009, 1406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18592PolyExtStep::Add(12348, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18593PolyExtStep::Mul(11019, 1407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18594PolyExtStep::Add(12350, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18595PolyExtStep::Add(12352, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18596PolyExtStep::Mul(10989, 535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18597PolyExtStep::Mul(10999, 2207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18598PolyExtStep::Add(12354, 12355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18599PolyExtStep::Mul(11009, 536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18600PolyExtStep::Add(12356, 12357), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18601PolyExtStep::Mul(11019, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18602PolyExtStep::Add(12358, 12359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18603PolyExtStep::Add(12360, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18604PolyExtStep::Mul(12353, 12361), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18605PolyExtStep::Mul(12353, 1844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18606PolyExtStep::Mul(1399, 12361), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18607PolyExtStep::Mul(10999, 597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18608PolyExtStep::Add(12354, 12365), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18609PolyExtStep::Mul(11009, 604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18610PolyExtStep::Add(12366, 12367), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18611PolyExtStep::Mul(11019, 611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18612PolyExtStep::Add(12368, 12369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18613PolyExtStep::Add(12370, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18614PolyExtStep::Mul(12362, 12371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18615PolyExtStep::Mul(12362, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18616PolyExtStep::Mul(12364, 12371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18617PolyExtStep::Mul(12363, 12371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18618PolyExtStep::Mul(11174, 12372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18619PolyExtStep::Sub(12376, 12374), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18620PolyExtStep::Sub(12377, 12375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18621PolyExtStep::Sub(12378, 12373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18622PolyExtStep::AndEqz(6214, 12379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18623PolyExtStep::Mul(10999, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18624PolyExtStep::Add(11992, 12380), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18625PolyExtStep::Mul(11009, 635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18626PolyExtStep::Add(12381, 12382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18627PolyExtStep::Mul(11019, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18628PolyExtStep::Add(12383, 12384), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18629PolyExtStep::Add(12385, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18630PolyExtStep::Mul(10999, 648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18631PolyExtStep::Add(11992, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18632PolyExtStep::Mul(11009, 655), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18633PolyExtStep::Add(12388, 12389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18634PolyExtStep::Mul(11019, 662), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18635PolyExtStep::Add(12390, 12391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18636PolyExtStep::Add(12392, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18637PolyExtStep::Mul(12386, 12393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18638PolyExtStep::Mul(12386, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18639PolyExtStep::Mul(618, 12393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18640PolyExtStep::Mul(10989, 672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18641PolyExtStep::Mul(10999, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18642PolyExtStep::Add(12397, 12398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18643PolyExtStep::Mul(11009, 548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18644PolyExtStep::Add(12399, 12400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18645PolyExtStep::Mul(11019, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18646PolyExtStep::Add(12401, 12402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18647PolyExtStep::Add(12403, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18648PolyExtStep::Mul(12394, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18649PolyExtStep::Mul(12394, 669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18650PolyExtStep::Mul(12396, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18651PolyExtStep::Mul(12395, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18652PolyExtStep::Mul(11213, 12405), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18653PolyExtStep::Sub(12409, 12407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18654PolyExtStep::Sub(12410, 12408), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18655PolyExtStep::Sub(12411, 12406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18656PolyExtStep::AndEqz(6215, 12412), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18657PolyExtStep::Add(12397, 12129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18658PolyExtStep::Add(12413, 12131), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18659PolyExtStep::Add(12414, 12133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18660PolyExtStep::Add(12415, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18661PolyExtStep::Mul(10989, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18662PolyExtStep::Add(12417, 11153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18663PolyExtStep::Add(12418, 11155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18664PolyExtStep::Add(12419, 11157), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18665PolyExtStep::Add(12420, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18666PolyExtStep::Mul(12416, 12421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18667PolyExtStep::Mul(12416, 568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18668PolyExtStep::Mul(552, 12421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18669PolyExtStep::Add(12417, 11179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18670PolyExtStep::Add(12425, 11181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18671PolyExtStep::Add(12426, 11183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18672PolyExtStep::Add(12427, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18673PolyExtStep::Mul(12422, 12428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18674PolyExtStep::Mul(12422, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18675PolyExtStep::Mul(12424, 12428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18676PolyExtStep::Mul(12423, 12428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18677PolyExtStep::Mul(11252, 12429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18678PolyExtStep::Sub(12433, 12431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18679PolyExtStep::Sub(12434, 12432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18680PolyExtStep::Sub(12435, 12430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18681PolyExtStep::AndEqz(6216, 12436), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18682PolyExtStep::Mul(11187, 11398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18683PolyExtStep::Mul(11187, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18684PolyExtStep::Mul(583, 11398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18685PolyExtStep::Mul(11029, 734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18686PolyExtStep::Add(12440, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18687PolyExtStep::Mul(12437, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18688PolyExtStep::Mul(12437, 733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18689PolyExtStep::Mul(12439, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18690PolyExtStep::Mul(12438, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18691PolyExtStep::Mul(11285, 12442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18692PolyExtStep::Sub(12446, 12444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18693PolyExtStep::Sub(12447, 12445), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18694PolyExtStep::Sub(12448, 12443), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18695PolyExtStep::AndEqz(6217, 12449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18696PolyExtStep::Mul(11029, 736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18697PolyExtStep::Add(12450, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18698PolyExtStep::Mul(11029, 738), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18699PolyExtStep::Add(12452, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18700PolyExtStep::Mul(12451, 12453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18701PolyExtStep::Mul(12451, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18702PolyExtStep::Mul(735, 12453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18703PolyExtStep::Mul(11029, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18704PolyExtStep::Add(12457, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18705PolyExtStep::Mul(12454, 12458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18706PolyExtStep::Mul(12454, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18707PolyExtStep::Mul(12456, 12458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18708PolyExtStep::Mul(12455, 12458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18709PolyExtStep::Mul(11313, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18710PolyExtStep::Sub(12463, 12461), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18711PolyExtStep::Sub(12464, 12462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18712PolyExtStep::Sub(12465, 12460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18713PolyExtStep::AndEqz(6218, 12466), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18714PolyExtStep::Mul(11029, 729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18715PolyExtStep::Add(12467, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18716PolyExtStep::Mul(11029, 754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18717PolyExtStep::Add(12469, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18718PolyExtStep::Mul(12468, 12470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18719PolyExtStep::Mul(12468, 755), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18720PolyExtStep::Mul(748, 12470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18721PolyExtStep::Mul(10979, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18722PolyExtStep::Add(12474, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18723PolyExtStep::Mul(12471, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18724PolyExtStep::Mul(12471, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18725PolyExtStep::Mul(12473, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18726PolyExtStep::Mul(12472, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18727PolyExtStep::Mul(11330, 12476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18728PolyExtStep::Sub(12480, 12478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18729PolyExtStep::Sub(12481, 12479), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18730PolyExtStep::Sub(12482, 12477), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18731PolyExtStep::AndEqz(6219, 12483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18732PolyExtStep::Mul(10979, 759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18733PolyExtStep::Add(12484, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18734PolyExtStep::Mul(10979, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18735PolyExtStep::Add(12486, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18736PolyExtStep::Mul(12485, 12487), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18737PolyExtStep::Mul(12485, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18738PolyExtStep::Mul(758, 12487), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18739PolyExtStep::Mul(10979, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18740PolyExtStep::Add(12491, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18741PolyExtStep::Mul(12488, 12492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18742PolyExtStep::Mul(12488, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18743PolyExtStep::Mul(12490, 12492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18744PolyExtStep::Mul(12489, 12492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18745PolyExtStep::Mul(11549, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18746PolyExtStep::Sub(12497, 12495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18747PolyExtStep::Sub(12498, 12496), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18748PolyExtStep::Sub(12499, 12494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18749PolyExtStep::AndEqz(6220, 12500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18750PolyExtStep::Mul(10979, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18751PolyExtStep::Add(12501, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18752PolyExtStep::Mul(12502, 12119), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18753PolyExtStep::Mul(12502, 782), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18754PolyExtStep::Mul(771, 12119), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18755PolyExtStep::Mul(10979, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18756PolyExtStep::Add(12506, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18757PolyExtStep::Mul(12503, 12507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18758PolyExtStep::Mul(12503, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18759PolyExtStep::Mul(12505, 12507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18760PolyExtStep::Mul(12504, 12507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18761PolyExtStep::Mul(11583, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18762PolyExtStep::Sub(12512, 12510), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18763PolyExtStep::Sub(12513, 12511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18764PolyExtStep::Sub(12514, 12509), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18765PolyExtStep::AndEqz(6221, 12515), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18766PolyExtStep::Mul(10979, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18767PolyExtStep::Add(12516, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18768PolyExtStep::Mul(10979, 803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18769PolyExtStep::Add(12518, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18770PolyExtStep::Mul(12517, 12519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18771PolyExtStep::Mul(12517, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18772PolyExtStep::Mul(794, 12519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18773PolyExtStep::Mul(12520, 12247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18774PolyExtStep::Mul(12520, 806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18775PolyExtStep::Mul(12522, 12247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18776PolyExtStep::Mul(12521, 12247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18777PolyExtStep::Mul(11616, 12523), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18778PolyExtStep::Sub(12527, 12525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18779PolyExtStep::Sub(12528, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18780PolyExtStep::Sub(12529, 12524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18781PolyExtStep::AndEqz(6222, 12530), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18782PolyExtStep::Mul(10979, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18783PolyExtStep::Add(12531, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18784PolyExtStep::Mul(10979, 821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18785PolyExtStep::Add(12533, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18786PolyExtStep::Mul(12532, 12534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18787PolyExtStep::Mul(12532, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18788PolyExtStep::Mul(812, 12534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18789PolyExtStep::Mul(10979, 827), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18790PolyExtStep::Add(12538, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18791PolyExtStep::Mul(12535, 12539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18792PolyExtStep::Mul(12535, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18793PolyExtStep::Mul(12537, 12539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18794PolyExtStep::Mul(12536, 12539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18795PolyExtStep::Mul(11633, 12540), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18796PolyExtStep::Sub(12544, 12542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18797PolyExtStep::Sub(12545, 12543), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18798PolyExtStep::Sub(12546, 12541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18799PolyExtStep::AndEqz(6223, 12547), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18800PolyExtStep::Mul(10979, 864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18801PolyExtStep::Add(12548, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18802PolyExtStep::Mul(10979, 870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18803PolyExtStep::Add(12550, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18804PolyExtStep::Mul(12549, 12551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18805PolyExtStep::Mul(12549, 867), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18806PolyExtStep::Mul(861, 12551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18807PolyExtStep::Mul(10979, 876), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18808PolyExtStep::Add(12555, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18809PolyExtStep::Mul(12552, 12556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18810PolyExtStep::Mul(12552, 873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18811PolyExtStep::Mul(12554, 12556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18812PolyExtStep::Mul(12553, 12556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18813PolyExtStep::Mul(11879, 12557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18814PolyExtStep::Sub(12561, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18815PolyExtStep::Sub(12562, 12560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18816PolyExtStep::Sub(12563, 12558), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18817PolyExtStep::AndEqz(6224, 12564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18818PolyExtStep::Mul(11353, 882), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18819PolyExtStep::Add(12565, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18820PolyExtStep::Mul(11353, 888), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18821PolyExtStep::Add(12567, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18822PolyExtStep::Mul(12566, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18823PolyExtStep::Mul(12566, 885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18824PolyExtStep::Mul(879, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18825PolyExtStep::Mul(11353, 894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18826PolyExtStep::Add(12572, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18827PolyExtStep::Mul(12569, 12573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18828PolyExtStep::Mul(12569, 891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18829PolyExtStep::Mul(12571, 12573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18830PolyExtStep::Mul(12570, 12573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18831PolyExtStep::Mul(11918, 12574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18832PolyExtStep::Sub(12578, 12576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18833PolyExtStep::Sub(12579, 12577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18834PolyExtStep::Sub(12580, 12575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18835PolyExtStep::AndEqz(6225, 12581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18836PolyExtStep::Mul(11353, 900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18837PolyExtStep::Add(12582, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18838PolyExtStep::Mul(11353, 906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18839PolyExtStep::Add(12584, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18840PolyExtStep::Mul(12583, 12585), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18841PolyExtStep::Mul(12583, 903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18842PolyExtStep::Mul(897, 12585), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18843PolyExtStep::Mul(11353, 943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18844PolyExtStep::Add(12589, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18845PolyExtStep::Mul(12586, 12590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18846PolyExtStep::Mul(12586, 940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18847PolyExtStep::Mul(12588, 12590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18848PolyExtStep::Mul(12587, 12590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18849PolyExtStep::Mul(11940, 12591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18850PolyExtStep::Sub(12595, 12593), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18851PolyExtStep::Sub(12596, 12594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18852PolyExtStep::Sub(12597, 12592), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18853PolyExtStep::AndEqz(6226, 12598), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18854PolyExtStep::Mul(11353, 949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18855PolyExtStep::Add(12599, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18856PolyExtStep::Mul(11353, 955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18857PolyExtStep::Add(12601, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18858PolyExtStep::Mul(12600, 12602), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18859PolyExtStep::Mul(12600, 952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18860PolyExtStep::Mul(946, 12602), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18861PolyExtStep::Mul(11353, 961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18862PolyExtStep::Add(12606, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18863PolyExtStep::Mul(12603, 12607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18864PolyExtStep::Mul(12603, 958), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18865PolyExtStep::Mul(12605, 12607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18866PolyExtStep::Mul(12604, 12607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18867PolyExtStep::Get(102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18868PolyExtStep::Get(101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18869PolyExtStep::Mul(12612, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18870PolyExtStep::Add(12613, 12614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18871PolyExtStep::Get(100), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18872PolyExtStep::Mul(12615, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18873PolyExtStep::Add(12616, 12617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18874PolyExtStep::Get(99), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18875PolyExtStep::Mul(12618, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18876PolyExtStep::Add(12619, 12620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18877PolyExtStep::Sub(12621, 11939), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18878PolyExtStep::Mul(12622, 12608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18879PolyExtStep::Sub(12623, 12610), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18880PolyExtStep::Sub(12624, 12611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18881PolyExtStep::Sub(12625, 12609), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18882PolyExtStep::AndEqz(6227, 12626), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18883PolyExtStep::Mul(11353, 967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18884PolyExtStep::Add(12627, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18885PolyExtStep::Mul(11353, 973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18886PolyExtStep::Add(12629, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18887PolyExtStep::Mul(12628, 12630), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18888PolyExtStep::Mul(12628, 970), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18889PolyExtStep::Mul(964, 12630), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18890PolyExtStep::Mul(11353, 979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18891PolyExtStep::Add(12634, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18892PolyExtStep::Mul(12631, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18893PolyExtStep::Mul(12631, 976), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18894PolyExtStep::Mul(12633, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18895PolyExtStep::Mul(12632, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18896PolyExtStep::Get(106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18897PolyExtStep::Get(105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18898PolyExtStep::Mul(12640, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18899PolyExtStep::Add(12641, 12642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18900PolyExtStep::Get(104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18901PolyExtStep::Mul(12643, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18902PolyExtStep::Add(12644, 12645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18903PolyExtStep::Get(103), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18904PolyExtStep::Mul(12646, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18905PolyExtStep::Add(12647, 12648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18906PolyExtStep::Sub(12649, 12621), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18907PolyExtStep::Mul(12650, 12636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18908PolyExtStep::Sub(12651, 12638), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18909PolyExtStep::Sub(12652, 12639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18910PolyExtStep::Sub(12653, 12637), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18911PolyExtStep::AndEqz(6228, 12654), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18912PolyExtStep::Mul(11353, 985), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18913PolyExtStep::Add(12655, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18914PolyExtStep::Mul(11353, 1022), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18915PolyExtStep::Add(12657, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18916PolyExtStep::Mul(12656, 12658), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18917PolyExtStep::Mul(12656, 1019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18918PolyExtStep::Mul(982, 12658), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18919PolyExtStep::Mul(11353, 1028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18920PolyExtStep::Add(12662, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18921PolyExtStep::Mul(12659, 12663), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18922PolyExtStep::Mul(12659, 1025), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18923PolyExtStep::Mul(12661, 12663), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18924PolyExtStep::Mul(12660, 12663), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18925PolyExtStep::Get(110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18926PolyExtStep::Get(109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18927PolyExtStep::Mul(12668, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18928PolyExtStep::Add(12669, 12670), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18929PolyExtStep::Get(108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18930PolyExtStep::Mul(12671, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18931PolyExtStep::Add(12672, 12673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18932PolyExtStep::Get(107), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18933PolyExtStep::Mul(12674, 353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18934PolyExtStep::Add(12675, 12676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18935PolyExtStep::Sub(12677, 12649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18936PolyExtStep::Mul(12678, 12664), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18937PolyExtStep::Sub(12679, 12666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18938PolyExtStep::Sub(12680, 12667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18939PolyExtStep::Sub(12681, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18940PolyExtStep::AndEqz(6229, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18941PolyExtStep::Mul(11353, 1034), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18942PolyExtStep::Add(12683, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18943PolyExtStep::Sub(11342, 12677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18944PolyExtStep::Mul(12685, 12684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18945PolyExtStep::Sub(12686, 1031), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18946PolyExtStep::AndEqz(6230, 12687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18947PolyExtStep::AndCond(6211, 440, 6231), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18948PolyExtStep::Mul(11029, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18949PolyExtStep::Add(12688, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18950PolyExtStep::Mul(11029, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18951PolyExtStep::Add(12690, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18952PolyExtStep::Mul(12689, 12691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18953PolyExtStep::Mul(12689, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18954PolyExtStep::Mul(568, 12691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18955PolyExtStep::Mul(10979, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18956PolyExtStep::Add(12695, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18957PolyExtStep::Mul(12692, 12696), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18958PolyExtStep::Mul(12692, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18959PolyExtStep::Mul(12694, 12696), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18960PolyExtStep::Mul(12693, 12696), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18961PolyExtStep::Mul(11073, 12697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18962PolyExtStep::Sub(12701, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18963PolyExtStep::Sub(12702, 12700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18964PolyExtStep::Sub(12703, 12698), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18965PolyExtStep::AndEqz(0, 12704), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18966PolyExtStep::Mul(12160, 12271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18967PolyExtStep::Mul(12160, 775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18968PolyExtStep::Mul(584, 12271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18969PolyExtStep::Mul(12705, 12286), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18970PolyExtStep::Mul(12705, 1116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18971PolyExtStep::Mul(12707, 12286), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18972PolyExtStep::Mul(12706, 12286), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18973PolyExtStep::Mul(11112, 12708), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18974PolyExtStep::Sub(12712, 12710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18975PolyExtStep::Sub(12713, 12711), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18976PolyExtStep::Sub(12714, 12709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18977PolyExtStep::AndEqz(6233, 12715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18978PolyExtStep::Mul(12294, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18979PolyExtStep::Mul(12294, 1351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18980PolyExtStep::Mul(1128, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18981PolyExtStep::Mul(12716, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18982PolyExtStep::Mul(12716, 1362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18983PolyExtStep::Mul(12718, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18984PolyExtStep::Mul(12717, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18985PolyExtStep::Mul(11140, 12719), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18986PolyExtStep::Sub(12723, 12721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18987PolyExtStep::Sub(12724, 12722), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18988PolyExtStep::Sub(12725, 12720), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18989PolyExtStep::AndEqz(6234, 12726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18990PolyExtStep::Mul(12327, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18991PolyExtStep::Mul(12327, 1396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18992PolyExtStep::Mul(1379, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18993PolyExtStep::Mul(12727, 12353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18994PolyExtStep::Mul(12727, 1399), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18995PolyExtStep::Mul(12729, 12353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18996PolyExtStep::Mul(12728, 12353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18997PolyExtStep::Mul(11174, 12730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18998PolyExtStep::Sub(12734, 12732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
18999PolyExtStep::Sub(12735, 12733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19000PolyExtStep::Sub(12736, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19001PolyExtStep::AndEqz(6235, 12737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19002PolyExtStep::Mul(11120, 11125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19003PolyExtStep::Mul(11120, 2207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19004PolyExtStep::Mul(1844, 11125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19005PolyExtStep::Mul(12738, 11355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19006PolyExtStep::Mul(12738, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19007PolyExtStep::Mul(12740, 11355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19008PolyExtStep::Mul(12739, 11355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19009PolyExtStep::Mul(11213, 12741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19010PolyExtStep::Sub(12745, 12743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19011PolyExtStep::Sub(12746, 12744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19012PolyExtStep::Sub(12747, 12742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19013PolyExtStep::AndEqz(6236, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19014PolyExtStep::Mul(11029, 604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19015PolyExtStep::Add(12749, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19016PolyExtStep::Mul(10979, 618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19017PolyExtStep::Add(12751, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19018PolyExtStep::Mul(12750, 12752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19019PolyExtStep::Mul(12750, 611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19020PolyExtStep::Mul(597, 12752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19021PolyExtStep::Mul(10979, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19022PolyExtStep::Add(12756, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19023PolyExtStep::Mul(12753, 12757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19024PolyExtStep::Mul(12753, 625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19025PolyExtStep::Mul(12755, 12757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19026PolyExtStep::Mul(12754, 12757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19027PolyExtStep::Mul(11252, 12758), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19028PolyExtStep::Sub(12762, 12760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19029PolyExtStep::Sub(12763, 12761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19030PolyExtStep::Sub(12764, 12759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19031PolyExtStep::AndEqz(6237, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19032PolyExtStep::Mul(10979, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19033PolyExtStep::Add(12766, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19034PolyExtStep::Mul(10979, 648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19035PolyExtStep::Add(12768, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19036PolyExtStep::Mul(12767, 12769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19037PolyExtStep::Mul(12767, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19038PolyExtStep::Mul(635, 12769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19039PolyExtStep::Mul(12770, 11857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19040PolyExtStep::Mul(12770, 655), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19041PolyExtStep::Mul(12772, 11857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19042PolyExtStep::Mul(12771, 11857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19043PolyExtStep::Mul(11285, 12773), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19044PolyExtStep::Sub(12777, 12775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19045PolyExtStep::Sub(12778, 12776), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19046PolyExtStep::Sub(12779, 12774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19047PolyExtStep::AndEqz(6238, 12780), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19048PolyExtStep::Mul(11859, 11864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19049PolyExtStep::Mul(11859, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19050PolyExtStep::Mul(669, 11864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19051PolyExtStep::Mul(11353, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19052PolyExtStep::Add(12784, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19053PolyExtStep::Mul(12781, 12785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19054PolyExtStep::Mul(12781, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19055PolyExtStep::Mul(12783, 12785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19056PolyExtStep::Mul(12782, 12785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19057PolyExtStep::Mul(11313, 12786), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19058PolyExtStep::Sub(12790, 12788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19059PolyExtStep::Sub(12791, 12789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19060PolyExtStep::Sub(12792, 12787), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19061PolyExtStep::AndEqz(6239, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19062PolyExtStep::Mul(10979, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19063PolyExtStep::Add(12794, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19064PolyExtStep::Mul(12532, 12795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19065PolyExtStep::Mul(12532, 821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19066PolyExtStep::Mul(812, 12795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19067PolyExtStep::Mul(11330, 12796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19068PolyExtStep::Sub(12799, 12798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19069PolyExtStep::Sub(12800, 12797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19070PolyExtStep::AndEqz(6240, 12801), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19071PolyExtStep::AndEqz(6241, 11343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19072PolyExtStep::AndCond(6232, 443, 6242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19073PolyExtStep::Mul(11029, 2666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19074PolyExtStep::Add(12802, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19075PolyExtStep::Mul(11029, 2672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19076PolyExtStep::Add(12804, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19077PolyExtStep::Mul(12803, 12805), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19078PolyExtStep::Mul(12803, 2667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19079PolyExtStep::Mul(2660, 12805), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19080PolyExtStep::Mul(10989, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19081PolyExtStep::Add(12809, 11975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19082PolyExtStep::Add(12810, 11977), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19083PolyExtStep::Add(12811, 11979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19084PolyExtStep::Add(12812, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19085PolyExtStep::Mul(12806, 12813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19086PolyExtStep::Mul(12806, 536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19087PolyExtStep::Mul(12808, 12813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19088PolyExtStep::Mul(12807, 12813), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19089PolyExtStep::Mul(11073, 12814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19090PolyExtStep::Sub(12818, 12816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19091PolyExtStep::Sub(12819, 12817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19092PolyExtStep::Sub(12820, 12815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19093PolyExtStep::AndEqz(0, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19094PolyExtStep::Mul(10999, 618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19095PolyExtStep::Add(12809, 12822), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19096PolyExtStep::Mul(11009, 625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19097PolyExtStep::Add(12823, 12824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19098PolyExtStep::Mul(11019, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19099PolyExtStep::Add(12825, 12826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19100PolyExtStep::Add(12827, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19101PolyExtStep::Mul(10989, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19102PolyExtStep::Mul(10999, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19103PolyExtStep::Add(12829, 12830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19104PolyExtStep::Mul(11009, 648), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19105PolyExtStep::Add(12831, 12832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19106PolyExtStep::Mul(11019, 655), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19107PolyExtStep::Add(12833, 12834), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19108PolyExtStep::Add(12835, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19109PolyExtStep::Mul(12828, 12836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19110PolyExtStep::Mul(12828, 635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19111PolyExtStep::Mul(611, 12836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19112PolyExtStep::Mul(10999, 669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19113PolyExtStep::Add(12829, 12840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19114PolyExtStep::Mul(11009, 672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19115PolyExtStep::Add(12841, 12842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19116PolyExtStep::Mul(11019, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19117PolyExtStep::Add(12843, 12844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19118PolyExtStep::Add(12845, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19119PolyExtStep::Mul(12837, 12846), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19120PolyExtStep::Mul(12837, 662), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19121PolyExtStep::Mul(12839, 12846), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19122PolyExtStep::Mul(12838, 12846), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19123PolyExtStep::Mul(11112, 12847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19124PolyExtStep::Sub(12851, 12849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19125PolyExtStep::Sub(12852, 12850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19126PolyExtStep::Sub(12853, 12848), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19127PolyExtStep::AndEqz(6244, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19128PolyExtStep::Mul(10999, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19129PolyExtStep::Add(12128, 12855), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19130PolyExtStep::Mul(11009, 553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19131PolyExtStep::Add(12856, 12857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19132PolyExtStep::Mul(11019, 560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19133PolyExtStep::Add(12858, 12859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19134PolyExtStep::Add(12860, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19135PolyExtStep::Mul(10999, 568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19136PolyExtStep::Add(12128, 12862), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19137PolyExtStep::Mul(11009, 567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19138PolyExtStep::Add(12863, 12864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19139PolyExtStep::Mul(11019, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19140PolyExtStep::Add(12865, 12866), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19141PolyExtStep::Add(12867, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19142PolyExtStep::Mul(12861, 12868), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19143PolyExtStep::Mul(12861, 561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19144PolyExtStep::Mul(548, 12868), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19145PolyExtStep::Mul(10989, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19146PolyExtStep::Mul(10999, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19147PolyExtStep::Add(12872, 12873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19148PolyExtStep::Mul(11009, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19149PolyExtStep::Add(12874, 12875), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19150PolyExtStep::Mul(11019, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19151PolyExtStep::Add(12876, 12877), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19152PolyExtStep::Add(12878, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19153PolyExtStep::Mul(12869, 12879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19154PolyExtStep::Mul(12869, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19155PolyExtStep::Mul(12871, 12879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19156PolyExtStep::Mul(12870, 12879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19157PolyExtStep::Mul(11140, 12880), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19158PolyExtStep::Sub(12884, 12882), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19159PolyExtStep::Sub(12885, 12883), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19160PolyExtStep::Sub(12886, 12881), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19161PolyExtStep::AndEqz(6245, 12887), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19162PolyExtStep::Mul(10999, 583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19163PolyExtStep::Add(12872, 12888), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19164PolyExtStep::Mul(11009, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19165PolyExtStep::Add(12889, 12890), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19166PolyExtStep::Mul(11019, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19167PolyExtStep::Add(12891, 12892), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19168PolyExtStep::Add(12893, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19169PolyExtStep::Mul(10999, 734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19170PolyExtStep::Add(11399, 12895), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19171PolyExtStep::Mul(11009, 735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19172PolyExtStep::Add(12896, 12897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19173PolyExtStep::Mul(11019, 736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19174PolyExtStep::Add(12898, 12899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19175PolyExtStep::Add(12900, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19176PolyExtStep::Mul(12894, 12901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19177PolyExtStep::Mul(12894, 731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19178PolyExtStep::Mul(575, 12901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19179PolyExtStep::Mul(10999, 738), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19180PolyExtStep::Add(11399, 12905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19181PolyExtStep::Mul(11009, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19182PolyExtStep::Add(12906, 12907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19183PolyExtStep::Mul(11019, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19184PolyExtStep::Add(12908, 12909), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19185PolyExtStep::Add(12910, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19186PolyExtStep::Mul(12902, 12911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19187PolyExtStep::Mul(12902, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19188PolyExtStep::Mul(12904, 12911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19189PolyExtStep::Mul(12903, 12911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19190PolyExtStep::Mul(11174, 12912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19191PolyExtStep::Sub(12916, 12914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19192PolyExtStep::Sub(12917, 12915), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19193PolyExtStep::Sub(12918, 12913), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19194PolyExtStep::AndEqz(6246, 12919), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19195PolyExtStep::Add(11656, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19196PolyExtStep::Add(12920, 12179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19197PolyExtStep::Add(12921, 12181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19198PolyExtStep::Add(12922, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19199PolyExtStep::Add(11656, 11428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19200PolyExtStep::Add(12924, 11430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19201PolyExtStep::Add(12925, 11432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19202PolyExtStep::Add(12926, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19203PolyExtStep::Mul(12923, 12927), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19204PolyExtStep::Mul(12923, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19205PolyExtStep::Mul(748, 12927), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19206PolyExtStep::Mul(10989, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19207PolyExtStep::Mul(10999, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19208PolyExtStep::Add(12931, 12932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19209PolyExtStep::Mul(11009, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19210PolyExtStep::Add(12933, 12934), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19211PolyExtStep::Mul(11019, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19212PolyExtStep::Add(12935, 12936), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19213PolyExtStep::Add(12937, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19214PolyExtStep::Mul(12928, 12938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19215PolyExtStep::Mul(12928, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19216PolyExtStep::Mul(12930, 12938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19217PolyExtStep::Mul(12929, 12938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19218PolyExtStep::Mul(11213, 12939), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19219PolyExtStep::Sub(12943, 12941), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19220PolyExtStep::Sub(12944, 12942), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19221PolyExtStep::Sub(12945, 12940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19222PolyExtStep::AndEqz(6247, 12946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19223PolyExtStep::Mul(10999, 785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19224PolyExtStep::Add(12931, 12947), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19225PolyExtStep::Mul(11009, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19226PolyExtStep::Add(12948, 12949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19227PolyExtStep::Mul(11019, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19228PolyExtStep::Add(12950, 12951), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19229PolyExtStep::Add(12952, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19230PolyExtStep::Mul(10989, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19231PolyExtStep::Mul(10999, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19232PolyExtStep::Add(12954, 12955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19233PolyExtStep::Mul(11009, 803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19234PolyExtStep::Add(12956, 12957), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19235PolyExtStep::Mul(11019, 806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19236PolyExtStep::Add(12958, 12959), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19237PolyExtStep::Add(12960, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19238PolyExtStep::Mul(12953, 12961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19239PolyExtStep::Mul(12953, 794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19240PolyExtStep::Mul(782, 12961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19241PolyExtStep::Mul(10999, 812), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19242PolyExtStep::Add(12954, 12965), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19243PolyExtStep::Mul(11009, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19244PolyExtStep::Add(12966, 12967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19245PolyExtStep::Mul(11019, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19246PolyExtStep::Add(12968, 12969), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19247PolyExtStep::Add(12970, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19248PolyExtStep::Mul(12962, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19249PolyExtStep::Mul(12962, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19250PolyExtStep::Mul(12964, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19251PolyExtStep::Mul(12963, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19252PolyExtStep::Mul(11252, 12972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19253PolyExtStep::Sub(12976, 12974), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19254PolyExtStep::Sub(12977, 12975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19255PolyExtStep::Sub(12978, 12973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19256PolyExtStep::AndEqz(6248, 12979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19257PolyExtStep::Mul(11029, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19258PolyExtStep::Add(12980, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19259PolyExtStep::Mul(11029, 861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19260PolyExtStep::Add(12982, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19261PolyExtStep::Mul(12981, 12983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19262PolyExtStep::Mul(12981, 827), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19263PolyExtStep::Mul(821, 12983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19264PolyExtStep::Mul(11029, 867), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19265PolyExtStep::Add(12987, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19266PolyExtStep::Mul(12984, 12988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19267PolyExtStep::Mul(12984, 864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19268PolyExtStep::Mul(12986, 12988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19269PolyExtStep::Mul(12985, 12988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19270PolyExtStep::Mul(11285, 12989), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19271PolyExtStep::Sub(12993, 12991), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19272PolyExtStep::Sub(12994, 12992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19273PolyExtStep::Sub(12995, 12990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19274PolyExtStep::AndEqz(6249, 12996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19275PolyExtStep::Mul(11029, 879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19276PolyExtStep::Add(12997, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19277PolyExtStep::Mul(11739, 12998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19278PolyExtStep::Mul(11739, 876), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19279PolyExtStep::Mul(870, 12998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19280PolyExtStep::Mul(11029, 885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19281PolyExtStep::Add(13002, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19282PolyExtStep::Mul(12999, 13003), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19283PolyExtStep::Mul(12999, 882), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19284PolyExtStep::Mul(13001, 13003), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19285PolyExtStep::Mul(13000, 13003), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19286PolyExtStep::Mul(11313, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19287PolyExtStep::Sub(13008, 13006), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19288PolyExtStep::Sub(13009, 13007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19289PolyExtStep::Sub(13010, 13005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19290PolyExtStep::AndEqz(6250, 13011), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19291PolyExtStep::Mul(11029, 891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19292PolyExtStep::Add(13012, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19293PolyExtStep::Mul(11029, 897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19294PolyExtStep::Add(13014, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19295PolyExtStep::Mul(13013, 13015), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19296PolyExtStep::Mul(13013, 894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19297PolyExtStep::Mul(888, 13015), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19298PolyExtStep::Mul(10979, 625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19299PolyExtStep::Add(13019, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19300PolyExtStep::Mul(13016, 13020), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19301PolyExtStep::Mul(13016, 900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19302PolyExtStep::Mul(13018, 13020), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19303PolyExtStep::Mul(13017, 13020), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19304PolyExtStep::Mul(11330, 13021), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19305PolyExtStep::Sub(13025, 13023), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19306PolyExtStep::Sub(13026, 13024), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19307PolyExtStep::Sub(13027, 13022), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19308PolyExtStep::AndEqz(6251, 13028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19309PolyExtStep::Mul(10979, 940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19310PolyExtStep::Add(13029, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19311PolyExtStep::Mul(12757, 13030), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19312PolyExtStep::Mul(12757, 906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19313PolyExtStep::Mul(903, 13030), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19314PolyExtStep::Mul(10979, 672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19315PolyExtStep::Add(13034, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19316PolyExtStep::Mul(13031, 13035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19317PolyExtStep::Mul(13031, 943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19318PolyExtStep::Mul(13033, 13035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19319PolyExtStep::Mul(13032, 13035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19320PolyExtStep::Mul(11549, 13036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19321PolyExtStep::Sub(13040, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19322PolyExtStep::Sub(13041, 13039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19323PolyExtStep::Sub(13042, 13037), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19324PolyExtStep::AndEqz(6252, 13043), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19325PolyExtStep::Mul(10979, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19326PolyExtStep::Add(13044, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19327PolyExtStep::Mul(13045, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19328PolyExtStep::Mul(13045, 949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19329PolyExtStep::Mul(946, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19330PolyExtStep::Mul(13046, 11370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19331PolyExtStep::Mul(13046, 955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19332PolyExtStep::Mul(13048, 11370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19333PolyExtStep::Mul(13047, 11370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19334PolyExtStep::Mul(11583, 13049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19335PolyExtStep::Sub(13053, 13051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19336PolyExtStep::Sub(13054, 13052), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19337PolyExtStep::Sub(13055, 13050), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19338PolyExtStep::AndEqz(6253, 13056), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19339PolyExtStep::Mul(10979, 569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19340PolyExtStep::Add(13057, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19341PolyExtStep::Mul(10979, 964), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19342PolyExtStep::Add(13059, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19343PolyExtStep::Mul(13058, 13060), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19344PolyExtStep::Mul(13058, 961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19345PolyExtStep::Mul(958, 13060), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19346PolyExtStep::Mul(10979, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19347PolyExtStep::Add(13064, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19348PolyExtStep::Mul(13061, 13065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19349PolyExtStep::Mul(13061, 967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19350PolyExtStep::Mul(13063, 13065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19351PolyExtStep::Mul(13062, 13065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19352PolyExtStep::Mul(11616, 13066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19353PolyExtStep::Sub(13070, 13068), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19354PolyExtStep::Sub(13071, 13069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19355PolyExtStep::Sub(13072, 13067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19356PolyExtStep::AndEqz(6254, 13073), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19357PolyExtStep::Mul(10979, 976), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19358PolyExtStep::Add(13074, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19359PolyExtStep::Mul(12160, 13075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19360PolyExtStep::Mul(12160, 973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19361PolyExtStep::Mul(970, 13075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19362PolyExtStep::Mul(10979, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19363PolyExtStep::Add(13079, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19364PolyExtStep::Mul(13076, 13080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19365PolyExtStep::Mul(13076, 979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19366PolyExtStep::Mul(13078, 13080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19367PolyExtStep::Mul(13077, 13080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19368PolyExtStep::Mul(11633, 13081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19369PolyExtStep::Sub(13085, 13083), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19370PolyExtStep::Sub(13086, 13084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19371PolyExtStep::Sub(13087, 13082), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19372PolyExtStep::AndEqz(6255, 13088), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19373PolyExtStep::Mul(10979, 1019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19374PolyExtStep::Add(13089, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19375PolyExtStep::Mul(12172, 13090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19376PolyExtStep::Mul(12172, 985), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19377PolyExtStep::Mul(982, 13090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19378PolyExtStep::Mul(13091, 12485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19379PolyExtStep::Mul(13091, 1022), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19380PolyExtStep::Mul(13093, 12485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19381PolyExtStep::Mul(13092, 12485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19382PolyExtStep::Mul(11879, 13094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19383PolyExtStep::Sub(13098, 13096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19384PolyExtStep::Sub(13099, 13097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19385PolyExtStep::Sub(13100, 13095), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19386PolyExtStep::AndEqz(6256, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19387PolyExtStep::Mul(10979, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19388PolyExtStep::Add(13102, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19389PolyExtStep::Mul(10979, 1031), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19390PolyExtStep::Add(13104, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19391PolyExtStep::Mul(13103, 13105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19392PolyExtStep::Mul(13103, 1028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19393PolyExtStep::Mul(1025, 13105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19394PolyExtStep::Mul(10979, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19395PolyExtStep::Add(13109, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19396PolyExtStep::Mul(13106, 13110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19397PolyExtStep::Mul(13106, 1034), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19398PolyExtStep::Mul(13108, 13110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19399PolyExtStep::Mul(13107, 13110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19400PolyExtStep::Mul(11918, 13111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19401PolyExtStep::Sub(13115, 13113), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19402PolyExtStep::Sub(13116, 13114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19403PolyExtStep::Sub(13117, 13112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19404PolyExtStep::AndEqz(6257, 13118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19405PolyExtStep::Mul(10979, 1043), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19406PolyExtStep::Add(13119, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19407PolyExtStep::Mul(12507, 13120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19408PolyExtStep::Mul(12507, 1040), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19409PolyExtStep::Mul(1037, 13120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19410PolyExtStep::Mul(13121, 12532), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19411PolyExtStep::Mul(13121, 1046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19412PolyExtStep::Mul(13123, 12532), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19413PolyExtStep::Mul(13122, 12532), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19414PolyExtStep::Mul(11940, 13124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19415PolyExtStep::Sub(13128, 13126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19416PolyExtStep::Sub(13129, 13127), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19417PolyExtStep::Sub(13130, 13125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19418PolyExtStep::AndEqz(6258, 13131), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19419PolyExtStep::Mul(10979, 1055), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19420PolyExtStep::Add(13132, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19421PolyExtStep::Mul(12249, 13133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19422PolyExtStep::Mul(12249, 1052), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19423PolyExtStep::Mul(1049, 13133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19424PolyExtStep::Mul(11353, 1061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19425PolyExtStep::Add(13137, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19426PolyExtStep::Mul(13134, 13138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19427PolyExtStep::Mul(13134, 1058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19428PolyExtStep::Mul(13136, 13138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19429PolyExtStep::Mul(13135, 13138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19430PolyExtStep::Mul(12622, 13139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19431PolyExtStep::Sub(13143, 13141), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19432PolyExtStep::Sub(13144, 13142), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19433PolyExtStep::Sub(13145, 13140), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19434PolyExtStep::AndEqz(6259, 13146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19435PolyExtStep::Mul(11353, 2659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19436PolyExtStep::Add(13147, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19437PolyExtStep::Mul(12650, 13148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19438PolyExtStep::Sub(13149, 1064), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19439PolyExtStep::AndEqz(6260, 13150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19440PolyExtStep::Sub(11342, 12649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19441PolyExtStep::AndEqz(6261, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19442PolyExtStep::AndCond(6243, 446, 6262), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19443PolyExtStep::Mul(11029, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19444PolyExtStep::Add(13152, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19445PolyExtStep::Mul(11029, 597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19446PolyExtStep::Add(13154, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19447PolyExtStep::Mul(13153, 13155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19448PolyExtStep::Mul(13153, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19449PolyExtStep::Mul(536, 13155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19450PolyExtStep::Mul(11073, 13156), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19451PolyExtStep::Sub(13159, 13158), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19452PolyExtStep::Sub(13160, 13157), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19453PolyExtStep::AndEqz(0, 13161), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19454PolyExtStep::Sub(11342, 11072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19455PolyExtStep::AndEqz(6264, 13162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19456PolyExtStep::AndCond(6263, 449, 6265), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19457PolyExtStep::Mul(11029, 1058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19458PolyExtStep::Add(13163, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19459PolyExtStep::Mul(11029, 1064), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19460PolyExtStep::Add(13165, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19461PolyExtStep::Mul(13164, 13166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19462PolyExtStep::Mul(13164, 1061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19463PolyExtStep::Mul(1055, 13166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19464PolyExtStep::Mul(10989, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19465PolyExtStep::Mul(10999, 803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19466PolyExtStep::Add(13170, 13171), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19467PolyExtStep::Mul(11009, 806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19468PolyExtStep::Add(13172, 13173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19469PolyExtStep::Mul(11019, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19470PolyExtStep::Add(13174, 13175), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19471PolyExtStep::Add(13176, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19472PolyExtStep::Mul(13167, 13177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19473PolyExtStep::Mul(13167, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19474PolyExtStep::Mul(13169, 13177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19475PolyExtStep::Mul(13168, 13177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19476PolyExtStep::Mul(11073, 13178), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19477PolyExtStep::Sub(13182, 13180), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19478PolyExtStep::Sub(13183, 13181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19479PolyExtStep::Sub(13184, 13179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19480PolyExtStep::AndEqz(0, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19481PolyExtStep::Mul(10999, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19482PolyExtStep::Add(13170, 13186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19483PolyExtStep::Mul(11009, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19484PolyExtStep::Add(13187, 13188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19485PolyExtStep::Mul(11019, 821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19486PolyExtStep::Add(13189, 13190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19487PolyExtStep::Add(13191, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19488PolyExtStep::Mul(10989, 827), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19489PolyExtStep::Add(13193, 11723), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19490PolyExtStep::Add(13194, 11725), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19491PolyExtStep::Add(13195, 11727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19492PolyExtStep::Add(13196, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19493PolyExtStep::Mul(13192, 13197), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19494PolyExtStep::Mul(13192, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19495PolyExtStep::Mul(812, 13197), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19496PolyExtStep::Mul(10999, 873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19497PolyExtStep::Add(13193, 13201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19498PolyExtStep::Mul(11009, 876), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19499PolyExtStep::Add(13202, 13203), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19500PolyExtStep::Mul(11019, 879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19501PolyExtStep::Add(13204, 13205), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19502PolyExtStep::Add(13206, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19503PolyExtStep::Mul(13198, 13207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19504PolyExtStep::Mul(13198, 870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19505PolyExtStep::Mul(13200, 13207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19506PolyExtStep::Mul(13199, 13207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19507PolyExtStep::Mul(11112, 13208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19508PolyExtStep::Sub(13212, 13210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19509PolyExtStep::Sub(13213, 13211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19510PolyExtStep::Sub(13214, 13209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19511PolyExtStep::AndEqz(6267, 13215), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19512PolyExtStep::Mul(10999, 888), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19513PolyExtStep::Add(11561, 13216), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19514PolyExtStep::Mul(11009, 891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19515PolyExtStep::Add(13217, 13218), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19516PolyExtStep::Mul(11019, 894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19517PolyExtStep::Add(13219, 13220), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19518PolyExtStep::Add(13221, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19519PolyExtStep::Mul(10999, 900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19520PolyExtStep::Add(11561, 13223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19521PolyExtStep::Mul(11009, 903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19522PolyExtStep::Add(13224, 13225), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19523PolyExtStep::Mul(11019, 906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19524PolyExtStep::Add(13226, 13227), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19525PolyExtStep::Add(13228, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19526PolyExtStep::Mul(13222, 13229), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19527PolyExtStep::Mul(13222, 897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19528PolyExtStep::Mul(882, 13229), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19529PolyExtStep::Mul(10989, 943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19530PolyExtStep::Mul(10999, 946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19531PolyExtStep::Add(13233, 13234), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19532PolyExtStep::Mul(11009, 949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19533PolyExtStep::Add(13235, 13236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19534PolyExtStep::Mul(11019, 952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19535PolyExtStep::Add(13237, 13238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19536PolyExtStep::Add(13239, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19537PolyExtStep::Mul(13230, 13240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19538PolyExtStep::Mul(13230, 940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19539PolyExtStep::Mul(13232, 13240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19540PolyExtStep::Mul(13231, 13240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19541PolyExtStep::Mul(11140, 13241), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19542PolyExtStep::Sub(13245, 13243), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19543PolyExtStep::Sub(13246, 13244), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19544PolyExtStep::Sub(13247, 13242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19545PolyExtStep::AndEqz(6268, 13248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19546PolyExtStep::Mul(10999, 958), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19547PolyExtStep::Add(13233, 13249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19548PolyExtStep::Mul(11009, 961), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19549PolyExtStep::Add(13250, 13251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19550PolyExtStep::Mul(11019, 964), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19551PolyExtStep::Add(13252, 13253), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19552PolyExtStep::Add(13254, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19553PolyExtStep::Mul(10989, 970), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19554PolyExtStep::Mul(10999, 973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19555PolyExtStep::Add(13256, 13257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19556PolyExtStep::Mul(11009, 976), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19557PolyExtStep::Add(13258, 13259), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19558PolyExtStep::Mul(11019, 979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19559PolyExtStep::Add(13260, 13261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19560PolyExtStep::Add(13262, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19561PolyExtStep::Mul(13255, 13263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19562PolyExtStep::Mul(13255, 967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19563PolyExtStep::Mul(955, 13263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19564PolyExtStep::Mul(10999, 985), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19565PolyExtStep::Add(13256, 13267), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19566PolyExtStep::Mul(11009, 1019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19567PolyExtStep::Add(13268, 13269), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19568PolyExtStep::Mul(11019, 1022), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19569PolyExtStep::Add(13270, 13271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19570PolyExtStep::Add(13272, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19571PolyExtStep::Mul(13264, 13273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19572PolyExtStep::Mul(13264, 982), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19573PolyExtStep::Mul(13266, 13273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19574PolyExtStep::Mul(13265, 13273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19575PolyExtStep::Mul(11174, 13274), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19576PolyExtStep::Sub(13278, 13276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19577PolyExtStep::Sub(13279, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19578PolyExtStep::Sub(13280, 13275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19579PolyExtStep::AndEqz(6269, 13281), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19580PolyExtStep::Mul(11029, 1028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19581PolyExtStep::Add(13282, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19582PolyExtStep::Mul(11029, 1034), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19583PolyExtStep::Add(13284, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19584PolyExtStep::Mul(13283, 13285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19585PolyExtStep::Mul(13283, 1031), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19586PolyExtStep::Mul(1025, 13285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19587PolyExtStep::Mul(11029, 1040), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19588PolyExtStep::Add(13289, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19589PolyExtStep::Mul(13286, 13290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19590PolyExtStep::Mul(13286, 1037), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19591PolyExtStep::Mul(13288, 13290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19592PolyExtStep::Mul(13287, 13290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19593PolyExtStep::Mul(11213, 13291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19594PolyExtStep::Sub(13295, 13293), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19595PolyExtStep::Sub(13296, 13294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19596PolyExtStep::Sub(13297, 13292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19597PolyExtStep::AndEqz(6270, 13298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19598PolyExtStep::Mul(11029, 1046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19599PolyExtStep::Add(13299, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19600PolyExtStep::Mul(11029, 1052), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19601PolyExtStep::Add(13301, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19602PolyExtStep::Mul(13300, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19603PolyExtStep::Mul(13300, 1049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19604PolyExtStep::Mul(1043, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19605PolyExtStep::Mul(11252, 13303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19606PolyExtStep::Sub(13306, 13305), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19607PolyExtStep::Sub(13307, 13304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19608PolyExtStep::AndEqz(6271, 13308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19609PolyExtStep::Sub(11342, 11251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19610PolyExtStep::AndEqz(6272, 13309), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19611PolyExtStep::AndCond(6266, 452, 6273), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19612PolyExtStep::Mul(11029, 949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19613PolyExtStep::Add(13310, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19614PolyExtStep::Mul(11029, 955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19615PolyExtStep::Add(13312, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19616PolyExtStep::Mul(13311, 13313), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19617PolyExtStep::Mul(13311, 952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19618PolyExtStep::Mul(946, 13313), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19619PolyExtStep::Mul(10989, 1379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19620PolyExtStep::Add(13317, 12321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19621PolyExtStep::Add(13318, 12323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19622PolyExtStep::Add(13319, 12325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19623PolyExtStep::Add(13320, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19624PolyExtStep::Mul(13314, 13321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19625PolyExtStep::Mul(13314, 1378), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19626PolyExtStep::Mul(13316, 13321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19627PolyExtStep::Mul(13315, 13321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19628PolyExtStep::Mul(11073, 13322), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19629PolyExtStep::Sub(13326, 13324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19630PolyExtStep::Sub(13327, 13325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19631PolyExtStep::Sub(13328, 13323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19632PolyExtStep::AndEqz(0, 13329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19633PolyExtStep::Mul(10999, 1773), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19634PolyExtStep::Add(13317, 13330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19635PolyExtStep::Mul(11009, 1774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19636PolyExtStep::Add(13331, 13332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19637PolyExtStep::Mul(11019, 1397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19638PolyExtStep::Add(13333, 13334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19639PolyExtStep::Add(13335, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19640PolyExtStep::Mul(10989, 1399), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19641PolyExtStep::Add(13337, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19642PolyExtStep::Add(13338, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19643PolyExtStep::Add(13339, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19644PolyExtStep::Add(13340, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19645PolyExtStep::Mul(13336, 13341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19646PolyExtStep::Mul(13336, 1398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19647PolyExtStep::Mul(1396, 13341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19648PolyExtStep::Add(13337, 11965), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19649PolyExtStep::Add(13345, 11967), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19650PolyExtStep::Add(13346, 11969), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19651PolyExtStep::Add(13347, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19652PolyExtStep::Mul(13342, 13348), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19653PolyExtStep::Mul(13342, 1844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19654PolyExtStep::Mul(13344, 13348), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19655PolyExtStep::Mul(13343, 13348), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19656PolyExtStep::Mul(11112, 13349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19657PolyExtStep::Sub(13353, 13351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19658PolyExtStep::Sub(13354, 13352), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19659PolyExtStep::Sub(13355, 13350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19660PolyExtStep::AndEqz(6275, 13356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19661PolyExtStep::Mul(10989, 590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19662PolyExtStep::Add(13357, 12365), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19663PolyExtStep::Add(13358, 12367), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19664PolyExtStep::Add(13359, 12369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19665PolyExtStep::Add(13360, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19666PolyExtStep::Mul(10999, 625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19667PolyExtStep::Add(13357, 13362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19668PolyExtStep::Mul(11009, 628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19669PolyExtStep::Add(13363, 13364), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19670PolyExtStep::Mul(11019, 635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19671PolyExtStep::Add(13365, 13366), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19672PolyExtStep::Add(13367, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19673PolyExtStep::Mul(13361, 13368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19674PolyExtStep::Mul(13361, 618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19675PolyExtStep::Mul(587, 13368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19676PolyExtStep::Mul(10989, 645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19677PolyExtStep::Add(13372, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19678PolyExtStep::Add(13373, 12389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19679PolyExtStep::Add(13374, 12391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19680PolyExtStep::Add(13375, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19681PolyExtStep::Mul(13369, 13376), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19682PolyExtStep::Mul(13369, 642), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19683PolyExtStep::Mul(13371, 13376), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19684PolyExtStep::Mul(13370, 13376), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19685PolyExtStep::Mul(11140, 13377), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19686PolyExtStep::Sub(13381, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19687PolyExtStep::Sub(13382, 13380), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19688PolyExtStep::Sub(13383, 13378), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19689PolyExtStep::AndEqz(6276, 13384), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19690PolyExtStep::Mul(10999, 672), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19691PolyExtStep::Add(13372, 13385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19692PolyExtStep::Mul(11009, 541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19693PolyExtStep::Add(13386, 13387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19694PolyExtStep::Mul(11019, 548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19695PolyExtStep::Add(13388, 13389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19696PolyExtStep::Add(13390, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19697PolyExtStep::Mul(10989, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19698PolyExtStep::Add(13392, 12129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19699PolyExtStep::Add(13393, 12131), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19700PolyExtStep::Add(13394, 12133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19701PolyExtStep::Add(13395, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19702PolyExtStep::Mul(13391, 13396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19703PolyExtStep::Mul(13391, 549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19704PolyExtStep::Mul(669, 13396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19705PolyExtStep::Add(13392, 12139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19706PolyExtStep::Add(13400, 12141), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19707PolyExtStep::Add(13401, 12143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19708PolyExtStep::Add(13402, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19709PolyExtStep::Mul(13397, 13403), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19710PolyExtStep::Mul(13397, 568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19711PolyExtStep::Mul(13399, 13403), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19712PolyExtStep::Mul(13398, 13403), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19713PolyExtStep::Mul(11174, 13404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19714PolyExtStep::Sub(13408, 13406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19715PolyExtStep::Sub(13409, 13407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19716PolyExtStep::Sub(13410, 13405), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19717PolyExtStep::AndEqz(6277, 13411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19718PolyExtStep::Mul(10989, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19719PolyExtStep::Add(13412, 11179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19720PolyExtStep::Add(13413, 11181), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19721PolyExtStep::Add(13414, 11183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19722PolyExtStep::Add(13415, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19723PolyExtStep::Mul(10999, 584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19724PolyExtStep::Add(13412, 13417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19725PolyExtStep::Mul(11009, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19726PolyExtStep::Add(13418, 13419), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19727PolyExtStep::Mul(11019, 731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19728PolyExtStep::Add(13420, 13421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19729PolyExtStep::Add(13422, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19730PolyExtStep::Mul(13416, 13423), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19731PolyExtStep::Mul(13416, 583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19732PolyExtStep::Mul(571, 13423), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19733PolyExtStep::Mul(13424, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19734PolyExtStep::Mul(13424, 733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19735PolyExtStep::Mul(13426, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19736PolyExtStep::Mul(13425, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19737PolyExtStep::Mul(11213, 13427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19738PolyExtStep::Sub(13431, 13429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19739PolyExtStep::Sub(13432, 13430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19740PolyExtStep::Sub(13433, 13428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19741PolyExtStep::AndEqz(6278, 13434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19742PolyExtStep::Mul(11252, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19743PolyExtStep::Sub(13435, 12461), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19744PolyExtStep::Sub(13436, 12462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19745PolyExtStep::Sub(13437, 12460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19746PolyExtStep::AndEqz(6279, 13438), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19747PolyExtStep::Mul(11353, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19748PolyExtStep::Add(13439, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19749PolyExtStep::Mul(12471, 13440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19750PolyExtStep::Mul(12473, 13440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19751PolyExtStep::Mul(12472, 13440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19752PolyExtStep::Mul(11285, 13441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19753PolyExtStep::Sub(13444, 13442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19754PolyExtStep::Sub(13445, 13443), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19755PolyExtStep::Sub(13446, 12477), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19756PolyExtStep::AndEqz(6280, 13447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19757PolyExtStep::Mul(11353, 759), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19758PolyExtStep::Add(13448, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19759PolyExtStep::Mul(11353, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19760PolyExtStep::Add(13450, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19761PolyExtStep::Mul(13449, 13451), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19762PolyExtStep::Mul(13449, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19763PolyExtStep::Mul(758, 13451), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19764PolyExtStep::Mul(11353, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19765PolyExtStep::Add(13455, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19766PolyExtStep::Mul(13452, 13456), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19767PolyExtStep::Mul(13452, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19768PolyExtStep::Mul(13454, 13456), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19769PolyExtStep::Mul(13453, 13456), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19770PolyExtStep::Mul(11313, 13457), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19771PolyExtStep::Sub(13461, 13459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19772PolyExtStep::Sub(13462, 13460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19773PolyExtStep::Sub(13463, 13458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19774PolyExtStep::AndEqz(6281, 13464), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19775PolyExtStep::Mul(11353, 752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19776PolyExtStep::Add(13465, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19777PolyExtStep::Mul(11353, 785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19778PolyExtStep::Add(13467, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19779PolyExtStep::Mul(13466, 13468), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19780PolyExtStep::Mul(13466, 782), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19781PolyExtStep::Mul(771, 13468), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19782PolyExtStep::Mul(11353, 791), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19783PolyExtStep::Add(13472, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19784PolyExtStep::Mul(13469, 13473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19785PolyExtStep::Mul(13469, 788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19786PolyExtStep::Mul(13471, 13473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19787PolyExtStep::Mul(13470, 13473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19788PolyExtStep::Mul(11330, 13474), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19789PolyExtStep::Sub(13478, 13476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19790PolyExtStep::Sub(13479, 13477), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19791PolyExtStep::Sub(13480, 13475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19792PolyExtStep::AndEqz(6282, 13481), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19793PolyExtStep::Mul(11353, 797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19794PolyExtStep::Add(13482, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19795PolyExtStep::Mul(11353, 803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19796PolyExtStep::Add(13484, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19797PolyExtStep::Mul(13483, 13485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19798PolyExtStep::Mul(13483, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19799PolyExtStep::Mul(794, 13485), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19800PolyExtStep::Mul(11353, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19801PolyExtStep::Add(13489, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19802PolyExtStep::Mul(13486, 13490), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19803PolyExtStep::Mul(13486, 806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19804PolyExtStep::Mul(13488, 13490), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19805PolyExtStep::Mul(13487, 13490), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19806PolyExtStep::Mul(11549, 13491), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19807PolyExtStep::Sub(13495, 13493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19808PolyExtStep::Sub(13496, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19809PolyExtStep::Sub(13497, 13492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19810PolyExtStep::AndEqz(6283, 13498), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19811PolyExtStep::Mul(11353, 815), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19812PolyExtStep::Add(13499, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19813PolyExtStep::Mul(11353, 821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19814PolyExtStep::Add(13501, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19815PolyExtStep::Mul(13500, 13502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19816PolyExtStep::Mul(13500, 818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19817PolyExtStep::Mul(812, 13502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19818PolyExtStep::Mul(11353, 827), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19819PolyExtStep::Add(13506, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19820PolyExtStep::Mul(13503, 13507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19821PolyExtStep::Mul(13503, 824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19822PolyExtStep::Mul(13505, 13507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19823PolyExtStep::Mul(13504, 13507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19824PolyExtStep::Mul(11583, 13508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19825PolyExtStep::Sub(13512, 13510), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19826PolyExtStep::Sub(13513, 13511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19827PolyExtStep::Sub(13514, 13509), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19828PolyExtStep::AndEqz(6284, 13515), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19829PolyExtStep::Mul(11353, 864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19830PolyExtStep::Add(13516, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19831PolyExtStep::Mul(11353, 870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19832PolyExtStep::Add(13518, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19833PolyExtStep::Mul(13517, 13519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19834PolyExtStep::Mul(13517, 867), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19835PolyExtStep::Mul(861, 13519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19836PolyExtStep::Mul(11353, 876), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19837PolyExtStep::Add(13523, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19838PolyExtStep::Mul(13520, 13524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19839PolyExtStep::Mul(13520, 873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19840PolyExtStep::Mul(13522, 13524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19841PolyExtStep::Mul(13521, 13524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19842PolyExtStep::Mul(11616, 13525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19843PolyExtStep::Sub(13529, 13527), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19844PolyExtStep::Sub(13530, 13528), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19845PolyExtStep::Sub(13531, 13526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19846PolyExtStep::AndEqz(6285, 13532), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19847PolyExtStep::Mul(10979, 894), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19848PolyExtStep::Add(13533, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19849PolyExtStep::Mul(12569, 13534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19850PolyExtStep::Mul(12571, 13534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19851PolyExtStep::Mul(12570, 13534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19852PolyExtStep::Mul(11633, 13535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19853PolyExtStep::Sub(13538, 13536), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19854PolyExtStep::Sub(13539, 13537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19855PolyExtStep::Sub(13540, 12575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19856PolyExtStep::AndEqz(6286, 13541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19857PolyExtStep::Mul(10979, 900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19858PolyExtStep::Add(13542, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19859PolyExtStep::Mul(10979, 906), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19860PolyExtStep::Add(13544, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19861PolyExtStep::Mul(13543, 13545), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19862PolyExtStep::Mul(13543, 903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19863PolyExtStep::Mul(897, 13545), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19864PolyExtStep::Mul(10979, 943), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19865PolyExtStep::Add(13549, 11039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19866PolyExtStep::Mul(13546, 13550), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19867PolyExtStep::Mul(13546, 940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19868PolyExtStep::Mul(13548, 13550), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19869PolyExtStep::Mul(13547, 13550), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19870PolyExtStep::Mul(11879, 13551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19871PolyExtStep::Sub(13555, 13553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19872PolyExtStep::Sub(13556, 13554), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19873PolyExtStep::Sub(13557, 13552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19874PolyExtStep::AndEqz(6287, 13558), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19875PolyExtStep::Sub(11342, 11878), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19876PolyExtStep::AndEqz(6288, 13559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19877PolyExtStep::AndCond(6274, 455, 6289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :590:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :526:9 at All Constraints )))
19878],
19879 ret: 6290,
19880};
19881
19882impl PolyExt<BabyBear> for CircuitImpl {
19883 fn poly_ext(
19884 &self,
19885 mix: &BabyBearExtElem,
19886 u: &[BabyBearExtElem],
19887 args: &[&[BabyBearElem]],
19888 ) -> MixState<BabyBearExtElem> {
19889 DEF.step::<BabyBear>(mix, u, args)
19890 }
19891}