Crate risc_v_disassembler

Expand description

A simple disassembler for the RISC-V instruction set architecture. It currently only supports 32 bit RV32I instructions.

§Supported Instruction Sets

RV32I

Parses a byte array slice into a ParsedInstruction32 enum representing a RISC-V instruction.

§Arguments

bytes - A slice of bytes representing the encoded instruction to be parsed.
is_big_endian - A boolean indicating whether the bytes are in big endian format.

§Returns

Ok(ParsedInstruction32) - If the parsing is successful, returns the parsed instruction.
Err(DisassemblerError) - If the parsing fails, returns an error indicating the reason for failure.

§Example

use risc_v_disassembler::{
    parse,
    ParsedInstruction32,
    parsed_instructions::*
};

let bytes = [0x93, 0x00, 0x51, 0x00];
let is_big_endian = false;
let use_abi_register_names = false;
let parsed_instruction = parse(&bytes, is_big_endian, use_abi_register_names).unwrap();

assert_eq!(parsed_instruction, ParsedInstruction32::addi (addi {
    rd: "x1",
    rs1: "x2",
    imm: 5
}));

Or using ABI register names:

use risc_v_disassembler::{
    parse,
    ParsedInstruction32,
    parsed_instructions::*
};

let bytes = [0x93, 0x00, 0x41, 0x00];
let is_big_endian = false;
let use_abi_register_names = true;
let parsed_instruction = parse(&bytes, is_big_endian, use_abi_register_names).unwrap();
assert_eq!(parsed_instruction, ParsedInstruction32::addi (addi {
   rd: "ra",
   rs1: "sp",
   imm: 4
}));
``` `