Crate reticle 

Reticle: a VHDL / Verilog compiler written from scratch in Rust.

Reticle takes hardware designs from source text through a unified intermediate representation (IR) to simulation, synthesis and physical targets. Both languages lower to the same IR, so mixed-language designs are handled uniformly by every later stage.

The crate is a library first; the reticle binary is a thin wrapper over it. The core never performs I/O: sources are handed in through a source::SourceMap and results are returned as values, so the compiler embeds cleanly in tests, build scripts and a WebAssembly playground.

Every stage is behind a Cargo feature (see Cargo.toml), and the plan for each is laid out in ROADMAP.md at the repository root.

Layout

Module	Feature	Role
source	always	Source files, byte spans, line/column lookup
diag	always	Diagnostics and their text rendering
fmt_doc	always	Document printer and diff behind the formatters
intern	always	Identifier interning (Symbol)
logic	always	Four-state bit vectors and std_ulogic
verilog	verilog	Verilog / SystemVerilog frontend
vhdl	vhdl	VHDL frontend
ir	always	The unified design IR
sim	sim	Event-driven simulator
synth	synth	Synthesis passes and technology mapping
formal	formal	SAT solver, CNF encoding, model checking
asic	asic	Liberty, LEF and DEF readers and writers
fpga	fpga	FPGA device database, primitive mapping, constraints
timing	timing	Static timing analysis and clock domain crossings
ip	ip	IP and project manifests, bus interfaces, interconnect
lsp	lsp	Language server for Verilog and VHDL
cache	cache	Incremental builds over a content-addressed store
viewer	viewer	Schematic and documentation HTML pages for a design
ffi	ffi	C ABI for embedding the compiler in another tool
wasm	wasm	WebAssembly surface for the browser playground

unsafe

unsafe_code is denied crate-wide rather than forbidden. forbid cannot be lifted even locally, and ffi and wasm have to hand raw pointers across an ABI boundary, which no safe formulation expresses. Those two modules are therefore the only place in the crate that opts back in, each with a file-scoped #![allow(unsafe_code)] and a comment on every block naming the invariant it relies on. Every other module stays safe; a compiler has no business touching raw memory.

Modules

asic

ASIC targets: the Liberty, LEF and DEF formats, standard-cell mapping and the hand-off to a place-and-route tool.

cache

Incremental compilation over a content-addressed cache.

diag

Diagnostics: errors, warnings and notes tied to source spans.

ffi

The C ABI: embedding Reticle in a tool written in another language.

fmt_doc

A Wadler / Prettier-style document printer, shared by the source formatters.

formal

Formal verification: SAT solving, and the engines built on it.

fpga

FPGA targets: device database, primitive mapping, constraints, placement, routing, bitstreams and hand-off to other tools.

intern

Identifier interning.

ip

IP integration: manifests, dependency resolution, bus interfaces, interconnect generation and black boxes.

ir

The unified design IR.

logic

Four-state logic values: single bits, VHDL std_ulogic, and arbitrary-width bit vectors with Verilog operator semantics.

lsp

A language server (LSP) for Verilog and VHDL.

sim

Event-driven simulator over the IR’s process form.

source

Source files, spans and position lookup.

synth

This module is the technology-independent front half of phase 5 of ROADMAP.md. It takes a validated Design whose modules hold processes and continuous assignments, and rewrites every module into cells (dff, dlatch, pmux, memory ports) plus continuous assignments whose expression trees hold the combinational logic. The result is still the same IR, so it can be simulated, checked and emitted like any other design; the later half of the phase (arithmetic lowering, the AIG optimiser and LUT / cell mapping) will consume it.

timing

Static timing analysis and clock domain crossing analysis.

verilog

Verilog / SystemVerilog frontend (IEEE 1364-2005 and the synthesisable and testbench subset of IEEE 1800).

vhdl

VHDL frontend (IEEE 1076-2008, with 1993 compatibility).

viewer

The schematic and documentation viewer: a design rendered as a small static web site.

wasm

The WebAssembly surface: the compiler as plain functions over linear memory.

Constants

VERSION

The crate version, as recorded in Cargo.toml.