redfish_codegen/models/processor/v1_18_0/
instruction_set.rs

1// Generated by redfish-codegen. Do not modify.
2
3
4#[derive(Clone, Debug, serde::Deserialize, serde::Serialize)]
5pub enum InstructionSet {
6    /// x86 32-bit.
7    #[serde(rename = "x86")]
8    X86,
9    /// x86 64-bit.
10    #[serde(rename = "x86-64")]
11    X8664,
12    /// Intel IA-64.
13    #[serde(rename = "IA-64")]
14    IA64,
15    /// ARM 32-bit.
16    #[serde(rename = "ARM-A32")]
17    ARMA32,
18    /// ARM 64-bit.
19    #[serde(rename = "ARM-A64")]
20    ARMA64,
21    /// MIPS 32-bit.
22    MIPS32,
23    /// MIPS 64-bit.
24    MIPS64,
25    /// PowerISA-64 or PowerISA-32. Added in version v1_4_0.
26    PowerISA,
27    /// OEM-defined.
28    OEM,
29}
30
31#[allow(clippy::derivable_impls)]
32impl Default for InstructionSet {
33     fn default() -> InstructionSet {
34        InstructionSet::X86
35     }
36}
37
38impl crate::Metadata<'static> for InstructionSet {
39    const JSON_SCHEMA: &'static str = "Processor.v1_18_0.json";
40}