Module page_cache 

SIEVE Page Cache Implementation

A simple, efficient page cache using the SIEVE eviction algorithm. SIEVE outperforms LRU in many workloads while being simpler to implement.

SIEVE Algorithm (NSDI ’24)

SIEVE uses a single “visited” bit instead of LRU’s complex list management:

1. On cache hit: set visited = true
2. On cache miss (insertion): add to FIFO queue
3. On eviction: sweep from “hand” position
   • If visited=true: clear bit, skip
   • If visited=false: evict this entry

References

• Turso core/storage/page_cache.rs:24-80 - PageCacheShardEntry with ref_bit
• Turso core/storage/page_cache.rs:129-150 - advance_clock_hand()
• “SIEVE is Simpler than LRU” (NSDI ’24)

Structs

CacheStats

Cache statistics

PageCache

Sharded page cache.

PageCacheShard

SIEVE-based page cache

Constants

DEFAULT_CACHE_CAPACITY

Default cache capacity (number of pages) Turso uses 100,000 pages (~400MB for 4KB pages)

MIN_CACHE_CAPACITY

Minimum cache capacity