reda_spice/simulate/
mod.rs1use crate::{
2 netlist::Circuit,
3 probe::{AcAnalysis, DcVoltageAnalysis, OpAnalysis, TranAnalysis},
4 AcCommand, DcCommand, ToSpice, TranCommand
5};
6pub mod ngspice;
7
8pub trait Simulate {
9 type Err;
10 fn run_op(&mut self, netlist: &str) -> Result<OpAnalysis, Self::Err>;
11 fn run_dc(&mut self, netlist: &str) -> Result<DcVoltageAnalysis, Self::Err>;
12 fn run_tran(&mut self, netlist: &str) -> Result<TranAnalysis, Self::Err>;
13 fn run_ac(&mut self, netlist: &str) -> Result<AcAnalysis, Self::Err>;
14}
15
16#[derive(Debug)]
17pub struct Simulator<S> {
18 pub circuit: Circuit,
19 pub simulate: S,
20}
21
22impl<S: Simulate> Simulator<S> {
23 pub fn new(circuit: Circuit, simulate: S) -> Self {
24 Self {
25 circuit,
26 simulate,
27 }
28 }
29
30 pub fn run_op(&mut self) -> Result<OpAnalysis, S::Err> {
31 let mut circuit = self.circuit.to_spice();
32 circuit.push_str("\n.op\n.end");
33 self.simulate.run_op(&circuit)
34 }
35
36 pub fn run_tran(&mut self, command: &TranCommand) -> Result<TranAnalysis, S::Err> {
37 let mut circuit = self.circuit.to_spice();
38 circuit.push('\n');
39 circuit.push_str(&command.to_spice());
40 circuit.push_str("\n.end");
41 self.simulate.run_tran(&circuit)
42 }
43
44 pub fn run_dc_voltage(&mut self, command: &DcCommand) -> Result<DcVoltageAnalysis, S::Err> {
45 let mut circuit = self.circuit.to_spice();
46 circuit.push('\n');
47 circuit.push_str(&command.to_spice());
48 circuit.push_str("\n.end");
49 self.simulate.run_dc(&circuit)
50 }
51
52 pub fn run_ac(&mut self, command: &AcCommand) -> Result<AcAnalysis, S::Err> {
53 let mut circuit = self.circuit.to_spice();
54 circuit.push('\n');
55 circuit.push_str(&command.to_spice());
56 circuit.push_str("\n.end");
57 self.simulate.run_ac(&circuit)
58 }
59}
60