reda_lib/model/
library.rs

1use reda_lib_macro::model;
2use crate::{lib_enum, model::LibCell};
3
4use super::{LibCapacitiveLoadUnit, LibCurrentUnit, LibLeakagePowerUnit, LibPullingResistanceUnit, LibTimeUnit, LibVoltageUnit};
5
6#[model]
7#[derive(Debug, Clone, Default)]
8pub struct LibLibrary {
9    pub name: String,
10
11    // documentation attributes
12    pub date: String,
13    pub revision: Option<String>,
14    pub comment: Option<String>,
15
16    // general attributes
17    pub delay_model: LibDelayModel,
18
19    // units attributes
20    pub time_unit: LibTimeUnit,
21    pub voltage_unit: LibVoltageUnit,
22    pub capacitive_load_unit: Option<LibCapacitiveLoadUnit>,
23    pub current_unit: Option<LibCurrentUnit>,
24    pub pulling_resistance_unit: Option<LibPullingResistanceUnit>,
25    pub leakage_power_unit: Option<LibLeakagePowerUnit>,
26
27    // operation conditions
28    pub nom_process: Option<f64>,
29    pub nom_temperature: Option<f64>,
30    pub nom_voltage: Option<f64>,
31    pub default_operating_conditions: Option<String>,
32
33    //  threshold definitions
34    pub slew_lower_threshold_pct_fall: f64,
35    pub slew_lower_threshold_pct_rise: f64,
36    pub slew_upper_threshold_pct_fall: f64,
37    pub slew_upper_threshold_pct_rise: f64,
38    pub slew_derate_from_library: f64,
39    pub input_threshold_pct_fall: f64,
40    pub input_threshold_pct_rise: f64,
41    pub output_threshold_pct_fall: f64,
42    pub output_threshold_pct_rise: f64,
43    pub default_leakage_power_density: f64,
44    pub default_cell_leakage_power: f64,
45
46    // default pin attributes
47    pub default_inout_pin_cap: Option<f64>,
48    pub default_input_pin_cap: Option<f64>,
49    pub default_output_pin_cap: Option<f64>,
50    pub default_fanout_load: Option<f64>,
51    pub default_max_transition: Option<f64>,
52
53    // groups
54    pub cells: Vec<LibCell>,
55    pub operating_conditions: Vec<LibOperatingConditions>,
56    pub lu_table_templates: Vec<LibLuTableTemplate>,
57}
58
59#[model]
60#[derive(Debug, Clone, Default)]
61pub struct LibLuTableTemplate {
62    pub name: String,
63    pub variable_1: Option<LibLuTableTemplateVariable>,
64    pub variable_2: Option<LibLuTableTemplateVariable>,
65    pub variable_3: Option<LibLuTableTemplateVariable>,
66    pub index_1: Option<Vec<f64>>,
67    pub index_2: Option<Vec<f64>>,
68    pub index_3: Option<Vec<f64>>,
69}
70
71impl LibLibrary {
72    pub fn new<S: Into<String>>(name: S) -> Self {
73        Self { 
74            name: name.into(),
75            ..Default::default()
76        }
77    }
78
79    pub fn cell(&self, name: &str) -> Option<&LibCell> {
80        self.cells.iter().find(|c| c.name == name)
81    }
82}
83
84#[model]
85#[derive(Debug, Clone)]
86pub struct LibOperatingConditions {
87    pub name: String,
88    pub process: f64,
89    pub voltage: f64,
90    pub temperature: f64,
91    pub calc_mode: Option<String>,
92    pub parameteri: Option<f64>,
93    pub process_label: Option<String>,
94    pub tree_type: Option<LibTreeType>,
95}
96
97lib_enum!(LibTechnology, coms, fpga);
98lib_enum!(LibDelayModel, table_lookup, polynomial);
99lib_enum!(LibTreeType, best_case_tree, balanced_tree, worst_case_tree);
100lib_enum!(LibLuTableTemplateVariable, 
101    input_net_transition, 
102    total_output_net_capacitance,
103    output_net_length, 
104    output_net_wire_cap,
105    output_net_pin_cap,
106    related_out_total_output_net_capacitance,
107    related_out_output_net_length,
108    related_out_output_net_wire_cap,
109    related_out_output_net_pin_cap,
110    constrained_pin_transition,
111    related_pin_transition
112);
reda_lib/model/library.rs

reda_lib/model/
library.rs
