Enum rcudnn_sys::cudaDeviceAttr[−][src]

#[repr(u32)]
#[non_exhaustive]
pub enum cudaDeviceAttr {
Show 113 variants    cudaDevAttrMaxThreadsPerBlock,
    cudaDevAttrMaxBlockDimX,
    cudaDevAttrMaxBlockDimY,
    cudaDevAttrMaxBlockDimZ,
    cudaDevAttrMaxGridDimX,
    cudaDevAttrMaxGridDimY,
    cudaDevAttrMaxGridDimZ,
    cudaDevAttrMaxSharedMemoryPerBlock,
    cudaDevAttrTotalConstantMemory,
    cudaDevAttrWarpSize,
    cudaDevAttrMaxPitch,
    cudaDevAttrMaxRegistersPerBlock,
    cudaDevAttrClockRate,
    cudaDevAttrTextureAlignment,
    cudaDevAttrGpuOverlap,
    cudaDevAttrMultiProcessorCount,
    cudaDevAttrKernelExecTimeout,
    cudaDevAttrIntegrated,
    cudaDevAttrCanMapHostMemory,
    cudaDevAttrComputeMode,
    cudaDevAttrMaxTexture1DWidth,
    cudaDevAttrMaxTexture2DWidth,
    cudaDevAttrMaxTexture2DHeight,
    cudaDevAttrMaxTexture3DWidth,
    cudaDevAttrMaxTexture3DHeight,
    cudaDevAttrMaxTexture3DDepth,
    cudaDevAttrMaxTexture2DLayeredWidth,
    cudaDevAttrMaxTexture2DLayeredHeight,
    cudaDevAttrMaxTexture2DLayeredLayers,
    cudaDevAttrSurfaceAlignment,
    cudaDevAttrConcurrentKernels,
    cudaDevAttrEccEnabled,
    cudaDevAttrPciBusId,
    cudaDevAttrPciDeviceId,
    cudaDevAttrTccDriver,
    cudaDevAttrMemoryClockRate,
    cudaDevAttrGlobalMemoryBusWidth,
    cudaDevAttrL2CacheSize,
    cudaDevAttrMaxThreadsPerMultiProcessor,
    cudaDevAttrAsyncEngineCount,
    cudaDevAttrUnifiedAddressing,
    cudaDevAttrMaxTexture1DLayeredWidth,
    cudaDevAttrMaxTexture1DLayeredLayers,
    cudaDevAttrMaxTexture2DGatherWidth,
    cudaDevAttrMaxTexture2DGatherHeight,
    cudaDevAttrMaxTexture3DWidthAlt,
    cudaDevAttrMaxTexture3DHeightAlt,
    cudaDevAttrMaxTexture3DDepthAlt,
    cudaDevAttrPciDomainId,
    cudaDevAttrTexturePitchAlignment,
    cudaDevAttrMaxTextureCubemapWidth,
    cudaDevAttrMaxTextureCubemapLayeredWidth,
    cudaDevAttrMaxTextureCubemapLayeredLayers,
    cudaDevAttrMaxSurface1DWidth,
    cudaDevAttrMaxSurface2DWidth,
    cudaDevAttrMaxSurface2DHeight,
    cudaDevAttrMaxSurface3DWidth,
    cudaDevAttrMaxSurface3DHeight,
    cudaDevAttrMaxSurface3DDepth,
    cudaDevAttrMaxSurface1DLayeredWidth,
    cudaDevAttrMaxSurface1DLayeredLayers,
    cudaDevAttrMaxSurface2DLayeredWidth,
    cudaDevAttrMaxSurface2DLayeredHeight,
    cudaDevAttrMaxSurface2DLayeredLayers,
    cudaDevAttrMaxSurfaceCubemapWidth,
    cudaDevAttrMaxSurfaceCubemapLayeredWidth,
    cudaDevAttrMaxSurfaceCubemapLayeredLayers,
    cudaDevAttrMaxTexture1DLinearWidth,
    cudaDevAttrMaxTexture2DLinearWidth,
    cudaDevAttrMaxTexture2DLinearHeight,
    cudaDevAttrMaxTexture2DLinearPitch,
    cudaDevAttrMaxTexture2DMipmappedWidth,
    cudaDevAttrMaxTexture2DMipmappedHeight,
    cudaDevAttrComputeCapabilityMajor,
    cudaDevAttrComputeCapabilityMinor,
    cudaDevAttrMaxTexture1DMipmappedWidth,
    cudaDevAttrStreamPrioritiesSupported,
    cudaDevAttrGlobalL1CacheSupported,
    cudaDevAttrLocalL1CacheSupported,
    cudaDevAttrMaxSharedMemoryPerMultiprocessor,
    cudaDevAttrMaxRegistersPerMultiprocessor,
    cudaDevAttrManagedMemory,
    cudaDevAttrIsMultiGpuBoard,
    cudaDevAttrMultiGpuBoardGroupID,
    cudaDevAttrHostNativeAtomicSupported,
    cudaDevAttrSingleToDoublePrecisionPerfRatio,
    cudaDevAttrPageableMemoryAccess,
    cudaDevAttrConcurrentManagedAccess,
    cudaDevAttrComputePreemptionSupported,
    cudaDevAttrCanUseHostPointerForRegisteredMem,
    cudaDevAttrReserved92,
    cudaDevAttrReserved93,
    cudaDevAttrReserved94,
    cudaDevAttrCooperativeLaunch,
    cudaDevAttrCooperativeMultiDeviceLaunch,
    cudaDevAttrMaxSharedMemoryPerBlockOptin,
    cudaDevAttrCanFlushRemoteWrites,
    cudaDevAttrHostRegisterSupported,
    cudaDevAttrPageableMemoryAccessUsesHostPageTables,
    cudaDevAttrDirectManagedMemAccessFromHost,
    cudaDevAttrMaxBlocksPerMultiprocessor,
    cudaDevAttrMaxPersistingL2CacheSize,
    cudaDevAttrMaxAccessPolicyWindowSize,
    cudaDevAttrReservedSharedMemoryPerBlock,
    cudaDevAttrSparseCudaArraySupported,
    cudaDevAttrHostRegisterReadOnlySupported,
    cudaDevAttrMaxTimelineSemaphoreInteropSupported,
    cudaDevAttrMemoryPoolsSupported,
    cudaDevAttrGPUDirectRDMASupported,
    cudaDevAttrGPUDirectRDMAFlushWritesOptions,
    cudaDevAttrGPUDirectRDMAWritesOrdering,
    cudaDevAttrMemoryPoolSupportedHandleTypes,
    cudaDevAttrMax,
}

Expand description

CUDA device attributes

Variants (Non-exhaustive)

This enum is marked as non-exhaustive

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

`cudaDevAttrMaxThreadsPerBlock`

< Maximum number of threads per block

`cudaDevAttrMaxBlockDimX`

< Maximum block dimension X

`cudaDevAttrMaxBlockDimY`

< Maximum block dimension Y

`cudaDevAttrMaxBlockDimZ`

< Maximum block dimension Z

`cudaDevAttrMaxGridDimX`

< Maximum grid dimension X

`cudaDevAttrMaxGridDimY`

< Maximum grid dimension Y

`cudaDevAttrMaxGridDimZ`

< Maximum grid dimension Z

`cudaDevAttrMaxSharedMemoryPerBlock`

< Maximum shared memory available per block in bytes

`cudaDevAttrTotalConstantMemory`

< Memory available on device for constant variables in a CUDA C kernel in bytes

`cudaDevAttrWarpSize`

< Warp size in threads

`cudaDevAttrMaxPitch`

< Maximum pitch in bytes allowed by memory copies

`cudaDevAttrMaxRegistersPerBlock`

< Maximum number of 32-bit registers available per block

`cudaDevAttrClockRate`

< Peak clock frequency in kilohertz

`cudaDevAttrTextureAlignment`

< Alignment requirement for textures

`cudaDevAttrGpuOverlap`

< Device can possibly copy memory and execute a kernel concurrently

`cudaDevAttrMultiProcessorCount`

< Number of multiprocessors on device

`cudaDevAttrKernelExecTimeout`

< Specifies whether there is a run time limit on kernels

`cudaDevAttrIntegrated`

< Device is integrated with host memory

`cudaDevAttrCanMapHostMemory`

< Device can map host memory into CUDA address space

`cudaDevAttrComputeMode`

< Compute mode (See ::cudaComputeMode for details)

`cudaDevAttrMaxTexture1DWidth`

< Maximum 1D texture width

`cudaDevAttrMaxTexture2DWidth`

< Maximum 2D texture width

`cudaDevAttrMaxTexture2DHeight`

< Maximum 2D texture height

`cudaDevAttrMaxTexture3DWidth`

< Maximum 3D texture width

`cudaDevAttrMaxTexture3DHeight`

< Maximum 3D texture height

`cudaDevAttrMaxTexture3DDepth`

< Maximum 3D texture depth

`cudaDevAttrMaxTexture2DLayeredWidth`

< Maximum 2D layered texture width

`cudaDevAttrMaxTexture2DLayeredHeight`

< Maximum 2D layered texture height

`cudaDevAttrMaxTexture2DLayeredLayers`

< Maximum layers in a 2D layered texture

`cudaDevAttrSurfaceAlignment`

< Alignment requirement for surfaces

`cudaDevAttrConcurrentKernels`

< Device can possibly execute multiple kernels concurrently

`cudaDevAttrEccEnabled`

< Device has ECC support enabled

`cudaDevAttrPciBusId`

< PCI bus ID of the device

`cudaDevAttrPciDeviceId`

< PCI device ID of the device

`cudaDevAttrTccDriver`

< Device is using TCC driver model

`cudaDevAttrMemoryClockRate`

< Peak memory clock frequency in kilohertz

`cudaDevAttrGlobalMemoryBusWidth`

< Global memory bus width in bits

`cudaDevAttrL2CacheSize`

< Size of L2 cache in bytes

`cudaDevAttrMaxThreadsPerMultiProcessor`

< Maximum resident threads per multiprocessor

`cudaDevAttrAsyncEngineCount`

< Number of asynchronous engines

`cudaDevAttrUnifiedAddressing`

< Device shares a unified address space with the host

`cudaDevAttrMaxTexture1DLayeredWidth`

< Maximum 1D layered texture width

`cudaDevAttrMaxTexture1DLayeredLayers`

< Maximum layers in a 1D layered texture

`cudaDevAttrMaxTexture2DGatherWidth`

< Maximum 2D texture width if cudaArrayTextureGather is set

`cudaDevAttrMaxTexture2DGatherHeight`

< Maximum 2D texture height if cudaArrayTextureGather is set

`cudaDevAttrMaxTexture3DWidthAlt`

< Alternate maximum 3D texture width

`cudaDevAttrMaxTexture3DHeightAlt`

< Alternate maximum 3D texture height

`cudaDevAttrMaxTexture3DDepthAlt`

< Alternate maximum 3D texture depth

`cudaDevAttrPciDomainId`

< PCI domain ID of the device

`cudaDevAttrTexturePitchAlignment`

< Pitch alignment requirement for textures

`cudaDevAttrMaxTextureCubemapWidth`

< Maximum cubemap texture width/height

`cudaDevAttrMaxTextureCubemapLayeredWidth`

< Maximum cubemap layered texture width/height

`cudaDevAttrMaxTextureCubemapLayeredLayers`

< Maximum layers in a cubemap layered texture

`cudaDevAttrMaxSurface1DWidth`

< Maximum 1D surface width

`cudaDevAttrMaxSurface2DWidth`

< Maximum 2D surface width

`cudaDevAttrMaxSurface2DHeight`

< Maximum 2D surface height

`cudaDevAttrMaxSurface3DWidth`

< Maximum 3D surface width

`cudaDevAttrMaxSurface3DHeight`

< Maximum 3D surface height

`cudaDevAttrMaxSurface3DDepth`

< Maximum 3D surface depth

`cudaDevAttrMaxSurface1DLayeredWidth`

< Maximum 1D layered surface width

`cudaDevAttrMaxSurface1DLayeredLayers`

< Maximum layers in a 1D layered surface

`cudaDevAttrMaxSurface2DLayeredWidth`

< Maximum 2D layered surface width

`cudaDevAttrMaxSurface2DLayeredHeight`

< Maximum 2D layered surface height

`cudaDevAttrMaxSurface2DLayeredLayers`

< Maximum layers in a 2D layered surface

`cudaDevAttrMaxSurfaceCubemapWidth`

< Maximum cubemap surface width

`cudaDevAttrMaxSurfaceCubemapLayeredWidth`

< Maximum cubemap layered surface width

`cudaDevAttrMaxSurfaceCubemapLayeredLayers`

< Maximum layers in a cubemap layered surface

`cudaDevAttrMaxTexture1DLinearWidth`

< Maximum 1D linear texture width

`cudaDevAttrMaxTexture2DLinearWidth`

< Maximum 2D linear texture width

`cudaDevAttrMaxTexture2DLinearHeight`

< Maximum 2D linear texture height

`cudaDevAttrMaxTexture2DLinearPitch`

< Maximum 2D linear texture pitch in bytes

`cudaDevAttrMaxTexture2DMipmappedWidth`

< Maximum mipmapped 2D texture width

`cudaDevAttrMaxTexture2DMipmappedHeight`

< Maximum mipmapped 2D texture height

`cudaDevAttrComputeCapabilityMajor`

< Major compute capability version number

`cudaDevAttrComputeCapabilityMinor`

< Minor compute capability version number

`cudaDevAttrMaxTexture1DMipmappedWidth`

< Maximum mipmapped 1D texture width

`cudaDevAttrStreamPrioritiesSupported`

< Device supports stream priorities

`cudaDevAttrGlobalL1CacheSupported`

< Device supports caching globals in L1

`cudaDevAttrLocalL1CacheSupported`

< Device supports caching locals in L1

`cudaDevAttrMaxSharedMemoryPerMultiprocessor`

< Maximum shared memory available per multiprocessor in bytes

`cudaDevAttrMaxRegistersPerMultiprocessor`

< Maximum number of 32-bit registers available per multiprocessor

`cudaDevAttrManagedMemory`

< Device can allocate managed memory on this system

`cudaDevAttrIsMultiGpuBoard`

< Device is on a multi-GPU board

`cudaDevAttrMultiGpuBoardGroupID`

< Unique identifier for a group of devices on the same multi-GPU board

`cudaDevAttrHostNativeAtomicSupported`

< Link between the device and the host supports native atomic operations

`cudaDevAttrSingleToDoublePrecisionPerfRatio`

< Ratio of single precision performance (in floating-point operations per second) to double precision performance

`cudaDevAttrPageableMemoryAccess`

< Device supports coherently accessing pageable memory without calling cudaHostRegister on it

`cudaDevAttrConcurrentManagedAccess`

< Device can coherently access managed memory concurrently with the CPU

`cudaDevAttrComputePreemptionSupported`

< Device supports Compute Preemption

`cudaDevAttrCanUseHostPointerForRegisteredMem`

< Device can access host registered memory at the same virtual address as the CPU

`cudaDevAttrReserved92`

`cudaDevAttrReserved93`

`cudaDevAttrReserved94`

`cudaDevAttrCooperativeLaunch`

< Device supports launching cooperative kernels via ::cudaLaunchCooperativeKernel

`cudaDevAttrCooperativeMultiDeviceLaunch`

< Deprecated, cudaLaunchCooperativeKernelMultiDevice is deprecated.

`cudaDevAttrMaxSharedMemoryPerBlockOptin`

< The maximum optin shared memory per block. This value may vary by chip. See ::cudaFuncSetAttribute

`cudaDevAttrCanFlushRemoteWrites`

< Device supports flushing of outstanding remote writes.

`cudaDevAttrHostRegisterSupported`

< Device supports host memory registration via ::cudaHostRegister.

`cudaDevAttrPageableMemoryAccessUsesHostPageTables`

< Device accesses pageable memory via the host’s page tables.

`cudaDevAttrDirectManagedMemAccessFromHost`

< Host can directly access managed memory on the device without migration.

`cudaDevAttrMaxBlocksPerMultiprocessor`

< Maximum number of blocks per multiprocessor

`cudaDevAttrMaxPersistingL2CacheSize`

< Maximum L2 persisting lines capacity setting in bytes.

`cudaDevAttrMaxAccessPolicyWindowSize`

< Maximum value of cudaAccessPolicyWindow::num_bytes.

`cudaDevAttrReservedSharedMemoryPerBlock`

< Shared memory reserved by CUDA driver per block in bytes

`cudaDevAttrSparseCudaArraySupported`

< Device supports sparse CUDA arrays and sparse CUDA mipmapped arrays

`cudaDevAttrHostRegisterReadOnlySupported`

< Device supports using the ::cudaHostRegister flag cudaHostRegisterReadOnly to register memory that must be mapped as read-only to the GPU

`cudaDevAttrMaxTimelineSemaphoreInteropSupported`

< External timeline semaphore interop is supported on the device

`cudaDevAttrMemoryPoolsSupported`

< Device supports using the ::cudaMallocAsync and ::cudaMemPool family of APIs

`cudaDevAttrGPUDirectRDMASupported`

< Device supports GPUDirect RDMA APIs, like nvidia_p2p_get_pages (see https://docs.nvidia.com/cuda/gpudirect-rdma for more information)

`cudaDevAttrGPUDirectRDMAFlushWritesOptions`

< The returned attribute shall be interpreted as a bitmask, where the individual bits are listed in the ::cudaFlushGPUDirectRDMAWritesOptions enum

`cudaDevAttrGPUDirectRDMAWritesOrdering`

< GPUDirect RDMA writes to the device do not need to be flushed for consumers within the scope indicated by the returned attribute. See ::cudaGPUDirectRDMAWritesOrdering for the numerical values returned here.