pub struct ProcessorTraceInfo { /* private fields */ }

Implementations§

If true, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH MSR can be accessed.

If true, Indicates support of Configurable PSB and Cycle-Accurate Mode.

If true, Indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across warm reset.

If true, Indicates support of MTC timing packet and suppression of COFI-based packets.

Indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets

Support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn) enabling Power Event Trace packet generation.

If true, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.

If true, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.

If true, Indicates support of Single-Range Output scheme.

If true, Indicates support of output to Trace Transport subsystem.

If true, Generated packets which contain IP payloads have LIP values, which include the CS base component.

Number of configurable Address Ranges for filtering (Bits 2:0).

Bitmap of supported MTC period encodings (Bit 31:16).

Bitmap of supported Cycle Threshold value encodings (Bits 15-0).

Bitmap of supported Configurable PSB frequency encodings (Bit 31:16)

Trait Implementations§

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