pub struct ExtendedFeatures { /* fields omitted */ }
Expand description
Structured Extended Feature Identifiers (LEAF=0x07).
🟡 AMD ✅ Intel
FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
✅ AMD ✅ Intel
IA32_TSC_ADJUST MSR is supported if 1.
❌ AMD (reserved) ✅ Intel
HLE
❌ AMD (reserved) ✅ Intel
FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if
1.
❌ AMD (reserved) ✅ Intel
SMEP. Supports Supervisor-Mode Execution Prevention if 1.
✅ AMD ✅ Intel
Supports Enhanced REP MOVSB/STOSB if 1.
❌ AMD (reserved) ✅ Intel
INVPCID. If 1, supports INVPCID instruction for system software that
manages process-context identifiers.
❌ AMD (reserved) ✅ Intel
RTM
❌ AMD (reserved) ✅ Intel
Supports Intel Resource Director Technology (RDT) Monitoring capability.
❌ AMD (reserved) ✅ Intel
Deprecates FPU CS and FPU DS values if 1.
❌ AMD (reserved) ✅ Intel
MPX. Supports Intel Memory Protection Extensions if 1.
❌ AMD (reserved) ✅ Intel
Supports Intel Resource Director Technology (RDT) Allocation capability.
❌ AMD (reserved) ✅ Intel
Supports RDSEED.
✅ AMD ✅ Intel
Supports ADX.
✅ AMD ✅ Intel
SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
instructions) if 1.
✅ AMD ✅ Intel
Supports CLFLUSHOPT.
✅ AMD ✅ Intel
Supports Intel Processor Trace.
❌ AMD (reserved) ✅ Intel
Supports SHA Instructions.
❌ AMD (reserved) ✅ Intel
Supports Intel® Software Guard Extensions (Intel® SGX Extensions).
❌ AMD (reserved) ✅ Intel
Supports AVX512F.
❌ AMD (reserved) ✅ Intel
Supports AVX512DQ.
❌ AMD (reserved) ✅ Intel
AVX512_IFMA
❌ AMD (reserved) ✅ Intel
AVX512PF
❌ AMD (reserved) ✅ Intel
AVX512ER
❌ AMD (reserved) ✅ Intel
AVX512CD
❌ AMD (reserved) ✅ Intel
AVX512BW
❌ AMD (reserved) ✅ Intel
AVX512VL
❌ AMD (reserved) ✅ Intel
Has PREFETCHWT1 (Intel® Xeon Phi™ only).
❌ AMD (reserved) ✅ Intel
Supports user-mode instruction prevention if 1.
❌ AMD (reserved) ✅ Intel
Supports protection keys for user-mode pages.
❌ AMD (reserved) ✅ Intel
OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU
instructions.
❌ AMD (reserved) ✅ Intel
RDPID and IA32_TSC_AUX are available.
The Intel manual lists RDPID as bit 22 in the ECX register, but AMD
lists it as bit 22 in the ebx register. We assumed that the AMD manual
was wrong and query ecx, let’s see what happens.
✅ AMD ✅ Intel
Supports SGX Launch Configuration.
❌ AMD (reserved) ✅ Intel
The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
❌ AMD (reserved) ✅ Intel
Formats the value using the given formatter. Read more
impl<T> Any for T where
T: 'static + ?Sized,
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more
impl<T, U> Into<U> for T where
U: From<T>,
The type returned in the event of a conversion error.
The type returned in the event of a conversion error.