raw_acpi/madt/
giccpu_interface.rs

1#[derive(Copy, Clone)]
2/// ## GIC CPU Interface Flags
3pub struct GICCPUInterfaceFlags(u32);
4impl GICCPUInterfaceFlags {
5    /// If this bit is set, the processor is ready for use. If this bit is clear and the Online Capable bit is set, the system supports enabling this processor during OS runtime.<br>
6    /// If this bit is clear and the Online Capable bit is also clear, this processor is unusable, and the operating system support will not attempt to use it.
7    pub const fn enabled(&self) -> bool {
8        self.0 & 0b0001 != 0
9    }
10    /// - 0 - Level-triggered
11    /// - 1 - Edge-triggered
12    pub const fn performance_interrupt_mode(&self) -> bool {
13        self.0 & 0b0010 != 0
14    }
15    /// - 0 - Level-triggered
16    /// - 1 - Edge-triggered
17    pub const fn vgic_maintenance_interrupt_mode_flags(&self) -> bool {
18        self.0 & 0b0100 != 0
19    }
20    /// The information conveyed by this bit depends on the value of the Enabled bit.
21    ///
22    /// If the Enabled bit is set, this bit is reserved and must be zero.
23    /// Otherwise, if this bit is set, the system supports enabling this processor later during OS runtime.
24    pub const fn online_capable(&self) -> bool {
25        self.0 & 0b1000 != 0
26    }
27    // JJ here, the rest of the bits are reserved; no need to implement.
28}
29
30#[derive(Copy, Clone)]
31#[repr(C, packed)]
32/// ## GIC CPU Interface (GICC) Structure
33///
34/// In the GIC interrupt model, logical processors are required to have a Processor Device object in the DSDT,
35/// and must convey each processor's GIC information to the OS using the GICC structure.
36pub struct GICCPUInterface {
37    /// 11 - GICC Structure
38    pub r#type: u8,
39    /// 82
40    pub length: u8,
41    reserved0: u16,
42    /// GIC's CPU Interface Number.
43    ///
44    /// In GICv1/v2 implementations, this value matches the bit index of the associated processor in the GIC distributor's GICD_ITARGETSR register.<br>
45    /// For GICv3/4 implementations, this field must be provided by the platform, if compatibility mode is supported.
46    ///
47    /// If it is not supported by the implementation, then this field must be zero.
48    pub cpu_interface_number: u32,
49    /// The OS associates this GICC Structure with a processor device object in the namespace
50    /// when the _UID child object of the processor device evaluates to a numeric value that matches the numeric value in this field.
51    pub acpi_processor_uid: u32,
52    /// GIC CPU Interface Flags.
53    pub flags: GICCPUInterfaceFlags,
54    /// Version of the ARM-Processor Parking Protocol implemented.
55    ///
56    /// See http://uefi.org/acpi.  The document link is listed under "Multiprocessor Startup for ARM Platforms."
57    ///
58    /// For systems that support PSCI exclusively and do not support the parking protocol, this field must be set to 0.
59    pub parking_protocol_version: u32,
60    /// The GSIV used for Performance Monitoring Interrupts.
61    pub performance_interrupt_gsiv: u32,
62    /// The 64-bit physical address of the processor's Parking Protocol mailbox.
63    pub parked_address: u64,
64    /// On GICv1/v2 systems and GICv3/4 systems in GICv2 compatibility mode,
65    /// this field holds the 64-bit physical address at which the processor can access this GIC CPU Interface.
66    ///
67    /// If provided here, the "Local Interrupt Controller Address" field in the MADT must be ignored by the OSPM.
68    pub physical_base_address: u64,
69    /// Address of the GIC virtual CPU interface registers.
70    ///
71    /// If the platform is not presenting a GICv2 with virtualization extensions this field can be 0.
72    pub gicv: u64,
73    /// Address of the GIC virtual interface control block registers.
74    ///
75    /// If the platform is not presenting a GICv2 with virtualization extensions this field can be 0.
76    pub gich: u64,
77    /// GSIV for Virtual GIC maintenance interrupt.
78    pub vgic_maintenance_interrupt: u32,
79    /// On systems supporting GICv3 and above, this field holds the 64-bit physical address of the associated Redistributor.
80    ///
81    /// If all of the GIC Redistributors are in the always-on power domain, GICR structures should be used to describe the Redistributors instead, and this field must be set to 0.
82    ///
83    /// If a GICR structure is present in the MADT then this field must be ignored by the OSPM.
84    pub gicr_base_address: u64,
85    /// This fields follows the MPIDR formatting of ARM architecture. If ARMv7 architecture is used then the format must be as follows:
86    ///
87    /// - **Bits [[63:24]]** - Must be zero.
88    /// - **Bits [[23:16]] Aff2** - Match Aff2 of target processor MPIDR.
89    /// - **Bits [[15:08]] Aff1** - Match Aff1 of target processor MPIDR.
90    /// - **Bits [[07:00]] Aff0** - Match Aff0 of target processor MPIDR.
91    ///
92    /// For platforms implementing ARMv8 the format must be:
93    ///
94    /// - **Bits [[63:40]]** - Must be zero
95    /// - **Bits [[39:32]] Aff3** - Match Aff3 of target processor MPIDR
96    /// - **Bits [[31:24]]** - Must be zero
97    /// - **Bits [[23:16]] Aff2** - Match Aff2 of target processor MPIDR
98    /// - **Bits [[15:08]] Aff1** - Match Aff1 of target processor MPIDR
99    /// - **Bits [[07:00]] Aff0** - Match Aff0 of target processor MPIDR
100    pub mpidr: u64,
101    /// Describes the relative power efficiency of the associated processor.
102    ///
103    /// Lower efficiency class numbers are more efficient than higher ones (e.g. efficiency class 0 should be treated as more efficient than efficiency class 1).
104    /// However, absolute values of this number have no meaning: 2 isn't necessarily half as efficient as 1.
105    pub processor_power_efficiency_class: u8,
106    reserved1: u8,
107    /// Statistical Profiling Extension buffer overflow GSIV.
108    ///
109    /// This interrupt is a level triggered PPI. Zero if SPE is not supported by this processor.
110    pub spe_overflow_interrupt: u16,
111    /// Trace Buffer Extension interrupt GSIV.
112    ///
113    /// This interrupt is a level triggered PPI. Zero if TRBE feature is not supported by this processor.
114    ///
115    /// NOTE: This field was introduced in ACPI Specification version 6.5.
116    ///
117    /// **JJ's Note: The previous note is EXTREMELY important.  This structure will be 2 bytes less (80 bytes total) in memory with ACPI 6.4 or lower.**
118    pub trbe_interrupt: u16,
119}
raw_acpi/madt/giccpu_interface.rs

raw_acpi/madt/
giccpu_interface.rs
