raw_acpi/madt/core_pic.rs
1#[derive(Copy, Clone)]
2/// ## CORE PIC Flags
3pub struct COREPICFlags(u32);
4impl COREPICFlags {
5 /// If Physical Processor ID is invalid, OSPM shall ignore this field, and OSPM shall ignore Core Programmable Interrupt Controller Structure.<br>
6 /// If Physical Processor ID is valid and if this Enabled bit is clear, this processor will be unusable on booting, and can be online during OS runtime.<br>
7 /// If Physical Processor ID is valid and if this Enabled bit is set, this processor is ready for using.
8 pub const fn enabled(&self) -> bool {
9 self.0 & 0b1 != 0
10 }
11 // JJ here, the rest of the bits are reserved; no need to implement.
12}
13
14#[derive(Copy, Clone)]
15#[repr(C, packed)]
16/// ## Core Programmable Interrupt Controller (CORE PIC) Structure
17///
18/// Each processor in Loongarch system has a Core Programmable Interrupt Controller record in the MADT, and a processor device object in the DSDT.
19pub struct CoreProgrammableInterruptController {
20 /// 17 - Core Programmable Interrupt Controller Structure
21 pub r#type: u8,
22 /// Length of the Core Programmable Interrupt Controller Structure in bytes.
23 ///
24 /// **JJ's Note: There doesn't seem to be any variable-sized fields in this struct. The size is 15 bytes...**
25 pub length: u8,
26 /// - **0x00** - Invalid
27 /// - **0x01** - CORE PIC v1
28 ///
29 /// Other values are reserved.
30 pub version: u8,
31 /// The OS associates this CORE PIC Structure with a processor device object in the namespace
32 /// when the _UID child object of the processor device evaluates to a numeric value that matches the numeric value in this field.
33 pub acpi_processor_id: u32,
34 /// The processor core physical id.
35 ///
36 /// 0xFFFFFFFF is invalid value.
37 ///
38 /// If invalid, this processor is unusable, and OSPM shall ignore Core Interrupt Controller Structure.
39 pub phsyical_processor_id: u32,
40 /// CORE PIC flags.
41 pub flags: COREPICFlags,
42}