1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"On-Chip Debug"]
28unsafe impl ::core::marker::Send for super::OcdCpu {}
29unsafe impl ::core::marker::Sync for super::OcdCpu {}
30impl super::OcdCpu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "MCU Control Register"]
38 #[inline(always)]
39 pub const fn mcuctrl(
40 &self,
41 ) -> &'static crate::common::Reg<self::Mcuctrl_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Mcuctrl_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(4usize),
45 )
46 }
47 }
48
49 #[doc = "JTAG Boot Mode Entry Register"]
50 #[inline(always)]
51 pub const fn jbmdr(&self) -> &'static crate::common::Reg<self::Jbmdr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Jbmdr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(256usize),
55 )
56 }
57 }
58
59 #[doc = "JTAG Boot Receive Data Register"]
60 #[inline(always)]
61 pub const fn jbrdr(&self) -> &'static crate::common::Reg<self::Jbrdr_SPEC, crate::common::RW> {
62 unsafe {
63 crate::common::Reg::<self::Jbrdr_SPEC, crate::common::RW>::from_ptr(
64 self._svd2pac_as_ptr().add(288usize),
65 )
66 }
67 }
68
69 #[doc = "JTAG Boot Transmit Data Register"]
70 #[inline(always)]
71 pub const fn jbtdr(&self) -> &'static crate::common::Reg<self::Jbtdr_SPEC, crate::common::RW> {
72 unsafe {
73 crate::common::Reg::<self::Jbtdr_SPEC, crate::common::RW>::from_ptr(
74 self._svd2pac_as_ptr().add(304usize),
75 )
76 }
77 }
78
79 #[doc = "JTAG Boot Status Register"]
80 #[inline(always)]
81 pub const fn jbstr(&self) -> &'static crate::common::Reg<self::Jbstr_SPEC, crate::common::RW> {
82 unsafe {
83 crate::common::Reg::<self::Jbstr_SPEC, crate::common::RW>::from_ptr(
84 self._svd2pac_as_ptr().add(320usize),
85 )
86 }
87 }
88
89 #[doc = "JTAG Boot Interrupt Control Register"]
90 #[inline(always)]
91 pub const fn jbicr(&self) -> &'static crate::common::Reg<self::Jbicr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Jbicr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(336usize),
95 )
96 }
97 }
98}
99#[doc(hidden)]
100#[derive(Copy, Clone, Eq, PartialEq)]
101pub struct Mcuctrl_SPEC;
102impl crate::sealed::RegSpec for Mcuctrl_SPEC {
103 type DataType = u32;
104}
105
106#[doc = "MCU Control Register"]
107pub type Mcuctrl = crate::RegValueT<Mcuctrl_SPEC>;
108
109impl Mcuctrl {
110 #[doc = "External Debug Request. Writing 1 to the bit causes a CPU Halt or Debug Monitor exception request."]
111 #[inline(always)]
112 pub fn edbgrq(
113 self,
114 ) -> crate::common::RegisterField<
115 0,
116 0x1,
117 1,
118 0,
119 mcuctrl::Edbgrq,
120 mcuctrl::Edbgrq,
121 Mcuctrl_SPEC,
122 crate::common::RW,
123 > {
124 crate::common::RegisterField::<
125 0,
126 0x1,
127 1,
128 0,
129 mcuctrl::Edbgrq,
130 mcuctrl::Edbgrq,
131 Mcuctrl_SPEC,
132 crate::common::RW,
133 >::from_register(self, 0)
134 }
135
136 #[inline(always)]
137 pub fn cpuwait(
138 self,
139 ) -> crate::common::RegisterField<
140 16,
141 0x1,
142 1,
143 0,
144 mcuctrl::Cpuwait,
145 mcuctrl::Cpuwait,
146 Mcuctrl_SPEC,
147 crate::common::RW,
148 > {
149 crate::common::RegisterField::<
150 16,
151 0x1,
152 1,
153 0,
154 mcuctrl::Cpuwait,
155 mcuctrl::Cpuwait,
156 Mcuctrl_SPEC,
157 crate::common::RW,
158 >::from_register(self, 0)
159 }
160}
161impl ::core::default::Default for Mcuctrl {
162 #[inline(always)]
163 fn default() -> Mcuctrl {
164 <crate::RegValueT<Mcuctrl_SPEC> as RegisterValue<_>>::new(0)
165 }
166}
167pub mod mcuctrl {
168
169 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
170 pub struct Edbgrq_SPEC;
171 pub type Edbgrq = crate::EnumBitfieldStruct<u8, Edbgrq_SPEC>;
172 impl Edbgrq {
173 #[doc = "Debug event is not requested"]
174 pub const _0: Self = Self::new(0);
175
176 #[doc = "Debug event is requested"]
177 pub const _1: Self = Self::new(1);
178 }
179 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
180 pub struct Cpuwait_SPEC;
181 pub type Cpuwait = crate::EnumBitfieldStruct<u8, Cpuwait_SPEC>;
182 impl Cpuwait {
183 #[doc = "Deassert CPUWAIT CPU starts boot-up sequence and instruction execution out of Reset."]
184 pub const _0: Self = Self::new(0);
185
186 #[doc = "Assert CPUWAIT CPU is forced into a quiescent state out of Reset."]
187 pub const _1: Self = Self::new(1);
188 }
189}
190#[doc(hidden)]
191#[derive(Copy, Clone, Eq, PartialEq)]
192pub struct Jbmdr_SPEC;
193impl crate::sealed::RegSpec for Jbmdr_SPEC {
194 type DataType = u32;
195}
196
197#[doc = "JTAG Boot Mode Entry Register"]
198pub type Jbmdr = crate::RegValueT<Jbmdr_SPEC>;
199
200impl Jbmdr {
201 #[doc = "Mode entry key"]
202 #[inline(always)]
203 pub fn key(
204 self,
205 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Jbmdr_SPEC, crate::common::RW> {
206 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Jbmdr_SPEC,crate::common::RW>::from_register(self,0)
207 }
208}
209impl ::core::default::Default for Jbmdr {
210 #[inline(always)]
211 fn default() -> Jbmdr {
212 <crate::RegValueT<Jbmdr_SPEC> as RegisterValue<_>>::new(0)
213 }
214}
215
216#[doc(hidden)]
217#[derive(Copy, Clone, Eq, PartialEq)]
218pub struct Jbrdr_SPEC;
219impl crate::sealed::RegSpec for Jbrdr_SPEC {
220 type DataType = u32;
221}
222
223#[doc = "JTAG Boot Receive Data Register"]
224pub type Jbrdr = crate::RegValueT<Jbrdr_SPEC>;
225
226impl Jbrdr {
227 #[doc = "Received data register"]
228 #[inline(always)]
229 pub fn rdat(
230 self,
231 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Jbrdr_SPEC, crate::common::RW>
232 {
233 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Jbrdr_SPEC,crate::common::RW>::from_register(self,0)
234 }
235}
236impl ::core::default::Default for Jbrdr {
237 #[inline(always)]
238 fn default() -> Jbrdr {
239 <crate::RegValueT<Jbrdr_SPEC> as RegisterValue<_>>::new(0)
240 }
241}
242
243#[doc(hidden)]
244#[derive(Copy, Clone, Eq, PartialEq)]
245pub struct Jbtdr_SPEC;
246impl crate::sealed::RegSpec for Jbtdr_SPEC {
247 type DataType = u32;
248}
249
250#[doc = "JTAG Boot Transmit Data Register"]
251pub type Jbtdr = crate::RegValueT<Jbtdr_SPEC>;
252
253impl Jbtdr {
254 #[doc = "Transmitted data register"]
255 #[inline(always)]
256 pub fn tdat(
257 self,
258 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Jbtdr_SPEC, crate::common::RW>
259 {
260 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Jbtdr_SPEC,crate::common::RW>::from_register(self,0)
261 }
262}
263impl ::core::default::Default for Jbtdr {
264 #[inline(always)]
265 fn default() -> Jbtdr {
266 <crate::RegValueT<Jbtdr_SPEC> as RegisterValue<_>>::new(0)
267 }
268}
269
270#[doc(hidden)]
271#[derive(Copy, Clone, Eq, PartialEq)]
272pub struct Jbstr_SPEC;
273impl crate::sealed::RegSpec for Jbstr_SPEC {
274 type DataType = u32;
275}
276
277#[doc = "JTAG Boot Status Register"]
278pub type Jbstr = crate::RegValueT<Jbstr_SPEC>;
279
280impl Jbstr {
281 #[doc = "Receive buffer full"]
282 #[inline(always)]
283 pub fn rdf(
284 self,
285 ) -> crate::common::RegisterField<
286 0,
287 0x1,
288 1,
289 0,
290 jbstr::Rdf,
291 jbstr::Rdf,
292 Jbstr_SPEC,
293 crate::common::RW,
294 > {
295 crate::common::RegisterField::<
296 0,
297 0x1,
298 1,
299 0,
300 jbstr::Rdf,
301 jbstr::Rdf,
302 Jbstr_SPEC,
303 crate::common::RW,
304 >::from_register(self, 0)
305 }
306
307 #[doc = "Transmit data empty"]
308 #[inline(always)]
309 pub fn tde(
310 self,
311 ) -> crate::common::RegisterField<
312 1,
313 0x1,
314 1,
315 0,
316 jbstr::Tde,
317 jbstr::Tde,
318 Jbstr_SPEC,
319 crate::common::RW,
320 > {
321 crate::common::RegisterField::<
322 1,
323 0x1,
324 1,
325 0,
326 jbstr::Tde,
327 jbstr::Tde,
328 Jbstr_SPEC,
329 crate::common::RW,
330 >::from_register(self, 0)
331 }
332}
333impl ::core::default::Default for Jbstr {
334 #[inline(always)]
335 fn default() -> Jbstr {
336 <crate::RegValueT<Jbstr_SPEC> as RegisterValue<_>>::new(2)
337 }
338}
339pub mod jbstr {
340
341 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
342 pub struct Rdf_SPEC;
343 pub type Rdf = crate::EnumBitfieldStruct<u8, Rdf_SPEC>;
344 impl Rdf {
345 #[doc = "No receiving data"]
346 pub const _0: Self = Self::new(0);
347
348 #[doc = "There is receiving data"]
349 pub const _1: Self = Self::new(1);
350 }
351 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
352 pub struct Tde_SPEC;
353 pub type Tde = crate::EnumBitfieldStruct<u8, Tde_SPEC>;
354 impl Tde {
355 #[doc = "There is data transmission"]
356 pub const _0: Self = Self::new(0);
357
358 #[doc = "No data transmission"]
359 pub const _1: Self = Self::new(1);
360 }
361}
362#[doc(hidden)]
363#[derive(Copy, Clone, Eq, PartialEq)]
364pub struct Jbicr_SPEC;
365impl crate::sealed::RegSpec for Jbicr_SPEC {
366 type DataType = u32;
367}
368
369#[doc = "JTAG Boot Interrupt Control Register"]
370pub type Jbicr = crate::RegValueT<Jbicr_SPEC>;
371
372impl Jbicr {
373 #[doc = "Receive buffer full interrupt enabled"]
374 #[inline(always)]
375 pub fn rdfie(
376 self,
377 ) -> crate::common::RegisterField<
378 0,
379 0x1,
380 1,
381 0,
382 jbicr::Rdfie,
383 jbicr::Rdfie,
384 Jbicr_SPEC,
385 crate::common::RW,
386 > {
387 crate::common::RegisterField::<
388 0,
389 0x1,
390 1,
391 0,
392 jbicr::Rdfie,
393 jbicr::Rdfie,
394 Jbicr_SPEC,
395 crate::common::RW,
396 >::from_register(self, 0)
397 }
398}
399impl ::core::default::Default for Jbicr {
400 #[inline(always)]
401 fn default() -> Jbicr {
402 <crate::RegValueT<Jbicr_SPEC> as RegisterValue<_>>::new(0)
403 }
404}
405pub mod jbicr {
406
407 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
408 pub struct Rdfie_SPEC;
409 pub type Rdfie = crate::EnumBitfieldStruct<u8, Rdfie_SPEC>;
410 impl Rdfie {
411 #[doc = "Interrupt request disabled by RDF = 1"]
412 pub const _0: Self = Self::new(0);
413
414 #[doc = "Enable interrupt request by RDF = 1"]
415 pub const _1: Self = Self::new(1);
416 }
417}