1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"System Control"]
28unsafe impl ::core::marker::Send for super::SyscNs {}
29unsafe impl ::core::marker::Sync for super::SyscNs {}
30impl super::SyscNs {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Standby Control Register"]
38 #[inline(always)]
39 pub const fn sbycr(&self) -> &'static crate::common::Reg<self::Sbycr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Sbycr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(12usize),
43 )
44 }
45 }
46
47 #[doc = "System Clock Division Control Register"]
48 #[inline(always)]
49 pub const fn sckdivcr(
50 &self,
51 ) -> &'static crate::common::Reg<self::Sckdivcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Sckdivcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(32usize),
55 )
56 }
57 }
58
59 #[doc = "System Clock Division Control Register 2"]
60 #[inline(always)]
61 pub const fn sckdivcr2(
62 &self,
63 ) -> &'static crate::common::Reg<self::Sckdivcr2_SPEC, crate::common::RW> {
64 unsafe {
65 crate::common::Reg::<self::Sckdivcr2_SPEC, crate::common::RW>::from_ptr(
66 self._svd2pac_as_ptr().add(36usize),
67 )
68 }
69 }
70
71 #[doc = "System Clock Source Control Register"]
72 #[inline(always)]
73 pub const fn sckscr(
74 &self,
75 ) -> &'static crate::common::Reg<self::Sckscr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Sckscr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(38usize),
79 )
80 }
81 }
82
83 #[doc = "PLL Clock Control Register"]
84 #[inline(always)]
85 pub const fn pllccr(
86 &self,
87 ) -> &'static crate::common::Reg<self::Pllccr_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Pllccr_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(40usize),
91 )
92 }
93 }
94
95 #[doc = "PLL Control Register"]
96 #[inline(always)]
97 pub const fn pllcr(&self) -> &'static crate::common::Reg<self::Pllcr_SPEC, crate::common::RW> {
98 unsafe {
99 crate::common::Reg::<self::Pllcr_SPEC, crate::common::RW>::from_ptr(
100 self._svd2pac_as_ptr().add(42usize),
101 )
102 }
103 }
104
105 #[doc = "External Bus Clock Control Register"]
106 #[inline(always)]
107 pub const fn bckcr(&self) -> &'static crate::common::Reg<self::Bckcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Bckcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(48usize),
111 )
112 }
113 }
114
115 #[doc = "Main Clock Oscillator Control Register"]
116 #[inline(always)]
117 pub const fn mosccr(
118 &self,
119 ) -> &'static crate::common::Reg<self::Mosccr_SPEC, crate::common::RW> {
120 unsafe {
121 crate::common::Reg::<self::Mosccr_SPEC, crate::common::RW>::from_ptr(
122 self._svd2pac_as_ptr().add(50usize),
123 )
124 }
125 }
126
127 #[doc = "High-Speed On-Chip Oscillator Control Register"]
128 #[inline(always)]
129 pub const fn hococr(
130 &self,
131 ) -> &'static crate::common::Reg<self::Hococr_SPEC, crate::common::RW> {
132 unsafe {
133 crate::common::Reg::<self::Hococr_SPEC, crate::common::RW>::from_ptr(
134 self._svd2pac_as_ptr().add(54usize),
135 )
136 }
137 }
138
139 #[doc = "High-Speed On-Chip Oscillator Control Register2"]
140 #[inline(always)]
141 pub const fn hococr2(
142 &self,
143 ) -> &'static crate::common::Reg<self::Hococr2_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Hococr2_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(55usize),
147 )
148 }
149 }
150
151 #[doc = "Middle-Speed On-Chip Oscillator Control Register"]
152 #[inline(always)]
153 pub const fn mococr(
154 &self,
155 ) -> &'static crate::common::Reg<self::Mococr_SPEC, crate::common::RW> {
156 unsafe {
157 crate::common::Reg::<self::Mococr_SPEC, crate::common::RW>::from_ptr(
158 self._svd2pac_as_ptr().add(56usize),
159 )
160 }
161 }
162
163 #[doc = "FLL Control Register1"]
164 #[inline(always)]
165 pub const fn fllcr1(
166 &self,
167 ) -> &'static crate::common::Reg<self::Fllcr1_SPEC, crate::common::RW> {
168 unsafe {
169 crate::common::Reg::<self::Fllcr1_SPEC, crate::common::RW>::from_ptr(
170 self._svd2pac_as_ptr().add(57usize),
171 )
172 }
173 }
174
175 #[doc = "FLL Control Register2"]
176 #[inline(always)]
177 pub const fn fllcr2(
178 &self,
179 ) -> &'static crate::common::Reg<self::Fllcr2_SPEC, crate::common::RW> {
180 unsafe {
181 crate::common::Reg::<self::Fllcr2_SPEC, crate::common::RW>::from_ptr(
182 self._svd2pac_as_ptr().add(58usize),
183 )
184 }
185 }
186
187 #[doc = "Oscillation Stabilization Flag Register"]
188 #[inline(always)]
189 pub const fn oscsf(&self) -> &'static crate::common::Reg<self::Oscsf_SPEC, crate::common::R> {
190 unsafe {
191 crate::common::Reg::<self::Oscsf_SPEC, crate::common::R>::from_ptr(
192 self._svd2pac_as_ptr().add(60usize),
193 )
194 }
195 }
196
197 #[doc = "Clock Out Control Register"]
198 #[inline(always)]
199 pub const fn ckocr(&self) -> &'static crate::common::Reg<self::Ckocr_SPEC, crate::common::RW> {
200 unsafe {
201 crate::common::Reg::<self::Ckocr_SPEC, crate::common::RW>::from_ptr(
202 self._svd2pac_as_ptr().add(62usize),
203 )
204 }
205 }
206
207 #[doc = "Trace Clock Control Register"]
208 #[inline(always)]
209 pub const fn trckcr(
210 &self,
211 ) -> &'static crate::common::Reg<self::Trckcr_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Trckcr_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(63usize),
215 )
216 }
217 }
218
219 #[doc = "Oscillation Stop Detection Control Register"]
220 #[inline(always)]
221 pub const fn ostdcr(
222 &self,
223 ) -> &'static crate::common::Reg<self::Ostdcr_SPEC, crate::common::RW> {
224 unsafe {
225 crate::common::Reg::<self::Ostdcr_SPEC, crate::common::RW>::from_ptr(
226 self._svd2pac_as_ptr().add(64usize),
227 )
228 }
229 }
230
231 #[doc = "Oscillation Stop Detection Status Register"]
232 #[inline(always)]
233 pub const fn ostdsr(
234 &self,
235 ) -> &'static crate::common::Reg<self::Ostdsr_SPEC, crate::common::RW> {
236 unsafe {
237 crate::common::Reg::<self::Ostdsr_SPEC, crate::common::RW>::from_ptr(
238 self._svd2pac_as_ptr().add(65usize),
239 )
240 }
241 }
242
243 #[doc = "Oscillator Monitor Register"]
244 #[inline(always)]
245 pub const fn oscmonr(
246 &self,
247 ) -> &'static crate::common::Reg<self::Oscmonr_SPEC, crate::common::RW> {
248 unsafe {
249 crate::common::Reg::<self::Oscmonr_SPEC, crate::common::RW>::from_ptr(
250 self._svd2pac_as_ptr().add(67usize),
251 )
252 }
253 }
254
255 #[doc = "PLL2 Clock Control Register"]
256 #[inline(always)]
257 pub const fn pll2ccr(
258 &self,
259 ) -> &'static crate::common::Reg<self::Pll2Ccr_SPEC, crate::common::RW> {
260 unsafe {
261 crate::common::Reg::<self::Pll2Ccr_SPEC, crate::common::RW>::from_ptr(
262 self._svd2pac_as_ptr().add(72usize),
263 )
264 }
265 }
266
267 #[doc = "PLL2 Control Register"]
268 #[inline(always)]
269 pub const fn pll2cr(
270 &self,
271 ) -> &'static crate::common::Reg<self::Pll2Cr_SPEC, crate::common::RW> {
272 unsafe {
273 crate::common::Reg::<self::Pll2Cr_SPEC, crate::common::RW>::from_ptr(
274 self._svd2pac_as_ptr().add(74usize),
275 )
276 }
277 }
278
279 #[doc = "PLL Clock Control Register 2"]
280 #[inline(always)]
281 pub const fn pllccr2(
282 &self,
283 ) -> &'static crate::common::Reg<self::Pllccr2_SPEC, crate::common::RW> {
284 unsafe {
285 crate::common::Reg::<self::Pllccr2_SPEC, crate::common::RW>::from_ptr(
286 self._svd2pac_as_ptr().add(76usize),
287 )
288 }
289 }
290
291 #[doc = "PLL2 Clock Control Register 2"]
292 #[inline(always)]
293 pub const fn pll2ccr2(
294 &self,
295 ) -> &'static crate::common::Reg<self::Pll2Ccr2_SPEC, crate::common::RW> {
296 unsafe {
297 crate::common::Reg::<self::Pll2Ccr2_SPEC, crate::common::RW>::from_ptr(
298 self._svd2pac_as_ptr().add(78usize),
299 )
300 }
301 }
302
303 #[doc = "External Bus Clock Output Control Register"]
304 #[inline(always)]
305 pub const fn ebckocr(
306 &self,
307 ) -> &'static crate::common::Reg<self::Ebckocr_SPEC, crate::common::RW> {
308 unsafe {
309 crate::common::Reg::<self::Ebckocr_SPEC, crate::common::RW>::from_ptr(
310 self._svd2pac_as_ptr().add(82usize),
311 )
312 }
313 }
314
315 #[doc = "SDRAM Clock Output Control Register"]
316 #[inline(always)]
317 pub const fn sdckocr(
318 &self,
319 ) -> &'static crate::common::Reg<self::Sdckocr_SPEC, crate::common::RW> {
320 unsafe {
321 crate::common::Reg::<self::Sdckocr_SPEC, crate::common::RW>::from_ptr(
322 self._svd2pac_as_ptr().add(83usize),
323 )
324 }
325 }
326
327 #[doc = "SCI clock Division control register"]
328 #[inline(always)]
329 pub const fn scickdivcr(
330 &self,
331 ) -> &'static crate::common::Reg<self::Scickdivcr_SPEC, crate::common::RW> {
332 unsafe {
333 crate::common::Reg::<self::Scickdivcr_SPEC, crate::common::RW>::from_ptr(
334 self._svd2pac_as_ptr().add(84usize),
335 )
336 }
337 }
338
339 #[doc = "SCI clock control register"]
340 #[inline(always)]
341 pub const fn scickcr(
342 &self,
343 ) -> &'static crate::common::Reg<self::Scickcr_SPEC, crate::common::RW> {
344 unsafe {
345 crate::common::Reg::<self::Scickcr_SPEC, crate::common::RW>::from_ptr(
346 self._svd2pac_as_ptr().add(85usize),
347 )
348 }
349 }
350
351 #[doc = "SPI clock Division control register"]
352 #[inline(always)]
353 pub const fn spickdivcr(
354 &self,
355 ) -> &'static crate::common::Reg<self::Spickdivcr_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Spickdivcr_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(86usize),
359 )
360 }
361 }
362
363 #[doc = "SPI clock control register"]
364 #[inline(always)]
365 pub const fn spickcr(
366 &self,
367 ) -> &'static crate::common::Reg<self::Spickcr_SPEC, crate::common::RW> {
368 unsafe {
369 crate::common::Reg::<self::Spickcr_SPEC, crate::common::RW>::from_ptr(
370 self._svd2pac_as_ptr().add(87usize),
371 )
372 }
373 }
374
375 #[doc = "LCD clock Division control register"]
376 #[inline(always)]
377 pub const fn lcdckdivcr(
378 &self,
379 ) -> &'static crate::common::Reg<self::Lcdckdivcr_SPEC, crate::common::RW> {
380 unsafe {
381 crate::common::Reg::<self::Lcdckdivcr_SPEC, crate::common::RW>::from_ptr(
382 self._svd2pac_as_ptr().add(94usize),
383 )
384 }
385 }
386
387 #[doc = "LCD clock control register"]
388 #[inline(always)]
389 pub const fn lcdckcr(
390 &self,
391 ) -> &'static crate::common::Reg<self::Lcdckcr_SPEC, crate::common::RW> {
392 unsafe {
393 crate::common::Reg::<self::Lcdckcr_SPEC, crate::common::RW>::from_ptr(
394 self._svd2pac_as_ptr().add(95usize),
395 )
396 }
397 }
398
399 #[doc = "MOCO User Trimming Control Register"]
400 #[inline(always)]
401 pub const fn mocoutcr(
402 &self,
403 ) -> &'static crate::common::Reg<self::Mocoutcr_SPEC, crate::common::RW> {
404 unsafe {
405 crate::common::Reg::<self::Mocoutcr_SPEC, crate::common::RW>::from_ptr(
406 self._svd2pac_as_ptr().add(97usize),
407 )
408 }
409 }
410
411 #[doc = "HOCO User Trimming Control Register"]
412 #[inline(always)]
413 pub const fn hocoutcr(
414 &self,
415 ) -> &'static crate::common::Reg<self::Hocoutcr_SPEC, crate::common::RW> {
416 unsafe {
417 crate::common::Reg::<self::Hocoutcr_SPEC, crate::common::RW>::from_ptr(
418 self._svd2pac_as_ptr().add(98usize),
419 )
420 }
421 }
422
423 #[doc = "USB Clock Division Control Register"]
424 #[inline(always)]
425 pub const fn usbckdivcr(
426 &self,
427 ) -> &'static crate::common::Reg<self::Usbckdivcr_SPEC, crate::common::RW> {
428 unsafe {
429 crate::common::Reg::<self::Usbckdivcr_SPEC, crate::common::RW>::from_ptr(
430 self._svd2pac_as_ptr().add(108usize),
431 )
432 }
433 }
434
435 #[doc = "Octal-SPI Clock Division Control Register"]
436 #[inline(always)]
437 pub const fn octackdivcr(
438 &self,
439 ) -> &'static crate::common::Reg<self::Octackdivcr_SPEC, crate::common::RW> {
440 unsafe {
441 crate::common::Reg::<self::Octackdivcr_SPEC, crate::common::RW>::from_ptr(
442 self._svd2pac_as_ptr().add(109usize),
443 )
444 }
445 }
446
447 #[doc = "CANFD Core Clock Division Control Register"]
448 #[inline(always)]
449 pub const fn canfdckdivcr(
450 &self,
451 ) -> &'static crate::common::Reg<self::Canfdckdivcr_SPEC, crate::common::RW> {
452 unsafe {
453 crate::common::Reg::<self::Canfdckdivcr_SPEC, crate::common::RW>::from_ptr(
454 self._svd2pac_as_ptr().add(110usize),
455 )
456 }
457 }
458
459 #[doc = "USB Clock Control Register"]
460 #[inline(always)]
461 pub const fn usbckcr(
462 &self,
463 ) -> &'static crate::common::Reg<self::Usbckcr_SPEC, crate::common::RW> {
464 unsafe {
465 crate::common::Reg::<self::Usbckcr_SPEC, crate::common::RW>::from_ptr(
466 self._svd2pac_as_ptr().add(116usize),
467 )
468 }
469 }
470
471 #[doc = "Octal-SPI Clock Control Register"]
472 #[inline(always)]
473 pub const fn octackcr(
474 &self,
475 ) -> &'static crate::common::Reg<self::Octackcr_SPEC, crate::common::RW> {
476 unsafe {
477 crate::common::Reg::<self::Octackcr_SPEC, crate::common::RW>::from_ptr(
478 self._svd2pac_as_ptr().add(117usize),
479 )
480 }
481 }
482
483 #[doc = "CANFD Core Clock Control Register"]
484 #[inline(always)]
485 pub const fn canfdckcr(
486 &self,
487 ) -> &'static crate::common::Reg<self::Canfdckcr_SPEC, crate::common::RW> {
488 unsafe {
489 crate::common::Reg::<self::Canfdckcr_SPEC, crate::common::RW>::from_ptr(
490 self._svd2pac_as_ptr().add(118usize),
491 )
492 }
493 }
494
495 #[doc = "Main Clock Oscillator Standby Control Register"]
496 #[inline(always)]
497 pub const fn moscscr(
498 &self,
499 ) -> &'static crate::common::Reg<self::Moscscr_SPEC, crate::common::RW> {
500 unsafe {
501 crate::common::Reg::<self::Moscscr_SPEC, crate::common::RW>::from_ptr(
502 self._svd2pac_as_ptr().add(124usize),
503 )
504 }
505 }
506
507 #[doc = "High-Speed On-Chip Oscillator Standby Control Register"]
508 #[inline(always)]
509 pub const fn hocoscr(
510 &self,
511 ) -> &'static crate::common::Reg<self::Hocoscr_SPEC, crate::common::RW> {
512 unsafe {
513 crate::common::Reg::<self::Hocoscr_SPEC, crate::common::RW>::from_ptr(
514 self._svd2pac_as_ptr().add(125usize),
515 )
516 }
517 }
518
519 #[doc = "Operating Power Control Register"]
520 #[inline(always)]
521 pub const fn opccr(&self) -> &'static crate::common::Reg<self::Opccr_SPEC, crate::common::RW> {
522 unsafe {
523 crate::common::Reg::<self::Opccr_SPEC, crate::common::RW>::from_ptr(
524 self._svd2pac_as_ptr().add(160usize),
525 )
526 }
527 }
528
529 #[doc = "Main Clock Oscillator Wait Control Register"]
530 #[inline(always)]
531 pub const fn moscwtcr(
532 &self,
533 ) -> &'static crate::common::Reg<self::Moscwtcr_SPEC, crate::common::RW> {
534 unsafe {
535 crate::common::Reg::<self::Moscwtcr_SPEC, crate::common::RW>::from_ptr(
536 self._svd2pac_as_ptr().add(162usize),
537 )
538 }
539 }
540
541 #[doc = "Reset Status Register 1"]
542 #[inline(always)]
543 pub const fn rstsr1(
544 &self,
545 ) -> &'static crate::common::Reg<self::Rstsr1_SPEC, crate::common::RW> {
546 unsafe {
547 crate::common::Reg::<self::Rstsr1_SPEC, crate::common::RW>::from_ptr(
548 self._svd2pac_as_ptr().add(192usize),
549 )
550 }
551 }
552
553 #[doc = "System Register Access Control Register"]
554 #[inline(always)]
555 pub const fn syraccr(
556 &self,
557 ) -> &'static crate::common::Reg<self::Syraccr_SPEC, crate::common::R> {
558 unsafe {
559 crate::common::Reg::<self::Syraccr_SPEC, crate::common::R>::from_ptr(
560 self._svd2pac_as_ptr().add(204usize),
561 )
562 }
563 }
564
565 #[doc = "Voltage Monitor %s Circuit Control Register 1"]
566 #[inline(always)]
567 pub const fn pvdcr1(
568 &self,
569 ) -> &'static crate::common::ClusterRegisterArray<
570 crate::common::Reg<self::Pvdcr1_SPEC, crate::common::RW>,
571 2,
572 0x2,
573 > {
574 unsafe {
575 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xe0usize))
576 }
577 }
578 #[inline(always)]
579 pub const fn pvd1cr1(
580 &self,
581 ) -> &'static crate::common::Reg<self::Pvdcr1_SPEC, crate::common::RW> {
582 unsafe {
583 crate::common::Reg::<self::Pvdcr1_SPEC, crate::common::RW>::from_ptr(
584 self._svd2pac_as_ptr().add(0xe0usize),
585 )
586 }
587 }
588 #[inline(always)]
589 pub const fn pvd2cr1(
590 &self,
591 ) -> &'static crate::common::Reg<self::Pvdcr1_SPEC, crate::common::RW> {
592 unsafe {
593 crate::common::Reg::<self::Pvdcr1_SPEC, crate::common::RW>::from_ptr(
594 self._svd2pac_as_ptr().add(0xe2usize),
595 )
596 }
597 }
598
599 #[doc = "Voltage Monitor %s Circuit Status Register"]
600 #[inline(always)]
601 pub const fn pvdsr(
602 &self,
603 ) -> &'static crate::common::ClusterRegisterArray<
604 crate::common::Reg<self::Pvdsr_SPEC, crate::common::RW>,
605 2,
606 0x2,
607 > {
608 unsafe {
609 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xe1usize))
610 }
611 }
612 #[inline(always)]
613 pub const fn pvd1sr(&self) -> &'static crate::common::Reg<self::Pvdsr_SPEC, crate::common::RW> {
614 unsafe {
615 crate::common::Reg::<self::Pvdsr_SPEC, crate::common::RW>::from_ptr(
616 self._svd2pac_as_ptr().add(0xe1usize),
617 )
618 }
619 }
620 #[inline(always)]
621 pub const fn pvd2sr(&self) -> &'static crate::common::Reg<self::Pvdsr_SPEC, crate::common::RW> {
622 unsafe {
623 crate::common::Reg::<self::Pvdsr_SPEC, crate::common::RW>::from_ptr(
624 self._svd2pac_as_ptr().add(0xe3usize),
625 )
626 }
627 }
628
629 #[doc = "Graphics Power Domain Control Register"]
630 #[inline(always)]
631 pub const fn pdctrgd(
632 &self,
633 ) -> &'static crate::common::Reg<self::Pdctrgd_SPEC, crate::common::RW> {
634 unsafe {
635 crate::common::Reg::<self::Pdctrgd_SPEC, crate::common::RW>::from_ptr(
636 self._svd2pac_as_ptr().add(272usize),
637 )
638 }
639 }
640
641 #[doc = "SRAM Power Domain Standby Control Register 0"]
642 #[inline(always)]
643 pub const fn pdramscr0(
644 &self,
645 ) -> &'static crate::common::Reg<self::Pdramscr0_SPEC, crate::common::RW> {
646 unsafe {
647 crate::common::Reg::<self::Pdramscr0_SPEC, crate::common::RW>::from_ptr(
648 self._svd2pac_as_ptr().add(320usize),
649 )
650 }
651 }
652
653 #[doc = "SRAM Power Domain Standby Control Register 1"]
654 #[inline(always)]
655 pub const fn pdramscr1(
656 &self,
657 ) -> &'static crate::common::Reg<self::Pdramscr1_SPEC, crate::common::RW> {
658 unsafe {
659 crate::common::Reg::<self::Pdramscr1_SPEC, crate::common::RW>::from_ptr(
660 self._svd2pac_as_ptr().add(322usize),
661 )
662 }
663 }
664
665 #[doc = "VBATT Backup Register Privilege Attribute Boundary Address Register for Non-secure Region"]
666 #[inline(always)]
667 pub const fn vbrpabarns(
668 &self,
669 ) -> &'static crate::common::Reg<self::Vbrpabarns_SPEC, crate::common::RW> {
670 unsafe {
671 crate::common::Reg::<self::Vbrpabarns_SPEC, crate::common::RW>::from_ptr(
672 self._svd2pac_as_ptr().add(952usize),
673 )
674 }
675 }
676
677 #[doc = "Clock Generation Function Security Attribute Register"]
678 #[inline(always)]
679 pub const fn cgfsar(
680 &self,
681 ) -> &'static crate::common::Reg<self::Cgfsar_SPEC, crate::common::RW> {
682 unsafe {
683 crate::common::Reg::<self::Cgfsar_SPEC, crate::common::RW>::from_ptr(
684 self._svd2pac_as_ptr().add(960usize),
685 )
686 }
687 }
688
689 #[doc = "Reset Security Attribution Register"]
690 #[inline(always)]
691 pub const fn rstsar(
692 &self,
693 ) -> &'static crate::common::Reg<self::Rstsar_SPEC, crate::common::RW> {
694 unsafe {
695 crate::common::Reg::<self::Rstsar_SPEC, crate::common::RW>::from_ptr(
696 self._svd2pac_as_ptr().add(964usize),
697 )
698 }
699 }
700
701 #[doc = "Low Power Mode Security Attribution Register"]
702 #[inline(always)]
703 pub const fn lpmsar(
704 &self,
705 ) -> &'static crate::common::Reg<self::Lpmsar_SPEC, crate::common::RW> {
706 unsafe {
707 crate::common::Reg::<self::Lpmsar_SPEC, crate::common::RW>::from_ptr(
708 self._svd2pac_as_ptr().add(968usize),
709 )
710 }
711 }
712
713 #[doc = "Programable Voltage Detection Security Attribution Register"]
714 #[inline(always)]
715 pub const fn pvdsar(
716 &self,
717 ) -> &'static crate::common::Reg<self::Pvdsar_SPEC, crate::common::RW> {
718 unsafe {
719 crate::common::Reg::<self::Pvdsar_SPEC, crate::common::RW>::from_ptr(
720 self._svd2pac_as_ptr().add(972usize),
721 )
722 }
723 }
724
725 #[doc = "Battery Backup Function Security Attribute Register"]
726 #[inline(always)]
727 pub const fn bbfsar(
728 &self,
729 ) -> &'static crate::common::Reg<self::Bbfsar_SPEC, crate::common::RW> {
730 unsafe {
731 crate::common::Reg::<self::Bbfsar_SPEC, crate::common::RW>::from_ptr(
732 self._svd2pac_as_ptr().add(976usize),
733 )
734 }
735 }
736
737 #[doc = "Power Gating Control Security Attribution Register"]
738 #[inline(always)]
739 pub const fn pgcsar(
740 &self,
741 ) -> &'static crate::common::Reg<self::Pgcsar_SPEC, crate::common::RW> {
742 unsafe {
743 crate::common::Reg::<self::Pgcsar_SPEC, crate::common::RW>::from_ptr(
744 self._svd2pac_as_ptr().add(984usize),
745 )
746 }
747 }
748
749 #[doc = "Deep Software Standby Interrupt Factor Security Attribution Register"]
750 #[inline(always)]
751 pub const fn dpfsar(
752 &self,
753 ) -> &'static crate::common::Reg<self::Dpfsar_SPEC, crate::common::RW> {
754 unsafe {
755 crate::common::Reg::<self::Dpfsar_SPEC, crate::common::RW>::from_ptr(
756 self._svd2pac_as_ptr().add(992usize),
757 )
758 }
759 }
760
761 #[doc = "RAM Standby Control Security Attribution Register"]
762 #[inline(always)]
763 pub const fn rscsar(
764 &self,
765 ) -> &'static crate::common::Reg<self::Rscsar_SPEC, crate::common::RW> {
766 unsafe {
767 crate::common::Reg::<self::Rscsar_SPEC, crate::common::RW>::from_ptr(
768 self._svd2pac_as_ptr().add(996usize),
769 )
770 }
771 }
772
773 #[doc = "Protect Register for Non-secure (PRCR_NS)"]
774 #[inline(always)]
775 pub const fn prcr_ns(
776 &self,
777 ) -> &'static crate::common::Reg<self::PrcrNs_SPEC, crate::common::RW> {
778 unsafe {
779 crate::common::Reg::<self::PrcrNs_SPEC, crate::common::RW>::from_ptr(
780 self._svd2pac_as_ptr().add(1022usize),
781 )
782 }
783 }
784
785 #[doc = "Low-Speed On-Chip Oscillator Control Register"]
786 #[inline(always)]
787 pub const fn lococr(
788 &self,
789 ) -> &'static crate::common::Reg<self::Lococr_SPEC, crate::common::RW> {
790 unsafe {
791 crate::common::Reg::<self::Lococr_SPEC, crate::common::RW>::from_ptr(
792 self._svd2pac_as_ptr().add(1024usize),
793 )
794 }
795 }
796
797 #[doc = "LOCO User Trimming Control Register"]
798 #[inline(always)]
799 pub const fn locoutcr(
800 &self,
801 ) -> &'static crate::common::Reg<self::Locoutcr_SPEC, crate::common::RW> {
802 unsafe {
803 crate::common::Reg::<self::Locoutcr_SPEC, crate::common::RW>::from_ptr(
804 self._svd2pac_as_ptr().add(1026usize),
805 )
806 }
807 }
808
809 #[doc = "Deep Software Standby Control Register"]
810 #[inline(always)]
811 pub const fn dpsbycr(
812 &self,
813 ) -> &'static crate::common::Reg<self::Dpsbycr_SPEC, crate::common::RW> {
814 unsafe {
815 crate::common::Reg::<self::Dpsbycr_SPEC, crate::common::RW>::from_ptr(
816 self._svd2pac_as_ptr().add(2560usize),
817 )
818 }
819 }
820
821 #[doc = "Deep Software Standby Wait Control Register"]
822 #[inline(always)]
823 pub const fn dpswcr(
824 &self,
825 ) -> &'static crate::common::Reg<self::Dpswcr_SPEC, crate::common::RW> {
826 unsafe {
827 crate::common::Reg::<self::Dpswcr_SPEC, crate::common::RW>::from_ptr(
828 self._svd2pac_as_ptr().add(2564usize),
829 )
830 }
831 }
832
833 #[doc = "Deep Software Standby Interrupt Enable Register 0"]
834 #[inline(always)]
835 pub const fn dpsier0(
836 &self,
837 ) -> &'static crate::common::Reg<self::Dpsier0_SPEC, crate::common::RW> {
838 unsafe {
839 crate::common::Reg::<self::Dpsier0_SPEC, crate::common::RW>::from_ptr(
840 self._svd2pac_as_ptr().add(2568usize),
841 )
842 }
843 }
844
845 #[doc = "Deep Software Standby Interrupt Enable Register 1"]
846 #[inline(always)]
847 pub const fn dpsier1(
848 &self,
849 ) -> &'static crate::common::Reg<self::Dpsier1_SPEC, crate::common::RW> {
850 unsafe {
851 crate::common::Reg::<self::Dpsier1_SPEC, crate::common::RW>::from_ptr(
852 self._svd2pac_as_ptr().add(2572usize),
853 )
854 }
855 }
856
857 #[doc = "Deep Software Standby Interrupt Enable Register 2"]
858 #[inline(always)]
859 pub const fn dpsier2(
860 &self,
861 ) -> &'static crate::common::Reg<self::Dpsier2_SPEC, crate::common::RW> {
862 unsafe {
863 crate::common::Reg::<self::Dpsier2_SPEC, crate::common::RW>::from_ptr(
864 self._svd2pac_as_ptr().add(2576usize),
865 )
866 }
867 }
868
869 #[doc = "Deep Software Standby Interrupt Enable Register 3"]
870 #[inline(always)]
871 pub const fn dpsier3(
872 &self,
873 ) -> &'static crate::common::Reg<self::Dpsier3_SPEC, crate::common::RW> {
874 unsafe {
875 crate::common::Reg::<self::Dpsier3_SPEC, crate::common::RW>::from_ptr(
876 self._svd2pac_as_ptr().add(2580usize),
877 )
878 }
879 }
880
881 #[doc = "Deep Software Standby Interrupt Flag Register 0"]
882 #[inline(always)]
883 pub const fn dpsifr0(
884 &self,
885 ) -> &'static crate::common::Reg<self::Dpsifr0_SPEC, crate::common::RW> {
886 unsafe {
887 crate::common::Reg::<self::Dpsifr0_SPEC, crate::common::RW>::from_ptr(
888 self._svd2pac_as_ptr().add(2584usize),
889 )
890 }
891 }
892
893 #[doc = "Deep Software Standby Interrupt Flag Register 1"]
894 #[inline(always)]
895 pub const fn dpsifr1(
896 &self,
897 ) -> &'static crate::common::Reg<self::Dpsifr1_SPEC, crate::common::RW> {
898 unsafe {
899 crate::common::Reg::<self::Dpsifr1_SPEC, crate::common::RW>::from_ptr(
900 self._svd2pac_as_ptr().add(2588usize),
901 )
902 }
903 }
904
905 #[doc = "Deep Software Standby Interrupt Flag Register 2"]
906 #[inline(always)]
907 pub const fn dpsifr2(
908 &self,
909 ) -> &'static crate::common::Reg<self::Dpsifr2_SPEC, crate::common::RW> {
910 unsafe {
911 crate::common::Reg::<self::Dpsifr2_SPEC, crate::common::RW>::from_ptr(
912 self._svd2pac_as_ptr().add(2592usize),
913 )
914 }
915 }
916
917 #[doc = "Deep Software Standby Interrupt Flag Register 3"]
918 #[inline(always)]
919 pub const fn dpsifr3(
920 &self,
921 ) -> &'static crate::common::Reg<self::Dpsifr3_SPEC, crate::common::RW> {
922 unsafe {
923 crate::common::Reg::<self::Dpsifr3_SPEC, crate::common::RW>::from_ptr(
924 self._svd2pac_as_ptr().add(2596usize),
925 )
926 }
927 }
928
929 #[doc = "Deep Software Standby Interrupt Edge Register 0"]
930 #[inline(always)]
931 pub const fn dpsiegr0(
932 &self,
933 ) -> &'static crate::common::Reg<self::Dpsiegr0_SPEC, crate::common::RW> {
934 unsafe {
935 crate::common::Reg::<self::Dpsiegr0_SPEC, crate::common::RW>::from_ptr(
936 self._svd2pac_as_ptr().add(2600usize),
937 )
938 }
939 }
940
941 #[doc = "Deep Software Standby Interrupt Edge Register 1"]
942 #[inline(always)]
943 pub const fn dpsiegr1(
944 &self,
945 ) -> &'static crate::common::Reg<self::Dpsiegr1_SPEC, crate::common::RW> {
946 unsafe {
947 crate::common::Reg::<self::Dpsiegr1_SPEC, crate::common::RW>::from_ptr(
948 self._svd2pac_as_ptr().add(2604usize),
949 )
950 }
951 }
952
953 #[doc = "Deep Software Standby Interrupt Edge Register 2"]
954 #[inline(always)]
955 pub const fn dpsiegr2(
956 &self,
957 ) -> &'static crate::common::Reg<self::Dpsiegr2_SPEC, crate::common::RW> {
958 unsafe {
959 crate::common::Reg::<self::Dpsiegr2_SPEC, crate::common::RW>::from_ptr(
960 self._svd2pac_as_ptr().add(2608usize),
961 )
962 }
963 }
964
965 #[doc = "System Control OCD Control Register"]
966 #[inline(always)]
967 pub const fn syocdcr(
968 &self,
969 ) -> &'static crate::common::Reg<self::Syocdcr_SPEC, crate::common::RW> {
970 unsafe {
971 crate::common::Reg::<self::Syocdcr_SPEC, crate::common::RW>::from_ptr(
972 self._svd2pac_as_ptr().add(2616usize),
973 )
974 }
975 }
976
977 #[doc = "Reset Status Register 0"]
978 #[inline(always)]
979 pub const fn rstsr0(
980 &self,
981 ) -> &'static crate::common::Reg<self::Rstsr0_SPEC, crate::common::RW> {
982 unsafe {
983 crate::common::Reg::<self::Rstsr0_SPEC, crate::common::RW>::from_ptr(
984 self._svd2pac_as_ptr().add(2624usize),
985 )
986 }
987 }
988
989 #[doc = "Reset Status Register 2"]
990 #[inline(always)]
991 pub const fn rstsr2(
992 &self,
993 ) -> &'static crate::common::Reg<self::Rstsr2_SPEC, crate::common::RW> {
994 unsafe {
995 crate::common::Reg::<self::Rstsr2_SPEC, crate::common::RW>::from_ptr(
996 self._svd2pac_as_ptr().add(2628usize),
997 )
998 }
999 }
1000
1001 #[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
1002 #[inline(always)]
1003 pub const fn momcr(&self) -> &'static crate::common::Reg<self::Momcr_SPEC, crate::common::RW> {
1004 unsafe {
1005 crate::common::Reg::<self::Momcr_SPEC, crate::common::RW>::from_ptr(
1006 self._svd2pac_as_ptr().add(2640usize),
1007 )
1008 }
1009 }
1010
1011 #[doc = "Flash P/E Protect Register"]
1012 #[inline(always)]
1013 pub const fn fwepror(
1014 &self,
1015 ) -> &'static crate::common::Reg<self::Fwepror_SPEC, crate::common::RW> {
1016 unsafe {
1017 crate::common::Reg::<self::Fwepror_SPEC, crate::common::RW>::from_ptr(
1018 self._svd2pac_as_ptr().add(2644usize),
1019 )
1020 }
1021 }
1022
1023 #[doc = "Voltage Monitor %s Comparator Control Register"]
1024 #[inline(always)]
1025 pub const fn pvdcmpcr(
1026 &self,
1027 ) -> &'static crate::common::ClusterRegisterArray<
1028 crate::common::Reg<self::Pvdcmpcr_SPEC, crate::common::RW>,
1029 2,
1030 0x4,
1031 > {
1032 unsafe {
1033 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xa58usize))
1034 }
1035 }
1036 #[inline(always)]
1037 pub const fn pvd1cmpcr(
1038 &self,
1039 ) -> &'static crate::common::Reg<self::Pvdcmpcr_SPEC, crate::common::RW> {
1040 unsafe {
1041 crate::common::Reg::<self::Pvdcmpcr_SPEC, crate::common::RW>::from_ptr(
1042 self._svd2pac_as_ptr().add(0xa58usize),
1043 )
1044 }
1045 }
1046 #[inline(always)]
1047 pub const fn pvd2cmpcr(
1048 &self,
1049 ) -> &'static crate::common::Reg<self::Pvdcmpcr_SPEC, crate::common::RW> {
1050 unsafe {
1051 crate::common::Reg::<self::Pvdcmpcr_SPEC, crate::common::RW>::from_ptr(
1052 self._svd2pac_as_ptr().add(0xa5cusize),
1053 )
1054 }
1055 }
1056
1057 #[doc = "Voltage Monitor %s Circuit Control Register 0"]
1058 #[inline(always)]
1059 pub const fn pvdcr0(
1060 &self,
1061 ) -> &'static crate::common::ClusterRegisterArray<
1062 crate::common::Reg<self::Pvdcr0_SPEC, crate::common::RW>,
1063 2,
1064 0x4,
1065 > {
1066 unsafe {
1067 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xa70usize))
1068 }
1069 }
1070 #[inline(always)]
1071 pub const fn pvd1cr0(
1072 &self,
1073 ) -> &'static crate::common::Reg<self::Pvdcr0_SPEC, crate::common::RW> {
1074 unsafe {
1075 crate::common::Reg::<self::Pvdcr0_SPEC, crate::common::RW>::from_ptr(
1076 self._svd2pac_as_ptr().add(0xa70usize),
1077 )
1078 }
1079 }
1080 #[inline(always)]
1081 pub const fn pvd2cr0(
1082 &self,
1083 ) -> &'static crate::common::Reg<self::Pvdcr0_SPEC, crate::common::RW> {
1084 unsafe {
1085 crate::common::Reg::<self::Pvdcr0_SPEC, crate::common::RW>::from_ptr(
1086 self._svd2pac_as_ptr().add(0xa74usize),
1087 )
1088 }
1089 }
1090
1091 #[doc = "Battery Backup Voltage Monitor Function Select Register"]
1092 #[inline(always)]
1093 pub const fn vbattmnselr(
1094 &self,
1095 ) -> &'static crate::common::Reg<self::Vbattmnselr_SPEC, crate::common::RW> {
1096 unsafe {
1097 crate::common::Reg::<self::Vbattmnselr_SPEC, crate::common::RW>::from_ptr(
1098 self._svd2pac_as_ptr().add(2692usize),
1099 )
1100 }
1101 }
1102
1103 #[doc = "VBATT Battery Power Supply Control Register 1"]
1104 #[inline(always)]
1105 pub const fn vbtbpcr1(
1106 &self,
1107 ) -> &'static crate::common::Reg<self::Vbtbpcr1_SPEC, crate::common::RW> {
1108 unsafe {
1109 crate::common::Reg::<self::Vbtbpcr1_SPEC, crate::common::RW>::from_ptr(
1110 self._svd2pac_as_ptr().add(2696usize),
1111 )
1112 }
1113 }
1114
1115 #[doc = "Low Power State Control Register"]
1116 #[inline(always)]
1117 pub const fn lpscr(&self) -> &'static crate::common::Reg<self::Lpscr_SPEC, crate::common::RW> {
1118 unsafe {
1119 crate::common::Reg::<self::Lpscr_SPEC, crate::common::RW>::from_ptr(
1120 self._svd2pac_as_ptr().add(2704usize),
1121 )
1122 }
1123 }
1124
1125 #[doc = "Software Standby Control Register 1"]
1126 #[inline(always)]
1127 pub const fn sscr1(&self) -> &'static crate::common::Reg<self::Sscr1_SPEC, crate::common::RW> {
1128 unsafe {
1129 crate::common::Reg::<self::Sscr1_SPEC, crate::common::RW>::from_ptr(
1130 self._svd2pac_as_ptr().add(2712usize),
1131 )
1132 }
1133 }
1134
1135 #[doc = "Low Voltage Operation Control register"]
1136 #[inline(always)]
1137 pub const fn lvocr(&self) -> &'static crate::common::Reg<self::Lvocr_SPEC, crate::common::RW> {
1138 unsafe {
1139 crate::common::Reg::<self::Lvocr_SPEC, crate::common::RW>::from_ptr(
1140 self._svd2pac_as_ptr().add(2736usize),
1141 )
1142 }
1143 }
1144
1145 #[doc = "PLL1-LDO Control Register"]
1146 #[inline(always)]
1147 pub const fn pll1ldocr(
1148 &self,
1149 ) -> &'static crate::common::Reg<self::Pll1Ldocr_SPEC, crate::common::RW> {
1150 unsafe {
1151 crate::common::Reg::<self::Pll1Ldocr_SPEC, crate::common::RW>::from_ptr(
1152 self._svd2pac_as_ptr().add(2820usize),
1153 )
1154 }
1155 }
1156
1157 #[doc = "PLL2-LDO Control Register"]
1158 #[inline(always)]
1159 pub const fn pll2ldocr(
1160 &self,
1161 ) -> &'static crate::common::Reg<self::Pll2Ldocr_SPEC, crate::common::RW> {
1162 unsafe {
1163 crate::common::Reg::<self::Pll2Ldocr_SPEC, crate::common::RW>::from_ptr(
1164 self._svd2pac_as_ptr().add(2824usize),
1165 )
1166 }
1167 }
1168
1169 #[doc = "HOCO-LDO Control Register"]
1170 #[inline(always)]
1171 pub const fn hocoldocr(
1172 &self,
1173 ) -> &'static crate::common::Reg<self::Hocoldocr_SPEC, crate::common::RW> {
1174 unsafe {
1175 crate::common::Reg::<self::Hocoldocr_SPEC, crate::common::RW>::from_ptr(
1176 self._svd2pac_as_ptr().add(2828usize),
1177 )
1178 }
1179 }
1180
1181 #[doc = "Voltage Monitor %s Function Control Register"]
1182 #[inline(always)]
1183 pub const fn pvdfcr(
1184 &self,
1185 ) -> &'static crate::common::ClusterRegisterArray<
1186 crate::common::Reg<self::Pvdfcr_SPEC, crate::common::RW>,
1187 2,
1188 0x4,
1189 > {
1190 unsafe {
1191 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb20usize))
1192 }
1193 }
1194 #[inline(always)]
1195 pub const fn pvd1fcr(
1196 &self,
1197 ) -> &'static crate::common::Reg<self::Pvdfcr_SPEC, crate::common::RW> {
1198 unsafe {
1199 crate::common::Reg::<self::Pvdfcr_SPEC, crate::common::RW>::from_ptr(
1200 self._svd2pac_as_ptr().add(0xb20usize),
1201 )
1202 }
1203 }
1204 #[inline(always)]
1205 pub const fn pvd2fcr(
1206 &self,
1207 ) -> &'static crate::common::Reg<self::Pvdfcr_SPEC, crate::common::RW> {
1208 unsafe {
1209 crate::common::Reg::<self::Pvdfcr_SPEC, crate::common::RW>::from_ptr(
1210 self._svd2pac_as_ptr().add(0xb24usize),
1211 )
1212 }
1213 }
1214
1215 #[doc = "Sub-Clock Oscillator Control Register"]
1216 #[inline(always)]
1217 pub const fn sosccr(
1218 &self,
1219 ) -> &'static crate::common::Reg<self::Sosccr_SPEC, crate::common::RW> {
1220 unsafe {
1221 crate::common::Reg::<self::Sosccr_SPEC, crate::common::RW>::from_ptr(
1222 self._svd2pac_as_ptr().add(3072usize),
1223 )
1224 }
1225 }
1226
1227 #[doc = "Sub-Clock Oscillator Mode Control Register"]
1228 #[inline(always)]
1229 pub const fn somcr(&self) -> &'static crate::common::Reg<self::Somcr_SPEC, crate::common::RW> {
1230 unsafe {
1231 crate::common::Reg::<self::Somcr_SPEC, crate::common::RW>::from_ptr(
1232 self._svd2pac_as_ptr().add(3073usize),
1233 )
1234 }
1235 }
1236
1237 #[doc = "VBATT Backup Enable Register"]
1238 #[inline(always)]
1239 pub const fn vbtber(
1240 &self,
1241 ) -> &'static crate::common::Reg<self::Vbtber_SPEC, crate::common::RW> {
1242 unsafe {
1243 crate::common::Reg::<self::Vbtber_SPEC, crate::common::RW>::from_ptr(
1244 self._svd2pac_as_ptr().add(3136usize),
1245 )
1246 }
1247 }
1248
1249 #[doc = "VBATT Battery Power Supply Control Register 2"]
1250 #[inline(always)]
1251 pub const fn vbtbpcr2(
1252 &self,
1253 ) -> &'static crate::common::Reg<self::Vbtbpcr2_SPEC, crate::common::RW> {
1254 unsafe {
1255 crate::common::Reg::<self::Vbtbpcr2_SPEC, crate::common::RW>::from_ptr(
1256 self._svd2pac_as_ptr().add(3141usize),
1257 )
1258 }
1259 }
1260
1261 #[doc = "VBATT Battery Power Supply Status Register"]
1262 #[inline(always)]
1263 pub const fn vbtbpsr(
1264 &self,
1265 ) -> &'static crate::common::Reg<self::Vbtbpsr_SPEC, crate::common::RW> {
1266 unsafe {
1267 crate::common::Reg::<self::Vbtbpsr_SPEC, crate::common::RW>::from_ptr(
1268 self._svd2pac_as_ptr().add(3142usize),
1269 )
1270 }
1271 }
1272
1273 #[doc = "VBATT Tamper detection Status Register"]
1274 #[inline(always)]
1275 pub const fn vbtadsr(
1276 &self,
1277 ) -> &'static crate::common::Reg<self::Vbtadsr_SPEC, crate::common::RW> {
1278 unsafe {
1279 crate::common::Reg::<self::Vbtadsr_SPEC, crate::common::RW>::from_ptr(
1280 self._svd2pac_as_ptr().add(3144usize),
1281 )
1282 }
1283 }
1284
1285 #[doc = "VBATT Tamper detection Control Register 1"]
1286 #[inline(always)]
1287 pub const fn vbtadcr1(
1288 &self,
1289 ) -> &'static crate::common::Reg<self::Vbtadcr1_SPEC, crate::common::RW> {
1290 unsafe {
1291 crate::common::Reg::<self::Vbtadcr1_SPEC, crate::common::RW>::from_ptr(
1292 self._svd2pac_as_ptr().add(3145usize),
1293 )
1294 }
1295 }
1296
1297 #[doc = "VBATT Tamper detection Control Register 2"]
1298 #[inline(always)]
1299 pub const fn vbtadcr2(
1300 &self,
1301 ) -> &'static crate::common::Reg<self::Vbtadcr2_SPEC, crate::common::RW> {
1302 unsafe {
1303 crate::common::Reg::<self::Vbtadcr2_SPEC, crate::common::RW>::from_ptr(
1304 self._svd2pac_as_ptr().add(3146usize),
1305 )
1306 }
1307 }
1308
1309 #[doc = "VBATT Input Control Register"]
1310 #[inline(always)]
1311 pub const fn vbtictlr(
1312 &self,
1313 ) -> &'static crate::common::Reg<self::Vbtictlr_SPEC, crate::common::RW> {
1314 unsafe {
1315 crate::common::Reg::<self::Vbtictlr_SPEC, crate::common::RW>::from_ptr(
1316 self._svd2pac_as_ptr().add(3148usize),
1317 )
1318 }
1319 }
1320
1321 #[doc = "VBATT Input Control Register 2"]
1322 #[inline(always)]
1323 pub const fn vbtictlr2(
1324 &self,
1325 ) -> &'static crate::common::Reg<self::Vbtictlr2_SPEC, crate::common::RW> {
1326 unsafe {
1327 crate::common::Reg::<self::Vbtictlr2_SPEC, crate::common::RW>::from_ptr(
1328 self._svd2pac_as_ptr().add(3149usize),
1329 )
1330 }
1331 }
1332
1333 #[doc = "VBATT Input Monitor Register"]
1334 #[inline(always)]
1335 pub const fn vbtimonr(
1336 &self,
1337 ) -> &'static crate::common::Reg<self::Vbtimonr_SPEC, crate::common::R> {
1338 unsafe {
1339 crate::common::Reg::<self::Vbtimonr_SPEC, crate::common::R>::from_ptr(
1340 self._svd2pac_as_ptr().add(3150usize),
1341 )
1342 }
1343 }
1344
1345 #[doc = "VBATT Backup Register"]
1346 #[inline(always)]
1347 pub const fn vbtbkr(
1348 &self,
1349 ) -> &'static crate::common::ClusterRegisterArray<
1350 crate::common::Reg<self::Vbtbkr_SPEC, crate::common::RW>,
1351 128,
1352 0x1,
1353 > {
1354 unsafe {
1355 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xd00usize))
1356 }
1357 }
1358}
1359#[doc(hidden)]
1360#[derive(Copy, Clone, Eq, PartialEq)]
1361pub struct Sbycr_SPEC;
1362impl crate::sealed::RegSpec for Sbycr_SPEC {
1363 type DataType = u8;
1364}
1365
1366#[doc = "Standby Control Register"]
1367pub type Sbycr = crate::RegValueT<Sbycr_SPEC>;
1368
1369impl Sbycr {
1370 #[doc = "Output Port Enable"]
1371 #[inline(always)]
1372 pub fn ope(
1373 self,
1374 ) -> crate::common::RegisterField<
1375 6,
1376 0x1,
1377 1,
1378 0,
1379 sbycr::Ope,
1380 sbycr::Ope,
1381 Sbycr_SPEC,
1382 crate::common::RW,
1383 > {
1384 crate::common::RegisterField::<
1385 6,
1386 0x1,
1387 1,
1388 0,
1389 sbycr::Ope,
1390 sbycr::Ope,
1391 Sbycr_SPEC,
1392 crate::common::RW,
1393 >::from_register(self, 0)
1394 }
1395}
1396impl ::core::default::Default for Sbycr {
1397 #[inline(always)]
1398 fn default() -> Sbycr {
1399 <crate::RegValueT<Sbycr_SPEC> as RegisterValue<_>>::new(64)
1400 }
1401}
1402pub mod sbycr {
1403
1404 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1405 pub struct Ope_SPEC;
1406 pub type Ope = crate::EnumBitfieldStruct<u8, Ope_SPEC>;
1407 impl Ope {
1408 #[doc = "In Software Standby mode or Deep Software Standby mode, set the address bus and other bus control signal to the high-impedance state."]
1409 pub const _0: Self = Self::new(0);
1410
1411 #[doc = "In Software Standby mode or Deep Software Standby mode, address bus and other bus control signal retain the output state."]
1412 pub const _1: Self = Self::new(1);
1413 }
1414}
1415#[doc(hidden)]
1416#[derive(Copy, Clone, Eq, PartialEq)]
1417pub struct Sckdivcr_SPEC;
1418impl crate::sealed::RegSpec for Sckdivcr_SPEC {
1419 type DataType = u32;
1420}
1421
1422#[doc = "System Clock Division Control Register"]
1423pub type Sckdivcr = crate::RegValueT<Sckdivcr_SPEC>;
1424
1425impl Sckdivcr {
1426 #[doc = "Peripheral Module Clock D (PCLKD) Select"]
1427 #[inline(always)]
1428 pub fn pckd(
1429 self,
1430 ) -> crate::common::RegisterField<
1431 0,
1432 0xf,
1433 1,
1434 0,
1435 sckdivcr::Pckd,
1436 sckdivcr::Pckd,
1437 Sckdivcr_SPEC,
1438 crate::common::RW,
1439 > {
1440 crate::common::RegisterField::<
1441 0,
1442 0xf,
1443 1,
1444 0,
1445 sckdivcr::Pckd,
1446 sckdivcr::Pckd,
1447 Sckdivcr_SPEC,
1448 crate::common::RW,
1449 >::from_register(self, 0)
1450 }
1451
1452 #[doc = "Peripheral Module Clock C (PCLKC) Select"]
1453 #[inline(always)]
1454 pub fn pckc(
1455 self,
1456 ) -> crate::common::RegisterField<
1457 4,
1458 0xf,
1459 1,
1460 0,
1461 sckdivcr::Pckc,
1462 sckdivcr::Pckc,
1463 Sckdivcr_SPEC,
1464 crate::common::RW,
1465 > {
1466 crate::common::RegisterField::<
1467 4,
1468 0xf,
1469 1,
1470 0,
1471 sckdivcr::Pckc,
1472 sckdivcr::Pckc,
1473 Sckdivcr_SPEC,
1474 crate::common::RW,
1475 >::from_register(self, 0)
1476 }
1477
1478 #[doc = "Peripheral Module Clock B (PCLKB) Select"]
1479 #[inline(always)]
1480 pub fn pckb(
1481 self,
1482 ) -> crate::common::RegisterField<
1483 8,
1484 0xf,
1485 1,
1486 0,
1487 sckdivcr::Pckb,
1488 sckdivcr::Pckb,
1489 Sckdivcr_SPEC,
1490 crate::common::RW,
1491 > {
1492 crate::common::RegisterField::<
1493 8,
1494 0xf,
1495 1,
1496 0,
1497 sckdivcr::Pckb,
1498 sckdivcr::Pckb,
1499 Sckdivcr_SPEC,
1500 crate::common::RW,
1501 >::from_register(self, 0)
1502 }
1503
1504 #[doc = "Peripheral Module Clock A (PCLKA) Select"]
1505 #[inline(always)]
1506 pub fn pcka(
1507 self,
1508 ) -> crate::common::RegisterField<
1509 12,
1510 0xf,
1511 1,
1512 0,
1513 sckdivcr::Pcka,
1514 sckdivcr::Pcka,
1515 Sckdivcr_SPEC,
1516 crate::common::RW,
1517 > {
1518 crate::common::RegisterField::<
1519 12,
1520 0xf,
1521 1,
1522 0,
1523 sckdivcr::Pcka,
1524 sckdivcr::Pcka,
1525 Sckdivcr_SPEC,
1526 crate::common::RW,
1527 >::from_register(self, 0)
1528 }
1529
1530 #[doc = "External Bus Clock (BCLK) Select"]
1531 #[inline(always)]
1532 pub fn bck(
1533 self,
1534 ) -> crate::common::RegisterField<
1535 16,
1536 0xf,
1537 1,
1538 0,
1539 sckdivcr::Bck,
1540 sckdivcr::Bck,
1541 Sckdivcr_SPEC,
1542 crate::common::RW,
1543 > {
1544 crate::common::RegisterField::<
1545 16,
1546 0xf,
1547 1,
1548 0,
1549 sckdivcr::Bck,
1550 sckdivcr::Bck,
1551 Sckdivcr_SPEC,
1552 crate::common::RW,
1553 >::from_register(self, 0)
1554 }
1555
1556 #[doc = "System Clock (ICLK) Select"]
1557 #[inline(always)]
1558 pub fn ick(
1559 self,
1560 ) -> crate::common::RegisterField<
1561 24,
1562 0xf,
1563 1,
1564 0,
1565 sckdivcr::Ick,
1566 sckdivcr::Ick,
1567 Sckdivcr_SPEC,
1568 crate::common::RW,
1569 > {
1570 crate::common::RegisterField::<
1571 24,
1572 0xf,
1573 1,
1574 0,
1575 sckdivcr::Ick,
1576 sckdivcr::Ick,
1577 Sckdivcr_SPEC,
1578 crate::common::RW,
1579 >::from_register(self, 0)
1580 }
1581
1582 #[doc = "FlashIF Clock (FCLK) Select"]
1583 #[inline(always)]
1584 pub fn fck(
1585 self,
1586 ) -> crate::common::RegisterField<
1587 28,
1588 0xf,
1589 1,
1590 0,
1591 sckdivcr::Fck,
1592 sckdivcr::Fck,
1593 Sckdivcr_SPEC,
1594 crate::common::RW,
1595 > {
1596 crate::common::RegisterField::<
1597 28,
1598 0xf,
1599 1,
1600 0,
1601 sckdivcr::Fck,
1602 sckdivcr::Fck,
1603 Sckdivcr_SPEC,
1604 crate::common::RW,
1605 >::from_register(self, 0)
1606 }
1607}
1608impl ::core::default::Default for Sckdivcr {
1609 #[inline(always)]
1610 fn default() -> Sckdivcr {
1611 <crate::RegValueT<Sckdivcr_SPEC> as RegisterValue<_>>::new(0)
1612 }
1613}
1614pub mod sckdivcr {
1615
1616 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1617 pub struct Pckd_SPEC;
1618 pub type Pckd = crate::EnumBitfieldStruct<u8, Pckd_SPEC>;
1619 impl Pckd {
1620 #[doc = "x 1/1"]
1621 pub const _0000: Self = Self::new(0);
1622
1623 #[doc = "x 1/2"]
1624 pub const _0001: Self = Self::new(1);
1625
1626 #[doc = "x 1/4"]
1627 pub const _0010: Self = Self::new(2);
1628
1629 #[doc = "x 1/8"]
1630 pub const _0011: Self = Self::new(3);
1631
1632 #[doc = "x 1/16"]
1633 pub const _0100: Self = Self::new(4);
1634
1635 #[doc = "x 1/32"]
1636 pub const _0101: Self = Self::new(5);
1637
1638 #[doc = "x 1/64"]
1639 pub const _0110: Self = Self::new(6);
1640
1641 #[doc = "x 1/3"]
1642 pub const _1000: Self = Self::new(8);
1643
1644 #[doc = "x 1/6"]
1645 pub const _1001: Self = Self::new(9);
1646
1647 #[doc = "x 1/12"]
1648 pub const _1010: Self = Self::new(10);
1649
1650 #[doc = "Setting prohibited."]
1651 pub const OTHERS: Self = Self::new(0);
1652 }
1653 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1654 pub struct Pckc_SPEC;
1655 pub type Pckc = crate::EnumBitfieldStruct<u8, Pckc_SPEC>;
1656 impl Pckc {
1657 #[doc = "x 1/1"]
1658 pub const _0000: Self = Self::new(0);
1659
1660 #[doc = "x 1/2"]
1661 pub const _0001: Self = Self::new(1);
1662
1663 #[doc = "x 1/4"]
1664 pub const _0010: Self = Self::new(2);
1665
1666 #[doc = "x 1/8"]
1667 pub const _0011: Self = Self::new(3);
1668
1669 #[doc = "x 1/16"]
1670 pub const _0100: Self = Self::new(4);
1671
1672 #[doc = "x 1/32"]
1673 pub const _0101: Self = Self::new(5);
1674
1675 #[doc = "x 1/64"]
1676 pub const _0110: Self = Self::new(6);
1677
1678 #[doc = "x 1/3"]
1679 pub const _1000: Self = Self::new(8);
1680
1681 #[doc = "x 1/6"]
1682 pub const _1001: Self = Self::new(9);
1683
1684 #[doc = "x 1/12"]
1685 pub const _1010: Self = Self::new(10);
1686
1687 #[doc = "Setting prohibited."]
1688 pub const OTHERS: Self = Self::new(0);
1689 }
1690 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1691 pub struct Pckb_SPEC;
1692 pub type Pckb = crate::EnumBitfieldStruct<u8, Pckb_SPEC>;
1693 impl Pckb {
1694 #[doc = "x 1/1"]
1695 pub const _0000: Self = Self::new(0);
1696
1697 #[doc = "x 1/2"]
1698 pub const _0001: Self = Self::new(1);
1699
1700 #[doc = "x 1/4"]
1701 pub const _0010: Self = Self::new(2);
1702
1703 #[doc = "x 1/8"]
1704 pub const _0011: Self = Self::new(3);
1705
1706 #[doc = "x 1/16"]
1707 pub const _0100: Self = Self::new(4);
1708
1709 #[doc = "x 1/32"]
1710 pub const _0101: Self = Self::new(5);
1711
1712 #[doc = "x 1/64"]
1713 pub const _0110: Self = Self::new(6);
1714
1715 #[doc = "x 1/3"]
1716 pub const _1000: Self = Self::new(8);
1717
1718 #[doc = "x 1/6"]
1719 pub const _1001: Self = Self::new(9);
1720
1721 #[doc = "x 1/12"]
1722 pub const _1010: Self = Self::new(10);
1723
1724 #[doc = "Setting prohibited."]
1725 pub const OTHERS: Self = Self::new(0);
1726 }
1727 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1728 pub struct Pcka_SPEC;
1729 pub type Pcka = crate::EnumBitfieldStruct<u8, Pcka_SPEC>;
1730 impl Pcka {
1731 #[doc = "x 1/1"]
1732 pub const _0000: Self = Self::new(0);
1733
1734 #[doc = "x 1/2"]
1735 pub const _0001: Self = Self::new(1);
1736
1737 #[doc = "x 1/4"]
1738 pub const _0010: Self = Self::new(2);
1739
1740 #[doc = "x 1/8"]
1741 pub const _0011: Self = Self::new(3);
1742
1743 #[doc = "x 1/16"]
1744 pub const _0100: Self = Self::new(4);
1745
1746 #[doc = "x 1/32"]
1747 pub const _0101: Self = Self::new(5);
1748
1749 #[doc = "x 1/64"]
1750 pub const _0110: Self = Self::new(6);
1751
1752 #[doc = "x 1/3"]
1753 pub const _1000: Self = Self::new(8);
1754
1755 #[doc = "x 1/6"]
1756 pub const _1001: Self = Self::new(9);
1757
1758 #[doc = "x 1/12"]
1759 pub const _1010: Self = Self::new(10);
1760
1761 #[doc = "Setting prohibited."]
1762 pub const OTHERS: Self = Self::new(0);
1763 }
1764 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1765 pub struct Bck_SPEC;
1766 pub type Bck = crate::EnumBitfieldStruct<u8, Bck_SPEC>;
1767 impl Bck {
1768 #[doc = "x 1/1"]
1769 pub const _0000: Self = Self::new(0);
1770
1771 #[doc = "x 1/2"]
1772 pub const _0001: Self = Self::new(1);
1773
1774 #[doc = "x 1/4"]
1775 pub const _0010: Self = Self::new(2);
1776
1777 #[doc = "x 1/8"]
1778 pub const _0011: Self = Self::new(3);
1779
1780 #[doc = "x 1/16"]
1781 pub const _0100: Self = Self::new(4);
1782
1783 #[doc = "x 1/32"]
1784 pub const _0101: Self = Self::new(5);
1785
1786 #[doc = "x 1/64"]
1787 pub const _0110: Self = Self::new(6);
1788
1789 #[doc = "x 1/3"]
1790 pub const _1000: Self = Self::new(8);
1791
1792 #[doc = "x 1/6"]
1793 pub const _1001: Self = Self::new(9);
1794
1795 #[doc = "x 1/12"]
1796 pub const _1010: Self = Self::new(10);
1797
1798 #[doc = "Settings prohibited"]
1799 pub const OTHERS: Self = Self::new(0);
1800 }
1801 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1802 pub struct Ick_SPEC;
1803 pub type Ick = crate::EnumBitfieldStruct<u8, Ick_SPEC>;
1804 impl Ick {
1805 #[doc = "x 1/1"]
1806 pub const _0000: Self = Self::new(0);
1807
1808 #[doc = "x 1/2"]
1809 pub const _0001: Self = Self::new(1);
1810
1811 #[doc = "x 1/4"]
1812 pub const _0010: Self = Self::new(2);
1813
1814 #[doc = "x 1/8"]
1815 pub const _0011: Self = Self::new(3);
1816
1817 #[doc = "x 1/16"]
1818 pub const _0100: Self = Self::new(4);
1819
1820 #[doc = "x 1/32"]
1821 pub const _0101: Self = Self::new(5);
1822
1823 #[doc = "x 1/64"]
1824 pub const _0110: Self = Self::new(6);
1825
1826 #[doc = "x 1/3"]
1827 pub const _1000: Self = Self::new(8);
1828
1829 #[doc = "x 1/6"]
1830 pub const _1001: Self = Self::new(9);
1831
1832 #[doc = "x 1/12"]
1833 pub const _1010: Self = Self::new(10);
1834
1835 #[doc = "Setting prohibited."]
1836 pub const OTHERS: Self = Self::new(0);
1837 }
1838 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1839 pub struct Fck_SPEC;
1840 pub type Fck = crate::EnumBitfieldStruct<u8, Fck_SPEC>;
1841 impl Fck {
1842 #[doc = "x 1/1"]
1843 pub const _0000: Self = Self::new(0);
1844
1845 #[doc = "x 1/2"]
1846 pub const _0001: Self = Self::new(1);
1847
1848 #[doc = "x 1/4"]
1849 pub const _0010: Self = Self::new(2);
1850
1851 #[doc = "x 1/8"]
1852 pub const _0011: Self = Self::new(3);
1853
1854 #[doc = "x 1/16"]
1855 pub const _0100: Self = Self::new(4);
1856
1857 #[doc = "x 1/32"]
1858 pub const _0101: Self = Self::new(5);
1859
1860 #[doc = "x 1/64"]
1861 pub const _0110: Self = Self::new(6);
1862
1863 #[doc = "x 1/3"]
1864 pub const _1000: Self = Self::new(8);
1865
1866 #[doc = "x 1/6"]
1867 pub const _1001: Self = Self::new(9);
1868
1869 #[doc = "x 1/12"]
1870 pub const _1010: Self = Self::new(10);
1871
1872 #[doc = "Setting prohibited."]
1873 pub const OTHERS: Self = Self::new(0);
1874 }
1875}
1876#[doc(hidden)]
1877#[derive(Copy, Clone, Eq, PartialEq)]
1878pub struct Sckdivcr2_SPEC;
1879impl crate::sealed::RegSpec for Sckdivcr2_SPEC {
1880 type DataType = u8;
1881}
1882
1883#[doc = "System Clock Division Control Register 2"]
1884pub type Sckdivcr2 = crate::RegValueT<Sckdivcr2_SPEC>;
1885
1886impl Sckdivcr2 {
1887 #[doc = "CPU Clock (CPUCLK) Select"]
1888 #[inline(always)]
1889 pub fn cpuck(
1890 self,
1891 ) -> crate::common::RegisterField<
1892 0,
1893 0xf,
1894 1,
1895 0,
1896 sckdivcr2::Cpuck,
1897 sckdivcr2::Cpuck,
1898 Sckdivcr2_SPEC,
1899 crate::common::RW,
1900 > {
1901 crate::common::RegisterField::<
1902 0,
1903 0xf,
1904 1,
1905 0,
1906 sckdivcr2::Cpuck,
1907 sckdivcr2::Cpuck,
1908 Sckdivcr2_SPEC,
1909 crate::common::RW,
1910 >::from_register(self, 0)
1911 }
1912}
1913impl ::core::default::Default for Sckdivcr2 {
1914 #[inline(always)]
1915 fn default() -> Sckdivcr2 {
1916 <crate::RegValueT<Sckdivcr2_SPEC> as RegisterValue<_>>::new(0)
1917 }
1918}
1919pub mod sckdivcr2 {
1920
1921 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1922 pub struct Cpuck_SPEC;
1923 pub type Cpuck = crate::EnumBitfieldStruct<u8, Cpuck_SPEC>;
1924 impl Cpuck {
1925 #[doc = "x 1/1"]
1926 pub const _0000: Self = Self::new(0);
1927
1928 #[doc = "x 1/2"]
1929 pub const _0001: Self = Self::new(1);
1930
1931 #[doc = "x 1/4"]
1932 pub const _0010: Self = Self::new(2);
1933
1934 #[doc = "x 1/8"]
1935 pub const _0011: Self = Self::new(3);
1936
1937 #[doc = "x 1/16"]
1938 pub const _0100: Self = Self::new(4);
1939
1940 #[doc = "x 1/32"]
1941 pub const _0101: Self = Self::new(5);
1942
1943 #[doc = "x 1/64"]
1944 pub const _0110: Self = Self::new(6);
1945
1946 #[doc = "x 1/3"]
1947 pub const _1000: Self = Self::new(8);
1948
1949 #[doc = "x 1/6"]
1950 pub const _1001: Self = Self::new(9);
1951
1952 #[doc = "x 1/12"]
1953 pub const _1010: Self = Self::new(10);
1954
1955 #[doc = "Setting prohibited."]
1956 pub const OTHERS: Self = Self::new(0);
1957 }
1958}
1959#[doc(hidden)]
1960#[derive(Copy, Clone, Eq, PartialEq)]
1961pub struct Sckscr_SPEC;
1962impl crate::sealed::RegSpec for Sckscr_SPEC {
1963 type DataType = u8;
1964}
1965
1966#[doc = "System Clock Source Control Register"]
1967pub type Sckscr = crate::RegValueT<Sckscr_SPEC>;
1968
1969impl Sckscr {
1970 #[doc = "Clock Source Select"]
1971 #[inline(always)]
1972 pub fn cksel(
1973 self,
1974 ) -> crate::common::RegisterField<
1975 0,
1976 0x7,
1977 1,
1978 0,
1979 sckscr::Cksel,
1980 sckscr::Cksel,
1981 Sckscr_SPEC,
1982 crate::common::RW,
1983 > {
1984 crate::common::RegisterField::<
1985 0,
1986 0x7,
1987 1,
1988 0,
1989 sckscr::Cksel,
1990 sckscr::Cksel,
1991 Sckscr_SPEC,
1992 crate::common::RW,
1993 >::from_register(self, 0)
1994 }
1995}
1996impl ::core::default::Default for Sckscr {
1997 #[inline(always)]
1998 fn default() -> Sckscr {
1999 <crate::RegValueT<Sckscr_SPEC> as RegisterValue<_>>::new(1)
2000 }
2001}
2002pub mod sckscr {
2003
2004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2005 pub struct Cksel_SPEC;
2006 pub type Cksel = crate::EnumBitfieldStruct<u8, Cksel_SPEC>;
2007 impl Cksel {
2008 #[doc = "HOCO"]
2009 pub const _000: Self = Self::new(0);
2010
2011 #[doc = "MOCO (Value after reset)"]
2012 pub const _001: Self = Self::new(1);
2013
2014 #[doc = "Setting prohibited"]
2015 pub const _010: Self = Self::new(2);
2016
2017 #[doc = "Main clock oscillator (MOSC)"]
2018 pub const _011: Self = Self::new(3);
2019
2020 #[doc = "Sub-clock oscillator (SOSC)"]
2021 pub const _100: Self = Self::new(4);
2022
2023 #[doc = "PLL1 output clock P (PLL1P)"]
2024 pub const _101: Self = Self::new(5);
2025
2026 #[doc = "Setting prohibited"]
2027 pub const _110: Self = Self::new(6);
2028
2029 #[doc = "Setting prohibited"]
2030 pub const _111: Self = Self::new(7);
2031 }
2032}
2033#[doc(hidden)]
2034#[derive(Copy, Clone, Eq, PartialEq)]
2035pub struct Pllccr_SPEC;
2036impl crate::sealed::RegSpec for Pllccr_SPEC {
2037 type DataType = u16;
2038}
2039
2040#[doc = "PLL Clock Control Register"]
2041pub type Pllccr = crate::RegValueT<Pllccr_SPEC>;
2042
2043impl Pllccr {
2044 #[doc = "PLL1 Input Frequency Division Ratio Select"]
2045 #[inline(always)]
2046 pub fn plidiv(
2047 self,
2048 ) -> crate::common::RegisterField<
2049 0,
2050 0x3,
2051 1,
2052 0,
2053 pllccr::Plidiv,
2054 pllccr::Plidiv,
2055 Pllccr_SPEC,
2056 crate::common::RW,
2057 > {
2058 crate::common::RegisterField::<
2059 0,
2060 0x3,
2061 1,
2062 0,
2063 pllccr::Plidiv,
2064 pllccr::Plidiv,
2065 Pllccr_SPEC,
2066 crate::common::RW,
2067 >::from_register(self, 0)
2068 }
2069
2070 #[doc = "PLL1 Clock Source Select"]
2071 #[inline(always)]
2072 pub fn plsrcsel(
2073 self,
2074 ) -> crate::common::RegisterField<
2075 4,
2076 0x1,
2077 1,
2078 0,
2079 pllccr::Plsrcsel,
2080 pllccr::Plsrcsel,
2081 Pllccr_SPEC,
2082 crate::common::RW,
2083 > {
2084 crate::common::RegisterField::<
2085 4,
2086 0x1,
2087 1,
2088 0,
2089 pllccr::Plsrcsel,
2090 pllccr::Plsrcsel,
2091 Pllccr_SPEC,
2092 crate::common::RW,
2093 >::from_register(self, 0)
2094 }
2095
2096 #[doc = "PLL1 Frequency Multiplication Fractional Factor Select"]
2097 #[inline(always)]
2098 pub fn pllmulnf(
2099 self,
2100 ) -> crate::common::RegisterField<
2101 6,
2102 0x3,
2103 1,
2104 0,
2105 pllccr::Pllmulnf,
2106 pllccr::Pllmulnf,
2107 Pllccr_SPEC,
2108 crate::common::RW,
2109 > {
2110 crate::common::RegisterField::<
2111 6,
2112 0x3,
2113 1,
2114 0,
2115 pllccr::Pllmulnf,
2116 pllccr::Pllmulnf,
2117 Pllccr_SPEC,
2118 crate::common::RW,
2119 >::from_register(self, 0)
2120 }
2121
2122 #[doc = "PLL1 Frequency Multiplication Factor Select"]
2123 #[inline(always)]
2124 pub fn pllmul(
2125 self,
2126 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Pllccr_SPEC, crate::common::RW> {
2127 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Pllccr_SPEC,crate::common::RW>::from_register(self,0)
2128 }
2129}
2130impl ::core::default::Default for Pllccr {
2131 #[inline(always)]
2132 fn default() -> Pllccr {
2133 <crate::RegValueT<Pllccr_SPEC> as RegisterValue<_>>::new(6400)
2134 }
2135}
2136pub mod pllccr {
2137
2138 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2139 pub struct Plidiv_SPEC;
2140 pub type Plidiv = crate::EnumBitfieldStruct<u8, Plidiv_SPEC>;
2141 impl Plidiv {
2142 #[doc = "1/1"]
2143 pub const _00: Self = Self::new(0);
2144
2145 #[doc = "1/2"]
2146 pub const _01: Self = Self::new(1);
2147
2148 #[doc = "1/3"]
2149 pub const _10: Self = Self::new(2);
2150
2151 #[doc = "1/4"]
2152 pub const _11: Self = Self::new(3);
2153 }
2154 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2155 pub struct Plsrcsel_SPEC;
2156 pub type Plsrcsel = crate::EnumBitfieldStruct<u8, Plsrcsel_SPEC>;
2157 impl Plsrcsel {
2158 #[doc = "Main clock oscillator"]
2159 pub const _0: Self = Self::new(0);
2160
2161 #[doc = "HOCO"]
2162 pub const _1: Self = Self::new(1);
2163 }
2164 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2165 pub struct Pllmulnf_SPEC;
2166 pub type Pllmulnf = crate::EnumBitfieldStruct<u8, Pllmulnf_SPEC>;
2167 impl Pllmulnf {
2168 #[doc = "0.00 (Value after reset)"]
2169 pub const _00: Self = Self::new(0);
2170
2171 #[doc = "0.33 (1/3)"]
2172 pub const _01: Self = Self::new(1);
2173
2174 #[doc = "0.66 (2/3)"]
2175 pub const _10: Self = Self::new(2);
2176
2177 #[doc = "0.50 (1/2)"]
2178 pub const _11: Self = Self::new(3);
2179 }
2180}
2181#[doc(hidden)]
2182#[derive(Copy, Clone, Eq, PartialEq)]
2183pub struct Pllcr_SPEC;
2184impl crate::sealed::RegSpec for Pllcr_SPEC {
2185 type DataType = u8;
2186}
2187
2188#[doc = "PLL Control Register"]
2189pub type Pllcr = crate::RegValueT<Pllcr_SPEC>;
2190
2191impl Pllcr {
2192 #[doc = "PLL1 Stop Control"]
2193 #[inline(always)]
2194 pub fn pllstp(
2195 self,
2196 ) -> crate::common::RegisterField<
2197 0,
2198 0x1,
2199 1,
2200 0,
2201 pllcr::Pllstp,
2202 pllcr::Pllstp,
2203 Pllcr_SPEC,
2204 crate::common::RW,
2205 > {
2206 crate::common::RegisterField::<
2207 0,
2208 0x1,
2209 1,
2210 0,
2211 pllcr::Pllstp,
2212 pllcr::Pllstp,
2213 Pllcr_SPEC,
2214 crate::common::RW,
2215 >::from_register(self, 0)
2216 }
2217}
2218impl ::core::default::Default for Pllcr {
2219 #[inline(always)]
2220 fn default() -> Pllcr {
2221 <crate::RegValueT<Pllcr_SPEC> as RegisterValue<_>>::new(1)
2222 }
2223}
2224pub mod pllcr {
2225
2226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2227 pub struct Pllstp_SPEC;
2228 pub type Pllstp = crate::EnumBitfieldStruct<u8, Pllstp_SPEC>;
2229 impl Pllstp {
2230 #[doc = "PLL1 is operating"]
2231 pub const _0: Self = Self::new(0);
2232
2233 #[doc = "PLL1 is stopped"]
2234 pub const _1: Self = Self::new(1);
2235 }
2236}
2237#[doc(hidden)]
2238#[derive(Copy, Clone, Eq, PartialEq)]
2239pub struct Bckcr_SPEC;
2240impl crate::sealed::RegSpec for Bckcr_SPEC {
2241 type DataType = u8;
2242}
2243
2244#[doc = "External Bus Clock Control Register"]
2245pub type Bckcr = crate::RegValueT<Bckcr_SPEC>;
2246
2247impl Bckcr {
2248 #[doc = "BCLK Pin Output Select"]
2249 #[inline(always)]
2250 pub fn bclkdiv(
2251 self,
2252 ) -> crate::common::RegisterField<
2253 0,
2254 0x1,
2255 1,
2256 0,
2257 bckcr::Bclkdiv,
2258 bckcr::Bclkdiv,
2259 Bckcr_SPEC,
2260 crate::common::RW,
2261 > {
2262 crate::common::RegisterField::<
2263 0,
2264 0x1,
2265 1,
2266 0,
2267 bckcr::Bclkdiv,
2268 bckcr::Bclkdiv,
2269 Bckcr_SPEC,
2270 crate::common::RW,
2271 >::from_register(self, 0)
2272 }
2273}
2274impl ::core::default::Default for Bckcr {
2275 #[inline(always)]
2276 fn default() -> Bckcr {
2277 <crate::RegValueT<Bckcr_SPEC> as RegisterValue<_>>::new(0)
2278 }
2279}
2280pub mod bckcr {
2281
2282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2283 pub struct Bclkdiv_SPEC;
2284 pub type Bclkdiv = crate::EnumBitfieldStruct<u8, Bclkdiv_SPEC>;
2285 impl Bclkdiv {
2286 #[doc = "BCLK"]
2287 pub const _0: Self = Self::new(0);
2288
2289 #[doc = "BCLK/2"]
2290 pub const _1: Self = Self::new(1);
2291 }
2292}
2293#[doc(hidden)]
2294#[derive(Copy, Clone, Eq, PartialEq)]
2295pub struct Mosccr_SPEC;
2296impl crate::sealed::RegSpec for Mosccr_SPEC {
2297 type DataType = u8;
2298}
2299
2300#[doc = "Main Clock Oscillator Control Register"]
2301pub type Mosccr = crate::RegValueT<Mosccr_SPEC>;
2302
2303impl Mosccr {
2304 #[doc = "Main Clock Oscillator Stop"]
2305 #[inline(always)]
2306 pub fn mostp(
2307 self,
2308 ) -> crate::common::RegisterField<
2309 0,
2310 0x1,
2311 1,
2312 0,
2313 mosccr::Mostp,
2314 mosccr::Mostp,
2315 Mosccr_SPEC,
2316 crate::common::RW,
2317 > {
2318 crate::common::RegisterField::<
2319 0,
2320 0x1,
2321 1,
2322 0,
2323 mosccr::Mostp,
2324 mosccr::Mostp,
2325 Mosccr_SPEC,
2326 crate::common::RW,
2327 >::from_register(self, 0)
2328 }
2329}
2330impl ::core::default::Default for Mosccr {
2331 #[inline(always)]
2332 fn default() -> Mosccr {
2333 <crate::RegValueT<Mosccr_SPEC> as RegisterValue<_>>::new(1)
2334 }
2335}
2336pub mod mosccr {
2337
2338 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2339 pub struct Mostp_SPEC;
2340 pub type Mostp = crate::EnumBitfieldStruct<u8, Mostp_SPEC>;
2341 impl Mostp {
2342 #[doc = "Operate the main clock oscillator"]
2343 pub const _0: Self = Self::new(0);
2344
2345 #[doc = "Stop the main clock oscillator"]
2346 pub const _1: Self = Self::new(1);
2347 }
2348}
2349#[doc(hidden)]
2350#[derive(Copy, Clone, Eq, PartialEq)]
2351pub struct Hococr_SPEC;
2352impl crate::sealed::RegSpec for Hococr_SPEC {
2353 type DataType = u8;
2354}
2355
2356#[doc = "High-Speed On-Chip Oscillator Control Register"]
2357pub type Hococr = crate::RegValueT<Hococr_SPEC>;
2358
2359impl Hococr {
2360 #[doc = "HOCO Stop"]
2361 #[inline(always)]
2362 pub fn hcstp(
2363 self,
2364 ) -> crate::common::RegisterField<
2365 0,
2366 0x1,
2367 1,
2368 0,
2369 hococr::Hcstp,
2370 hococr::Hcstp,
2371 Hococr_SPEC,
2372 crate::common::RW,
2373 > {
2374 crate::common::RegisterField::<
2375 0,
2376 0x1,
2377 1,
2378 0,
2379 hococr::Hcstp,
2380 hococr::Hcstp,
2381 Hococr_SPEC,
2382 crate::common::RW,
2383 >::from_register(self, 0)
2384 }
2385}
2386impl ::core::default::Default for Hococr {
2387 #[inline(always)]
2388 fn default() -> Hococr {
2389 <crate::RegValueT<Hococr_SPEC> as RegisterValue<_>>::new(0)
2390 }
2391}
2392pub mod hococr {
2393
2394 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2395 pub struct Hcstp_SPEC;
2396 pub type Hcstp = crate::EnumBitfieldStruct<u8, Hcstp_SPEC>;
2397 impl Hcstp {
2398 #[doc = "Operate the HOCO clock"]
2399 pub const _0: Self = Self::new(0);
2400
2401 #[doc = "Stop the HOCO clock"]
2402 pub const _1: Self = Self::new(1);
2403 }
2404}
2405#[doc(hidden)]
2406#[derive(Copy, Clone, Eq, PartialEq)]
2407pub struct Hococr2_SPEC;
2408impl crate::sealed::RegSpec for Hococr2_SPEC {
2409 type DataType = u8;
2410}
2411
2412#[doc = "High-Speed On-Chip Oscillator Control Register2"]
2413pub type Hococr2 = crate::RegValueT<Hococr2_SPEC>;
2414
2415impl Hococr2 {
2416 #[doc = "HOCO Frequency Setting 0"]
2417 #[inline(always)]
2418 pub fn hcfrq0(
2419 self,
2420 ) -> crate::common::RegisterField<
2421 0,
2422 0x7,
2423 1,
2424 0,
2425 hococr2::Hcfrq0,
2426 hococr2::Hcfrq0,
2427 Hococr2_SPEC,
2428 crate::common::RW,
2429 > {
2430 crate::common::RegisterField::<
2431 0,
2432 0x7,
2433 1,
2434 0,
2435 hococr2::Hcfrq0,
2436 hococr2::Hcfrq0,
2437 Hococr2_SPEC,
2438 crate::common::RW,
2439 >::from_register(self, 0)
2440 }
2441}
2442impl ::core::default::Default for Hococr2 {
2443 #[inline(always)]
2444 fn default() -> Hococr2 {
2445 <crate::RegValueT<Hococr2_SPEC> as RegisterValue<_>>::new(0)
2446 }
2447}
2448pub mod hococr2 {
2449
2450 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2451 pub struct Hcfrq0_SPEC;
2452 pub type Hcfrq0 = crate::EnumBitfieldStruct<u8, Hcfrq0_SPEC>;
2453 impl Hcfrq0 {
2454 #[doc = "16MHz"]
2455 pub const _000: Self = Self::new(0);
2456
2457 #[doc = "18MHz"]
2458 pub const _001: Self = Self::new(1);
2459
2460 #[doc = "20MHz"]
2461 pub const _010: Self = Self::new(2);
2462
2463 #[doc = "32MHz"]
2464 pub const _100: Self = Self::new(4);
2465
2466 #[doc = "48MHz"]
2467 pub const _111: Self = Self::new(7);
2468 }
2469}
2470#[doc(hidden)]
2471#[derive(Copy, Clone, Eq, PartialEq)]
2472pub struct Mococr_SPEC;
2473impl crate::sealed::RegSpec for Mococr_SPEC {
2474 type DataType = u8;
2475}
2476
2477#[doc = "Middle-Speed On-Chip Oscillator Control Register"]
2478pub type Mococr = crate::RegValueT<Mococr_SPEC>;
2479
2480impl Mococr {
2481 #[doc = "MOCO Stop"]
2482 #[inline(always)]
2483 pub fn mcstp(
2484 self,
2485 ) -> crate::common::RegisterField<
2486 0,
2487 0x1,
2488 1,
2489 0,
2490 mococr::Mcstp,
2491 mococr::Mcstp,
2492 Mococr_SPEC,
2493 crate::common::RW,
2494 > {
2495 crate::common::RegisterField::<
2496 0,
2497 0x1,
2498 1,
2499 0,
2500 mococr::Mcstp,
2501 mococr::Mcstp,
2502 Mococr_SPEC,
2503 crate::common::RW,
2504 >::from_register(self, 0)
2505 }
2506}
2507impl ::core::default::Default for Mococr {
2508 #[inline(always)]
2509 fn default() -> Mococr {
2510 <crate::RegValueT<Mococr_SPEC> as RegisterValue<_>>::new(0)
2511 }
2512}
2513pub mod mococr {
2514
2515 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2516 pub struct Mcstp_SPEC;
2517 pub type Mcstp = crate::EnumBitfieldStruct<u8, Mcstp_SPEC>;
2518 impl Mcstp {
2519 #[doc = "MOCO clock is operating"]
2520 pub const _0: Self = Self::new(0);
2521
2522 #[doc = "MOCO clock is stopped"]
2523 pub const _1: Self = Self::new(1);
2524 }
2525}
2526#[doc(hidden)]
2527#[derive(Copy, Clone, Eq, PartialEq)]
2528pub struct Fllcr1_SPEC;
2529impl crate::sealed::RegSpec for Fllcr1_SPEC {
2530 type DataType = u8;
2531}
2532
2533#[doc = "FLL Control Register1"]
2534pub type Fllcr1 = crate::RegValueT<Fllcr1_SPEC>;
2535
2536impl Fllcr1 {
2537 #[doc = "FLL Enable"]
2538 #[inline(always)]
2539 pub fn fllen(
2540 self,
2541 ) -> crate::common::RegisterField<
2542 0,
2543 0x1,
2544 1,
2545 0,
2546 fllcr1::Fllen,
2547 fllcr1::Fllen,
2548 Fllcr1_SPEC,
2549 crate::common::RW,
2550 > {
2551 crate::common::RegisterField::<
2552 0,
2553 0x1,
2554 1,
2555 0,
2556 fllcr1::Fllen,
2557 fllcr1::Fllen,
2558 Fllcr1_SPEC,
2559 crate::common::RW,
2560 >::from_register(self, 0)
2561 }
2562}
2563impl ::core::default::Default for Fllcr1 {
2564 #[inline(always)]
2565 fn default() -> Fllcr1 {
2566 <crate::RegValueT<Fllcr1_SPEC> as RegisterValue<_>>::new(0)
2567 }
2568}
2569pub mod fllcr1 {
2570
2571 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2572 pub struct Fllen_SPEC;
2573 pub type Fllen = crate::EnumBitfieldStruct<u8, Fllen_SPEC>;
2574 impl Fllen {
2575 #[doc = "FLL function is disabled"]
2576 pub const _0: Self = Self::new(0);
2577
2578 #[doc = "FLL function is enabled."]
2579 pub const _1: Self = Self::new(1);
2580 }
2581}
2582#[doc(hidden)]
2583#[derive(Copy, Clone, Eq, PartialEq)]
2584pub struct Fllcr2_SPEC;
2585impl crate::sealed::RegSpec for Fllcr2_SPEC {
2586 type DataType = u16;
2587}
2588
2589#[doc = "FLL Control Register2"]
2590pub type Fllcr2 = crate::RegValueT<Fllcr2_SPEC>;
2591
2592impl Fllcr2 {
2593 #[doc = "FLL Multiplication Control"]
2594 #[inline(always)]
2595 pub fn fllcntl(
2596 self,
2597 ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Fllcr2_SPEC, crate::common::RW>
2598 {
2599 crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Fllcr2_SPEC,crate::common::RW>::from_register(self,0)
2600 }
2601}
2602impl ::core::default::Default for Fllcr2 {
2603 #[inline(always)]
2604 fn default() -> Fllcr2 {
2605 <crate::RegValueT<Fllcr2_SPEC> as RegisterValue<_>>::new(0)
2606 }
2607}
2608
2609#[doc(hidden)]
2610#[derive(Copy, Clone, Eq, PartialEq)]
2611pub struct Oscsf_SPEC;
2612impl crate::sealed::RegSpec for Oscsf_SPEC {
2613 type DataType = u8;
2614}
2615
2616#[doc = "Oscillation Stabilization Flag Register"]
2617pub type Oscsf = crate::RegValueT<Oscsf_SPEC>;
2618
2619impl Oscsf {
2620 #[doc = "HOCO Clock Oscillation Stabilization Flag"]
2621 #[inline(always)]
2622 pub fn hocosf(
2623 self,
2624 ) -> crate::common::RegisterField<
2625 0,
2626 0x1,
2627 1,
2628 0,
2629 oscsf::Hocosf,
2630 oscsf::Hocosf,
2631 Oscsf_SPEC,
2632 crate::common::R,
2633 > {
2634 crate::common::RegisterField::<
2635 0,
2636 0x1,
2637 1,
2638 0,
2639 oscsf::Hocosf,
2640 oscsf::Hocosf,
2641 Oscsf_SPEC,
2642 crate::common::R,
2643 >::from_register(self, 0)
2644 }
2645
2646 #[doc = "Main Clock Oscillation Stabilization Flag"]
2647 #[inline(always)]
2648 pub fn moscsf(
2649 self,
2650 ) -> crate::common::RegisterField<
2651 3,
2652 0x1,
2653 1,
2654 0,
2655 oscsf::Moscsf,
2656 oscsf::Moscsf,
2657 Oscsf_SPEC,
2658 crate::common::R,
2659 > {
2660 crate::common::RegisterField::<
2661 3,
2662 0x1,
2663 1,
2664 0,
2665 oscsf::Moscsf,
2666 oscsf::Moscsf,
2667 Oscsf_SPEC,
2668 crate::common::R,
2669 >::from_register(self, 0)
2670 }
2671
2672 #[doc = "PLL1 Clock Oscillation Stabilization Flag"]
2673 #[inline(always)]
2674 pub fn pllsf(
2675 self,
2676 ) -> crate::common::RegisterField<
2677 5,
2678 0x1,
2679 1,
2680 0,
2681 oscsf::Pllsf,
2682 oscsf::Pllsf,
2683 Oscsf_SPEC,
2684 crate::common::R,
2685 > {
2686 crate::common::RegisterField::<
2687 5,
2688 0x1,
2689 1,
2690 0,
2691 oscsf::Pllsf,
2692 oscsf::Pllsf,
2693 Oscsf_SPEC,
2694 crate::common::R,
2695 >::from_register(self, 0)
2696 }
2697
2698 #[doc = "PLL2 Clock Oscillation Stabilization Flag"]
2699 #[inline(always)]
2700 pub fn pll2sf(
2701 self,
2702 ) -> crate::common::RegisterField<
2703 6,
2704 0x1,
2705 1,
2706 0,
2707 oscsf::Pll2Sf,
2708 oscsf::Pll2Sf,
2709 Oscsf_SPEC,
2710 crate::common::R,
2711 > {
2712 crate::common::RegisterField::<
2713 6,
2714 0x1,
2715 1,
2716 0,
2717 oscsf::Pll2Sf,
2718 oscsf::Pll2Sf,
2719 Oscsf_SPEC,
2720 crate::common::R,
2721 >::from_register(self, 0)
2722 }
2723}
2724impl ::core::default::Default for Oscsf {
2725 #[inline(always)]
2726 fn default() -> Oscsf {
2727 <crate::RegValueT<Oscsf_SPEC> as RegisterValue<_>>::new(0)
2728 }
2729}
2730pub mod oscsf {
2731
2732 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2733 pub struct Hocosf_SPEC;
2734 pub type Hocosf = crate::EnumBitfieldStruct<u8, Hocosf_SPEC>;
2735 impl Hocosf {
2736 #[doc = "The HOCO clock is stopped or is not yet stable"]
2737 pub const _0: Self = Self::new(0);
2738
2739 #[doc = "The HOCO clock is stable, so is available for use as the system clock source"]
2740 pub const _1: Self = Self::new(1);
2741 }
2742 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2743 pub struct Moscsf_SPEC;
2744 pub type Moscsf = crate::EnumBitfieldStruct<u8, Moscsf_SPEC>;
2745 impl Moscsf {
2746 #[doc = "The main clock oscillator is stopped or is not yet stable"]
2747 pub const _0: Self = Self::new(0);
2748
2749 #[doc = "The main clock oscillator is stable, so is available for use as the system clock source"]
2750 pub const _1: Self = Self::new(1);
2751 }
2752 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2753 pub struct Pllsf_SPEC;
2754 pub type Pllsf = crate::EnumBitfieldStruct<u8, Pllsf_SPEC>;
2755 impl Pllsf {
2756 #[doc = "The PLL1 clock is stopped or is not yet stable."]
2757 pub const _0: Self = Self::new(0);
2758
2759 #[doc = "The PLL1 clock is stable, so is available for use as the system clock source"]
2760 pub const _1: Self = Self::new(1);
2761 }
2762 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2763 pub struct Pll2Sf_SPEC;
2764 pub type Pll2Sf = crate::EnumBitfieldStruct<u8, Pll2Sf_SPEC>;
2765 impl Pll2Sf {
2766 #[doc = "The PLL2 clock is stopped or is not yet stable."]
2767 pub const _0: Self = Self::new(0);
2768
2769 #[doc = "The PLL2 clock is stable"]
2770 pub const _1: Self = Self::new(1);
2771 }
2772}
2773#[doc(hidden)]
2774#[derive(Copy, Clone, Eq, PartialEq)]
2775pub struct Ckocr_SPEC;
2776impl crate::sealed::RegSpec for Ckocr_SPEC {
2777 type DataType = u8;
2778}
2779
2780#[doc = "Clock Out Control Register"]
2781pub type Ckocr = crate::RegValueT<Ckocr_SPEC>;
2782
2783impl Ckocr {
2784 #[doc = "Clock Out Source Select"]
2785 #[inline(always)]
2786 pub fn ckosel(
2787 self,
2788 ) -> crate::common::RegisterField<
2789 0,
2790 0x7,
2791 1,
2792 0,
2793 ckocr::Ckosel,
2794 ckocr::Ckosel,
2795 Ckocr_SPEC,
2796 crate::common::RW,
2797 > {
2798 crate::common::RegisterField::<
2799 0,
2800 0x7,
2801 1,
2802 0,
2803 ckocr::Ckosel,
2804 ckocr::Ckosel,
2805 Ckocr_SPEC,
2806 crate::common::RW,
2807 >::from_register(self, 0)
2808 }
2809
2810 #[doc = "Clock Output Frequency Division Ratio"]
2811 #[inline(always)]
2812 pub fn ckodiv(
2813 self,
2814 ) -> crate::common::RegisterField<
2815 4,
2816 0x7,
2817 1,
2818 0,
2819 ckocr::Ckodiv,
2820 ckocr::Ckodiv,
2821 Ckocr_SPEC,
2822 crate::common::RW,
2823 > {
2824 crate::common::RegisterField::<
2825 4,
2826 0x7,
2827 1,
2828 0,
2829 ckocr::Ckodiv,
2830 ckocr::Ckodiv,
2831 Ckocr_SPEC,
2832 crate::common::RW,
2833 >::from_register(self, 0)
2834 }
2835
2836 #[doc = "Clock Out Enable"]
2837 #[inline(always)]
2838 pub fn ckoen(
2839 self,
2840 ) -> crate::common::RegisterField<
2841 7,
2842 0x1,
2843 1,
2844 0,
2845 ckocr::Ckoen,
2846 ckocr::Ckoen,
2847 Ckocr_SPEC,
2848 crate::common::RW,
2849 > {
2850 crate::common::RegisterField::<
2851 7,
2852 0x1,
2853 1,
2854 0,
2855 ckocr::Ckoen,
2856 ckocr::Ckoen,
2857 Ckocr_SPEC,
2858 crate::common::RW,
2859 >::from_register(self, 0)
2860 }
2861}
2862impl ::core::default::Default for Ckocr {
2863 #[inline(always)]
2864 fn default() -> Ckocr {
2865 <crate::RegValueT<Ckocr_SPEC> as RegisterValue<_>>::new(1)
2866 }
2867}
2868pub mod ckocr {
2869
2870 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2871 pub struct Ckosel_SPEC;
2872 pub type Ckosel = crate::EnumBitfieldStruct<u8, Ckosel_SPEC>;
2873 impl Ckosel {
2874 #[doc = "HOCO"]
2875 pub const _000: Self = Self::new(0);
2876
2877 #[doc = "MOCO (Value after reset)"]
2878 pub const _001: Self = Self::new(1);
2879
2880 #[doc = "LOCO"]
2881 pub const _010: Self = Self::new(2);
2882
2883 #[doc = "MOSC"]
2884 pub const _011: Self = Self::new(3);
2885
2886 #[doc = "SOSC"]
2887 pub const _100: Self = Self::new(4);
2888
2889 #[doc = "Setting prohibited"]
2890 pub const OTHERS: Self = Self::new(0);
2891 }
2892 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2893 pub struct Ckodiv_SPEC;
2894 pub type Ckodiv = crate::EnumBitfieldStruct<u8, Ckodiv_SPEC>;
2895 impl Ckodiv {
2896 #[doc = "x 1/1"]
2897 pub const _000: Self = Self::new(0);
2898
2899 #[doc = "x 1/2"]
2900 pub const _001: Self = Self::new(1);
2901
2902 #[doc = "x 1/4"]
2903 pub const _010: Self = Self::new(2);
2904
2905 #[doc = "x 1/8"]
2906 pub const _011: Self = Self::new(3);
2907
2908 #[doc = "x 1/16"]
2909 pub const _100: Self = Self::new(4);
2910
2911 #[doc = "x 1/32"]
2912 pub const _101: Self = Self::new(5);
2913
2914 #[doc = "x 1/64"]
2915 pub const _110: Self = Self::new(6);
2916
2917 #[doc = "x 1/128"]
2918 pub const _111: Self = Self::new(7);
2919 }
2920 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2921 pub struct Ckoen_SPEC;
2922 pub type Ckoen = crate::EnumBitfieldStruct<u8, Ckoen_SPEC>;
2923 impl Ckoen {
2924 #[doc = "Disable clock out"]
2925 pub const _0: Self = Self::new(0);
2926
2927 #[doc = "Enable clock out"]
2928 pub const _1: Self = Self::new(1);
2929 }
2930}
2931#[doc(hidden)]
2932#[derive(Copy, Clone, Eq, PartialEq)]
2933pub struct Trckcr_SPEC;
2934impl crate::sealed::RegSpec for Trckcr_SPEC {
2935 type DataType = u8;
2936}
2937
2938#[doc = "Trace Clock Control Register"]
2939pub type Trckcr = crate::RegValueT<Trckcr_SPEC>;
2940
2941impl Trckcr {
2942 #[doc = "Trace Clock operating frequency select"]
2943 #[inline(always)]
2944 pub fn trck(
2945 self,
2946 ) -> crate::common::RegisterField<
2947 0,
2948 0xf,
2949 1,
2950 0,
2951 trckcr::Trck,
2952 trckcr::Trck,
2953 Trckcr_SPEC,
2954 crate::common::RW,
2955 > {
2956 crate::common::RegisterField::<
2957 0,
2958 0xf,
2959 1,
2960 0,
2961 trckcr::Trck,
2962 trckcr::Trck,
2963 Trckcr_SPEC,
2964 crate::common::RW,
2965 >::from_register(self, 0)
2966 }
2967
2968 #[doc = "Trace Clock source select"]
2969 #[inline(always)]
2970 pub fn trcksel(
2971 self,
2972 ) -> crate::common::RegisterField<
2973 4,
2974 0x1,
2975 1,
2976 0,
2977 trckcr::Trcksel,
2978 trckcr::Trcksel,
2979 Trckcr_SPEC,
2980 crate::common::RW,
2981 > {
2982 crate::common::RegisterField::<
2983 4,
2984 0x1,
2985 1,
2986 0,
2987 trckcr::Trcksel,
2988 trckcr::Trcksel,
2989 Trckcr_SPEC,
2990 crate::common::RW,
2991 >::from_register(self, 0)
2992 }
2993
2994 #[doc = "Trace Clock operating Enable"]
2995 #[inline(always)]
2996 pub fn trcken(
2997 self,
2998 ) -> crate::common::RegisterField<
2999 7,
3000 0x1,
3001 1,
3002 0,
3003 trckcr::Trcken,
3004 trckcr::Trcken,
3005 Trckcr_SPEC,
3006 crate::common::RW,
3007 > {
3008 crate::common::RegisterField::<
3009 7,
3010 0x1,
3011 1,
3012 0,
3013 trckcr::Trcken,
3014 trckcr::Trcken,
3015 Trckcr_SPEC,
3016 crate::common::RW,
3017 >::from_register(self, 0)
3018 }
3019}
3020impl ::core::default::Default for Trckcr {
3021 #[inline(always)]
3022 fn default() -> Trckcr {
3023 <crate::RegValueT<Trckcr_SPEC> as RegisterValue<_>>::new(2)
3024 }
3025}
3026pub mod trckcr {
3027
3028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3029 pub struct Trck_SPEC;
3030 pub type Trck = crate::EnumBitfieldStruct<u8, Trck_SPEC>;
3031 impl Trck {
3032 #[doc = "1/1"]
3033 pub const _0000: Self = Self::new(0);
3034
3035 #[doc = "1/2"]
3036 pub const _0001: Self = Self::new(1);
3037
3038 #[doc = "1/4 (Value after reset)"]
3039 pub const _0010: Self = Self::new(2);
3040
3041 #[doc = "1/8"]
3042 pub const _0011: Self = Self::new(3);
3043
3044 #[doc = "1/16"]
3045 pub const _0100: Self = Self::new(4);
3046
3047 #[doc = "1/32"]
3048 pub const _0101: Self = Self::new(5);
3049
3050 #[doc = "1/64"]
3051 pub const _0110: Self = Self::new(6);
3052
3053 #[doc = "1/128"]
3054 pub const _0111: Self = Self::new(7);
3055
3056 #[doc = "1/256"]
3057 pub const _1000: Self = Self::new(8);
3058
3059 #[doc = "1/3"]
3060 pub const _1001: Self = Self::new(9);
3061
3062 #[doc = "1/6"]
3063 pub const _1010: Self = Self::new(10);
3064
3065 #[doc = "1/12"]
3066 pub const _1011: Self = Self::new(11);
3067
3068 #[doc = "Setting prohibited"]
3069 pub const OTHERS: Self = Self::new(0);
3070 }
3071 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3072 pub struct Trcksel_SPEC;
3073 pub type Trcksel = crate::EnumBitfieldStruct<u8, Trcksel_SPEC>;
3074 impl Trcksel {
3075 #[doc = "System clock source (Value after reset)"]
3076 pub const _0: Self = Self::new(0);
3077
3078 #[doc = "HOCO (oscillation in debug mode)"]
3079 pub const _1: Self = Self::new(1);
3080 }
3081 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3082 pub struct Trcken_SPEC;
3083 pub type Trcken = crate::EnumBitfieldStruct<u8, Trcken_SPEC>;
3084 impl Trcken {
3085 #[doc = "Stop"]
3086 pub const _0: Self = Self::new(0);
3087
3088 #[doc = "Operation enable"]
3089 pub const _1: Self = Self::new(1);
3090 }
3091}
3092#[doc(hidden)]
3093#[derive(Copy, Clone, Eq, PartialEq)]
3094pub struct Ostdcr_SPEC;
3095impl crate::sealed::RegSpec for Ostdcr_SPEC {
3096 type DataType = u8;
3097}
3098
3099#[doc = "Oscillation Stop Detection Control Register"]
3100pub type Ostdcr = crate::RegValueT<Ostdcr_SPEC>;
3101
3102impl Ostdcr {
3103 #[doc = "Oscillation Stop Detection Interrupt Enable"]
3104 #[inline(always)]
3105 pub fn ostdie(
3106 self,
3107 ) -> crate::common::RegisterField<
3108 0,
3109 0x1,
3110 1,
3111 0,
3112 ostdcr::Ostdie,
3113 ostdcr::Ostdie,
3114 Ostdcr_SPEC,
3115 crate::common::RW,
3116 > {
3117 crate::common::RegisterField::<
3118 0,
3119 0x1,
3120 1,
3121 0,
3122 ostdcr::Ostdie,
3123 ostdcr::Ostdie,
3124 Ostdcr_SPEC,
3125 crate::common::RW,
3126 >::from_register(self, 0)
3127 }
3128
3129 #[doc = "Oscillation Stop Detection Function Enable"]
3130 #[inline(always)]
3131 pub fn ostde(
3132 self,
3133 ) -> crate::common::RegisterField<
3134 7,
3135 0x1,
3136 1,
3137 0,
3138 ostdcr::Ostde,
3139 ostdcr::Ostde,
3140 Ostdcr_SPEC,
3141 crate::common::RW,
3142 > {
3143 crate::common::RegisterField::<
3144 7,
3145 0x1,
3146 1,
3147 0,
3148 ostdcr::Ostde,
3149 ostdcr::Ostde,
3150 Ostdcr_SPEC,
3151 crate::common::RW,
3152 >::from_register(self, 0)
3153 }
3154}
3155impl ::core::default::Default for Ostdcr {
3156 #[inline(always)]
3157 fn default() -> Ostdcr {
3158 <crate::RegValueT<Ostdcr_SPEC> as RegisterValue<_>>::new(0)
3159 }
3160}
3161pub mod ostdcr {
3162
3163 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3164 pub struct Ostdie_SPEC;
3165 pub type Ostdie = crate::EnumBitfieldStruct<u8, Ostdie_SPEC>;
3166 impl Ostdie {
3167 #[doc = "Disable oscillation stop detection interrupt (do not notify the POEG)"]
3168 pub const _0: Self = Self::new(0);
3169
3170 #[doc = "Enable oscillation stop detection interrupt (notify the POEG)"]
3171 pub const _1: Self = Self::new(1);
3172 }
3173 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3174 pub struct Ostde_SPEC;
3175 pub type Ostde = crate::EnumBitfieldStruct<u8, Ostde_SPEC>;
3176 impl Ostde {
3177 #[doc = "Disable oscillation stop detection function"]
3178 pub const _0: Self = Self::new(0);
3179
3180 #[doc = "Enable oscillation stop detection function"]
3181 pub const _1: Self = Self::new(1);
3182 }
3183}
3184#[doc(hidden)]
3185#[derive(Copy, Clone, Eq, PartialEq)]
3186pub struct Ostdsr_SPEC;
3187impl crate::sealed::RegSpec for Ostdsr_SPEC {
3188 type DataType = u8;
3189}
3190
3191#[doc = "Oscillation Stop Detection Status Register"]
3192pub type Ostdsr = crate::RegValueT<Ostdsr_SPEC>;
3193
3194impl Ostdsr {
3195 #[doc = "Oscillation Stop Detection Flag"]
3196 #[inline(always)]
3197 pub fn ostdf(
3198 self,
3199 ) -> crate::common::RegisterField<
3200 0,
3201 0x1,
3202 1,
3203 0,
3204 ostdsr::Ostdf,
3205 ostdsr::Ostdf,
3206 Ostdsr_SPEC,
3207 crate::common::RW,
3208 > {
3209 crate::common::RegisterField::<
3210 0,
3211 0x1,
3212 1,
3213 0,
3214 ostdsr::Ostdf,
3215 ostdsr::Ostdf,
3216 Ostdsr_SPEC,
3217 crate::common::RW,
3218 >::from_register(self, 0)
3219 }
3220}
3221impl ::core::default::Default for Ostdsr {
3222 #[inline(always)]
3223 fn default() -> Ostdsr {
3224 <crate::RegValueT<Ostdsr_SPEC> as RegisterValue<_>>::new(0)
3225 }
3226}
3227pub mod ostdsr {
3228
3229 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3230 pub struct Ostdf_SPEC;
3231 pub type Ostdf = crate::EnumBitfieldStruct<u8, Ostdf_SPEC>;
3232 impl Ostdf {
3233 #[doc = "Main clock oscillation stop not detected"]
3234 pub const _0: Self = Self::new(0);
3235
3236 #[doc = "Main clock oscillation stop detected"]
3237 pub const _1: Self = Self::new(1);
3238 }
3239}
3240#[doc(hidden)]
3241#[derive(Copy, Clone, Eq, PartialEq)]
3242pub struct Oscmonr_SPEC;
3243impl crate::sealed::RegSpec for Oscmonr_SPEC {
3244 type DataType = u8;
3245}
3246
3247#[doc = "Oscillator Monitor Register"]
3248pub type Oscmonr = crate::RegValueT<Oscmonr_SPEC>;
3249
3250impl Oscmonr {
3251 #[doc = "MOCO operation monitor"]
3252 #[inline(always)]
3253 pub fn mocomon(
3254 self,
3255 ) -> crate::common::RegisterField<
3256 1,
3257 0x1,
3258 1,
3259 0,
3260 oscmonr::Mocomon,
3261 oscmonr::Mocomon,
3262 Oscmonr_SPEC,
3263 crate::common::R,
3264 > {
3265 crate::common::RegisterField::<
3266 1,
3267 0x1,
3268 1,
3269 0,
3270 oscmonr::Mocomon,
3271 oscmonr::Mocomon,
3272 Oscmonr_SPEC,
3273 crate::common::R,
3274 >::from_register(self, 0)
3275 }
3276
3277 #[doc = "LOCO operation monitor"]
3278 #[inline(always)]
3279 pub fn locomon(
3280 self,
3281 ) -> crate::common::RegisterField<
3282 2,
3283 0x1,
3284 1,
3285 0,
3286 oscmonr::Locomon,
3287 oscmonr::Locomon,
3288 Oscmonr_SPEC,
3289 crate::common::R,
3290 > {
3291 crate::common::RegisterField::<
3292 2,
3293 0x1,
3294 1,
3295 0,
3296 oscmonr::Locomon,
3297 oscmonr::Locomon,
3298 Oscmonr_SPEC,
3299 crate::common::R,
3300 >::from_register(self, 0)
3301 }
3302}
3303impl ::core::default::Default for Oscmonr {
3304 #[inline(always)]
3305 fn default() -> Oscmonr {
3306 <crate::RegValueT<Oscmonr_SPEC> as RegisterValue<_>>::new(0)
3307 }
3308}
3309pub mod oscmonr {
3310
3311 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3312 pub struct Mocomon_SPEC;
3313 pub type Mocomon = crate::EnumBitfieldStruct<u8, Mocomon_SPEC>;
3314 impl Mocomon {
3315 #[doc = "MOCO is set to operate."]
3316 pub const _0: Self = Self::new(0);
3317
3318 #[doc = "MOCO is set to stop."]
3319 pub const _1: Self = Self::new(1);
3320 }
3321 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3322 pub struct Locomon_SPEC;
3323 pub type Locomon = crate::EnumBitfieldStruct<u8, Locomon_SPEC>;
3324 impl Locomon {
3325 #[doc = "LOCO is set to operate."]
3326 pub const _0: Self = Self::new(0);
3327
3328 #[doc = "LOCO is set to stop."]
3329 pub const _1: Self = Self::new(1);
3330 }
3331}
3332#[doc(hidden)]
3333#[derive(Copy, Clone, Eq, PartialEq)]
3334pub struct Pll2Ccr_SPEC;
3335impl crate::sealed::RegSpec for Pll2Ccr_SPEC {
3336 type DataType = u16;
3337}
3338
3339#[doc = "PLL2 Clock Control Register"]
3340pub type Pll2Ccr = crate::RegValueT<Pll2Ccr_SPEC>;
3341
3342impl Pll2Ccr {
3343 #[doc = "PLL2 Input Frequency Division Ratio Select"]
3344 #[inline(always)]
3345 pub fn pl2idiv(
3346 self,
3347 ) -> crate::common::RegisterField<
3348 0,
3349 0x3,
3350 1,
3351 0,
3352 pll2ccr::Pl2Idiv,
3353 pll2ccr::Pl2Idiv,
3354 Pll2Ccr_SPEC,
3355 crate::common::RW,
3356 > {
3357 crate::common::RegisterField::<
3358 0,
3359 0x3,
3360 1,
3361 0,
3362 pll2ccr::Pl2Idiv,
3363 pll2ccr::Pl2Idiv,
3364 Pll2Ccr_SPEC,
3365 crate::common::RW,
3366 >::from_register(self, 0)
3367 }
3368
3369 #[doc = "PLL2 Clock Source Select"]
3370 #[inline(always)]
3371 pub fn pl2srcsel(
3372 self,
3373 ) -> crate::common::RegisterField<
3374 4,
3375 0x1,
3376 1,
3377 0,
3378 pll2ccr::Pl2Srcsel,
3379 pll2ccr::Pl2Srcsel,
3380 Pll2Ccr_SPEC,
3381 crate::common::RW,
3382 > {
3383 crate::common::RegisterField::<
3384 4,
3385 0x1,
3386 1,
3387 0,
3388 pll2ccr::Pl2Srcsel,
3389 pll2ccr::Pl2Srcsel,
3390 Pll2Ccr_SPEC,
3391 crate::common::RW,
3392 >::from_register(self, 0)
3393 }
3394
3395 #[doc = "PLL2 Frequency Multiplication Fractional Factor Select"]
3396 #[inline(always)]
3397 pub fn pll2mulnf(
3398 self,
3399 ) -> crate::common::RegisterField<
3400 6,
3401 0x3,
3402 1,
3403 0,
3404 pll2ccr::Pll2Mulnf,
3405 pll2ccr::Pll2Mulnf,
3406 Pll2Ccr_SPEC,
3407 crate::common::RW,
3408 > {
3409 crate::common::RegisterField::<
3410 6,
3411 0x3,
3412 1,
3413 0,
3414 pll2ccr::Pll2Mulnf,
3415 pll2ccr::Pll2Mulnf,
3416 Pll2Ccr_SPEC,
3417 crate::common::RW,
3418 >::from_register(self, 0)
3419 }
3420
3421 #[doc = "PLL2 Frequency Multiplication Factor Select"]
3422 #[inline(always)]
3423 pub fn pll2mul(
3424 self,
3425 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Pll2Ccr_SPEC, crate::common::RW> {
3426 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Pll2Ccr_SPEC,crate::common::RW>::from_register(self,0)
3427 }
3428}
3429impl ::core::default::Default for Pll2Ccr {
3430 #[inline(always)]
3431 fn default() -> Pll2Ccr {
3432 <crate::RegValueT<Pll2Ccr_SPEC> as RegisterValue<_>>::new(6400)
3433 }
3434}
3435pub mod pll2ccr {
3436
3437 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3438 pub struct Pl2Idiv_SPEC;
3439 pub type Pl2Idiv = crate::EnumBitfieldStruct<u8, Pl2Idiv_SPEC>;
3440 impl Pl2Idiv {
3441 #[doc = "1/1 (Value after reset)"]
3442 pub const _00: Self = Self::new(0);
3443
3444 #[doc = "1/2"]
3445 pub const _01: Self = Self::new(1);
3446
3447 #[doc = "1/3"]
3448 pub const _10: Self = Self::new(2);
3449
3450 #[doc = "1/4"]
3451 pub const _11: Self = Self::new(3);
3452 }
3453 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3454 pub struct Pl2Srcsel_SPEC;
3455 pub type Pl2Srcsel = crate::EnumBitfieldStruct<u8, Pl2Srcsel_SPEC>;
3456 impl Pl2Srcsel {
3457 #[doc = "Main clock oscillator"]
3458 pub const _0: Self = Self::new(0);
3459
3460 #[doc = "HOCO"]
3461 pub const _1: Self = Self::new(1);
3462 }
3463 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3464 pub struct Pll2Mulnf_SPEC;
3465 pub type Pll2Mulnf = crate::EnumBitfieldStruct<u8, Pll2Mulnf_SPEC>;
3466 impl Pll2Mulnf {
3467 #[doc = "0.00 (Value after reset)"]
3468 pub const _00: Self = Self::new(0);
3469
3470 #[doc = "0.33 (1/3)"]
3471 pub const _01: Self = Self::new(1);
3472
3473 #[doc = "0.66 (2/3)"]
3474 pub const _10: Self = Self::new(2);
3475
3476 #[doc = "0.50 (1/2)"]
3477 pub const _11: Self = Self::new(3);
3478 }
3479}
3480#[doc(hidden)]
3481#[derive(Copy, Clone, Eq, PartialEq)]
3482pub struct Pll2Cr_SPEC;
3483impl crate::sealed::RegSpec for Pll2Cr_SPEC {
3484 type DataType = u8;
3485}
3486
3487#[doc = "PLL2 Control Register"]
3488pub type Pll2Cr = crate::RegValueT<Pll2Cr_SPEC>;
3489
3490impl Pll2Cr {
3491 #[doc = "PLL2 Stop Control"]
3492 #[inline(always)]
3493 pub fn pll2stp(
3494 self,
3495 ) -> crate::common::RegisterField<
3496 0,
3497 0x1,
3498 1,
3499 0,
3500 pll2cr::Pll2Stp,
3501 pll2cr::Pll2Stp,
3502 Pll2Cr_SPEC,
3503 crate::common::RW,
3504 > {
3505 crate::common::RegisterField::<
3506 0,
3507 0x1,
3508 1,
3509 0,
3510 pll2cr::Pll2Stp,
3511 pll2cr::Pll2Stp,
3512 Pll2Cr_SPEC,
3513 crate::common::RW,
3514 >::from_register(self, 0)
3515 }
3516}
3517impl ::core::default::Default for Pll2Cr {
3518 #[inline(always)]
3519 fn default() -> Pll2Cr {
3520 <crate::RegValueT<Pll2Cr_SPEC> as RegisterValue<_>>::new(1)
3521 }
3522}
3523pub mod pll2cr {
3524
3525 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3526 pub struct Pll2Stp_SPEC;
3527 pub type Pll2Stp = crate::EnumBitfieldStruct<u8, Pll2Stp_SPEC>;
3528 impl Pll2Stp {
3529 #[doc = "PLL2 is operating"]
3530 pub const _0: Self = Self::new(0);
3531
3532 #[doc = "PLL2 is stopped"]
3533 pub const _1: Self = Self::new(1);
3534 }
3535}
3536#[doc(hidden)]
3537#[derive(Copy, Clone, Eq, PartialEq)]
3538pub struct Pllccr2_SPEC;
3539impl crate::sealed::RegSpec for Pllccr2_SPEC {
3540 type DataType = u16;
3541}
3542
3543#[doc = "PLL Clock Control Register 2"]
3544pub type Pllccr2 = crate::RegValueT<Pllccr2_SPEC>;
3545
3546impl Pllccr2 {
3547 #[doc = "PLL1 Output Frequency Division Ratio Select for output clock P"]
3548 #[inline(always)]
3549 pub fn plodivp(
3550 self,
3551 ) -> crate::common::RegisterField<
3552 0,
3553 0xf,
3554 1,
3555 0,
3556 pllccr2::Plodivp,
3557 pllccr2::Plodivp,
3558 Pllccr2_SPEC,
3559 crate::common::RW,
3560 > {
3561 crate::common::RegisterField::<
3562 0,
3563 0xf,
3564 1,
3565 0,
3566 pllccr2::Plodivp,
3567 pllccr2::Plodivp,
3568 Pllccr2_SPEC,
3569 crate::common::RW,
3570 >::from_register(self, 0)
3571 }
3572
3573 #[doc = "PLL1 Output Frequency Division Ratio Select for output clock Q"]
3574 #[inline(always)]
3575 pub fn plodivq(
3576 self,
3577 ) -> crate::common::RegisterField<
3578 4,
3579 0xf,
3580 1,
3581 0,
3582 pllccr2::Plodivq,
3583 pllccr2::Plodivq,
3584 Pllccr2_SPEC,
3585 crate::common::RW,
3586 > {
3587 crate::common::RegisterField::<
3588 4,
3589 0xf,
3590 1,
3591 0,
3592 pllccr2::Plodivq,
3593 pllccr2::Plodivq,
3594 Pllccr2_SPEC,
3595 crate::common::RW,
3596 >::from_register(self, 0)
3597 }
3598
3599 #[doc = "PLL1 Output Frequency Division Ratio Select for output clock R"]
3600 #[inline(always)]
3601 pub fn plodivr(
3602 self,
3603 ) -> crate::common::RegisterField<
3604 8,
3605 0xf,
3606 1,
3607 0,
3608 pllccr2::Plodivr,
3609 pllccr2::Plodivr,
3610 Pllccr2_SPEC,
3611 crate::common::RW,
3612 > {
3613 crate::common::RegisterField::<
3614 8,
3615 0xf,
3616 1,
3617 0,
3618 pllccr2::Plodivr,
3619 pllccr2::Plodivr,
3620 Pllccr2_SPEC,
3621 crate::common::RW,
3622 >::from_register(self, 0)
3623 }
3624}
3625impl ::core::default::Default for Pllccr2 {
3626 #[inline(always)]
3627 fn default() -> Pllccr2 {
3628 <crate::RegValueT<Pllccr2_SPEC> as RegisterValue<_>>::new(1365)
3629 }
3630}
3631pub mod pllccr2 {
3632
3633 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3634 pub struct Plodivp_SPEC;
3635 pub type Plodivp = crate::EnumBitfieldStruct<u8, Plodivp_SPEC>;
3636 impl Plodivp {
3637 #[doc = "× 1/2"]
3638 pub const _0001: Self = Self::new(1);
3639
3640 #[doc = "× 1/4"]
3641 pub const _0011: Self = Self::new(3);
3642
3643 #[doc = "× 1/6 (Value after reset)"]
3644 pub const _0101: Self = Self::new(5);
3645
3646 #[doc = "× 1/8"]
3647 pub const _0111: Self = Self::new(7);
3648
3649 #[doc = "× 1/16"]
3650 pub const _1111: Self = Self::new(15);
3651
3652 #[doc = "Setting prohibited."]
3653 pub const OTHERS: Self = Self::new(0);
3654 }
3655 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3656 pub struct Plodivq_SPEC;
3657 pub type Plodivq = crate::EnumBitfieldStruct<u8, Plodivq_SPEC>;
3658 impl Plodivq {
3659 #[doc = "× 1/2"]
3660 pub const _0001: Self = Self::new(1);
3661
3662 #[doc = "× 1/3"]
3663 pub const _0010: Self = Self::new(2);
3664
3665 #[doc = "× 1/4"]
3666 pub const _0011: Self = Self::new(3);
3667
3668 #[doc = "× 1/5"]
3669 pub const _0100: Self = Self::new(4);
3670
3671 #[doc = "× 1/6 (Value after reset)"]
3672 pub const _0101: Self = Self::new(5);
3673
3674 #[doc = "× 1/8"]
3675 pub const _0111: Self = Self::new(7);
3676
3677 #[doc = "× 1/9"]
3678 pub const _1000: Self = Self::new(8);
3679
3680 #[doc = "Setting prohibited."]
3681 pub const OTHERS: Self = Self::new(0);
3682 }
3683 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3684 pub struct Plodivr_SPEC;
3685 pub type Plodivr = crate::EnumBitfieldStruct<u8, Plodivr_SPEC>;
3686 impl Plodivr {
3687 #[doc = "× 1/2"]
3688 pub const _0001: Self = Self::new(1);
3689
3690 #[doc = "× 1/3"]
3691 pub const _0010: Self = Self::new(2);
3692
3693 #[doc = "× 1/4"]
3694 pub const _0011: Self = Self::new(3);
3695
3696 #[doc = "× 1/5"]
3697 pub const _0100: Self = Self::new(4);
3698
3699 #[doc = "× 1/6 (Value after reset)"]
3700 pub const _0101: Self = Self::new(5);
3701
3702 #[doc = "× 1/8"]
3703 pub const _0111: Self = Self::new(7);
3704
3705 #[doc = "× 1/9"]
3706 pub const _1000: Self = Self::new(8);
3707
3708 #[doc = "Setting prohibited."]
3709 pub const OTHERS: Self = Self::new(0);
3710 }
3711}
3712#[doc(hidden)]
3713#[derive(Copy, Clone, Eq, PartialEq)]
3714pub struct Pll2Ccr2_SPEC;
3715impl crate::sealed::RegSpec for Pll2Ccr2_SPEC {
3716 type DataType = u16;
3717}
3718
3719#[doc = "PLL2 Clock Control Register 2"]
3720pub type Pll2Ccr2 = crate::RegValueT<Pll2Ccr2_SPEC>;
3721
3722impl Pll2Ccr2 {
3723 #[doc = "PLL2 Output Frequency Division Ratio Select for output clock P"]
3724 #[inline(always)]
3725 pub fn pl2odivp(
3726 self,
3727 ) -> crate::common::RegisterField<
3728 0,
3729 0xf,
3730 1,
3731 0,
3732 pll2ccr2::Pl2Odivp,
3733 pll2ccr2::Pl2Odivp,
3734 Pll2Ccr2_SPEC,
3735 crate::common::RW,
3736 > {
3737 crate::common::RegisterField::<
3738 0,
3739 0xf,
3740 1,
3741 0,
3742 pll2ccr2::Pl2Odivp,
3743 pll2ccr2::Pl2Odivp,
3744 Pll2Ccr2_SPEC,
3745 crate::common::RW,
3746 >::from_register(self, 0)
3747 }
3748
3749 #[doc = "PLL2 Output Frequency Division Ratio Select for output clock Q"]
3750 #[inline(always)]
3751 pub fn pl2odivq(
3752 self,
3753 ) -> crate::common::RegisterField<
3754 4,
3755 0xf,
3756 1,
3757 0,
3758 pll2ccr2::Pl2Odivq,
3759 pll2ccr2::Pl2Odivq,
3760 Pll2Ccr2_SPEC,
3761 crate::common::RW,
3762 > {
3763 crate::common::RegisterField::<
3764 4,
3765 0xf,
3766 1,
3767 0,
3768 pll2ccr2::Pl2Odivq,
3769 pll2ccr2::Pl2Odivq,
3770 Pll2Ccr2_SPEC,
3771 crate::common::RW,
3772 >::from_register(self, 0)
3773 }
3774
3775 #[doc = "PLL2 Output Frequency Division Ratio Select for output clock R"]
3776 #[inline(always)]
3777 pub fn pl2odivr(
3778 self,
3779 ) -> crate::common::RegisterField<
3780 8,
3781 0xf,
3782 1,
3783 0,
3784 pll2ccr2::Pl2Odivr,
3785 pll2ccr2::Pl2Odivr,
3786 Pll2Ccr2_SPEC,
3787 crate::common::RW,
3788 > {
3789 crate::common::RegisterField::<
3790 8,
3791 0xf,
3792 1,
3793 0,
3794 pll2ccr2::Pl2Odivr,
3795 pll2ccr2::Pl2Odivr,
3796 Pll2Ccr2_SPEC,
3797 crate::common::RW,
3798 >::from_register(self, 0)
3799 }
3800}
3801impl ::core::default::Default for Pll2Ccr2 {
3802 #[inline(always)]
3803 fn default() -> Pll2Ccr2 {
3804 <crate::RegValueT<Pll2Ccr2_SPEC> as RegisterValue<_>>::new(1365)
3805 }
3806}
3807pub mod pll2ccr2 {
3808
3809 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3810 pub struct Pl2Odivp_SPEC;
3811 pub type Pl2Odivp = crate::EnumBitfieldStruct<u8, Pl2Odivp_SPEC>;
3812 impl Pl2Odivp {
3813 #[doc = "× 1/2"]
3814 pub const _0001: Self = Self::new(1);
3815
3816 #[doc = "× 1/4"]
3817 pub const _0011: Self = Self::new(3);
3818
3819 #[doc = "× 1/6 (Value after reset)"]
3820 pub const _0101: Self = Self::new(5);
3821
3822 #[doc = "× 1/8"]
3823 pub const _0111: Self = Self::new(7);
3824
3825 #[doc = "× 1/16"]
3826 pub const _1111: Self = Self::new(15);
3827
3828 #[doc = "Setting prohibited."]
3829 pub const OTHERS: Self = Self::new(0);
3830 }
3831 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3832 pub struct Pl2Odivq_SPEC;
3833 pub type Pl2Odivq = crate::EnumBitfieldStruct<u8, Pl2Odivq_SPEC>;
3834 impl Pl2Odivq {
3835 #[doc = "× 1/2"]
3836 pub const _0001: Self = Self::new(1);
3837
3838 #[doc = "× 1/3"]
3839 pub const _0010: Self = Self::new(2);
3840
3841 #[doc = "× 1/4"]
3842 pub const _0011: Self = Self::new(3);
3843
3844 #[doc = "× 1/5"]
3845 pub const _0100: Self = Self::new(4);
3846
3847 #[doc = "× 1/6 (Value after reset)"]
3848 pub const _0101: Self = Self::new(5);
3849
3850 #[doc = "× 1/8"]
3851 pub const _0111: Self = Self::new(7);
3852
3853 #[doc = "× 1/9"]
3854 pub const _1000: Self = Self::new(8);
3855
3856 #[doc = "Setting prohibited."]
3857 pub const OTHERS: Self = Self::new(0);
3858 }
3859 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3860 pub struct Pl2Odivr_SPEC;
3861 pub type Pl2Odivr = crate::EnumBitfieldStruct<u8, Pl2Odivr_SPEC>;
3862 impl Pl2Odivr {
3863 #[doc = "× 1/2"]
3864 pub const _0001: Self = Self::new(1);
3865
3866 #[doc = "× 1/3"]
3867 pub const _0010: Self = Self::new(2);
3868
3869 #[doc = "× 1/4"]
3870 pub const _0011: Self = Self::new(3);
3871
3872 #[doc = "× 1/5"]
3873 pub const _0100: Self = Self::new(4);
3874
3875 #[doc = "× 1/6 (Value after reset)"]
3876 pub const _0101: Self = Self::new(5);
3877
3878 #[doc = "× 1/8"]
3879 pub const _0111: Self = Self::new(7);
3880
3881 #[doc = "× 1/9"]
3882 pub const _1000: Self = Self::new(8);
3883
3884 #[doc = "Setting prohibited."]
3885 pub const OTHERS: Self = Self::new(0);
3886 }
3887}
3888#[doc(hidden)]
3889#[derive(Copy, Clone, Eq, PartialEq)]
3890pub struct Ebckocr_SPEC;
3891impl crate::sealed::RegSpec for Ebckocr_SPEC {
3892 type DataType = u8;
3893}
3894
3895#[doc = "External Bus Clock Output Control Register"]
3896pub type Ebckocr = crate::RegValueT<Ebckocr_SPEC>;
3897
3898impl Ebckocr {
3899 #[doc = "EBCLK Pin Output Control"]
3900 #[inline(always)]
3901 pub fn ebckoen(
3902 self,
3903 ) -> crate::common::RegisterField<
3904 0,
3905 0x1,
3906 1,
3907 0,
3908 ebckocr::Ebckoen,
3909 ebckocr::Ebckoen,
3910 Ebckocr_SPEC,
3911 crate::common::RW,
3912 > {
3913 crate::common::RegisterField::<
3914 0,
3915 0x1,
3916 1,
3917 0,
3918 ebckocr::Ebckoen,
3919 ebckocr::Ebckoen,
3920 Ebckocr_SPEC,
3921 crate::common::RW,
3922 >::from_register(self, 0)
3923 }
3924}
3925impl ::core::default::Default for Ebckocr {
3926 #[inline(always)]
3927 fn default() -> Ebckocr {
3928 <crate::RegValueT<Ebckocr_SPEC> as RegisterValue<_>>::new(0)
3929 }
3930}
3931pub mod ebckocr {
3932
3933 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3934 pub struct Ebckoen_SPEC;
3935 pub type Ebckoen = crate::EnumBitfieldStruct<u8, Ebckoen_SPEC>;
3936 impl Ebckoen {
3937 #[doc = "EBCLK pin output is disabled (fixed high)"]
3938 pub const _0: Self = Self::new(0);
3939
3940 #[doc = "EBCLK pin output is enabled."]
3941 pub const _1: Self = Self::new(1);
3942 }
3943}
3944#[doc(hidden)]
3945#[derive(Copy, Clone, Eq, PartialEq)]
3946pub struct Sdckocr_SPEC;
3947impl crate::sealed::RegSpec for Sdckocr_SPEC {
3948 type DataType = u8;
3949}
3950
3951#[doc = "SDRAM Clock Output Control Register"]
3952pub type Sdckocr = crate::RegValueT<Sdckocr_SPEC>;
3953
3954impl Sdckocr {
3955 #[doc = "SDCLK Pin Output Control"]
3956 #[inline(always)]
3957 pub fn sdckoen(
3958 self,
3959 ) -> crate::common::RegisterField<
3960 0,
3961 0x1,
3962 1,
3963 0,
3964 sdckocr::Sdckoen,
3965 sdckocr::Sdckoen,
3966 Sdckocr_SPEC,
3967 crate::common::RW,
3968 > {
3969 crate::common::RegisterField::<
3970 0,
3971 0x1,
3972 1,
3973 0,
3974 sdckocr::Sdckoen,
3975 sdckocr::Sdckoen,
3976 Sdckocr_SPEC,
3977 crate::common::RW,
3978 >::from_register(self, 0)
3979 }
3980}
3981impl ::core::default::Default for Sdckocr {
3982 #[inline(always)]
3983 fn default() -> Sdckocr {
3984 <crate::RegValueT<Sdckocr_SPEC> as RegisterValue<_>>::new(0)
3985 }
3986}
3987pub mod sdckocr {
3988
3989 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3990 pub struct Sdckoen_SPEC;
3991 pub type Sdckoen = crate::EnumBitfieldStruct<u8, Sdckoen_SPEC>;
3992 impl Sdckoen {
3993 #[doc = "SDCLK pin output is disabled. (Fixed high)"]
3994 pub const _0: Self = Self::new(0);
3995
3996 #[doc = "SDCLK pin output is enabled."]
3997 pub const _1: Self = Self::new(1);
3998 }
3999}
4000#[doc(hidden)]
4001#[derive(Copy, Clone, Eq, PartialEq)]
4002pub struct Scickdivcr_SPEC;
4003impl crate::sealed::RegSpec for Scickdivcr_SPEC {
4004 type DataType = u8;
4005}
4006
4007#[doc = "SCI clock Division control register"]
4008pub type Scickdivcr = crate::RegValueT<Scickdivcr_SPEC>;
4009
4010impl Scickdivcr {
4011 #[doc = "SCI clock (SCICLK) Division Select"]
4012 #[inline(always)]
4013 pub fn scickdiv(
4014 self,
4015 ) -> crate::common::RegisterField<
4016 0,
4017 0x7,
4018 1,
4019 0,
4020 scickdivcr::Scickdiv,
4021 scickdivcr::Scickdiv,
4022 Scickdivcr_SPEC,
4023 crate::common::RW,
4024 > {
4025 crate::common::RegisterField::<
4026 0,
4027 0x7,
4028 1,
4029 0,
4030 scickdivcr::Scickdiv,
4031 scickdivcr::Scickdiv,
4032 Scickdivcr_SPEC,
4033 crate::common::RW,
4034 >::from_register(self, 0)
4035 }
4036}
4037impl ::core::default::Default for Scickdivcr {
4038 #[inline(always)]
4039 fn default() -> Scickdivcr {
4040 <crate::RegValueT<Scickdivcr_SPEC> as RegisterValue<_>>::new(0)
4041 }
4042}
4043pub mod scickdivcr {
4044
4045 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4046 pub struct Scickdiv_SPEC;
4047 pub type Scickdiv = crate::EnumBitfieldStruct<u8, Scickdiv_SPEC>;
4048 impl Scickdiv {
4049 #[doc = "1/1 (Value after reset)"]
4050 pub const _000: Self = Self::new(0);
4051
4052 #[doc = "1/2"]
4053 pub const _001: Self = Self::new(1);
4054
4055 #[doc = "1/4"]
4056 pub const _010: Self = Self::new(2);
4057
4058 #[doc = "1/6"]
4059 pub const _011: Self = Self::new(3);
4060
4061 #[doc = "1/8"]
4062 pub const _100: Self = Self::new(4);
4063
4064 #[doc = "1/3"]
4065 pub const _101: Self = Self::new(5);
4066
4067 #[doc = "1/5"]
4068 pub const _110: Self = Self::new(6);
4069
4070 #[doc = "Setting prohibited."]
4071 pub const OTHERS: Self = Self::new(0);
4072 }
4073}
4074#[doc(hidden)]
4075#[derive(Copy, Clone, Eq, PartialEq)]
4076pub struct Scickcr_SPEC;
4077impl crate::sealed::RegSpec for Scickcr_SPEC {
4078 type DataType = u8;
4079}
4080
4081#[doc = "SCI clock control register"]
4082pub type Scickcr = crate::RegValueT<Scickcr_SPEC>;
4083
4084impl Scickcr {
4085 #[doc = "SCI clock (SCICLK) Source Select"]
4086 #[inline(always)]
4087 pub fn scicksel(
4088 self,
4089 ) -> crate::common::RegisterField<
4090 0,
4091 0xf,
4092 1,
4093 0,
4094 scickcr::Scicksel,
4095 scickcr::Scicksel,
4096 Scickcr_SPEC,
4097 crate::common::RW,
4098 > {
4099 crate::common::RegisterField::<
4100 0,
4101 0xf,
4102 1,
4103 0,
4104 scickcr::Scicksel,
4105 scickcr::Scicksel,
4106 Scickcr_SPEC,
4107 crate::common::RW,
4108 >::from_register(self, 0)
4109 }
4110
4111 #[doc = "SCI clock (SCICLK) Switching Request"]
4112 #[inline(always)]
4113 pub fn scicksreq(
4114 self,
4115 ) -> crate::common::RegisterField<
4116 6,
4117 0x1,
4118 1,
4119 0,
4120 scickcr::Scicksreq,
4121 scickcr::Scicksreq,
4122 Scickcr_SPEC,
4123 crate::common::RW,
4124 > {
4125 crate::common::RegisterField::<
4126 6,
4127 0x1,
4128 1,
4129 0,
4130 scickcr::Scicksreq,
4131 scickcr::Scicksreq,
4132 Scickcr_SPEC,
4133 crate::common::RW,
4134 >::from_register(self, 0)
4135 }
4136
4137 #[doc = "SCI clock (SCICLK) Switching Ready state flag"]
4138 #[inline(always)]
4139 pub fn scicksrdy(
4140 self,
4141 ) -> crate::common::RegisterField<
4142 7,
4143 0x1,
4144 1,
4145 0,
4146 scickcr::Scicksrdy,
4147 scickcr::Scicksrdy,
4148 Scickcr_SPEC,
4149 crate::common::R,
4150 > {
4151 crate::common::RegisterField::<
4152 7,
4153 0x1,
4154 1,
4155 0,
4156 scickcr::Scicksrdy,
4157 scickcr::Scicksrdy,
4158 Scickcr_SPEC,
4159 crate::common::R,
4160 >::from_register(self, 0)
4161 }
4162}
4163impl ::core::default::Default for Scickcr {
4164 #[inline(always)]
4165 fn default() -> Scickcr {
4166 <crate::RegValueT<Scickcr_SPEC> as RegisterValue<_>>::new(1)
4167 }
4168}
4169pub mod scickcr {
4170
4171 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4172 pub struct Scicksel_SPEC;
4173 pub type Scicksel = crate::EnumBitfieldStruct<u8, Scicksel_SPEC>;
4174 impl Scicksel {
4175 #[doc = "HOCO"]
4176 pub const _0000: Self = Self::new(0);
4177
4178 #[doc = "MOCO (Value after reset)"]
4179 pub const _0001: Self = Self::new(1);
4180
4181 #[doc = "LOCO"]
4182 pub const _0010: Self = Self::new(2);
4183
4184 #[doc = "Main clock oscillator"]
4185 pub const _0011: Self = Self::new(3);
4186
4187 #[doc = "Sub-clock oscillator"]
4188 pub const _0100: Self = Self::new(4);
4189
4190 #[doc = "PLL1P"]
4191 pub const _0101: Self = Self::new(5);
4192
4193 #[doc = "PLL2P"]
4194 pub const _0110: Self = Self::new(6);
4195
4196 #[doc = "PLL1Q"]
4197 pub const _0111: Self = Self::new(7);
4198
4199 #[doc = "PLL1R"]
4200 pub const _1000: Self = Self::new(8);
4201
4202 #[doc = "PLL2Q"]
4203 pub const _1001: Self = Self::new(9);
4204
4205 #[doc = "PLL2R"]
4206 pub const _1010: Self = Self::new(10);
4207
4208 #[doc = "Setting prohibited."]
4209 pub const OTHERS: Self = Self::new(0);
4210 }
4211 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4212 pub struct Scicksreq_SPEC;
4213 pub type Scicksreq = crate::EnumBitfieldStruct<u8, Scicksreq_SPEC>;
4214 impl Scicksreq {
4215 #[doc = "No request"]
4216 pub const _0: Self = Self::new(0);
4217
4218 #[doc = "Request switching"]
4219 pub const _1: Self = Self::new(1);
4220 }
4221 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4222 pub struct Scicksrdy_SPEC;
4223 pub type Scicksrdy = crate::EnumBitfieldStruct<u8, Scicksrdy_SPEC>;
4224 impl Scicksrdy {
4225 #[doc = "Impossible to Switch"]
4226 pub const _0: Self = Self::new(0);
4227
4228 #[doc = "Possible to Switch"]
4229 pub const _1: Self = Self::new(1);
4230 }
4231}
4232#[doc(hidden)]
4233#[derive(Copy, Clone, Eq, PartialEq)]
4234pub struct Spickdivcr_SPEC;
4235impl crate::sealed::RegSpec for Spickdivcr_SPEC {
4236 type DataType = u8;
4237}
4238
4239#[doc = "SPI clock Division control register"]
4240pub type Spickdivcr = crate::RegValueT<Spickdivcr_SPEC>;
4241
4242impl Spickdivcr {
4243 #[doc = "SPI clock (SPICLK) Division Select"]
4244 #[inline(always)]
4245 pub fn spickdiv(
4246 self,
4247 ) -> crate::common::RegisterField<
4248 0,
4249 0x7,
4250 1,
4251 0,
4252 spickdivcr::Spickdiv,
4253 spickdivcr::Spickdiv,
4254 Spickdivcr_SPEC,
4255 crate::common::RW,
4256 > {
4257 crate::common::RegisterField::<
4258 0,
4259 0x7,
4260 1,
4261 0,
4262 spickdivcr::Spickdiv,
4263 spickdivcr::Spickdiv,
4264 Spickdivcr_SPEC,
4265 crate::common::RW,
4266 >::from_register(self, 0)
4267 }
4268}
4269impl ::core::default::Default for Spickdivcr {
4270 #[inline(always)]
4271 fn default() -> Spickdivcr {
4272 <crate::RegValueT<Spickdivcr_SPEC> as RegisterValue<_>>::new(0)
4273 }
4274}
4275pub mod spickdivcr {
4276
4277 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4278 pub struct Spickdiv_SPEC;
4279 pub type Spickdiv = crate::EnumBitfieldStruct<u8, Spickdiv_SPEC>;
4280 impl Spickdiv {
4281 #[doc = "1/1 (Value after reset)"]
4282 pub const _000: Self = Self::new(0);
4283
4284 #[doc = "1/2"]
4285 pub const _001: Self = Self::new(1);
4286
4287 #[doc = "1/4"]
4288 pub const _010: Self = Self::new(2);
4289
4290 #[doc = "1/6"]
4291 pub const _011: Self = Self::new(3);
4292
4293 #[doc = "1/8"]
4294 pub const _100: Self = Self::new(4);
4295
4296 #[doc = "1/3"]
4297 pub const _101: Self = Self::new(5);
4298
4299 #[doc = "1/5"]
4300 pub const _110: Self = Self::new(6);
4301
4302 #[doc = "Setting prohibited."]
4303 pub const OTHERS: Self = Self::new(0);
4304 }
4305}
4306#[doc(hidden)]
4307#[derive(Copy, Clone, Eq, PartialEq)]
4308pub struct Spickcr_SPEC;
4309impl crate::sealed::RegSpec for Spickcr_SPEC {
4310 type DataType = u8;
4311}
4312
4313#[doc = "SPI clock control register"]
4314pub type Spickcr = crate::RegValueT<Spickcr_SPEC>;
4315
4316impl Spickcr {
4317 #[doc = "SPI clock (SPICLK) Source Select"]
4318 #[inline(always)]
4319 pub fn spicksel(
4320 self,
4321 ) -> crate::common::RegisterField<
4322 0,
4323 0xf,
4324 1,
4325 0,
4326 spickcr::Spicksel,
4327 spickcr::Spicksel,
4328 Spickcr_SPEC,
4329 crate::common::RW,
4330 > {
4331 crate::common::RegisterField::<
4332 0,
4333 0xf,
4334 1,
4335 0,
4336 spickcr::Spicksel,
4337 spickcr::Spicksel,
4338 Spickcr_SPEC,
4339 crate::common::RW,
4340 >::from_register(self, 0)
4341 }
4342
4343 #[doc = "SPI clock (SPICLK) Switching Request"]
4344 #[inline(always)]
4345 pub fn spicksreq(
4346 self,
4347 ) -> crate::common::RegisterField<
4348 6,
4349 0x1,
4350 1,
4351 0,
4352 spickcr::Spicksreq,
4353 spickcr::Spicksreq,
4354 Spickcr_SPEC,
4355 crate::common::RW,
4356 > {
4357 crate::common::RegisterField::<
4358 6,
4359 0x1,
4360 1,
4361 0,
4362 spickcr::Spicksreq,
4363 spickcr::Spicksreq,
4364 Spickcr_SPEC,
4365 crate::common::RW,
4366 >::from_register(self, 0)
4367 }
4368
4369 #[doc = "SPI clock (SPICLK) Switching Ready state flag"]
4370 #[inline(always)]
4371 pub fn spicksrdy(
4372 self,
4373 ) -> crate::common::RegisterField<
4374 7,
4375 0x1,
4376 1,
4377 0,
4378 spickcr::Spicksrdy,
4379 spickcr::Spicksrdy,
4380 Spickcr_SPEC,
4381 crate::common::R,
4382 > {
4383 crate::common::RegisterField::<
4384 7,
4385 0x1,
4386 1,
4387 0,
4388 spickcr::Spicksrdy,
4389 spickcr::Spicksrdy,
4390 Spickcr_SPEC,
4391 crate::common::R,
4392 >::from_register(self, 0)
4393 }
4394}
4395impl ::core::default::Default for Spickcr {
4396 #[inline(always)]
4397 fn default() -> Spickcr {
4398 <crate::RegValueT<Spickcr_SPEC> as RegisterValue<_>>::new(0)
4399 }
4400}
4401pub mod spickcr {
4402
4403 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4404 pub struct Spicksel_SPEC;
4405 pub type Spicksel = crate::EnumBitfieldStruct<u8, Spicksel_SPEC>;
4406 impl Spicksel {
4407 #[doc = "HOCO"]
4408 pub const _0000: Self = Self::new(0);
4409
4410 #[doc = "MOCO (Value after reset)"]
4411 pub const _0001: Self = Self::new(1);
4412
4413 #[doc = "LOCO"]
4414 pub const _0010: Self = Self::new(2);
4415
4416 #[doc = "Main clock oscillator"]
4417 pub const _0011: Self = Self::new(3);
4418
4419 #[doc = "Sub-clock oscillator"]
4420 pub const _0100: Self = Self::new(4);
4421
4422 #[doc = "PLL1P"]
4423 pub const _0101: Self = Self::new(5);
4424
4425 #[doc = "PLL2P"]
4426 pub const _0110: Self = Self::new(6);
4427
4428 #[doc = "PLL1Q"]
4429 pub const _0111: Self = Self::new(7);
4430
4431 #[doc = "PLL1R"]
4432 pub const _1000: Self = Self::new(8);
4433
4434 #[doc = "PLL2Q"]
4435 pub const _1001: Self = Self::new(9);
4436
4437 #[doc = "PLL2R"]
4438 pub const _1010: Self = Self::new(10);
4439
4440 #[doc = "Setting prohibited."]
4441 pub const OTHERS: Self = Self::new(0);
4442 }
4443 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4444 pub struct Spicksreq_SPEC;
4445 pub type Spicksreq = crate::EnumBitfieldStruct<u8, Spicksreq_SPEC>;
4446 impl Spicksreq {
4447 #[doc = "No request"]
4448 pub const _0: Self = Self::new(0);
4449
4450 #[doc = "Request switching"]
4451 pub const _1: Self = Self::new(1);
4452 }
4453 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4454 pub struct Spicksrdy_SPEC;
4455 pub type Spicksrdy = crate::EnumBitfieldStruct<u8, Spicksrdy_SPEC>;
4456 impl Spicksrdy {
4457 #[doc = "Impossible to Switch"]
4458 pub const _0: Self = Self::new(0);
4459
4460 #[doc = "Possible to Switch"]
4461 pub const _1: Self = Self::new(1);
4462 }
4463}
4464#[doc(hidden)]
4465#[derive(Copy, Clone, Eq, PartialEq)]
4466pub struct Lcdckdivcr_SPEC;
4467impl crate::sealed::RegSpec for Lcdckdivcr_SPEC {
4468 type DataType = u8;
4469}
4470
4471#[doc = "LCD clock Division control register"]
4472pub type Lcdckdivcr = crate::RegValueT<Lcdckdivcr_SPEC>;
4473
4474impl Lcdckdivcr {
4475 #[doc = "LCD clock (LCDCLK) Division Select"]
4476 #[inline(always)]
4477 pub fn lcdckdiv(
4478 self,
4479 ) -> crate::common::RegisterField<
4480 0,
4481 0x7,
4482 1,
4483 0,
4484 lcdckdivcr::Lcdckdiv,
4485 lcdckdivcr::Lcdckdiv,
4486 Lcdckdivcr_SPEC,
4487 crate::common::RW,
4488 > {
4489 crate::common::RegisterField::<
4490 0,
4491 0x7,
4492 1,
4493 0,
4494 lcdckdivcr::Lcdckdiv,
4495 lcdckdivcr::Lcdckdiv,
4496 Lcdckdivcr_SPEC,
4497 crate::common::RW,
4498 >::from_register(self, 0)
4499 }
4500}
4501impl ::core::default::Default for Lcdckdivcr {
4502 #[inline(always)]
4503 fn default() -> Lcdckdivcr {
4504 <crate::RegValueT<Lcdckdivcr_SPEC> as RegisterValue<_>>::new(0)
4505 }
4506}
4507pub mod lcdckdivcr {
4508
4509 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4510 pub struct Lcdckdiv_SPEC;
4511 pub type Lcdckdiv = crate::EnumBitfieldStruct<u8, Lcdckdiv_SPEC>;
4512 impl Lcdckdiv {
4513 #[doc = "1/1"]
4514 pub const _000: Self = Self::new(0);
4515
4516 #[doc = "1/2"]
4517 pub const _001: Self = Self::new(1);
4518
4519 #[doc = "1/4"]
4520 pub const _010: Self = Self::new(2);
4521
4522 #[doc = "1/6"]
4523 pub const _011: Self = Self::new(3);
4524
4525 #[doc = "1/8"]
4526 pub const _100: Self = Self::new(4);
4527
4528 #[doc = "1/3"]
4529 pub const _101: Self = Self::new(5);
4530
4531 #[doc = "1/5"]
4532 pub const _110: Self = Self::new(6);
4533
4534 #[doc = "Setting prohibited."]
4535 pub const OTHERS: Self = Self::new(0);
4536 }
4537}
4538#[doc(hidden)]
4539#[derive(Copy, Clone, Eq, PartialEq)]
4540pub struct Lcdckcr_SPEC;
4541impl crate::sealed::RegSpec for Lcdckcr_SPEC {
4542 type DataType = u8;
4543}
4544
4545#[doc = "LCD clock control register"]
4546pub type Lcdckcr = crate::RegValueT<Lcdckcr_SPEC>;
4547
4548impl Lcdckcr {
4549 #[doc = "LCD clock (LCDCLK) Source Select"]
4550 #[inline(always)]
4551 pub fn lcdcksel(
4552 self,
4553 ) -> crate::common::RegisterField<
4554 0,
4555 0xf,
4556 1,
4557 0,
4558 lcdckcr::Lcdcksel,
4559 lcdckcr::Lcdcksel,
4560 Lcdckcr_SPEC,
4561 crate::common::RW,
4562 > {
4563 crate::common::RegisterField::<
4564 0,
4565 0xf,
4566 1,
4567 0,
4568 lcdckcr::Lcdcksel,
4569 lcdckcr::Lcdcksel,
4570 Lcdckcr_SPEC,
4571 crate::common::RW,
4572 >::from_register(self, 0)
4573 }
4574
4575 #[doc = "LCD clock (LCDCLK) Switching Request"]
4576 #[inline(always)]
4577 pub fn lcdcksreq(
4578 self,
4579 ) -> crate::common::RegisterField<
4580 6,
4581 0x1,
4582 1,
4583 0,
4584 lcdckcr::Lcdcksreq,
4585 lcdckcr::Lcdcksreq,
4586 Lcdckcr_SPEC,
4587 crate::common::RW,
4588 > {
4589 crate::common::RegisterField::<
4590 6,
4591 0x1,
4592 1,
4593 0,
4594 lcdckcr::Lcdcksreq,
4595 lcdckcr::Lcdcksreq,
4596 Lcdckcr_SPEC,
4597 crate::common::RW,
4598 >::from_register(self, 0)
4599 }
4600
4601 #[doc = "LCD clock (LCDCLK) Switching Ready state flag"]
4602 #[inline(always)]
4603 pub fn lcdcksrdy(
4604 self,
4605 ) -> crate::common::RegisterField<
4606 7,
4607 0x1,
4608 1,
4609 0,
4610 lcdckcr::Lcdcksrdy,
4611 lcdckcr::Lcdcksrdy,
4612 Lcdckcr_SPEC,
4613 crate::common::R,
4614 > {
4615 crate::common::RegisterField::<
4616 7,
4617 0x1,
4618 1,
4619 0,
4620 lcdckcr::Lcdcksrdy,
4621 lcdckcr::Lcdcksrdy,
4622 Lcdckcr_SPEC,
4623 crate::common::R,
4624 >::from_register(self, 0)
4625 }
4626}
4627impl ::core::default::Default for Lcdckcr {
4628 #[inline(always)]
4629 fn default() -> Lcdckcr {
4630 <crate::RegValueT<Lcdckcr_SPEC> as RegisterValue<_>>::new(1)
4631 }
4632}
4633pub mod lcdckcr {
4634
4635 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4636 pub struct Lcdcksel_SPEC;
4637 pub type Lcdcksel = crate::EnumBitfieldStruct<u8, Lcdcksel_SPEC>;
4638 impl Lcdcksel {
4639 #[doc = "MOCO (Value after reset)"]
4640 pub const _0001: Self = Self::new(1);
4641
4642 #[doc = "PLL1P"]
4643 pub const _0101: Self = Self::new(5);
4644
4645 #[doc = "PLL2P"]
4646 pub const _0110: Self = Self::new(6);
4647
4648 #[doc = "PLL1Q"]
4649 pub const _0111: Self = Self::new(7);
4650
4651 #[doc = "PLL1R"]
4652 pub const _1000: Self = Self::new(8);
4653
4654 #[doc = "PLL2Q"]
4655 pub const _1001: Self = Self::new(9);
4656
4657 #[doc = "PLL2R"]
4658 pub const _1010: Self = Self::new(10);
4659
4660 #[doc = "Setting prohibited."]
4661 pub const OTHERS: Self = Self::new(0);
4662 }
4663 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4664 pub struct Lcdcksreq_SPEC;
4665 pub type Lcdcksreq = crate::EnumBitfieldStruct<u8, Lcdcksreq_SPEC>;
4666 impl Lcdcksreq {
4667 #[doc = "No request"]
4668 pub const _0: Self = Self::new(0);
4669
4670 #[doc = "Request switching"]
4671 pub const _1: Self = Self::new(1);
4672 }
4673 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4674 pub struct Lcdcksrdy_SPEC;
4675 pub type Lcdcksrdy = crate::EnumBitfieldStruct<u8, Lcdcksrdy_SPEC>;
4676 impl Lcdcksrdy {
4677 #[doc = "Impossible to Switch"]
4678 pub const _0: Self = Self::new(0);
4679
4680 #[doc = "Possible to Switch"]
4681 pub const _1: Self = Self::new(1);
4682 }
4683}
4684#[doc(hidden)]
4685#[derive(Copy, Clone, Eq, PartialEq)]
4686pub struct Mocoutcr_SPEC;
4687impl crate::sealed::RegSpec for Mocoutcr_SPEC {
4688 type DataType = u8;
4689}
4690
4691#[doc = "MOCO User Trimming Control Register"]
4692pub type Mocoutcr = crate::RegValueT<Mocoutcr_SPEC>;
4693
4694impl Mocoutcr {
4695 #[doc = "MOCO User Trimming"]
4696 #[inline(always)]
4697 pub fn mocoutrm(
4698 self,
4699 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Mocoutcr_SPEC, crate::common::RW> {
4700 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Mocoutcr_SPEC,crate::common::RW>::from_register(self,0)
4701 }
4702}
4703impl ::core::default::Default for Mocoutcr {
4704 #[inline(always)]
4705 fn default() -> Mocoutcr {
4706 <crate::RegValueT<Mocoutcr_SPEC> as RegisterValue<_>>::new(0)
4707 }
4708}
4709
4710#[doc(hidden)]
4711#[derive(Copy, Clone, Eq, PartialEq)]
4712pub struct Hocoutcr_SPEC;
4713impl crate::sealed::RegSpec for Hocoutcr_SPEC {
4714 type DataType = u8;
4715}
4716
4717#[doc = "HOCO User Trimming Control Register"]
4718pub type Hocoutcr = crate::RegValueT<Hocoutcr_SPEC>;
4719
4720impl Hocoutcr {
4721 #[doc = "HOCO User Trimming"]
4722 #[inline(always)]
4723 pub fn hocoutrm(
4724 self,
4725 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Hocoutcr_SPEC, crate::common::RW> {
4726 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Hocoutcr_SPEC,crate::common::RW>::from_register(self,0)
4727 }
4728}
4729impl ::core::default::Default for Hocoutcr {
4730 #[inline(always)]
4731 fn default() -> Hocoutcr {
4732 <crate::RegValueT<Hocoutcr_SPEC> as RegisterValue<_>>::new(0)
4733 }
4734}
4735
4736#[doc(hidden)]
4737#[derive(Copy, Clone, Eq, PartialEq)]
4738pub struct Usbckdivcr_SPEC;
4739impl crate::sealed::RegSpec for Usbckdivcr_SPEC {
4740 type DataType = u8;
4741}
4742
4743#[doc = "USB Clock Division Control Register"]
4744pub type Usbckdivcr = crate::RegValueT<Usbckdivcr_SPEC>;
4745
4746impl Usbckdivcr {
4747 #[doc = "USB Clock (USBCLK) Division Select"]
4748 #[inline(always)]
4749 pub fn usbckdiv(
4750 self,
4751 ) -> crate::common::RegisterField<
4752 0,
4753 0x7,
4754 1,
4755 0,
4756 usbckdivcr::Usbckdiv,
4757 usbckdivcr::Usbckdiv,
4758 Usbckdivcr_SPEC,
4759 crate::common::RW,
4760 > {
4761 crate::common::RegisterField::<
4762 0,
4763 0x7,
4764 1,
4765 0,
4766 usbckdivcr::Usbckdiv,
4767 usbckdivcr::Usbckdiv,
4768 Usbckdivcr_SPEC,
4769 crate::common::RW,
4770 >::from_register(self, 0)
4771 }
4772}
4773impl ::core::default::Default for Usbckdivcr {
4774 #[inline(always)]
4775 fn default() -> Usbckdivcr {
4776 <crate::RegValueT<Usbckdivcr_SPEC> as RegisterValue<_>>::new(0)
4777 }
4778}
4779pub mod usbckdivcr {
4780
4781 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4782 pub struct Usbckdiv_SPEC;
4783 pub type Usbckdiv = crate::EnumBitfieldStruct<u8, Usbckdiv_SPEC>;
4784 impl Usbckdiv {
4785 #[doc = "1/1"]
4786 pub const _000: Self = Self::new(0);
4787
4788 #[doc = "1/2"]
4789 pub const _001: Self = Self::new(1);
4790
4791 #[doc = "1/4"]
4792 pub const _010: Self = Self::new(2);
4793
4794 #[doc = "1/6"]
4795 pub const _011: Self = Self::new(3);
4796
4797 #[doc = "1/8"]
4798 pub const _100: Self = Self::new(4);
4799
4800 #[doc = "1/3"]
4801 pub const _101: Self = Self::new(5);
4802
4803 #[doc = "1/5"]
4804 pub const _110: Self = Self::new(6);
4805
4806 #[doc = "Setting prohibited."]
4807 pub const OTHERS: Self = Self::new(0);
4808 }
4809}
4810#[doc(hidden)]
4811#[derive(Copy, Clone, Eq, PartialEq)]
4812pub struct Octackdivcr_SPEC;
4813impl crate::sealed::RegSpec for Octackdivcr_SPEC {
4814 type DataType = u8;
4815}
4816
4817#[doc = "Octal-SPI Clock Division Control Register"]
4818pub type Octackdivcr = crate::RegValueT<Octackdivcr_SPEC>;
4819
4820impl Octackdivcr {
4821 #[doc = "Octal-SPI Clock (OCTACLK) Division Select"]
4822 #[inline(always)]
4823 pub fn octackdiv(
4824 self,
4825 ) -> crate::common::RegisterField<
4826 0,
4827 0x7,
4828 1,
4829 0,
4830 octackdivcr::Octackdiv,
4831 octackdivcr::Octackdiv,
4832 Octackdivcr_SPEC,
4833 crate::common::RW,
4834 > {
4835 crate::common::RegisterField::<
4836 0,
4837 0x7,
4838 1,
4839 0,
4840 octackdivcr::Octackdiv,
4841 octackdivcr::Octackdiv,
4842 Octackdivcr_SPEC,
4843 crate::common::RW,
4844 >::from_register(self, 0)
4845 }
4846}
4847impl ::core::default::Default for Octackdivcr {
4848 #[inline(always)]
4849 fn default() -> Octackdivcr {
4850 <crate::RegValueT<Octackdivcr_SPEC> as RegisterValue<_>>::new(0)
4851 }
4852}
4853pub mod octackdivcr {
4854
4855 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4856 pub struct Octackdiv_SPEC;
4857 pub type Octackdiv = crate::EnumBitfieldStruct<u8, Octackdiv_SPEC>;
4858 impl Octackdiv {
4859 #[doc = "1/1 (Value after reset)"]
4860 pub const _000: Self = Self::new(0);
4861
4862 #[doc = "1/2"]
4863 pub const _001: Self = Self::new(1);
4864
4865 #[doc = "1/4"]
4866 pub const _010: Self = Self::new(2);
4867
4868 #[doc = "1/6"]
4869 pub const _011: Self = Self::new(3);
4870
4871 #[doc = "1/8"]
4872 pub const _100: Self = Self::new(4);
4873
4874 #[doc = "1/3"]
4875 pub const _101: Self = Self::new(5);
4876
4877 #[doc = "1/5"]
4878 pub const _110: Self = Self::new(6);
4879
4880 #[doc = "Setting prohibited."]
4881 pub const OTHERS: Self = Self::new(0);
4882 }
4883}
4884#[doc(hidden)]
4885#[derive(Copy, Clone, Eq, PartialEq)]
4886pub struct Canfdckdivcr_SPEC;
4887impl crate::sealed::RegSpec for Canfdckdivcr_SPEC {
4888 type DataType = u8;
4889}
4890
4891#[doc = "CANFD Core Clock Division Control Register"]
4892pub type Canfdckdivcr = crate::RegValueT<Canfdckdivcr_SPEC>;
4893
4894impl Canfdckdivcr {
4895 #[doc = "CANFD core clock (CANFDCLK) Division Select"]
4896 #[inline(always)]
4897 pub fn canfdckdiv(
4898 self,
4899 ) -> crate::common::RegisterField<
4900 0,
4901 0x7,
4902 1,
4903 0,
4904 canfdckdivcr::Canfdckdiv,
4905 canfdckdivcr::Canfdckdiv,
4906 Canfdckdivcr_SPEC,
4907 crate::common::RW,
4908 > {
4909 crate::common::RegisterField::<
4910 0,
4911 0x7,
4912 1,
4913 0,
4914 canfdckdivcr::Canfdckdiv,
4915 canfdckdivcr::Canfdckdiv,
4916 Canfdckdivcr_SPEC,
4917 crate::common::RW,
4918 >::from_register(self, 0)
4919 }
4920}
4921impl ::core::default::Default for Canfdckdivcr {
4922 #[inline(always)]
4923 fn default() -> Canfdckdivcr {
4924 <crate::RegValueT<Canfdckdivcr_SPEC> as RegisterValue<_>>::new(0)
4925 }
4926}
4927pub mod canfdckdivcr {
4928
4929 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4930 pub struct Canfdckdiv_SPEC;
4931 pub type Canfdckdiv = crate::EnumBitfieldStruct<u8, Canfdckdiv_SPEC>;
4932 impl Canfdckdiv {
4933 #[doc = "1/1 (Value after reset)"]
4934 pub const _000: Self = Self::new(0);
4935
4936 #[doc = "1/2"]
4937 pub const _001: Self = Self::new(1);
4938
4939 #[doc = "1/4"]
4940 pub const _010: Self = Self::new(2);
4941
4942 #[doc = "1/6"]
4943 pub const _011: Self = Self::new(3);
4944
4945 #[doc = "1/8"]
4946 pub const _100: Self = Self::new(4);
4947
4948 #[doc = "1/3"]
4949 pub const _101: Self = Self::new(5);
4950
4951 #[doc = "1/5"]
4952 pub const _110: Self = Self::new(6);
4953
4954 #[doc = "Setting prohibited"]
4955 pub const OTHERS: Self = Self::new(0);
4956 }
4957}
4958#[doc(hidden)]
4959#[derive(Copy, Clone, Eq, PartialEq)]
4960pub struct Usbckcr_SPEC;
4961impl crate::sealed::RegSpec for Usbckcr_SPEC {
4962 type DataType = u8;
4963}
4964
4965#[doc = "USB Clock Control Register"]
4966pub type Usbckcr = crate::RegValueT<Usbckcr_SPEC>;
4967
4968impl Usbckcr {
4969 #[doc = "USB Clock (USBCLK) Source Select"]
4970 #[inline(always)]
4971 pub fn usbcksel(
4972 self,
4973 ) -> crate::common::RegisterField<
4974 0,
4975 0xf,
4976 1,
4977 0,
4978 usbckcr::Usbcksel,
4979 usbckcr::Usbcksel,
4980 Usbckcr_SPEC,
4981 crate::common::RW,
4982 > {
4983 crate::common::RegisterField::<
4984 0,
4985 0xf,
4986 1,
4987 0,
4988 usbckcr::Usbcksel,
4989 usbckcr::Usbcksel,
4990 Usbckcr_SPEC,
4991 crate::common::RW,
4992 >::from_register(self, 0)
4993 }
4994
4995 #[doc = "USB Clock (USBCLK) Switching Request"]
4996 #[inline(always)]
4997 pub fn usbcksreq(
4998 self,
4999 ) -> crate::common::RegisterField<
5000 6,
5001 0x1,
5002 1,
5003 0,
5004 usbckcr::Usbcksreq,
5005 usbckcr::Usbcksreq,
5006 Usbckcr_SPEC,
5007 crate::common::RW,
5008 > {
5009 crate::common::RegisterField::<
5010 6,
5011 0x1,
5012 1,
5013 0,
5014 usbckcr::Usbcksreq,
5015 usbckcr::Usbcksreq,
5016 Usbckcr_SPEC,
5017 crate::common::RW,
5018 >::from_register(self, 0)
5019 }
5020
5021 #[doc = "USB Clock (USBCLK) Switching Ready state flag"]
5022 #[inline(always)]
5023 pub fn usbcksrdy(
5024 self,
5025 ) -> crate::common::RegisterField<
5026 7,
5027 0x1,
5028 1,
5029 0,
5030 usbckcr::Usbcksrdy,
5031 usbckcr::Usbcksrdy,
5032 Usbckcr_SPEC,
5033 crate::common::R,
5034 > {
5035 crate::common::RegisterField::<
5036 7,
5037 0x1,
5038 1,
5039 0,
5040 usbckcr::Usbcksrdy,
5041 usbckcr::Usbcksrdy,
5042 Usbckcr_SPEC,
5043 crate::common::R,
5044 >::from_register(self, 0)
5045 }
5046}
5047impl ::core::default::Default for Usbckcr {
5048 #[inline(always)]
5049 fn default() -> Usbckcr {
5050 <crate::RegValueT<Usbckcr_SPEC> as RegisterValue<_>>::new(1)
5051 }
5052}
5053pub mod usbckcr {
5054
5055 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5056 pub struct Usbcksel_SPEC;
5057 pub type Usbcksel = crate::EnumBitfieldStruct<u8, Usbcksel_SPEC>;
5058 impl Usbcksel {
5059 #[doc = "HOCO"]
5060 pub const _0000: Self = Self::new(0);
5061
5062 #[doc = "MOCO (Value after reset)"]
5063 pub const _0001: Self = Self::new(1);
5064
5065 #[doc = "Main clock oscillator"]
5066 pub const _0011: Self = Self::new(3);
5067
5068 #[doc = "PLL1P"]
5069 pub const _0101: Self = Self::new(5);
5070
5071 #[doc = "PLL2P"]
5072 pub const _0110: Self = Self::new(6);
5073
5074 #[doc = "PLL1Q"]
5075 pub const _0111: Self = Self::new(7);
5076
5077 #[doc = "PLL1R"]
5078 pub const _1000: Self = Self::new(8);
5079
5080 #[doc = "PLL2Q"]
5081 pub const _1001: Self = Self::new(9);
5082
5083 #[doc = "PLL2R"]
5084 pub const _1010: Self = Self::new(10);
5085
5086 #[doc = "Setting prohibited."]
5087 pub const OTHERS: Self = Self::new(0);
5088 }
5089 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5090 pub struct Usbcksreq_SPEC;
5091 pub type Usbcksreq = crate::EnumBitfieldStruct<u8, Usbcksreq_SPEC>;
5092 impl Usbcksreq {
5093 #[doc = "No request"]
5094 pub const _0: Self = Self::new(0);
5095
5096 #[doc = "Request switching."]
5097 pub const _1: Self = Self::new(1);
5098 }
5099 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5100 pub struct Usbcksrdy_SPEC;
5101 pub type Usbcksrdy = crate::EnumBitfieldStruct<u8, Usbcksrdy_SPEC>;
5102 impl Usbcksrdy {
5103 #[doc = "Impossible to Switch"]
5104 pub const _0: Self = Self::new(0);
5105
5106 #[doc = "Possible to Switch"]
5107 pub const _1: Self = Self::new(1);
5108 }
5109}
5110#[doc(hidden)]
5111#[derive(Copy, Clone, Eq, PartialEq)]
5112pub struct Octackcr_SPEC;
5113impl crate::sealed::RegSpec for Octackcr_SPEC {
5114 type DataType = u8;
5115}
5116
5117#[doc = "Octal-SPI Clock Control Register"]
5118pub type Octackcr = crate::RegValueT<Octackcr_SPEC>;
5119
5120impl Octackcr {
5121 #[doc = "Octal-SPI Clock (OCTACLK) Source Select"]
5122 #[inline(always)]
5123 pub fn octacksel(
5124 self,
5125 ) -> crate::common::RegisterField<
5126 0,
5127 0xf,
5128 1,
5129 0,
5130 octackcr::Octacksel,
5131 octackcr::Octacksel,
5132 Octackcr_SPEC,
5133 crate::common::RW,
5134 > {
5135 crate::common::RegisterField::<
5136 0,
5137 0xf,
5138 1,
5139 0,
5140 octackcr::Octacksel,
5141 octackcr::Octacksel,
5142 Octackcr_SPEC,
5143 crate::common::RW,
5144 >::from_register(self, 0)
5145 }
5146
5147 #[doc = "Octal-SPI Clock (OCTACLK) Switching Request"]
5148 #[inline(always)]
5149 pub fn octacksreq(
5150 self,
5151 ) -> crate::common::RegisterField<
5152 6,
5153 0x1,
5154 1,
5155 0,
5156 octackcr::Octacksreq,
5157 octackcr::Octacksreq,
5158 Octackcr_SPEC,
5159 crate::common::RW,
5160 > {
5161 crate::common::RegisterField::<
5162 6,
5163 0x1,
5164 1,
5165 0,
5166 octackcr::Octacksreq,
5167 octackcr::Octacksreq,
5168 Octackcr_SPEC,
5169 crate::common::RW,
5170 >::from_register(self, 0)
5171 }
5172
5173 #[doc = "Octal-SPI Clock (OCTACLK) Switching Ready state flag"]
5174 #[inline(always)]
5175 pub fn octacksrdy(
5176 self,
5177 ) -> crate::common::RegisterField<
5178 7,
5179 0x1,
5180 1,
5181 0,
5182 octackcr::Octacksrdy,
5183 octackcr::Octacksrdy,
5184 Octackcr_SPEC,
5185 crate::common::R,
5186 > {
5187 crate::common::RegisterField::<
5188 7,
5189 0x1,
5190 1,
5191 0,
5192 octackcr::Octacksrdy,
5193 octackcr::Octacksrdy,
5194 Octackcr_SPEC,
5195 crate::common::R,
5196 >::from_register(self, 0)
5197 }
5198}
5199impl ::core::default::Default for Octackcr {
5200 #[inline(always)]
5201 fn default() -> Octackcr {
5202 <crate::RegValueT<Octackcr_SPEC> as RegisterValue<_>>::new(1)
5203 }
5204}
5205pub mod octackcr {
5206
5207 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5208 pub struct Octacksel_SPEC;
5209 pub type Octacksel = crate::EnumBitfieldStruct<u8, Octacksel_SPEC>;
5210 impl Octacksel {
5211 #[doc = "HOCO"]
5212 pub const _0000: Self = Self::new(0);
5213
5214 #[doc = "MOCO (Value after reset)"]
5215 pub const _0001: Self = Self::new(1);
5216
5217 #[doc = "LOCO"]
5218 pub const _0010: Self = Self::new(2);
5219
5220 #[doc = "Main clock oscillator"]
5221 pub const _0011: Self = Self::new(3);
5222
5223 #[doc = "Sub-clock oscillator"]
5224 pub const _0100: Self = Self::new(4);
5225
5226 #[doc = "PLL1P"]
5227 pub const _0101: Self = Self::new(5);
5228
5229 #[doc = "PLL2P"]
5230 pub const _0110: Self = Self::new(6);
5231
5232 #[doc = "PLL1Q"]
5233 pub const _0111: Self = Self::new(7);
5234
5235 #[doc = "PLL1R"]
5236 pub const _1000: Self = Self::new(8);
5237
5238 #[doc = "PLL2Q"]
5239 pub const _1001: Self = Self::new(9);
5240
5241 #[doc = "PLL2R"]
5242 pub const _1010: Self = Self::new(10);
5243
5244 #[doc = "Setting prohibited."]
5245 pub const OTHERS: Self = Self::new(0);
5246 }
5247 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5248 pub struct Octacksreq_SPEC;
5249 pub type Octacksreq = crate::EnumBitfieldStruct<u8, Octacksreq_SPEC>;
5250 impl Octacksreq {
5251 #[doc = "No request"]
5252 pub const _0: Self = Self::new(0);
5253
5254 #[doc = "Request switching."]
5255 pub const _1: Self = Self::new(1);
5256 }
5257 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5258 pub struct Octacksrdy_SPEC;
5259 pub type Octacksrdy = crate::EnumBitfieldStruct<u8, Octacksrdy_SPEC>;
5260 impl Octacksrdy {
5261 #[doc = "Impossible to Switch"]
5262 pub const _0: Self = Self::new(0);
5263
5264 #[doc = "Possible to Switch"]
5265 pub const _1: Self = Self::new(1);
5266 }
5267}
5268#[doc(hidden)]
5269#[derive(Copy, Clone, Eq, PartialEq)]
5270pub struct Canfdckcr_SPEC;
5271impl crate::sealed::RegSpec for Canfdckcr_SPEC {
5272 type DataType = u8;
5273}
5274
5275#[doc = "CANFD Core Clock Control Register"]
5276pub type Canfdckcr = crate::RegValueT<Canfdckcr_SPEC>;
5277
5278impl Canfdckcr {
5279 #[doc = "CANFD Core Clock (CANFDCLK) Source Select"]
5280 #[inline(always)]
5281 pub fn canfdcksel(
5282 self,
5283 ) -> crate::common::RegisterField<
5284 0,
5285 0xf,
5286 1,
5287 0,
5288 canfdckcr::Canfdcksel,
5289 canfdckcr::Canfdcksel,
5290 Canfdckcr_SPEC,
5291 crate::common::RW,
5292 > {
5293 crate::common::RegisterField::<
5294 0,
5295 0xf,
5296 1,
5297 0,
5298 canfdckcr::Canfdcksel,
5299 canfdckcr::Canfdcksel,
5300 Canfdckcr_SPEC,
5301 crate::common::RW,
5302 >::from_register(self, 0)
5303 }
5304
5305 #[doc = "CANFD Core Clock (CANFDCLK) Switching Request"]
5306 #[inline(always)]
5307 pub fn canfdcksreq(
5308 self,
5309 ) -> crate::common::RegisterField<
5310 6,
5311 0x1,
5312 1,
5313 0,
5314 canfdckcr::Canfdcksreq,
5315 canfdckcr::Canfdcksreq,
5316 Canfdckcr_SPEC,
5317 crate::common::RW,
5318 > {
5319 crate::common::RegisterField::<
5320 6,
5321 0x1,
5322 1,
5323 0,
5324 canfdckcr::Canfdcksreq,
5325 canfdckcr::Canfdcksreq,
5326 Canfdckcr_SPEC,
5327 crate::common::RW,
5328 >::from_register(self, 0)
5329 }
5330}
5331impl ::core::default::Default for Canfdckcr {
5332 #[inline(always)]
5333 fn default() -> Canfdckcr {
5334 <crate::RegValueT<Canfdckcr_SPEC> as RegisterValue<_>>::new(1)
5335 }
5336}
5337pub mod canfdckcr {
5338
5339 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5340 pub struct Canfdcksel_SPEC;
5341 pub type Canfdcksel = crate::EnumBitfieldStruct<u8, Canfdcksel_SPEC>;
5342 impl Canfdcksel {
5343 #[doc = "HOCO"]
5344 pub const _0000: Self = Self::new(0);
5345
5346 #[doc = "MOCO (Value after reset)"]
5347 pub const _0001: Self = Self::new(1);
5348
5349 #[doc = "LOCO"]
5350 pub const _0010: Self = Self::new(2);
5351
5352 #[doc = "Main clock oscillator"]
5353 pub const _0011: Self = Self::new(3);
5354
5355 #[doc = "Sub-clock oscillator"]
5356 pub const _0100: Self = Self::new(4);
5357
5358 #[doc = "PLL1P"]
5359 pub const _0101: Self = Self::new(5);
5360
5361 #[doc = "PLL2P"]
5362 pub const _0110: Self = Self::new(6);
5363
5364 #[doc = "PLL1Q"]
5365 pub const _0111: Self = Self::new(7);
5366
5367 #[doc = "PLL1R"]
5368 pub const _1000: Self = Self::new(8);
5369
5370 #[doc = "PLL2Q"]
5371 pub const _1001: Self = Self::new(9);
5372
5373 #[doc = "PLL2R"]
5374 pub const _1010: Self = Self::new(10);
5375
5376 #[doc = "Setting prohibited."]
5377 pub const OTHERS: Self = Self::new(0);
5378 }
5379 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5380 pub struct Canfdcksreq_SPEC;
5381 pub type Canfdcksreq = crate::EnumBitfieldStruct<u8, Canfdcksreq_SPEC>;
5382 impl Canfdcksreq {
5383 #[doc = "No request"]
5384 pub const _0: Self = Self::new(0);
5385
5386 #[doc = "Request switching"]
5387 pub const _1: Self = Self::new(1);
5388 }
5389}
5390#[doc(hidden)]
5391#[derive(Copy, Clone, Eq, PartialEq)]
5392pub struct Moscscr_SPEC;
5393impl crate::sealed::RegSpec for Moscscr_SPEC {
5394 type DataType = u8;
5395}
5396
5397#[doc = "Main Clock Oscillator Standby Control Register"]
5398pub type Moscscr = crate::RegValueT<Moscscr_SPEC>;
5399
5400impl Moscscr {
5401 #[doc = "Main Clock Oscillator Standby Oscillation Keep select"]
5402 #[inline(always)]
5403 pub fn moscsokp(
5404 self,
5405 ) -> crate::common::RegisterField<
5406 0,
5407 0x1,
5408 1,
5409 0,
5410 moscscr::Moscsokp,
5411 moscscr::Moscsokp,
5412 Moscscr_SPEC,
5413 crate::common::RW,
5414 > {
5415 crate::common::RegisterField::<
5416 0,
5417 0x1,
5418 1,
5419 0,
5420 moscscr::Moscsokp,
5421 moscscr::Moscsokp,
5422 Moscscr_SPEC,
5423 crate::common::RW,
5424 >::from_register(self, 0)
5425 }
5426}
5427impl ::core::default::Default for Moscscr {
5428 #[inline(always)]
5429 fn default() -> Moscscr {
5430 <crate::RegValueT<Moscscr_SPEC> as RegisterValue<_>>::new(0)
5431 }
5432}
5433pub mod moscscr {
5434
5435 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5436 pub struct Moscsokp_SPEC;
5437 pub type Moscsokp = crate::EnumBitfieldStruct<u8, Moscsokp_SPEC>;
5438 impl Moscsokp {
5439 #[doc = "Disable"]
5440 pub const _0: Self = Self::new(0);
5441
5442 #[doc = "Enable"]
5443 pub const _1: Self = Self::new(1);
5444 }
5445}
5446#[doc(hidden)]
5447#[derive(Copy, Clone, Eq, PartialEq)]
5448pub struct Hocoscr_SPEC;
5449impl crate::sealed::RegSpec for Hocoscr_SPEC {
5450 type DataType = u8;
5451}
5452
5453#[doc = "High-Speed On-Chip Oscillator Standby Control Register"]
5454pub type Hocoscr = crate::RegValueT<Hocoscr_SPEC>;
5455
5456impl Hocoscr {
5457 #[doc = "HOCO Standby Oscillation Keep select."]
5458 #[inline(always)]
5459 pub fn hocosokp(
5460 self,
5461 ) -> crate::common::RegisterField<
5462 0,
5463 0x1,
5464 1,
5465 0,
5466 hocoscr::Hocosokp,
5467 hocoscr::Hocosokp,
5468 Hocoscr_SPEC,
5469 crate::common::RW,
5470 > {
5471 crate::common::RegisterField::<
5472 0,
5473 0x1,
5474 1,
5475 0,
5476 hocoscr::Hocosokp,
5477 hocoscr::Hocosokp,
5478 Hocoscr_SPEC,
5479 crate::common::RW,
5480 >::from_register(self, 0)
5481 }
5482}
5483impl ::core::default::Default for Hocoscr {
5484 #[inline(always)]
5485 fn default() -> Hocoscr {
5486 <crate::RegValueT<Hocoscr_SPEC> as RegisterValue<_>>::new(0)
5487 }
5488}
5489pub mod hocoscr {
5490
5491 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5492 pub struct Hocosokp_SPEC;
5493 pub type Hocosokp = crate::EnumBitfieldStruct<u8, Hocosokp_SPEC>;
5494 impl Hocosokp {
5495 #[doc = "Disable"]
5496 pub const _0: Self = Self::new(0);
5497
5498 #[doc = "Enable"]
5499 pub const _1: Self = Self::new(1);
5500 }
5501}
5502#[doc(hidden)]
5503#[derive(Copy, Clone, Eq, PartialEq)]
5504pub struct Opccr_SPEC;
5505impl crate::sealed::RegSpec for Opccr_SPEC {
5506 type DataType = u8;
5507}
5508
5509#[doc = "Operating Power Control Register"]
5510pub type Opccr = crate::RegValueT<Opccr_SPEC>;
5511
5512impl Opccr {
5513 #[doc = "Operating Power Control Mode Select"]
5514 #[inline(always)]
5515 pub fn opcm(
5516 self,
5517 ) -> crate::common::RegisterField<
5518 0,
5519 0x3,
5520 1,
5521 0,
5522 opccr::Opcm,
5523 opccr::Opcm,
5524 Opccr_SPEC,
5525 crate::common::RW,
5526 > {
5527 crate::common::RegisterField::<
5528 0,
5529 0x3,
5530 1,
5531 0,
5532 opccr::Opcm,
5533 opccr::Opcm,
5534 Opccr_SPEC,
5535 crate::common::RW,
5536 >::from_register(self, 0)
5537 }
5538
5539 #[doc = "Operating Power Control Mode Transition Status Flag"]
5540 #[inline(always)]
5541 pub fn opcmtsf(
5542 self,
5543 ) -> crate::common::RegisterField<
5544 4,
5545 0x1,
5546 1,
5547 0,
5548 opccr::Opcmtsf,
5549 opccr::Opcmtsf,
5550 Opccr_SPEC,
5551 crate::common::R,
5552 > {
5553 crate::common::RegisterField::<
5554 4,
5555 0x1,
5556 1,
5557 0,
5558 opccr::Opcmtsf,
5559 opccr::Opcmtsf,
5560 Opccr_SPEC,
5561 crate::common::R,
5562 >::from_register(self, 0)
5563 }
5564}
5565impl ::core::default::Default for Opccr {
5566 #[inline(always)]
5567 fn default() -> Opccr {
5568 <crate::RegValueT<Opccr_SPEC> as RegisterValue<_>>::new(0)
5569 }
5570}
5571pub mod opccr {
5572
5573 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5574 pub struct Opcm_SPEC;
5575 pub type Opcm = crate::EnumBitfieldStruct<u8, Opcm_SPEC>;
5576 impl Opcm {
5577 #[doc = "High-speed mode"]
5578 pub const _00: Self = Self::new(0);
5579
5580 #[doc = "Setting prohibited"]
5581 pub const _01: Self = Self::new(1);
5582
5583 #[doc = "Setting prohibited"]
5584 pub const _10: Self = Self::new(2);
5585
5586 #[doc = "Low-speed mode"]
5587 pub const _11: Self = Self::new(3);
5588 }
5589 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5590 pub struct Opcmtsf_SPEC;
5591 pub type Opcmtsf = crate::EnumBitfieldStruct<u8, Opcmtsf_SPEC>;
5592 impl Opcmtsf {
5593 #[doc = "Transition completed"]
5594 pub const _0: Self = Self::new(0);
5595
5596 #[doc = "During transition"]
5597 pub const _1: Self = Self::new(1);
5598 }
5599}
5600#[doc(hidden)]
5601#[derive(Copy, Clone, Eq, PartialEq)]
5602pub struct Moscwtcr_SPEC;
5603impl crate::sealed::RegSpec for Moscwtcr_SPEC {
5604 type DataType = u8;
5605}
5606
5607#[doc = "Main Clock Oscillator Wait Control Register"]
5608pub type Moscwtcr = crate::RegValueT<Moscwtcr_SPEC>;
5609
5610impl Moscwtcr {
5611 #[doc = "Main Clock Oscillator Wait Time Setting"]
5612 #[inline(always)]
5613 pub fn msts(
5614 self,
5615 ) -> crate::common::RegisterField<
5616 0,
5617 0xf,
5618 1,
5619 0,
5620 moscwtcr::Msts,
5621 moscwtcr::Msts,
5622 Moscwtcr_SPEC,
5623 crate::common::RW,
5624 > {
5625 crate::common::RegisterField::<
5626 0,
5627 0xf,
5628 1,
5629 0,
5630 moscwtcr::Msts,
5631 moscwtcr::Msts,
5632 Moscwtcr_SPEC,
5633 crate::common::RW,
5634 >::from_register(self, 0)
5635 }
5636}
5637impl ::core::default::Default for Moscwtcr {
5638 #[inline(always)]
5639 fn default() -> Moscwtcr {
5640 <crate::RegValueT<Moscwtcr_SPEC> as RegisterValue<_>>::new(5)
5641 }
5642}
5643pub mod moscwtcr {
5644
5645 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5646 pub struct Msts_SPEC;
5647 pub type Msts = crate::EnumBitfieldStruct<u8, Msts_SPEC>;
5648 impl Msts {
5649 #[doc = "Wait time = 3 cycles (11.4 us)"]
5650 pub const _0_X_0: Self = Self::new(0);
5651
5652 #[doc = "Wait time = 35 cycles (133.5 us)"]
5653 pub const _0_X_1: Self = Self::new(1);
5654
5655 #[doc = "Wait time = 67 cycles (255.6 us)"]
5656 pub const _0_X_2: Self = Self::new(2);
5657
5658 #[doc = "Wait time = 131 cycles (499.7 us)"]
5659 pub const _0_X_3: Self = Self::new(3);
5660
5661 #[doc = "Wait time = 259 cycles (988.0 us)"]
5662 pub const _0_X_4: Self = Self::new(4);
5663
5664 #[doc = "Wait time = 547 cycles (2086.6 us)"]
5665 pub const _0_X_5: Self = Self::new(5);
5666
5667 #[doc = "Wait time = 1059 cycles (4039.8 us)"]
5668 pub const _0_X_6: Self = Self::new(6);
5669
5670 #[doc = "Wait time = 2147 cycles (8190.2 us)"]
5671 pub const _0_X_7: Self = Self::new(7);
5672
5673 #[doc = "Wait time = 4291 cycles (16368.9 us)"]
5674 pub const _0_X_8: Self = Self::new(8);
5675
5676 #[doc = "Wait time = 8163 cycles (31139.4 us)"]
5677 pub const _0_X_9: Self = Self::new(9);
5678
5679 #[doc = "Setting prohibited"]
5680 pub const OTHERS: Self = Self::new(0);
5681 }
5682}
5683#[doc(hidden)]
5684#[derive(Copy, Clone, Eq, PartialEq)]
5685pub struct Rstsr1_SPEC;
5686impl crate::sealed::RegSpec for Rstsr1_SPEC {
5687 type DataType = u32;
5688}
5689
5690#[doc = "Reset Status Register 1"]
5691pub type Rstsr1 = crate::RegValueT<Rstsr1_SPEC>;
5692
5693impl Rstsr1 {
5694 #[doc = "Independent Watchdog Timer Reset Detect Flag"]
5695 #[inline(always)]
5696 pub fn iwdtrf(
5697 self,
5698 ) -> crate::common::RegisterField<
5699 0,
5700 0x1,
5701 1,
5702 0,
5703 rstsr1::Iwdtrf,
5704 rstsr1::Iwdtrf,
5705 Rstsr1_SPEC,
5706 crate::common::RW,
5707 > {
5708 crate::common::RegisterField::<
5709 0,
5710 0x1,
5711 1,
5712 0,
5713 rstsr1::Iwdtrf,
5714 rstsr1::Iwdtrf,
5715 Rstsr1_SPEC,
5716 crate::common::RW,
5717 >::from_register(self, 0)
5718 }
5719
5720 #[doc = "Watchdog Timer Reset Detect Flag"]
5721 #[inline(always)]
5722 pub fn wdt0rf(
5723 self,
5724 ) -> crate::common::RegisterField<
5725 1,
5726 0x1,
5727 1,
5728 0,
5729 rstsr1::Wdt0Rf,
5730 rstsr1::Wdt0Rf,
5731 Rstsr1_SPEC,
5732 crate::common::RW,
5733 > {
5734 crate::common::RegisterField::<
5735 1,
5736 0x1,
5737 1,
5738 0,
5739 rstsr1::Wdt0Rf,
5740 rstsr1::Wdt0Rf,
5741 Rstsr1_SPEC,
5742 crate::common::RW,
5743 >::from_register(self, 0)
5744 }
5745
5746 #[doc = "Software Reset Detect Flag"]
5747 #[inline(always)]
5748 pub fn swrf(
5749 self,
5750 ) -> crate::common::RegisterField<
5751 2,
5752 0x1,
5753 1,
5754 0,
5755 rstsr1::Swrf,
5756 rstsr1::Swrf,
5757 Rstsr1_SPEC,
5758 crate::common::RW,
5759 > {
5760 crate::common::RegisterField::<
5761 2,
5762 0x1,
5763 1,
5764 0,
5765 rstsr1::Swrf,
5766 rstsr1::Swrf,
5767 Rstsr1_SPEC,
5768 crate::common::RW,
5769 >::from_register(self, 0)
5770 }
5771
5772 #[doc = "CPU Lockup Reset Detect Flag"]
5773 #[inline(always)]
5774 pub fn clu0rf(
5775 self,
5776 ) -> crate::common::RegisterField<
5777 4,
5778 0x1,
5779 1,
5780 0,
5781 rstsr1::Clu0Rf,
5782 rstsr1::Clu0Rf,
5783 Rstsr1_SPEC,
5784 crate::common::RW,
5785 > {
5786 crate::common::RegisterField::<
5787 4,
5788 0x1,
5789 1,
5790 0,
5791 rstsr1::Clu0Rf,
5792 rstsr1::Clu0Rf,
5793 Rstsr1_SPEC,
5794 crate::common::RW,
5795 >::from_register(self, 0)
5796 }
5797
5798 #[doc = "Bus Error Reset Detect Flag"]
5799 #[inline(always)]
5800 pub fn busrf(
5801 self,
5802 ) -> crate::common::RegisterField<
5803 10,
5804 0x1,
5805 1,
5806 0,
5807 rstsr1::Busrf,
5808 rstsr1::Busrf,
5809 Rstsr1_SPEC,
5810 crate::common::RW,
5811 > {
5812 crate::common::RegisterField::<
5813 10,
5814 0x1,
5815 1,
5816 0,
5817 rstsr1::Busrf,
5818 rstsr1::Busrf,
5819 Rstsr1_SPEC,
5820 crate::common::RW,
5821 >::from_register(self, 0)
5822 }
5823
5824 #[doc = "Common Memory Error Reset Detect Flag"]
5825 #[inline(always)]
5826 pub fn cmrf(
5827 self,
5828 ) -> crate::common::RegisterField<
5829 14,
5830 0x1,
5831 1,
5832 0,
5833 rstsr1::Cmrf,
5834 rstsr1::Cmrf,
5835 Rstsr1_SPEC,
5836 crate::common::RW,
5837 > {
5838 crate::common::RegisterField::<
5839 14,
5840 0x1,
5841 1,
5842 0,
5843 rstsr1::Cmrf,
5844 rstsr1::Cmrf,
5845 Rstsr1_SPEC,
5846 crate::common::RW,
5847 >::from_register(self, 0)
5848 }
5849}
5850impl ::core::default::Default for Rstsr1 {
5851 #[inline(always)]
5852 fn default() -> Rstsr1 {
5853 <crate::RegValueT<Rstsr1_SPEC> as RegisterValue<_>>::new(0)
5854 }
5855}
5856pub mod rstsr1 {
5857
5858 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5859 pub struct Iwdtrf_SPEC;
5860 pub type Iwdtrf = crate::EnumBitfieldStruct<u8, Iwdtrf_SPEC>;
5861 impl Iwdtrf {
5862 #[doc = "Independent watchdog timer reset not detected"]
5863 pub const _0: Self = Self::new(0);
5864
5865 #[doc = "Independent watchdog timer reset detected"]
5866 pub const _1: Self = Self::new(1);
5867 }
5868 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5869 pub struct Wdt0Rf_SPEC;
5870 pub type Wdt0Rf = crate::EnumBitfieldStruct<u8, Wdt0Rf_SPEC>;
5871 impl Wdt0Rf {
5872 #[doc = "Watchdog timer reset not detected"]
5873 pub const _0: Self = Self::new(0);
5874
5875 #[doc = "Watchdog timer reset detected"]
5876 pub const _1: Self = Self::new(1);
5877 }
5878 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5879 pub struct Swrf_SPEC;
5880 pub type Swrf = crate::EnumBitfieldStruct<u8, Swrf_SPEC>;
5881 impl Swrf {
5882 #[doc = "Software reset not detected"]
5883 pub const _0: Self = Self::new(0);
5884
5885 #[doc = "Software reset detected"]
5886 pub const _1: Self = Self::new(1);
5887 }
5888 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5889 pub struct Clu0Rf_SPEC;
5890 pub type Clu0Rf = crate::EnumBitfieldStruct<u8, Clu0Rf_SPEC>;
5891 impl Clu0Rf {
5892 #[doc = "CPU Lockup reset not detected"]
5893 pub const _0: Self = Self::new(0);
5894
5895 #[doc = "CPU Lockup reset detected"]
5896 pub const _1: Self = Self::new(1);
5897 }
5898 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5899 pub struct Busrf_SPEC;
5900 pub type Busrf = crate::EnumBitfieldStruct<u8, Busrf_SPEC>;
5901 impl Busrf {
5902 #[doc = "Bus error reset not detected"]
5903 pub const _0: Self = Self::new(0);
5904
5905 #[doc = "Bus error reset detected"]
5906 pub const _1: Self = Self::new(1);
5907 }
5908 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5909 pub struct Cmrf_SPEC;
5910 pub type Cmrf = crate::EnumBitfieldStruct<u8, Cmrf_SPEC>;
5911 impl Cmrf {
5912 #[doc = "Common memory error reset not detected"]
5913 pub const _0: Self = Self::new(0);
5914
5915 #[doc = "Common memory error reset detected"]
5916 pub const _1: Self = Self::new(1);
5917 }
5918}
5919#[doc(hidden)]
5920#[derive(Copy, Clone, Eq, PartialEq)]
5921pub struct Syraccr_SPEC;
5922impl crate::sealed::RegSpec for Syraccr_SPEC {
5923 type DataType = u8;
5924}
5925
5926#[doc = "System Register Access Control Register"]
5927pub type Syraccr = crate::RegValueT<Syraccr_SPEC>;
5928
5929impl Syraccr {
5930 #[doc = "Access Ready monitor"]
5931 #[inline(always)]
5932 pub fn busy(
5933 self,
5934 ) -> crate::common::RegisterField<
5935 0,
5936 0x1,
5937 1,
5938 0,
5939 syraccr::Busy,
5940 syraccr::Busy,
5941 Syraccr_SPEC,
5942 crate::common::R,
5943 > {
5944 crate::common::RegisterField::<
5945 0,
5946 0x1,
5947 1,
5948 0,
5949 syraccr::Busy,
5950 syraccr::Busy,
5951 Syraccr_SPEC,
5952 crate::common::R,
5953 >::from_register(self, 0)
5954 }
5955}
5956impl ::core::default::Default for Syraccr {
5957 #[inline(always)]
5958 fn default() -> Syraccr {
5959 <crate::RegValueT<Syraccr_SPEC> as RegisterValue<_>>::new(0)
5960 }
5961}
5962pub mod syraccr {
5963
5964 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5965 pub struct Busy_SPEC;
5966 pub type Busy = crate::EnumBitfieldStruct<u8, Busy_SPEC>;
5967 impl Busy {
5968 #[doc = "Ready to read/write access"]
5969 pub const _0: Self = Self::new(0);
5970
5971 #[doc = "Writing in progress"]
5972 pub const _1: Self = Self::new(1);
5973 }
5974}
5975#[doc(hidden)]
5976#[derive(Copy, Clone, Eq, PartialEq)]
5977pub struct Pvdcr1_SPEC;
5978impl crate::sealed::RegSpec for Pvdcr1_SPEC {
5979 type DataType = u8;
5980}
5981
5982#[doc = "Voltage Monitor %s Circuit Control Register 1"]
5983pub type Pvdcr1 = crate::RegValueT<Pvdcr1_SPEC>;
5984
5985impl Pvdcr1 {
5986 #[doc = "Voltage Monitor m Interrupt Generation Condition Select"]
5987 #[inline(always)]
5988 pub fn idtsel(
5989 self,
5990 ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Pvdcr1_SPEC, crate::common::RW> {
5991 crate::common::RegisterField::<0,0x3,1,0,u8,u8,Pvdcr1_SPEC,crate::common::RW>::from_register(self,0)
5992 }
5993
5994 #[doc = "Voltage Monitor m Interrupt Type Select"]
5995 #[inline(always)]
5996 pub fn irqsel(
5997 self,
5998 ) -> crate::common::RegisterField<
5999 2,
6000 0x1,
6001 1,
6002 0,
6003 pvdcr1::Irqsel,
6004 pvdcr1::Irqsel,
6005 Pvdcr1_SPEC,
6006 crate::common::RW,
6007 > {
6008 crate::common::RegisterField::<
6009 2,
6010 0x1,
6011 1,
6012 0,
6013 pvdcr1::Irqsel,
6014 pvdcr1::Irqsel,
6015 Pvdcr1_SPEC,
6016 crate::common::RW,
6017 >::from_register(self, 0)
6018 }
6019}
6020impl ::core::default::Default for Pvdcr1 {
6021 #[inline(always)]
6022 fn default() -> Pvdcr1 {
6023 <crate::RegValueT<Pvdcr1_SPEC> as RegisterValue<_>>::new(1)
6024 }
6025}
6026pub mod pvdcr1 {
6027
6028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6029 pub struct Irqsel_SPEC;
6030 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
6031 impl Irqsel {
6032 #[doc = "Non-maskable interrupt"]
6033 pub const _0: Self = Self::new(0);
6034
6035 #[doc = "Maskable interrupt"]
6036 pub const _1: Self = Self::new(1);
6037 }
6038}
6039#[doc(hidden)]
6040#[derive(Copy, Clone, Eq, PartialEq)]
6041pub struct Pvdsr_SPEC;
6042impl crate::sealed::RegSpec for Pvdsr_SPEC {
6043 type DataType = u8;
6044}
6045
6046#[doc = "Voltage Monitor %s Circuit Status Register"]
6047pub type Pvdsr = crate::RegValueT<Pvdsr_SPEC>;
6048
6049impl Pvdsr {
6050 #[doc = "Voltage Monitor m Voltage Change Detection Flag"]
6051 #[inline(always)]
6052 pub fn det(self) -> crate::common::RegisterFieldBool<0, 1, 0, Pvdsr_SPEC, crate::common::RW> {
6053 crate::common::RegisterFieldBool::<0, 1, 0, Pvdsr_SPEC, crate::common::RW>::from_register(
6054 self, 0,
6055 )
6056 }
6057
6058 #[doc = "Voltage Monitor 1 Signal Monitor Flag"]
6059 #[inline(always)]
6060 pub fn mon(self) -> crate::common::RegisterFieldBool<1, 1, 0, Pvdsr_SPEC, crate::common::RW> {
6061 crate::common::RegisterFieldBool::<1, 1, 0, Pvdsr_SPEC, crate::common::RW>::from_register(
6062 self, 0,
6063 )
6064 }
6065}
6066impl ::core::default::Default for Pvdsr {
6067 #[inline(always)]
6068 fn default() -> Pvdsr {
6069 <crate::RegValueT<Pvdsr_SPEC> as RegisterValue<_>>::new(2)
6070 }
6071}
6072
6073#[doc(hidden)]
6074#[derive(Copy, Clone, Eq, PartialEq)]
6075pub struct Pdctrgd_SPEC;
6076impl crate::sealed::RegSpec for Pdctrgd_SPEC {
6077 type DataType = u8;
6078}
6079
6080#[doc = "Graphics Power Domain Control Register"]
6081pub type Pdctrgd = crate::RegValueT<Pdctrgd_SPEC>;
6082
6083impl Pdctrgd {
6084 #[doc = "Power control enable"]
6085 #[inline(always)]
6086 pub fn pdde(
6087 self,
6088 ) -> crate::common::RegisterField<
6089 0,
6090 0x1,
6091 1,
6092 0,
6093 pdctrgd::Pdde,
6094 pdctrgd::Pdde,
6095 Pdctrgd_SPEC,
6096 crate::common::RW,
6097 > {
6098 crate::common::RegisterField::<
6099 0,
6100 0x1,
6101 1,
6102 0,
6103 pdctrgd::Pdde,
6104 pdctrgd::Pdde,
6105 Pdctrgd_SPEC,
6106 crate::common::RW,
6107 >::from_register(self, 0)
6108 }
6109
6110 #[doc = "Power control status flag"]
6111 #[inline(always)]
6112 pub fn pdcsf(
6113 self,
6114 ) -> crate::common::RegisterField<
6115 6,
6116 0x1,
6117 1,
6118 0,
6119 pdctrgd::Pdcsf,
6120 pdctrgd::Pdcsf,
6121 Pdctrgd_SPEC,
6122 crate::common::R,
6123 > {
6124 crate::common::RegisterField::<
6125 6,
6126 0x1,
6127 1,
6128 0,
6129 pdctrgd::Pdcsf,
6130 pdctrgd::Pdcsf,
6131 Pdctrgd_SPEC,
6132 crate::common::R,
6133 >::from_register(self, 0)
6134 }
6135
6136 #[doc = "Power gating status flag"]
6137 #[inline(always)]
6138 pub fn pdpgsf(
6139 self,
6140 ) -> crate::common::RegisterField<
6141 7,
6142 0x1,
6143 1,
6144 0,
6145 pdctrgd::Pdpgsf,
6146 pdctrgd::Pdpgsf,
6147 Pdctrgd_SPEC,
6148 crate::common::R,
6149 > {
6150 crate::common::RegisterField::<
6151 7,
6152 0x1,
6153 1,
6154 0,
6155 pdctrgd::Pdpgsf,
6156 pdctrgd::Pdpgsf,
6157 Pdctrgd_SPEC,
6158 crate::common::R,
6159 >::from_register(self, 0)
6160 }
6161}
6162impl ::core::default::Default for Pdctrgd {
6163 #[inline(always)]
6164 fn default() -> Pdctrgd {
6165 <crate::RegValueT<Pdctrgd_SPEC> as RegisterValue<_>>::new(129)
6166 }
6167}
6168pub mod pdctrgd {
6169
6170 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6171 pub struct Pdde_SPEC;
6172 pub type Pdde = crate::EnumBitfieldStruct<u8, Pdde_SPEC>;
6173 impl Pdde {
6174 #[doc = "Power on the target domain"]
6175 pub const _0: Self = Self::new(0);
6176
6177 #[doc = "Power off the target domain"]
6178 pub const _1: Self = Self::new(1);
6179 }
6180 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6181 pub struct Pdcsf_SPEC;
6182 pub type Pdcsf = crate::EnumBitfieldStruct<u8, Pdcsf_SPEC>;
6183 impl Pdcsf {
6184 #[doc = "Power gating control is not executed (idle)"]
6185 pub const _0: Self = Self::new(0);
6186
6187 #[doc = "Power gating control is in progress"]
6188 pub const _1: Self = Self::new(1);
6189 }
6190 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6191 pub struct Pdpgsf_SPEC;
6192 pub type Pdpgsf = crate::EnumBitfieldStruct<u8, Pdpgsf_SPEC>;
6193 impl Pdpgsf {
6194 #[doc = "Target domain is power on (not gating)"]
6195 pub const _0: Self = Self::new(0);
6196
6197 #[doc = "Target domain is power off (during Gating)"]
6198 pub const _1: Self = Self::new(1);
6199 }
6200}
6201#[doc(hidden)]
6202#[derive(Copy, Clone, Eq, PartialEq)]
6203pub struct Pdramscr0_SPEC;
6204impl crate::sealed::RegSpec for Pdramscr0_SPEC {
6205 type DataType = u16;
6206}
6207
6208#[doc = "SRAM Power Domain Standby Control Register 0"]
6209pub type Pdramscr0 = crate::RegValueT<Pdramscr0_SPEC>;
6210
6211impl Pdramscr0 {
6212 #[doc = "Unnecessary Circuit Retention"]
6213 #[inline(always)]
6214 pub fn rkeep0(
6215 self,
6216 ) -> crate::common::RegisterField<
6217 0,
6218 0x1,
6219 1,
6220 0,
6221 pdramscr0::Rkeep0,
6222 pdramscr0::Rkeep0,
6223 Pdramscr0_SPEC,
6224 crate::common::RW,
6225 > {
6226 crate::common::RegisterField::<
6227 0,
6228 0x1,
6229 1,
6230 0,
6231 pdramscr0::Rkeep0,
6232 pdramscr0::Rkeep0,
6233 Pdramscr0_SPEC,
6234 crate::common::RW,
6235 >::from_register(self, 0)
6236 }
6237
6238 #[doc = "Unnecessary Circuit Retention"]
6239 #[inline(always)]
6240 pub fn rkeep1(
6241 self,
6242 ) -> crate::common::RegisterField<
6243 1,
6244 0x1,
6245 1,
6246 0,
6247 pdramscr0::Rkeep1,
6248 pdramscr0::Rkeep1,
6249 Pdramscr0_SPEC,
6250 crate::common::RW,
6251 > {
6252 crate::common::RegisterField::<
6253 1,
6254 0x1,
6255 1,
6256 0,
6257 pdramscr0::Rkeep1,
6258 pdramscr0::Rkeep1,
6259 Pdramscr0_SPEC,
6260 crate::common::RW,
6261 >::from_register(self, 0)
6262 }
6263
6264 #[doc = "RAM Retention"]
6265 #[inline(always)]
6266 pub fn rkeep2(
6267 self,
6268 ) -> crate::common::RegisterField<
6269 2,
6270 0x1,
6271 1,
6272 0,
6273 pdramscr0::Rkeep2,
6274 pdramscr0::Rkeep2,
6275 Pdramscr0_SPEC,
6276 crate::common::RW,
6277 > {
6278 crate::common::RegisterField::<
6279 2,
6280 0x1,
6281 1,
6282 0,
6283 pdramscr0::Rkeep2,
6284 pdramscr0::Rkeep2,
6285 Pdramscr0_SPEC,
6286 crate::common::RW,
6287 >::from_register(self, 0)
6288 }
6289
6290 #[doc = "RAM Retention"]
6291 #[inline(always)]
6292 pub fn rkeep3(
6293 self,
6294 ) -> crate::common::RegisterField<
6295 3,
6296 0x1,
6297 1,
6298 0,
6299 pdramscr0::Rkeep3,
6300 pdramscr0::Rkeep3,
6301 Pdramscr0_SPEC,
6302 crate::common::RW,
6303 > {
6304 crate::common::RegisterField::<
6305 3,
6306 0x1,
6307 1,
6308 0,
6309 pdramscr0::Rkeep3,
6310 pdramscr0::Rkeep3,
6311 Pdramscr0_SPEC,
6312 crate::common::RW,
6313 >::from_register(self, 0)
6314 }
6315
6316 #[doc = "RAM Retention"]
6317 #[inline(always)]
6318 pub fn rkeep4(
6319 self,
6320 ) -> crate::common::RegisterField<
6321 4,
6322 0x1,
6323 1,
6324 0,
6325 pdramscr0::Rkeep4,
6326 pdramscr0::Rkeep4,
6327 Pdramscr0_SPEC,
6328 crate::common::RW,
6329 > {
6330 crate::common::RegisterField::<
6331 4,
6332 0x1,
6333 1,
6334 0,
6335 pdramscr0::Rkeep4,
6336 pdramscr0::Rkeep4,
6337 Pdramscr0_SPEC,
6338 crate::common::RW,
6339 >::from_register(self, 0)
6340 }
6341
6342 #[doc = "RAM Retention"]
6343 #[inline(always)]
6344 pub fn rkeep5(
6345 self,
6346 ) -> crate::common::RegisterField<
6347 5,
6348 0x1,
6349 1,
6350 0,
6351 pdramscr0::Rkeep5,
6352 pdramscr0::Rkeep5,
6353 Pdramscr0_SPEC,
6354 crate::common::RW,
6355 > {
6356 crate::common::RegisterField::<
6357 5,
6358 0x1,
6359 1,
6360 0,
6361 pdramscr0::Rkeep5,
6362 pdramscr0::Rkeep5,
6363 Pdramscr0_SPEC,
6364 crate::common::RW,
6365 >::from_register(self, 0)
6366 }
6367
6368 #[doc = "RAM Retention"]
6369 #[inline(always)]
6370 pub fn rkeep6(
6371 self,
6372 ) -> crate::common::RegisterField<
6373 6,
6374 0x1,
6375 1,
6376 0,
6377 pdramscr0::Rkeep6,
6378 pdramscr0::Rkeep6,
6379 Pdramscr0_SPEC,
6380 crate::common::RW,
6381 > {
6382 crate::common::RegisterField::<
6383 6,
6384 0x1,
6385 1,
6386 0,
6387 pdramscr0::Rkeep6,
6388 pdramscr0::Rkeep6,
6389 Pdramscr0_SPEC,
6390 crate::common::RW,
6391 >::from_register(self, 0)
6392 }
6393}
6394impl ::core::default::Default for Pdramscr0 {
6395 #[inline(always)]
6396 fn default() -> Pdramscr0 {
6397 <crate::RegValueT<Pdramscr0_SPEC> as RegisterValue<_>>::new(32767)
6398 }
6399}
6400pub mod pdramscr0 {
6401
6402 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6403 pub struct Rkeep0_SPEC;
6404 pub type Rkeep0 = crate::EnumBitfieldStruct<u8, Rkeep0_SPEC>;
6405 impl Rkeep0 {
6406 #[doc = "When entering the Software Standby mode, the contents of unnecessary circuit are not kept."]
6407 pub const _0: Self = Self::new(0);
6408
6409 #[doc = "When entering the Software Standby mode, the contents of unnecessary circuit are kept."]
6410 pub const _1: Self = Self::new(1);
6411 }
6412 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6413 pub struct Rkeep1_SPEC;
6414 pub type Rkeep1 = crate::EnumBitfieldStruct<u8, Rkeep1_SPEC>;
6415 impl Rkeep1 {
6416 #[doc = "When entering the Software Standby mode, the contents of unnecessary circuit are not kept."]
6417 pub const _0: Self = Self::new(0);
6418
6419 #[doc = "When entering the Software Standby mode, the contents of unnecessary circuit are kept."]
6420 pub const _1: Self = Self::new(1);
6421 }
6422 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6423 pub struct Rkeep2_SPEC;
6424 pub type Rkeep2 = crate::EnumBitfieldStruct<u8, Rkeep2_SPEC>;
6425 impl Rkeep2 {
6426 #[doc = "When entering the Software Standby mode, the contents of the target RAM are not kept."]
6427 pub const _0: Self = Self::new(0);
6428
6429 #[doc = "When entering the Software Standby mode, the contents of the target RAM are kept."]
6430 pub const _1: Self = Self::new(1);
6431 }
6432 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6433 pub struct Rkeep3_SPEC;
6434 pub type Rkeep3 = crate::EnumBitfieldStruct<u8, Rkeep3_SPEC>;
6435 impl Rkeep3 {
6436 #[doc = "When entering the Software Standby mode, the contents of the target RAM are not kept."]
6437 pub const _0: Self = Self::new(0);
6438
6439 #[doc = "When entering the Software Standby mode, the contents of the target RAM are kept."]
6440 pub const _1: Self = Self::new(1);
6441 }
6442 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6443 pub struct Rkeep4_SPEC;
6444 pub type Rkeep4 = crate::EnumBitfieldStruct<u8, Rkeep4_SPEC>;
6445 impl Rkeep4 {
6446 #[doc = "When entering the Software Standby mode, the contents of the target RAM are not kept."]
6447 pub const _0: Self = Self::new(0);
6448
6449 #[doc = "When entering the Software Standby mode, the contents of the target RAM are kept."]
6450 pub const _1: Self = Self::new(1);
6451 }
6452 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6453 pub struct Rkeep5_SPEC;
6454 pub type Rkeep5 = crate::EnumBitfieldStruct<u8, Rkeep5_SPEC>;
6455 impl Rkeep5 {
6456 #[doc = "When entering the Software Standby mode, the contents of the target RAM are not kept."]
6457 pub const _0: Self = Self::new(0);
6458
6459 #[doc = "When entering the Software Standby mode, the contents of the target RAM are kept."]
6460 pub const _1: Self = Self::new(1);
6461 }
6462 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6463 pub struct Rkeep6_SPEC;
6464 pub type Rkeep6 = crate::EnumBitfieldStruct<u8, Rkeep6_SPEC>;
6465 impl Rkeep6 {
6466 #[doc = "When entering the Software Standby mode, the contents of the target RAM are not kept."]
6467 pub const _0: Self = Self::new(0);
6468
6469 #[doc = "When entering the Software Standby mode, the contents of the target RAM are kept."]
6470 pub const _1: Self = Self::new(1);
6471 }
6472}
6473#[doc(hidden)]
6474#[derive(Copy, Clone, Eq, PartialEq)]
6475pub struct Pdramscr1_SPEC;
6476impl crate::sealed::RegSpec for Pdramscr1_SPEC {
6477 type DataType = u8;
6478}
6479
6480#[doc = "SRAM Power Domain Standby Control Register 1"]
6481pub type Pdramscr1 = crate::RegValueT<Pdramscr1_SPEC>;
6482
6483impl Pdramscr1 {
6484 #[doc = "RAM Retention"]
6485 #[inline(always)]
6486 pub fn rkeep0(
6487 self,
6488 ) -> crate::common::RegisterField<
6489 0,
6490 0x1,
6491 1,
6492 0,
6493 pdramscr1::Rkeep0,
6494 pdramscr1::Rkeep0,
6495 Pdramscr1_SPEC,
6496 crate::common::RW,
6497 > {
6498 crate::common::RegisterField::<
6499 0,
6500 0x1,
6501 1,
6502 0,
6503 pdramscr1::Rkeep0,
6504 pdramscr1::Rkeep0,
6505 Pdramscr1_SPEC,
6506 crate::common::RW,
6507 >::from_register(self, 0)
6508 }
6509}
6510impl ::core::default::Default for Pdramscr1 {
6511 #[inline(always)]
6512 fn default() -> Pdramscr1 {
6513 <crate::RegValueT<Pdramscr1_SPEC> as RegisterValue<_>>::new(3)
6514 }
6515}
6516pub mod pdramscr1 {
6517
6518 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6519 pub struct Rkeep0_SPEC;
6520 pub type Rkeep0 = crate::EnumBitfieldStruct<u8, Rkeep0_SPEC>;
6521 impl Rkeep0 {
6522 #[doc = "When entering the CPU Deep Sleep and Software Standby mode, the contents of the target RAM are not kept."]
6523 pub const _0: Self = Self::new(0);
6524
6525 #[doc = "When entering the CPU Deep Sleep and Software Standby mode, the contents of the target RAM are kept."]
6526 pub const _1: Self = Self::new(1);
6527 }
6528}
6529#[doc(hidden)]
6530#[derive(Copy, Clone, Eq, PartialEq)]
6531pub struct Vbrpabarns_SPEC;
6532impl crate::sealed::RegSpec for Vbrpabarns_SPEC {
6533 type DataType = u16;
6534}
6535
6536#[doc = "VBATT Backup Register Privilege Attribute Boundary Address Register for Non-secure Region"]
6537pub type Vbrpabarns = crate::RegValueT<Vbrpabarns_SPEC>;
6538
6539impl Vbrpabarns {
6540 #[doc = "Boundary address between privileged and unprivileged."]
6541 #[inline(always)]
6542 pub fn pabans(
6543 self,
6544 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Vbrpabarns_SPEC, crate::common::RW>
6545 {
6546 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Vbrpabarns_SPEC,crate::common::RW>::from_register(self,0)
6547 }
6548}
6549impl ::core::default::Default for Vbrpabarns {
6550 #[inline(always)]
6551 fn default() -> Vbrpabarns {
6552 <crate::RegValueT<Vbrpabarns_SPEC> as RegisterValue<_>>::new(0)
6553 }
6554}
6555
6556#[doc(hidden)]
6557#[derive(Copy, Clone, Eq, PartialEq)]
6558pub struct Cgfsar_SPEC;
6559impl crate::sealed::RegSpec for Cgfsar_SPEC {
6560 type DataType = u32;
6561}
6562
6563#[doc = "Clock Generation Function Security Attribute Register"]
6564pub type Cgfsar = crate::RegValueT<Cgfsar_SPEC>;
6565
6566impl Cgfsar {
6567 #[doc = "Non Secure Attribute bit 00"]
6568 #[inline(always)]
6569 pub fn nonsec00(
6570 self,
6571 ) -> crate::common::RegisterField<
6572 0,
6573 0x1,
6574 1,
6575 0,
6576 cgfsar::Nonsec00,
6577 cgfsar::Nonsec00,
6578 Cgfsar_SPEC,
6579 crate::common::RW,
6580 > {
6581 crate::common::RegisterField::<
6582 0,
6583 0x1,
6584 1,
6585 0,
6586 cgfsar::Nonsec00,
6587 cgfsar::Nonsec00,
6588 Cgfsar_SPEC,
6589 crate::common::RW,
6590 >::from_register(self, 0)
6591 }
6592
6593 #[doc = "Non Secure Attribute bit 02"]
6594 #[inline(always)]
6595 pub fn nonsec02(
6596 self,
6597 ) -> crate::common::RegisterField<
6598 2,
6599 0x1,
6600 1,
6601 0,
6602 cgfsar::Nonsec02,
6603 cgfsar::Nonsec02,
6604 Cgfsar_SPEC,
6605 crate::common::RW,
6606 > {
6607 crate::common::RegisterField::<
6608 2,
6609 0x1,
6610 1,
6611 0,
6612 cgfsar::Nonsec02,
6613 cgfsar::Nonsec02,
6614 Cgfsar_SPEC,
6615 crate::common::RW,
6616 >::from_register(self, 0)
6617 }
6618
6619 #[doc = "Non Secure Attribute bit 03"]
6620 #[inline(always)]
6621 pub fn nonsec03(
6622 self,
6623 ) -> crate::common::RegisterField<
6624 3,
6625 0x1,
6626 1,
6627 0,
6628 cgfsar::Nonsec03,
6629 cgfsar::Nonsec03,
6630 Cgfsar_SPEC,
6631 crate::common::RW,
6632 > {
6633 crate::common::RegisterField::<
6634 3,
6635 0x1,
6636 1,
6637 0,
6638 cgfsar::Nonsec03,
6639 cgfsar::Nonsec03,
6640 Cgfsar_SPEC,
6641 crate::common::RW,
6642 >::from_register(self, 0)
6643 }
6644
6645 #[doc = "Non Secure Attribute bit 04"]
6646 #[inline(always)]
6647 pub fn nonsec04(
6648 self,
6649 ) -> crate::common::RegisterField<
6650 4,
6651 0x1,
6652 1,
6653 0,
6654 cgfsar::Nonsec04,
6655 cgfsar::Nonsec04,
6656 Cgfsar_SPEC,
6657 crate::common::RW,
6658 > {
6659 crate::common::RegisterField::<
6660 4,
6661 0x1,
6662 1,
6663 0,
6664 cgfsar::Nonsec04,
6665 cgfsar::Nonsec04,
6666 Cgfsar_SPEC,
6667 crate::common::RW,
6668 >::from_register(self, 0)
6669 }
6670
6671 #[doc = "Non Secure Attribute bit 05"]
6672 #[inline(always)]
6673 pub fn nonsec05(
6674 self,
6675 ) -> crate::common::RegisterField<
6676 5,
6677 0x1,
6678 1,
6679 0,
6680 cgfsar::Nonsec05,
6681 cgfsar::Nonsec05,
6682 Cgfsar_SPEC,
6683 crate::common::RW,
6684 > {
6685 crate::common::RegisterField::<
6686 5,
6687 0x1,
6688 1,
6689 0,
6690 cgfsar::Nonsec05,
6691 cgfsar::Nonsec05,
6692 Cgfsar_SPEC,
6693 crate::common::RW,
6694 >::from_register(self, 0)
6695 }
6696
6697 #[doc = "Non Secure Attribute bit 06"]
6698 #[inline(always)]
6699 pub fn nonsec06(
6700 self,
6701 ) -> crate::common::RegisterField<
6702 6,
6703 0x1,
6704 1,
6705 0,
6706 cgfsar::Nonsec06,
6707 cgfsar::Nonsec06,
6708 Cgfsar_SPEC,
6709 crate::common::RW,
6710 > {
6711 crate::common::RegisterField::<
6712 6,
6713 0x1,
6714 1,
6715 0,
6716 cgfsar::Nonsec06,
6717 cgfsar::Nonsec06,
6718 Cgfsar_SPEC,
6719 crate::common::RW,
6720 >::from_register(self, 0)
6721 }
6722
6723 #[doc = "Non Secure Attribute bit 07"]
6724 #[inline(always)]
6725 pub fn nonsec07(
6726 self,
6727 ) -> crate::common::RegisterField<
6728 7,
6729 0x1,
6730 1,
6731 0,
6732 cgfsar::Nonsec07,
6733 cgfsar::Nonsec07,
6734 Cgfsar_SPEC,
6735 crate::common::RW,
6736 > {
6737 crate::common::RegisterField::<
6738 7,
6739 0x1,
6740 1,
6741 0,
6742 cgfsar::Nonsec07,
6743 cgfsar::Nonsec07,
6744 Cgfsar_SPEC,
6745 crate::common::RW,
6746 >::from_register(self, 0)
6747 }
6748
6749 #[doc = "Non Secure Attribute bit 08"]
6750 #[inline(always)]
6751 pub fn nonsec08(
6752 self,
6753 ) -> crate::common::RegisterField<
6754 8,
6755 0x1,
6756 1,
6757 0,
6758 cgfsar::Nonsec08,
6759 cgfsar::Nonsec08,
6760 Cgfsar_SPEC,
6761 crate::common::RW,
6762 > {
6763 crate::common::RegisterField::<
6764 8,
6765 0x1,
6766 1,
6767 0,
6768 cgfsar::Nonsec08,
6769 cgfsar::Nonsec08,
6770 Cgfsar_SPEC,
6771 crate::common::RW,
6772 >::from_register(self, 0)
6773 }
6774
6775 #[doc = "Non Secure Attribute bit 09"]
6776 #[inline(always)]
6777 pub fn nonsec09(
6778 self,
6779 ) -> crate::common::RegisterField<
6780 9,
6781 0x1,
6782 1,
6783 0,
6784 cgfsar::Nonsec09,
6785 cgfsar::Nonsec09,
6786 Cgfsar_SPEC,
6787 crate::common::RW,
6788 > {
6789 crate::common::RegisterField::<
6790 9,
6791 0x1,
6792 1,
6793 0,
6794 cgfsar::Nonsec09,
6795 cgfsar::Nonsec09,
6796 Cgfsar_SPEC,
6797 crate::common::RW,
6798 >::from_register(self, 0)
6799 }
6800
6801 #[doc = "Non Secure Attribute bit 11"]
6802 #[inline(always)]
6803 pub fn nonsec11(
6804 self,
6805 ) -> crate::common::RegisterField<
6806 11,
6807 0x1,
6808 1,
6809 0,
6810 cgfsar::Nonsec11,
6811 cgfsar::Nonsec11,
6812 Cgfsar_SPEC,
6813 crate::common::RW,
6814 > {
6815 crate::common::RegisterField::<
6816 11,
6817 0x1,
6818 1,
6819 0,
6820 cgfsar::Nonsec11,
6821 cgfsar::Nonsec11,
6822 Cgfsar_SPEC,
6823 crate::common::RW,
6824 >::from_register(self, 0)
6825 }
6826
6827 #[doc = "Non Secure Attribute bit 12"]
6828 #[inline(always)]
6829 pub fn nonsec12(
6830 self,
6831 ) -> crate::common::RegisterField<
6832 12,
6833 0x1,
6834 1,
6835 0,
6836 cgfsar::Nonsec12,
6837 cgfsar::Nonsec12,
6838 Cgfsar_SPEC,
6839 crate::common::RW,
6840 > {
6841 crate::common::RegisterField::<
6842 12,
6843 0x1,
6844 1,
6845 0,
6846 cgfsar::Nonsec12,
6847 cgfsar::Nonsec12,
6848 Cgfsar_SPEC,
6849 crate::common::RW,
6850 >::from_register(self, 0)
6851 }
6852
6853 #[doc = "Non Secure Attribute bit 13"]
6854 #[inline(always)]
6855 pub fn nonsec13(
6856 self,
6857 ) -> crate::common::RegisterField<
6858 13,
6859 0x1,
6860 1,
6861 0,
6862 cgfsar::Nonsec13,
6863 cgfsar::Nonsec13,
6864 Cgfsar_SPEC,
6865 crate::common::RW,
6866 > {
6867 crate::common::RegisterField::<
6868 13,
6869 0x1,
6870 1,
6871 0,
6872 cgfsar::Nonsec13,
6873 cgfsar::Nonsec13,
6874 Cgfsar_SPEC,
6875 crate::common::RW,
6876 >::from_register(self, 0)
6877 }
6878
6879 #[doc = "Non Secure Attribute bit 16"]
6880 #[inline(always)]
6881 pub fn nonsec16(
6882 self,
6883 ) -> crate::common::RegisterField<
6884 16,
6885 0x1,
6886 1,
6887 0,
6888 cgfsar::Nonsec16,
6889 cgfsar::Nonsec16,
6890 Cgfsar_SPEC,
6891 crate::common::RW,
6892 > {
6893 crate::common::RegisterField::<
6894 16,
6895 0x1,
6896 1,
6897 0,
6898 cgfsar::Nonsec16,
6899 cgfsar::Nonsec16,
6900 Cgfsar_SPEC,
6901 crate::common::RW,
6902 >::from_register(self, 0)
6903 }
6904
6905 #[doc = "Non Secure Attribute bit 17"]
6906 #[inline(always)]
6907 pub fn nonsec17(
6908 self,
6909 ) -> crate::common::RegisterField<
6910 17,
6911 0x1,
6912 1,
6913 0,
6914 cgfsar::Nonsec17,
6915 cgfsar::Nonsec17,
6916 Cgfsar_SPEC,
6917 crate::common::RW,
6918 > {
6919 crate::common::RegisterField::<
6920 17,
6921 0x1,
6922 1,
6923 0,
6924 cgfsar::Nonsec17,
6925 cgfsar::Nonsec17,
6926 Cgfsar_SPEC,
6927 crate::common::RW,
6928 >::from_register(self, 0)
6929 }
6930
6931 #[doc = "Non Secure Attribute bit 18"]
6932 #[inline(always)]
6933 pub fn nonsec18(
6934 self,
6935 ) -> crate::common::RegisterField<
6936 18,
6937 0x1,
6938 1,
6939 0,
6940 cgfsar::Nonsec18,
6941 cgfsar::Nonsec18,
6942 Cgfsar_SPEC,
6943 crate::common::RW,
6944 > {
6945 crate::common::RegisterField::<
6946 18,
6947 0x1,
6948 1,
6949 0,
6950 cgfsar::Nonsec18,
6951 cgfsar::Nonsec18,
6952 Cgfsar_SPEC,
6953 crate::common::RW,
6954 >::from_register(self, 0)
6955 }
6956
6957 #[doc = "Non Secure Attribute bit 21"]
6958 #[inline(always)]
6959 pub fn nonsec21(
6960 self,
6961 ) -> crate::common::RegisterField<
6962 21,
6963 0x1,
6964 1,
6965 0,
6966 cgfsar::Nonsec21,
6967 cgfsar::Nonsec21,
6968 Cgfsar_SPEC,
6969 crate::common::RW,
6970 > {
6971 crate::common::RegisterField::<
6972 21,
6973 0x1,
6974 1,
6975 0,
6976 cgfsar::Nonsec21,
6977 cgfsar::Nonsec21,
6978 Cgfsar_SPEC,
6979 crate::common::RW,
6980 >::from_register(self, 0)
6981 }
6982
6983 #[doc = "Non Secure Attribute bit 22"]
6984 #[inline(always)]
6985 pub fn nonsec22(
6986 self,
6987 ) -> crate::common::RegisterField<
6988 22,
6989 0x1,
6990 1,
6991 0,
6992 cgfsar::Nonsec22,
6993 cgfsar::Nonsec22,
6994 Cgfsar_SPEC,
6995 crate::common::RW,
6996 > {
6997 crate::common::RegisterField::<
6998 22,
6999 0x1,
7000 1,
7001 0,
7002 cgfsar::Nonsec22,
7003 cgfsar::Nonsec22,
7004 Cgfsar_SPEC,
7005 crate::common::RW,
7006 >::from_register(self, 0)
7007 }
7008
7009 #[doc = "Non Secure Attribute bit 26"]
7010 #[inline(always)]
7011 pub fn nonsec26(
7012 self,
7013 ) -> crate::common::RegisterField<
7014 26,
7015 0x1,
7016 1,
7017 0,
7018 cgfsar::Nonsec26,
7019 cgfsar::Nonsec26,
7020 Cgfsar_SPEC,
7021 crate::common::RW,
7022 > {
7023 crate::common::RegisterField::<
7024 26,
7025 0x1,
7026 1,
7027 0,
7028 cgfsar::Nonsec26,
7029 cgfsar::Nonsec26,
7030 Cgfsar_SPEC,
7031 crate::common::RW,
7032 >::from_register(self, 0)
7033 }
7034}
7035impl ::core::default::Default for Cgfsar {
7036 #[inline(always)]
7037 fn default() -> Cgfsar {
7038 <crate::RegValueT<Cgfsar_SPEC> as RegisterValue<_>>::new(0)
7039 }
7040}
7041pub mod cgfsar {
7042
7043 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7044 pub struct Nonsec00_SPEC;
7045 pub type Nonsec00 = crate::EnumBitfieldStruct<u8, Nonsec00_SPEC>;
7046 impl Nonsec00 {
7047 #[doc = "Secure"]
7048 pub const _0: Self = Self::new(0);
7049
7050 #[doc = "Non Secure"]
7051 pub const _1: Self = Self::new(1);
7052 }
7053 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7054 pub struct Nonsec02_SPEC;
7055 pub type Nonsec02 = crate::EnumBitfieldStruct<u8, Nonsec02_SPEC>;
7056 impl Nonsec02 {
7057 #[doc = "Secure"]
7058 pub const _0: Self = Self::new(0);
7059
7060 #[doc = "Non Secure"]
7061 pub const _1: Self = Self::new(1);
7062 }
7063 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7064 pub struct Nonsec03_SPEC;
7065 pub type Nonsec03 = crate::EnumBitfieldStruct<u8, Nonsec03_SPEC>;
7066 impl Nonsec03 {
7067 #[doc = "Secure"]
7068 pub const _0: Self = Self::new(0);
7069
7070 #[doc = "Non Secure"]
7071 pub const _1: Self = Self::new(1);
7072 }
7073 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7074 pub struct Nonsec04_SPEC;
7075 pub type Nonsec04 = crate::EnumBitfieldStruct<u8, Nonsec04_SPEC>;
7076 impl Nonsec04 {
7077 #[doc = "Secure"]
7078 pub const _0: Self = Self::new(0);
7079
7080 #[doc = "Non Secure"]
7081 pub const _1: Self = Self::new(1);
7082 }
7083 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7084 pub struct Nonsec05_SPEC;
7085 pub type Nonsec05 = crate::EnumBitfieldStruct<u8, Nonsec05_SPEC>;
7086 impl Nonsec05 {
7087 #[doc = "Secure"]
7088 pub const _0: Self = Self::new(0);
7089
7090 #[doc = "Non Secure"]
7091 pub const _1: Self = Self::new(1);
7092 }
7093 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7094 pub struct Nonsec06_SPEC;
7095 pub type Nonsec06 = crate::EnumBitfieldStruct<u8, Nonsec06_SPEC>;
7096 impl Nonsec06 {
7097 #[doc = "Secure"]
7098 pub const _0: Self = Self::new(0);
7099
7100 #[doc = "Non Secure"]
7101 pub const _1: Self = Self::new(1);
7102 }
7103 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7104 pub struct Nonsec07_SPEC;
7105 pub type Nonsec07 = crate::EnumBitfieldStruct<u8, Nonsec07_SPEC>;
7106 impl Nonsec07 {
7107 #[doc = "Secure"]
7108 pub const _0: Self = Self::new(0);
7109
7110 #[doc = "Non Secure"]
7111 pub const _1: Self = Self::new(1);
7112 }
7113 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7114 pub struct Nonsec08_SPEC;
7115 pub type Nonsec08 = crate::EnumBitfieldStruct<u8, Nonsec08_SPEC>;
7116 impl Nonsec08 {
7117 #[doc = "Secure"]
7118 pub const _0: Self = Self::new(0);
7119
7120 #[doc = "Non Secure"]
7121 pub const _1: Self = Self::new(1);
7122 }
7123 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7124 pub struct Nonsec09_SPEC;
7125 pub type Nonsec09 = crate::EnumBitfieldStruct<u8, Nonsec09_SPEC>;
7126 impl Nonsec09 {
7127 #[doc = "Secure"]
7128 pub const _0: Self = Self::new(0);
7129
7130 #[doc = "Non Secure"]
7131 pub const _1: Self = Self::new(1);
7132 }
7133 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7134 pub struct Nonsec11_SPEC;
7135 pub type Nonsec11 = crate::EnumBitfieldStruct<u8, Nonsec11_SPEC>;
7136 impl Nonsec11 {
7137 #[doc = "Secure"]
7138 pub const _0: Self = Self::new(0);
7139
7140 #[doc = "Non Secure"]
7141 pub const _1: Self = Self::new(1);
7142 }
7143 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7144 pub struct Nonsec12_SPEC;
7145 pub type Nonsec12 = crate::EnumBitfieldStruct<u8, Nonsec12_SPEC>;
7146 impl Nonsec12 {
7147 #[doc = "Secure"]
7148 pub const _0: Self = Self::new(0);
7149
7150 #[doc = "Non Secure"]
7151 pub const _1: Self = Self::new(1);
7152 }
7153 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7154 pub struct Nonsec13_SPEC;
7155 pub type Nonsec13 = crate::EnumBitfieldStruct<u8, Nonsec13_SPEC>;
7156 impl Nonsec13 {
7157 #[doc = "Secure"]
7158 pub const _0: Self = Self::new(0);
7159
7160 #[doc = "Non Secure"]
7161 pub const _1: Self = Self::new(1);
7162 }
7163 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7164 pub struct Nonsec16_SPEC;
7165 pub type Nonsec16 = crate::EnumBitfieldStruct<u8, Nonsec16_SPEC>;
7166 impl Nonsec16 {
7167 #[doc = "Secure"]
7168 pub const _0: Self = Self::new(0);
7169
7170 #[doc = "Non Secure"]
7171 pub const _1: Self = Self::new(1);
7172 }
7173 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7174 pub struct Nonsec17_SPEC;
7175 pub type Nonsec17 = crate::EnumBitfieldStruct<u8, Nonsec17_SPEC>;
7176 impl Nonsec17 {
7177 #[doc = "Secure"]
7178 pub const _0: Self = Self::new(0);
7179
7180 #[doc = "Non Secure"]
7181 pub const _1: Self = Self::new(1);
7182 }
7183 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7184 pub struct Nonsec18_SPEC;
7185 pub type Nonsec18 = crate::EnumBitfieldStruct<u8, Nonsec18_SPEC>;
7186 impl Nonsec18 {
7187 #[doc = "Secure"]
7188 pub const _0: Self = Self::new(0);
7189
7190 #[doc = "Non Secure"]
7191 pub const _1: Self = Self::new(1);
7192 }
7193 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7194 pub struct Nonsec21_SPEC;
7195 pub type Nonsec21 = crate::EnumBitfieldStruct<u8, Nonsec21_SPEC>;
7196 impl Nonsec21 {
7197 #[doc = "Secure"]
7198 pub const _0: Self = Self::new(0);
7199
7200 #[doc = "Non Secure"]
7201 pub const _1: Self = Self::new(1);
7202 }
7203 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7204 pub struct Nonsec22_SPEC;
7205 pub type Nonsec22 = crate::EnumBitfieldStruct<u8, Nonsec22_SPEC>;
7206 impl Nonsec22 {
7207 #[doc = "Secure"]
7208 pub const _0: Self = Self::new(0);
7209
7210 #[doc = "Non Secure"]
7211 pub const _1: Self = Self::new(1);
7212 }
7213 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7214 pub struct Nonsec26_SPEC;
7215 pub type Nonsec26 = crate::EnumBitfieldStruct<u8, Nonsec26_SPEC>;
7216 impl Nonsec26 {
7217 #[doc = "Secure"]
7218 pub const _0: Self = Self::new(0);
7219
7220 #[doc = "Non Secure"]
7221 pub const _1: Self = Self::new(1);
7222 }
7223}
7224#[doc(hidden)]
7225#[derive(Copy, Clone, Eq, PartialEq)]
7226pub struct Rstsar_SPEC;
7227impl crate::sealed::RegSpec for Rstsar_SPEC {
7228 type DataType = u32;
7229}
7230
7231#[doc = "Reset Security Attribution Register"]
7232pub type Rstsar = crate::RegValueT<Rstsar_SPEC>;
7233
7234impl Rstsar {
7235 #[doc = "Non-secure Attribute bit 0"]
7236 #[inline(always)]
7237 pub fn nonsec0(
7238 self,
7239 ) -> crate::common::RegisterField<
7240 0,
7241 0x1,
7242 1,
7243 0,
7244 rstsar::Nonsec0,
7245 rstsar::Nonsec0,
7246 Rstsar_SPEC,
7247 crate::common::RW,
7248 > {
7249 crate::common::RegisterField::<
7250 0,
7251 0x1,
7252 1,
7253 0,
7254 rstsar::Nonsec0,
7255 rstsar::Nonsec0,
7256 Rstsar_SPEC,
7257 crate::common::RW,
7258 >::from_register(self, 0)
7259 }
7260
7261 #[doc = "Non-secure Attribute bit 1"]
7262 #[inline(always)]
7263 pub fn nonsec1(
7264 self,
7265 ) -> crate::common::RegisterField<
7266 1,
7267 0x1,
7268 1,
7269 0,
7270 rstsar::Nonsec1,
7271 rstsar::Nonsec1,
7272 Rstsar_SPEC,
7273 crate::common::RW,
7274 > {
7275 crate::common::RegisterField::<
7276 1,
7277 0x1,
7278 1,
7279 0,
7280 rstsar::Nonsec1,
7281 rstsar::Nonsec1,
7282 Rstsar_SPEC,
7283 crate::common::RW,
7284 >::from_register(self, 0)
7285 }
7286
7287 #[doc = "Non-secure Attribute bit 2"]
7288 #[inline(always)]
7289 pub fn nonsec2(
7290 self,
7291 ) -> crate::common::RegisterField<
7292 2,
7293 0x1,
7294 1,
7295 0,
7296 rstsar::Nonsec2,
7297 rstsar::Nonsec2,
7298 Rstsar_SPEC,
7299 crate::common::RW,
7300 > {
7301 crate::common::RegisterField::<
7302 2,
7303 0x1,
7304 1,
7305 0,
7306 rstsar::Nonsec2,
7307 rstsar::Nonsec2,
7308 Rstsar_SPEC,
7309 crate::common::RW,
7310 >::from_register(self, 0)
7311 }
7312}
7313impl ::core::default::Default for Rstsar {
7314 #[inline(always)]
7315 fn default() -> Rstsar {
7316 <crate::RegValueT<Rstsar_SPEC> as RegisterValue<_>>::new(0)
7317 }
7318}
7319pub mod rstsar {
7320
7321 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7322 pub struct Nonsec0_SPEC;
7323 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
7324 impl Nonsec0 {
7325 #[doc = "Secure"]
7326 pub const _0: Self = Self::new(0);
7327
7328 #[doc = "Non-secure"]
7329 pub const _1: Self = Self::new(1);
7330 }
7331 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7332 pub struct Nonsec1_SPEC;
7333 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
7334 impl Nonsec1 {
7335 #[doc = "Secure"]
7336 pub const _0: Self = Self::new(0);
7337
7338 #[doc = "Non-secure"]
7339 pub const _1: Self = Self::new(1);
7340 }
7341 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7342 pub struct Nonsec2_SPEC;
7343 pub type Nonsec2 = crate::EnumBitfieldStruct<u8, Nonsec2_SPEC>;
7344 impl Nonsec2 {
7345 #[doc = "Secure"]
7346 pub const _0: Self = Self::new(0);
7347
7348 #[doc = "Non-secure"]
7349 pub const _1: Self = Self::new(1);
7350 }
7351}
7352#[doc(hidden)]
7353#[derive(Copy, Clone, Eq, PartialEq)]
7354pub struct Lpmsar_SPEC;
7355impl crate::sealed::RegSpec for Lpmsar_SPEC {
7356 type DataType = u32;
7357}
7358
7359#[doc = "Low Power Mode Security Attribution Register"]
7360pub type Lpmsar = crate::RegValueT<Lpmsar_SPEC>;
7361
7362impl Lpmsar {
7363 #[doc = "Non-secure Attribute bit 0"]
7364 #[inline(always)]
7365 pub fn nonsec0(
7366 self,
7367 ) -> crate::common::RegisterField<
7368 0,
7369 0x1,
7370 1,
7371 0,
7372 lpmsar::Nonsec0,
7373 lpmsar::Nonsec0,
7374 Lpmsar_SPEC,
7375 crate::common::RW,
7376 > {
7377 crate::common::RegisterField::<
7378 0,
7379 0x1,
7380 1,
7381 0,
7382 lpmsar::Nonsec0,
7383 lpmsar::Nonsec0,
7384 Lpmsar_SPEC,
7385 crate::common::RW,
7386 >::from_register(self, 0)
7387 }
7388
7389 #[doc = "Non-secure Attribute bit 1"]
7390 #[inline(always)]
7391 pub fn nonsec1(
7392 self,
7393 ) -> crate::common::RegisterField<
7394 1,
7395 0x1,
7396 1,
7397 0,
7398 lpmsar::Nonsec1,
7399 lpmsar::Nonsec1,
7400 Lpmsar_SPEC,
7401 crate::common::RW,
7402 > {
7403 crate::common::RegisterField::<
7404 1,
7405 0x1,
7406 1,
7407 0,
7408 lpmsar::Nonsec1,
7409 lpmsar::Nonsec1,
7410 Lpmsar_SPEC,
7411 crate::common::RW,
7412 >::from_register(self, 0)
7413 }
7414
7415 #[doc = "Non-secure Attribute bit 2"]
7416 #[inline(always)]
7417 pub fn nonsec2(
7418 self,
7419 ) -> crate::common::RegisterField<
7420 2,
7421 0x1,
7422 1,
7423 0,
7424 lpmsar::Nonsec2,
7425 lpmsar::Nonsec2,
7426 Lpmsar_SPEC,
7427 crate::common::RW,
7428 > {
7429 crate::common::RegisterField::<
7430 2,
7431 0x1,
7432 1,
7433 0,
7434 lpmsar::Nonsec2,
7435 lpmsar::Nonsec2,
7436 Lpmsar_SPEC,
7437 crate::common::RW,
7438 >::from_register(self, 0)
7439 }
7440
7441 #[doc = "Non-secure Attribute bit 8"]
7442 #[inline(always)]
7443 pub fn nonsec8(
7444 self,
7445 ) -> crate::common::RegisterField<
7446 8,
7447 0x1,
7448 1,
7449 0,
7450 lpmsar::Nonsec8,
7451 lpmsar::Nonsec8,
7452 Lpmsar_SPEC,
7453 crate::common::RW,
7454 > {
7455 crate::common::RegisterField::<
7456 8,
7457 0x1,
7458 1,
7459 0,
7460 lpmsar::Nonsec8,
7461 lpmsar::Nonsec8,
7462 Lpmsar_SPEC,
7463 crate::common::RW,
7464 >::from_register(self, 0)
7465 }
7466
7467 #[doc = "Non-secure Attribute bit 17"]
7468 #[inline(always)]
7469 pub fn nonsec17(
7470 self,
7471 ) -> crate::common::RegisterField<
7472 17,
7473 0x1,
7474 1,
7475 0,
7476 lpmsar::Nonsec17,
7477 lpmsar::Nonsec17,
7478 Lpmsar_SPEC,
7479 crate::common::RW,
7480 > {
7481 crate::common::RegisterField::<
7482 17,
7483 0x1,
7484 1,
7485 0,
7486 lpmsar::Nonsec17,
7487 lpmsar::Nonsec17,
7488 Lpmsar_SPEC,
7489 crate::common::RW,
7490 >::from_register(self, 0)
7491 }
7492
7493 #[doc = "Non-secure Attribute bit 18"]
7494 #[inline(always)]
7495 pub fn nonsec18(
7496 self,
7497 ) -> crate::common::RegisterField<
7498 18,
7499 0x1,
7500 1,
7501 0,
7502 lpmsar::Nonsec18,
7503 lpmsar::Nonsec18,
7504 Lpmsar_SPEC,
7505 crate::common::RW,
7506 > {
7507 crate::common::RegisterField::<
7508 18,
7509 0x1,
7510 1,
7511 0,
7512 lpmsar::Nonsec18,
7513 lpmsar::Nonsec18,
7514 Lpmsar_SPEC,
7515 crate::common::RW,
7516 >::from_register(self, 0)
7517 }
7518
7519 #[doc = "Non-secure Attribute bit 19"]
7520 #[inline(always)]
7521 pub fn nonsec19(
7522 self,
7523 ) -> crate::common::RegisterField<
7524 19,
7525 0x1,
7526 1,
7527 0,
7528 lpmsar::Nonsec19,
7529 lpmsar::Nonsec19,
7530 Lpmsar_SPEC,
7531 crate::common::RW,
7532 > {
7533 crate::common::RegisterField::<
7534 19,
7535 0x1,
7536 1,
7537 0,
7538 lpmsar::Nonsec19,
7539 lpmsar::Nonsec19,
7540 Lpmsar_SPEC,
7541 crate::common::RW,
7542 >::from_register(self, 0)
7543 }
7544
7545 #[doc = "Non-secure Attribute bit 21"]
7546 #[inline(always)]
7547 pub fn nonsec21(
7548 self,
7549 ) -> crate::common::RegisterField<
7550 21,
7551 0x1,
7552 1,
7553 0,
7554 lpmsar::Nonsec21,
7555 lpmsar::Nonsec21,
7556 Lpmsar_SPEC,
7557 crate::common::RW,
7558 > {
7559 crate::common::RegisterField::<
7560 21,
7561 0x1,
7562 1,
7563 0,
7564 lpmsar::Nonsec21,
7565 lpmsar::Nonsec21,
7566 Lpmsar_SPEC,
7567 crate::common::RW,
7568 >::from_register(self, 0)
7569 }
7570}
7571impl ::core::default::Default for Lpmsar {
7572 #[inline(always)]
7573 fn default() -> Lpmsar {
7574 <crate::RegValueT<Lpmsar_SPEC> as RegisterValue<_>>::new(0)
7575 }
7576}
7577pub mod lpmsar {
7578
7579 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7580 pub struct Nonsec0_SPEC;
7581 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
7582 impl Nonsec0 {
7583 #[doc = "Secure"]
7584 pub const _0: Self = Self::new(0);
7585
7586 #[doc = "Non-secure"]
7587 pub const _1: Self = Self::new(1);
7588 }
7589 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7590 pub struct Nonsec1_SPEC;
7591 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
7592 impl Nonsec1 {
7593 #[doc = "Secure"]
7594 pub const _0: Self = Self::new(0);
7595
7596 #[doc = "Non-secure"]
7597 pub const _1: Self = Self::new(1);
7598 }
7599 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7600 pub struct Nonsec2_SPEC;
7601 pub type Nonsec2 = crate::EnumBitfieldStruct<u8, Nonsec2_SPEC>;
7602 impl Nonsec2 {
7603 #[doc = "Secure"]
7604 pub const _0: Self = Self::new(0);
7605
7606 #[doc = "Non-secure"]
7607 pub const _1: Self = Self::new(1);
7608 }
7609 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7610 pub struct Nonsec8_SPEC;
7611 pub type Nonsec8 = crate::EnumBitfieldStruct<u8, Nonsec8_SPEC>;
7612 impl Nonsec8 {
7613 #[doc = "Secure"]
7614 pub const _0: Self = Self::new(0);
7615
7616 #[doc = "Non-secure"]
7617 pub const _1: Self = Self::new(1);
7618 }
7619 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7620 pub struct Nonsec17_SPEC;
7621 pub type Nonsec17 = crate::EnumBitfieldStruct<u8, Nonsec17_SPEC>;
7622 impl Nonsec17 {
7623 #[doc = "Secure"]
7624 pub const _0: Self = Self::new(0);
7625
7626 #[doc = "Non-secure"]
7627 pub const _1: Self = Self::new(1);
7628 }
7629 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7630 pub struct Nonsec18_SPEC;
7631 pub type Nonsec18 = crate::EnumBitfieldStruct<u8, Nonsec18_SPEC>;
7632 impl Nonsec18 {
7633 #[doc = "Secure"]
7634 pub const _0: Self = Self::new(0);
7635
7636 #[doc = "Non-secure"]
7637 pub const _1: Self = Self::new(1);
7638 }
7639 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7640 pub struct Nonsec19_SPEC;
7641 pub type Nonsec19 = crate::EnumBitfieldStruct<u8, Nonsec19_SPEC>;
7642 impl Nonsec19 {
7643 #[doc = "Secure"]
7644 pub const _0: Self = Self::new(0);
7645
7646 #[doc = "Non-secure"]
7647 pub const _1: Self = Self::new(1);
7648 }
7649 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7650 pub struct Nonsec21_SPEC;
7651 pub type Nonsec21 = crate::EnumBitfieldStruct<u8, Nonsec21_SPEC>;
7652 impl Nonsec21 {
7653 #[doc = "Secure"]
7654 pub const _0: Self = Self::new(0);
7655
7656 #[doc = "Non-secure"]
7657 pub const _1: Self = Self::new(1);
7658 }
7659}
7660#[doc(hidden)]
7661#[derive(Copy, Clone, Eq, PartialEq)]
7662pub struct Pvdsar_SPEC;
7663impl crate::sealed::RegSpec for Pvdsar_SPEC {
7664 type DataType = u32;
7665}
7666
7667#[doc = "Programable Voltage Detection Security Attribution Register"]
7668pub type Pvdsar = crate::RegValueT<Pvdsar_SPEC>;
7669
7670impl Pvdsar {
7671 #[doc = "Non Secure Attribute bit 0"]
7672 #[inline(always)]
7673 pub fn nonsec0(
7674 self,
7675 ) -> crate::common::RegisterField<
7676 0,
7677 0x1,
7678 1,
7679 0,
7680 pvdsar::Nonsec0,
7681 pvdsar::Nonsec0,
7682 Pvdsar_SPEC,
7683 crate::common::RW,
7684 > {
7685 crate::common::RegisterField::<
7686 0,
7687 0x1,
7688 1,
7689 0,
7690 pvdsar::Nonsec0,
7691 pvdsar::Nonsec0,
7692 Pvdsar_SPEC,
7693 crate::common::RW,
7694 >::from_register(self, 0)
7695 }
7696
7697 #[doc = "Non Secure Attribute bit 1"]
7698 #[inline(always)]
7699 pub fn nonsec1(
7700 self,
7701 ) -> crate::common::RegisterField<
7702 1,
7703 0x1,
7704 1,
7705 0,
7706 pvdsar::Nonsec1,
7707 pvdsar::Nonsec1,
7708 Pvdsar_SPEC,
7709 crate::common::RW,
7710 > {
7711 crate::common::RegisterField::<
7712 1,
7713 0x1,
7714 1,
7715 0,
7716 pvdsar::Nonsec1,
7717 pvdsar::Nonsec1,
7718 Pvdsar_SPEC,
7719 crate::common::RW,
7720 >::from_register(self, 0)
7721 }
7722}
7723impl ::core::default::Default for Pvdsar {
7724 #[inline(always)]
7725 fn default() -> Pvdsar {
7726 <crate::RegValueT<Pvdsar_SPEC> as RegisterValue<_>>::new(0)
7727 }
7728}
7729pub mod pvdsar {
7730
7731 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7732 pub struct Nonsec0_SPEC;
7733 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
7734 impl Nonsec0 {
7735 #[doc = "Secure"]
7736 pub const _0: Self = Self::new(0);
7737
7738 #[doc = "Non Secure"]
7739 pub const _1: Self = Self::new(1);
7740 }
7741 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7742 pub struct Nonsec1_SPEC;
7743 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
7744 impl Nonsec1 {
7745 #[doc = "Secure"]
7746 pub const _0: Self = Self::new(0);
7747
7748 #[doc = "Non Secure"]
7749 pub const _1: Self = Self::new(1);
7750 }
7751}
7752#[doc(hidden)]
7753#[derive(Copy, Clone, Eq, PartialEq)]
7754pub struct Bbfsar_SPEC;
7755impl crate::sealed::RegSpec for Bbfsar_SPEC {
7756 type DataType = u32;
7757}
7758
7759#[doc = "Battery Backup Function Security Attribute Register"]
7760pub type Bbfsar = crate::RegValueT<Bbfsar_SPEC>;
7761
7762impl Bbfsar {
7763 #[doc = "Non Secure Attribute bit 0"]
7764 #[inline(always)]
7765 pub fn nonsec0(
7766 self,
7767 ) -> crate::common::RegisterField<
7768 0,
7769 0x1,
7770 1,
7771 0,
7772 bbfsar::Nonsec0,
7773 bbfsar::Nonsec0,
7774 Bbfsar_SPEC,
7775 crate::common::RW,
7776 > {
7777 crate::common::RegisterField::<
7778 0,
7779 0x1,
7780 1,
7781 0,
7782 bbfsar::Nonsec0,
7783 bbfsar::Nonsec0,
7784 Bbfsar_SPEC,
7785 crate::common::RW,
7786 >::from_register(self, 0)
7787 }
7788
7789 #[doc = "Non Secure Attribute bit 1"]
7790 #[inline(always)]
7791 pub fn nonsec1(
7792 self,
7793 ) -> crate::common::RegisterField<
7794 1,
7795 0x1,
7796 1,
7797 0,
7798 bbfsar::Nonsec1,
7799 bbfsar::Nonsec1,
7800 Bbfsar_SPEC,
7801 crate::common::RW,
7802 > {
7803 crate::common::RegisterField::<
7804 1,
7805 0x1,
7806 1,
7807 0,
7808 bbfsar::Nonsec1,
7809 bbfsar::Nonsec1,
7810 Bbfsar_SPEC,
7811 crate::common::RW,
7812 >::from_register(self, 0)
7813 }
7814
7815 #[doc = "Non Secure Attribute bit 2"]
7816 #[inline(always)]
7817 pub fn nonsec2(
7818 self,
7819 ) -> crate::common::RegisterField<
7820 2,
7821 0x1,
7822 1,
7823 0,
7824 bbfsar::Nonsec2,
7825 bbfsar::Nonsec2,
7826 Bbfsar_SPEC,
7827 crate::common::RW,
7828 > {
7829 crate::common::RegisterField::<
7830 2,
7831 0x1,
7832 1,
7833 0,
7834 bbfsar::Nonsec2,
7835 bbfsar::Nonsec2,
7836 Bbfsar_SPEC,
7837 crate::common::RW,
7838 >::from_register(self, 0)
7839 }
7840
7841 #[doc = "Non Secure Attribute bit 3"]
7842 #[inline(always)]
7843 pub fn nonsec3(
7844 self,
7845 ) -> crate::common::RegisterField<
7846 3,
7847 0x1,
7848 1,
7849 0,
7850 bbfsar::Nonsec3,
7851 bbfsar::Nonsec3,
7852 Bbfsar_SPEC,
7853 crate::common::RW,
7854 > {
7855 crate::common::RegisterField::<
7856 3,
7857 0x1,
7858 1,
7859 0,
7860 bbfsar::Nonsec3,
7861 bbfsar::Nonsec3,
7862 Bbfsar_SPEC,
7863 crate::common::RW,
7864 >::from_register(self, 0)
7865 }
7866
7867 #[doc = "Non Secure Attribute bit 4"]
7868 #[inline(always)]
7869 pub fn nonsec4(
7870 self,
7871 ) -> crate::common::RegisterField<
7872 4,
7873 0x1,
7874 1,
7875 0,
7876 bbfsar::Nonsec4,
7877 bbfsar::Nonsec4,
7878 Bbfsar_SPEC,
7879 crate::common::RW,
7880 > {
7881 crate::common::RegisterField::<
7882 4,
7883 0x1,
7884 1,
7885 0,
7886 bbfsar::Nonsec4,
7887 bbfsar::Nonsec4,
7888 Bbfsar_SPEC,
7889 crate::common::RW,
7890 >::from_register(self, 0)
7891 }
7892}
7893impl ::core::default::Default for Bbfsar {
7894 #[inline(always)]
7895 fn default() -> Bbfsar {
7896 <crate::RegValueT<Bbfsar_SPEC> as RegisterValue<_>>::new(0)
7897 }
7898}
7899pub mod bbfsar {
7900
7901 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7902 pub struct Nonsec0_SPEC;
7903 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
7904 impl Nonsec0 {
7905 #[doc = "Secure"]
7906 pub const _0: Self = Self::new(0);
7907
7908 #[doc = "Non Secure"]
7909 pub const _1: Self = Self::new(1);
7910 }
7911 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7912 pub struct Nonsec1_SPEC;
7913 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
7914 impl Nonsec1 {
7915 #[doc = "Secure"]
7916 pub const _0: Self = Self::new(0);
7917
7918 #[doc = "Non Secure"]
7919 pub const _1: Self = Self::new(1);
7920 }
7921 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7922 pub struct Nonsec2_SPEC;
7923 pub type Nonsec2 = crate::EnumBitfieldStruct<u8, Nonsec2_SPEC>;
7924 impl Nonsec2 {
7925 #[doc = "Secure"]
7926 pub const _0: Self = Self::new(0);
7927
7928 #[doc = "Non Secure"]
7929 pub const _1: Self = Self::new(1);
7930 }
7931 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7932 pub struct Nonsec3_SPEC;
7933 pub type Nonsec3 = crate::EnumBitfieldStruct<u8, Nonsec3_SPEC>;
7934 impl Nonsec3 {
7935 #[doc = "Secure"]
7936 pub const _0: Self = Self::new(0);
7937
7938 #[doc = "Non Secure"]
7939 pub const _1: Self = Self::new(1);
7940 }
7941 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7942 pub struct Nonsec4_SPEC;
7943 pub type Nonsec4 = crate::EnumBitfieldStruct<u8, Nonsec4_SPEC>;
7944 impl Nonsec4 {
7945 #[doc = "Secure"]
7946 pub const _0: Self = Self::new(0);
7947
7948 #[doc = "Non Secure"]
7949 pub const _1: Self = Self::new(1);
7950 }
7951}
7952#[doc(hidden)]
7953#[derive(Copy, Clone, Eq, PartialEq)]
7954pub struct Pgcsar_SPEC;
7955impl crate::sealed::RegSpec for Pgcsar_SPEC {
7956 type DataType = u32;
7957}
7958
7959#[doc = "Power Gating Control Security Attribution Register"]
7960pub type Pgcsar = crate::RegValueT<Pgcsar_SPEC>;
7961
7962impl Pgcsar {
7963 #[doc = "Non-secure Attribute bit 1"]
7964 #[inline(always)]
7965 pub fn nonsec1(
7966 self,
7967 ) -> crate::common::RegisterField<
7968 1,
7969 0x1,
7970 1,
7971 0,
7972 pgcsar::Nonsec1,
7973 pgcsar::Nonsec1,
7974 Pgcsar_SPEC,
7975 crate::common::RW,
7976 > {
7977 crate::common::RegisterField::<
7978 1,
7979 0x1,
7980 1,
7981 0,
7982 pgcsar::Nonsec1,
7983 pgcsar::Nonsec1,
7984 Pgcsar_SPEC,
7985 crate::common::RW,
7986 >::from_register(self, 0)
7987 }
7988}
7989impl ::core::default::Default for Pgcsar {
7990 #[inline(always)]
7991 fn default() -> Pgcsar {
7992 <crate::RegValueT<Pgcsar_SPEC> as RegisterValue<_>>::new(0)
7993 }
7994}
7995pub mod pgcsar {
7996
7997 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7998 pub struct Nonsec1_SPEC;
7999 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
8000 impl Nonsec1 {
8001 #[doc = "Secure"]
8002 pub const _0: Self = Self::new(0);
8003
8004 #[doc = "Non-secure"]
8005 pub const _1: Self = Self::new(1);
8006 }
8007}
8008#[doc(hidden)]
8009#[derive(Copy, Clone, Eq, PartialEq)]
8010pub struct Dpfsar_SPEC;
8011impl crate::sealed::RegSpec for Dpfsar_SPEC {
8012 type DataType = u32;
8013}
8014
8015#[doc = "Deep Software Standby Interrupt Factor Security Attribution Register"]
8016pub type Dpfsar = crate::RegValueT<Dpfsar_SPEC>;
8017
8018impl Dpfsar {
8019 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8020 #[inline(always)]
8021 pub fn dpfsa0(
8022 self,
8023 ) -> crate::common::RegisterField<
8024 0,
8025 0x1,
8026 1,
8027 0,
8028 dpfsar::Dpfsa0,
8029 dpfsar::Dpfsa0,
8030 Dpfsar_SPEC,
8031 crate::common::RW,
8032 > {
8033 crate::common::RegisterField::<
8034 0,
8035 0x1,
8036 1,
8037 0,
8038 dpfsar::Dpfsa0,
8039 dpfsar::Dpfsa0,
8040 Dpfsar_SPEC,
8041 crate::common::RW,
8042 >::from_register(self, 0)
8043 }
8044
8045 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8046 #[inline(always)]
8047 pub fn dpfsa1(
8048 self,
8049 ) -> crate::common::RegisterField<
8050 1,
8051 0x1,
8052 1,
8053 0,
8054 dpfsar::Dpfsa1,
8055 dpfsar::Dpfsa1,
8056 Dpfsar_SPEC,
8057 crate::common::RW,
8058 > {
8059 crate::common::RegisterField::<
8060 1,
8061 0x1,
8062 1,
8063 0,
8064 dpfsar::Dpfsa1,
8065 dpfsar::Dpfsa1,
8066 Dpfsar_SPEC,
8067 crate::common::RW,
8068 >::from_register(self, 0)
8069 }
8070
8071 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8072 #[inline(always)]
8073 pub fn dpfsa2(
8074 self,
8075 ) -> crate::common::RegisterField<
8076 2,
8077 0x1,
8078 1,
8079 0,
8080 dpfsar::Dpfsa2,
8081 dpfsar::Dpfsa2,
8082 Dpfsar_SPEC,
8083 crate::common::RW,
8084 > {
8085 crate::common::RegisterField::<
8086 2,
8087 0x1,
8088 1,
8089 0,
8090 dpfsar::Dpfsa2,
8091 dpfsar::Dpfsa2,
8092 Dpfsar_SPEC,
8093 crate::common::RW,
8094 >::from_register(self, 0)
8095 }
8096
8097 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8098 #[inline(always)]
8099 pub fn dpfsa3(
8100 self,
8101 ) -> crate::common::RegisterField<
8102 3,
8103 0x1,
8104 1,
8105 0,
8106 dpfsar::Dpfsa3,
8107 dpfsar::Dpfsa3,
8108 Dpfsar_SPEC,
8109 crate::common::RW,
8110 > {
8111 crate::common::RegisterField::<
8112 3,
8113 0x1,
8114 1,
8115 0,
8116 dpfsar::Dpfsa3,
8117 dpfsar::Dpfsa3,
8118 Dpfsar_SPEC,
8119 crate::common::RW,
8120 >::from_register(self, 0)
8121 }
8122
8123 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8124 #[inline(always)]
8125 pub fn dpfsa4(
8126 self,
8127 ) -> crate::common::RegisterField<
8128 4,
8129 0x1,
8130 1,
8131 0,
8132 dpfsar::Dpfsa4,
8133 dpfsar::Dpfsa4,
8134 Dpfsar_SPEC,
8135 crate::common::RW,
8136 > {
8137 crate::common::RegisterField::<
8138 4,
8139 0x1,
8140 1,
8141 0,
8142 dpfsar::Dpfsa4,
8143 dpfsar::Dpfsa4,
8144 Dpfsar_SPEC,
8145 crate::common::RW,
8146 >::from_register(self, 0)
8147 }
8148
8149 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8150 #[inline(always)]
8151 pub fn dpfsa5(
8152 self,
8153 ) -> crate::common::RegisterField<
8154 5,
8155 0x1,
8156 1,
8157 0,
8158 dpfsar::Dpfsa5,
8159 dpfsar::Dpfsa5,
8160 Dpfsar_SPEC,
8161 crate::common::RW,
8162 > {
8163 crate::common::RegisterField::<
8164 5,
8165 0x1,
8166 1,
8167 0,
8168 dpfsar::Dpfsa5,
8169 dpfsar::Dpfsa5,
8170 Dpfsar_SPEC,
8171 crate::common::RW,
8172 >::from_register(self, 0)
8173 }
8174
8175 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8176 #[inline(always)]
8177 pub fn dpfsa6(
8178 self,
8179 ) -> crate::common::RegisterField<
8180 6,
8181 0x1,
8182 1,
8183 0,
8184 dpfsar::Dpfsa6,
8185 dpfsar::Dpfsa6,
8186 Dpfsar_SPEC,
8187 crate::common::RW,
8188 > {
8189 crate::common::RegisterField::<
8190 6,
8191 0x1,
8192 1,
8193 0,
8194 dpfsar::Dpfsa6,
8195 dpfsar::Dpfsa6,
8196 Dpfsar_SPEC,
8197 crate::common::RW,
8198 >::from_register(self, 0)
8199 }
8200
8201 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)"]
8202 #[inline(always)]
8203 pub fn dpfsa7(
8204 self,
8205 ) -> crate::common::RegisterField<
8206 7,
8207 0x1,
8208 1,
8209 0,
8210 dpfsar::Dpfsa7,
8211 dpfsar::Dpfsa7,
8212 Dpfsar_SPEC,
8213 crate::common::RW,
8214 > {
8215 crate::common::RegisterField::<
8216 7,
8217 0x1,
8218 1,
8219 0,
8220 dpfsar::Dpfsa7,
8221 dpfsar::Dpfsa7,
8222 Dpfsar_SPEC,
8223 crate::common::RW,
8224 >::from_register(self, 0)
8225 }
8226
8227 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8228 #[inline(always)]
8229 pub fn dpfsa08(
8230 self,
8231 ) -> crate::common::RegisterField<
8232 8,
8233 0x1,
8234 1,
8235 0,
8236 dpfsar::Dpfsa08,
8237 dpfsar::Dpfsa08,
8238 Dpfsar_SPEC,
8239 crate::common::RW,
8240 > {
8241 crate::common::RegisterField::<
8242 8,
8243 0x1,
8244 1,
8245 0,
8246 dpfsar::Dpfsa08,
8247 dpfsar::Dpfsa08,
8248 Dpfsar_SPEC,
8249 crate::common::RW,
8250 >::from_register(self, 0)
8251 }
8252
8253 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8254 #[inline(always)]
8255 pub fn dpfsa09(
8256 self,
8257 ) -> crate::common::RegisterField<
8258 9,
8259 0x1,
8260 1,
8261 0,
8262 dpfsar::Dpfsa09,
8263 dpfsar::Dpfsa09,
8264 Dpfsar_SPEC,
8265 crate::common::RW,
8266 > {
8267 crate::common::RegisterField::<
8268 9,
8269 0x1,
8270 1,
8271 0,
8272 dpfsar::Dpfsa09,
8273 dpfsar::Dpfsa09,
8274 Dpfsar_SPEC,
8275 crate::common::RW,
8276 >::from_register(self, 0)
8277 }
8278
8279 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8280 #[inline(always)]
8281 pub fn dpfsa10(
8282 self,
8283 ) -> crate::common::RegisterField<
8284 10,
8285 0x1,
8286 1,
8287 0,
8288 dpfsar::Dpfsa10,
8289 dpfsar::Dpfsa10,
8290 Dpfsar_SPEC,
8291 crate::common::RW,
8292 > {
8293 crate::common::RegisterField::<
8294 10,
8295 0x1,
8296 1,
8297 0,
8298 dpfsar::Dpfsa10,
8299 dpfsar::Dpfsa10,
8300 Dpfsar_SPEC,
8301 crate::common::RW,
8302 >::from_register(self, 0)
8303 }
8304
8305 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8306 #[inline(always)]
8307 pub fn dpfsa11(
8308 self,
8309 ) -> crate::common::RegisterField<
8310 11,
8311 0x1,
8312 1,
8313 0,
8314 dpfsar::Dpfsa11,
8315 dpfsar::Dpfsa11,
8316 Dpfsar_SPEC,
8317 crate::common::RW,
8318 > {
8319 crate::common::RegisterField::<
8320 11,
8321 0x1,
8322 1,
8323 0,
8324 dpfsar::Dpfsa11,
8325 dpfsar::Dpfsa11,
8326 Dpfsar_SPEC,
8327 crate::common::RW,
8328 >::from_register(self, 0)
8329 }
8330
8331 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8332 #[inline(always)]
8333 pub fn dpfsa12(
8334 self,
8335 ) -> crate::common::RegisterField<
8336 12,
8337 0x1,
8338 1,
8339 0,
8340 dpfsar::Dpfsa12,
8341 dpfsar::Dpfsa12,
8342 Dpfsar_SPEC,
8343 crate::common::RW,
8344 > {
8345 crate::common::RegisterField::<
8346 12,
8347 0x1,
8348 1,
8349 0,
8350 dpfsar::Dpfsa12,
8351 dpfsar::Dpfsa12,
8352 Dpfsar_SPEC,
8353 crate::common::RW,
8354 >::from_register(self, 0)
8355 }
8356
8357 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8358 #[inline(always)]
8359 pub fn dpfsa13(
8360 self,
8361 ) -> crate::common::RegisterField<
8362 13,
8363 0x1,
8364 1,
8365 0,
8366 dpfsar::Dpfsa13,
8367 dpfsar::Dpfsa13,
8368 Dpfsar_SPEC,
8369 crate::common::RW,
8370 > {
8371 crate::common::RegisterField::<
8372 13,
8373 0x1,
8374 1,
8375 0,
8376 dpfsar::Dpfsa13,
8377 dpfsar::Dpfsa13,
8378 Dpfsar_SPEC,
8379 crate::common::RW,
8380 >::from_register(self, 0)
8381 }
8382
8383 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8384 #[inline(always)]
8385 pub fn dpfsa14(
8386 self,
8387 ) -> crate::common::RegisterField<
8388 14,
8389 0x1,
8390 1,
8391 0,
8392 dpfsar::Dpfsa14,
8393 dpfsar::Dpfsa14,
8394 Dpfsar_SPEC,
8395 crate::common::RW,
8396 > {
8397 crate::common::RegisterField::<
8398 14,
8399 0x1,
8400 1,
8401 0,
8402 dpfsar::Dpfsa14,
8403 dpfsar::Dpfsa14,
8404 Dpfsar_SPEC,
8405 crate::common::RW,
8406 >::from_register(self, 0)
8407 }
8408
8409 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)"]
8410 #[inline(always)]
8411 pub fn dpfsa15(
8412 self,
8413 ) -> crate::common::RegisterField<
8414 15,
8415 0x1,
8416 1,
8417 0,
8418 dpfsar::Dpfsa15,
8419 dpfsar::Dpfsa15,
8420 Dpfsar_SPEC,
8421 crate::common::RW,
8422 > {
8423 crate::common::RegisterField::<
8424 15,
8425 0x1,
8426 1,
8427 0,
8428 dpfsar::Dpfsa15,
8429 dpfsar::Dpfsa15,
8430 Dpfsar_SPEC,
8431 crate::common::RW,
8432 >::from_register(self, 0)
8433 }
8434
8435 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 16"]
8436 #[inline(always)]
8437 pub fn dpfsa16(
8438 self,
8439 ) -> crate::common::RegisterField<
8440 16,
8441 0x1,
8442 1,
8443 0,
8444 dpfsar::Dpfsa16,
8445 dpfsar::Dpfsa16,
8446 Dpfsar_SPEC,
8447 crate::common::RW,
8448 > {
8449 crate::common::RegisterField::<
8450 16,
8451 0x1,
8452 1,
8453 0,
8454 dpfsar::Dpfsa16,
8455 dpfsar::Dpfsa16,
8456 Dpfsar_SPEC,
8457 crate::common::RW,
8458 >::from_register(self, 0)
8459 }
8460
8461 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 17"]
8462 #[inline(always)]
8463 pub fn dpfsa17(
8464 self,
8465 ) -> crate::common::RegisterField<
8466 17,
8467 0x1,
8468 1,
8469 0,
8470 dpfsar::Dpfsa17,
8471 dpfsar::Dpfsa17,
8472 Dpfsar_SPEC,
8473 crate::common::RW,
8474 > {
8475 crate::common::RegisterField::<
8476 17,
8477 0x1,
8478 1,
8479 0,
8480 dpfsar::Dpfsa17,
8481 dpfsar::Dpfsa17,
8482 Dpfsar_SPEC,
8483 crate::common::RW,
8484 >::from_register(self, 0)
8485 }
8486
8487 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 18"]
8488 #[inline(always)]
8489 pub fn dpfsa18(
8490 self,
8491 ) -> crate::common::RegisterField<
8492 18,
8493 0x1,
8494 1,
8495 0,
8496 dpfsar::Dpfsa18,
8497 dpfsar::Dpfsa18,
8498 Dpfsar_SPEC,
8499 crate::common::RW,
8500 > {
8501 crate::common::RegisterField::<
8502 18,
8503 0x1,
8504 1,
8505 0,
8506 dpfsar::Dpfsa18,
8507 dpfsar::Dpfsa18,
8508 Dpfsar_SPEC,
8509 crate::common::RW,
8510 >::from_register(self, 0)
8511 }
8512
8513 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 19"]
8514 #[inline(always)]
8515 pub fn dpfsa19(
8516 self,
8517 ) -> crate::common::RegisterField<
8518 19,
8519 0x1,
8520 1,
8521 0,
8522 dpfsar::Dpfsa19,
8523 dpfsar::Dpfsa19,
8524 Dpfsar_SPEC,
8525 crate::common::RW,
8526 > {
8527 crate::common::RegisterField::<
8528 19,
8529 0x1,
8530 1,
8531 0,
8532 dpfsar::Dpfsa19,
8533 dpfsar::Dpfsa19,
8534 Dpfsar_SPEC,
8535 crate::common::RW,
8536 >::from_register(self, 0)
8537 }
8538
8539 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 20"]
8540 #[inline(always)]
8541 pub fn dpfsa20(
8542 self,
8543 ) -> crate::common::RegisterField<
8544 20,
8545 0x1,
8546 1,
8547 0,
8548 dpfsar::Dpfsa20,
8549 dpfsar::Dpfsa20,
8550 Dpfsar_SPEC,
8551 crate::common::RW,
8552 > {
8553 crate::common::RegisterField::<
8554 20,
8555 0x1,
8556 1,
8557 0,
8558 dpfsar::Dpfsa20,
8559 dpfsar::Dpfsa20,
8560 Dpfsar_SPEC,
8561 crate::common::RW,
8562 >::from_register(self, 0)
8563 }
8564
8565 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 24"]
8566 #[inline(always)]
8567 pub fn dpfsa24(
8568 self,
8569 ) -> crate::common::RegisterField<
8570 24,
8571 0x1,
8572 1,
8573 0,
8574 dpfsar::Dpfsa24,
8575 dpfsar::Dpfsa24,
8576 Dpfsar_SPEC,
8577 crate::common::RW,
8578 > {
8579 crate::common::RegisterField::<
8580 24,
8581 0x1,
8582 1,
8583 0,
8584 dpfsar::Dpfsa24,
8585 dpfsar::Dpfsa24,
8586 Dpfsar_SPEC,
8587 crate::common::RW,
8588 >::from_register(self, 0)
8589 }
8590
8591 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 26"]
8592 #[inline(always)]
8593 pub fn dpfsa26(
8594 self,
8595 ) -> crate::common::RegisterField<
8596 26,
8597 0x1,
8598 1,
8599 0,
8600 dpfsar::Dpfsa26,
8601 dpfsar::Dpfsa26,
8602 Dpfsar_SPEC,
8603 crate::common::RW,
8604 > {
8605 crate::common::RegisterField::<
8606 26,
8607 0x1,
8608 1,
8609 0,
8610 dpfsar::Dpfsa26,
8611 dpfsar::Dpfsa26,
8612 Dpfsar_SPEC,
8613 crate::common::RW,
8614 >::from_register(self, 0)
8615 }
8616
8617 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 27"]
8618 #[inline(always)]
8619 pub fn dpfsa27(
8620 self,
8621 ) -> crate::common::RegisterField<
8622 27,
8623 0x1,
8624 1,
8625 0,
8626 dpfsar::Dpfsa27,
8627 dpfsar::Dpfsa27,
8628 Dpfsar_SPEC,
8629 crate::common::RW,
8630 > {
8631 crate::common::RegisterField::<
8632 27,
8633 0x1,
8634 1,
8635 0,
8636 dpfsar::Dpfsa27,
8637 dpfsar::Dpfsa27,
8638 Dpfsar_SPEC,
8639 crate::common::RW,
8640 >::from_register(self, 0)
8641 }
8642
8643 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 29"]
8644 #[inline(always)]
8645 pub fn dpfsa29(
8646 self,
8647 ) -> crate::common::RegisterField<
8648 29,
8649 0x1,
8650 1,
8651 0,
8652 dpfsar::Dpfsa29,
8653 dpfsar::Dpfsa29,
8654 Dpfsar_SPEC,
8655 crate::common::RW,
8656 > {
8657 crate::common::RegisterField::<
8658 29,
8659 0x1,
8660 1,
8661 0,
8662 dpfsar::Dpfsa29,
8663 dpfsar::Dpfsa29,
8664 Dpfsar_SPEC,
8665 crate::common::RW,
8666 >::from_register(self, 0)
8667 }
8668
8669 #[doc = "Deep Software Standby Interrupt Factor Security Attribute bit 31"]
8670 #[inline(always)]
8671 pub fn dpfsa31(
8672 self,
8673 ) -> crate::common::RegisterField<
8674 31,
8675 0x1,
8676 1,
8677 0,
8678 dpfsar::Dpfsa31,
8679 dpfsar::Dpfsa31,
8680 Dpfsar_SPEC,
8681 crate::common::RW,
8682 > {
8683 crate::common::RegisterField::<
8684 31,
8685 0x1,
8686 1,
8687 0,
8688 dpfsar::Dpfsa31,
8689 dpfsar::Dpfsa31,
8690 Dpfsar_SPEC,
8691 crate::common::RW,
8692 >::from_register(self, 0)
8693 }
8694}
8695impl ::core::default::Default for Dpfsar {
8696 #[inline(always)]
8697 fn default() -> Dpfsar {
8698 <crate::RegValueT<Dpfsar_SPEC> as RegisterValue<_>>::new(0)
8699 }
8700}
8701pub mod dpfsar {
8702
8703 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8704 pub struct Dpfsa0_SPEC;
8705 pub type Dpfsa0 = crate::EnumBitfieldStruct<u8, Dpfsa0_SPEC>;
8706 impl Dpfsa0 {
8707 #[doc = "Secure"]
8708 pub const _0: Self = Self::new(0);
8709
8710 #[doc = "Non-secure"]
8711 pub const _1: Self = Self::new(1);
8712 }
8713 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8714 pub struct Dpfsa1_SPEC;
8715 pub type Dpfsa1 = crate::EnumBitfieldStruct<u8, Dpfsa1_SPEC>;
8716 impl Dpfsa1 {
8717 #[doc = "Secure"]
8718 pub const _0: Self = Self::new(0);
8719
8720 #[doc = "Non-secure"]
8721 pub const _1: Self = Self::new(1);
8722 }
8723 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8724 pub struct Dpfsa2_SPEC;
8725 pub type Dpfsa2 = crate::EnumBitfieldStruct<u8, Dpfsa2_SPEC>;
8726 impl Dpfsa2 {
8727 #[doc = "Secure"]
8728 pub const _0: Self = Self::new(0);
8729
8730 #[doc = "Non-secure"]
8731 pub const _1: Self = Self::new(1);
8732 }
8733 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8734 pub struct Dpfsa3_SPEC;
8735 pub type Dpfsa3 = crate::EnumBitfieldStruct<u8, Dpfsa3_SPEC>;
8736 impl Dpfsa3 {
8737 #[doc = "Secure"]
8738 pub const _0: Self = Self::new(0);
8739
8740 #[doc = "Non-secure"]
8741 pub const _1: Self = Self::new(1);
8742 }
8743 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8744 pub struct Dpfsa4_SPEC;
8745 pub type Dpfsa4 = crate::EnumBitfieldStruct<u8, Dpfsa4_SPEC>;
8746 impl Dpfsa4 {
8747 #[doc = "Secure"]
8748 pub const _0: Self = Self::new(0);
8749
8750 #[doc = "Non-secure"]
8751 pub const _1: Self = Self::new(1);
8752 }
8753 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8754 pub struct Dpfsa5_SPEC;
8755 pub type Dpfsa5 = crate::EnumBitfieldStruct<u8, Dpfsa5_SPEC>;
8756 impl Dpfsa5 {
8757 #[doc = "Secure"]
8758 pub const _0: Self = Self::new(0);
8759
8760 #[doc = "Non-secure"]
8761 pub const _1: Self = Self::new(1);
8762 }
8763 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8764 pub struct Dpfsa6_SPEC;
8765 pub type Dpfsa6 = crate::EnumBitfieldStruct<u8, Dpfsa6_SPEC>;
8766 impl Dpfsa6 {
8767 #[doc = "Secure"]
8768 pub const _0: Self = Self::new(0);
8769
8770 #[doc = "Non-secure"]
8771 pub const _1: Self = Self::new(1);
8772 }
8773 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8774 pub struct Dpfsa7_SPEC;
8775 pub type Dpfsa7 = crate::EnumBitfieldStruct<u8, Dpfsa7_SPEC>;
8776 impl Dpfsa7 {
8777 #[doc = "Secure"]
8778 pub const _0: Self = Self::new(0);
8779
8780 #[doc = "Non-secure"]
8781 pub const _1: Self = Self::new(1);
8782 }
8783 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8784 pub struct Dpfsa08_SPEC;
8785 pub type Dpfsa08 = crate::EnumBitfieldStruct<u8, Dpfsa08_SPEC>;
8786 impl Dpfsa08 {
8787 #[doc = "Secure"]
8788 pub const _0: Self = Self::new(0);
8789
8790 #[doc = "Non-secure"]
8791 pub const _1: Self = Self::new(1);
8792 }
8793 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8794 pub struct Dpfsa09_SPEC;
8795 pub type Dpfsa09 = crate::EnumBitfieldStruct<u8, Dpfsa09_SPEC>;
8796 impl Dpfsa09 {
8797 #[doc = "Secure"]
8798 pub const _0: Self = Self::new(0);
8799
8800 #[doc = "Non-secure"]
8801 pub const _1: Self = Self::new(1);
8802 }
8803 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8804 pub struct Dpfsa10_SPEC;
8805 pub type Dpfsa10 = crate::EnumBitfieldStruct<u8, Dpfsa10_SPEC>;
8806 impl Dpfsa10 {
8807 #[doc = "Secure"]
8808 pub const _0: Self = Self::new(0);
8809
8810 #[doc = "Non-secure"]
8811 pub const _1: Self = Self::new(1);
8812 }
8813 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8814 pub struct Dpfsa11_SPEC;
8815 pub type Dpfsa11 = crate::EnumBitfieldStruct<u8, Dpfsa11_SPEC>;
8816 impl Dpfsa11 {
8817 #[doc = "Secure"]
8818 pub const _0: Self = Self::new(0);
8819
8820 #[doc = "Non-secure"]
8821 pub const _1: Self = Self::new(1);
8822 }
8823 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8824 pub struct Dpfsa12_SPEC;
8825 pub type Dpfsa12 = crate::EnumBitfieldStruct<u8, Dpfsa12_SPEC>;
8826 impl Dpfsa12 {
8827 #[doc = "Secure"]
8828 pub const _0: Self = Self::new(0);
8829
8830 #[doc = "Non-secure"]
8831 pub const _1: Self = Self::new(1);
8832 }
8833 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8834 pub struct Dpfsa13_SPEC;
8835 pub type Dpfsa13 = crate::EnumBitfieldStruct<u8, Dpfsa13_SPEC>;
8836 impl Dpfsa13 {
8837 #[doc = "Secure"]
8838 pub const _0: Self = Self::new(0);
8839
8840 #[doc = "Non-secure"]
8841 pub const _1: Self = Self::new(1);
8842 }
8843 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8844 pub struct Dpfsa14_SPEC;
8845 pub type Dpfsa14 = crate::EnumBitfieldStruct<u8, Dpfsa14_SPEC>;
8846 impl Dpfsa14 {
8847 #[doc = "Secure"]
8848 pub const _0: Self = Self::new(0);
8849
8850 #[doc = "Non-secure"]
8851 pub const _1: Self = Self::new(1);
8852 }
8853 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8854 pub struct Dpfsa15_SPEC;
8855 pub type Dpfsa15 = crate::EnumBitfieldStruct<u8, Dpfsa15_SPEC>;
8856 impl Dpfsa15 {
8857 #[doc = "Secure"]
8858 pub const _0: Self = Self::new(0);
8859
8860 #[doc = "Non-secure"]
8861 pub const _1: Self = Self::new(1);
8862 }
8863 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8864 pub struct Dpfsa16_SPEC;
8865 pub type Dpfsa16 = crate::EnumBitfieldStruct<u8, Dpfsa16_SPEC>;
8866 impl Dpfsa16 {
8867 #[doc = "Secure"]
8868 pub const _0: Self = Self::new(0);
8869
8870 #[doc = "Non-secure"]
8871 pub const _1: Self = Self::new(1);
8872 }
8873 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8874 pub struct Dpfsa17_SPEC;
8875 pub type Dpfsa17 = crate::EnumBitfieldStruct<u8, Dpfsa17_SPEC>;
8876 impl Dpfsa17 {
8877 #[doc = "Secure"]
8878 pub const _0: Self = Self::new(0);
8879
8880 #[doc = "Non-secure"]
8881 pub const _1: Self = Self::new(1);
8882 }
8883 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8884 pub struct Dpfsa18_SPEC;
8885 pub type Dpfsa18 = crate::EnumBitfieldStruct<u8, Dpfsa18_SPEC>;
8886 impl Dpfsa18 {
8887 #[doc = "Secure"]
8888 pub const _0: Self = Self::new(0);
8889
8890 #[doc = "Non-secure"]
8891 pub const _1: Self = Self::new(1);
8892 }
8893 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8894 pub struct Dpfsa19_SPEC;
8895 pub type Dpfsa19 = crate::EnumBitfieldStruct<u8, Dpfsa19_SPEC>;
8896 impl Dpfsa19 {
8897 #[doc = "Secure"]
8898 pub const _0: Self = Self::new(0);
8899
8900 #[doc = "Non-secure"]
8901 pub const _1: Self = Self::new(1);
8902 }
8903 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8904 pub struct Dpfsa20_SPEC;
8905 pub type Dpfsa20 = crate::EnumBitfieldStruct<u8, Dpfsa20_SPEC>;
8906 impl Dpfsa20 {
8907 #[doc = "Secure"]
8908 pub const _0: Self = Self::new(0);
8909
8910 #[doc = "Non-secure"]
8911 pub const _1: Self = Self::new(1);
8912 }
8913 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8914 pub struct Dpfsa24_SPEC;
8915 pub type Dpfsa24 = crate::EnumBitfieldStruct<u8, Dpfsa24_SPEC>;
8916 impl Dpfsa24 {
8917 #[doc = "Secure"]
8918 pub const _0: Self = Self::new(0);
8919
8920 #[doc = "Non-secure"]
8921 pub const _1: Self = Self::new(1);
8922 }
8923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8924 pub struct Dpfsa26_SPEC;
8925 pub type Dpfsa26 = crate::EnumBitfieldStruct<u8, Dpfsa26_SPEC>;
8926 impl Dpfsa26 {
8927 #[doc = "Secure"]
8928 pub const _0: Self = Self::new(0);
8929
8930 #[doc = "Non-secure"]
8931 pub const _1: Self = Self::new(1);
8932 }
8933 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8934 pub struct Dpfsa27_SPEC;
8935 pub type Dpfsa27 = crate::EnumBitfieldStruct<u8, Dpfsa27_SPEC>;
8936 impl Dpfsa27 {
8937 #[doc = "Secure"]
8938 pub const _0: Self = Self::new(0);
8939
8940 #[doc = "Non-secure"]
8941 pub const _1: Self = Self::new(1);
8942 }
8943 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8944 pub struct Dpfsa29_SPEC;
8945 pub type Dpfsa29 = crate::EnumBitfieldStruct<u8, Dpfsa29_SPEC>;
8946 impl Dpfsa29 {
8947 #[doc = "Secure"]
8948 pub const _0: Self = Self::new(0);
8949
8950 #[doc = "Non-secure"]
8951 pub const _1: Self = Self::new(1);
8952 }
8953 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8954 pub struct Dpfsa31_SPEC;
8955 pub type Dpfsa31 = crate::EnumBitfieldStruct<u8, Dpfsa31_SPEC>;
8956 impl Dpfsa31 {
8957 #[doc = "Secure"]
8958 pub const _0: Self = Self::new(0);
8959
8960 #[doc = "Non-secure"]
8961 pub const _1: Self = Self::new(1);
8962 }
8963}
8964#[doc(hidden)]
8965#[derive(Copy, Clone, Eq, PartialEq)]
8966pub struct Rscsar_SPEC;
8967impl crate::sealed::RegSpec for Rscsar_SPEC {
8968 type DataType = u32;
8969}
8970
8971#[doc = "RAM Standby Control Security Attribution Register"]
8972pub type Rscsar = crate::RegValueT<Rscsar_SPEC>;
8973
8974impl Rscsar {
8975 #[doc = "Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)"]
8976 #[inline(always)]
8977 pub fn rscsa0(
8978 self,
8979 ) -> crate::common::RegisterField<
8980 0,
8981 0x1,
8982 1,
8983 0,
8984 rscsar::Rscsa0,
8985 rscsar::Rscsa0,
8986 Rscsar_SPEC,
8987 crate::common::RW,
8988 > {
8989 crate::common::RegisterField::<
8990 0,
8991 0x1,
8992 1,
8993 0,
8994 rscsar::Rscsa0,
8995 rscsar::Rscsa0,
8996 Rscsar_SPEC,
8997 crate::common::RW,
8998 >::from_register(self, 0)
8999 }
9000
9001 #[doc = "Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)"]
9002 #[inline(always)]
9003 pub fn rscsa1(
9004 self,
9005 ) -> crate::common::RegisterField<
9006 1,
9007 0x1,
9008 1,
9009 0,
9010 rscsar::Rscsa1,
9011 rscsar::Rscsa1,
9012 Rscsar_SPEC,
9013 crate::common::RW,
9014 > {
9015 crate::common::RegisterField::<
9016 1,
9017 0x1,
9018 1,
9019 0,
9020 rscsar::Rscsa1,
9021 rscsar::Rscsa1,
9022 Rscsar_SPEC,
9023 crate::common::RW,
9024 >::from_register(self, 0)
9025 }
9026
9027 #[doc = "RAM Standby Control Security Attribute bit n (n = 2 to 6)"]
9028 #[inline(always)]
9029 pub fn rscsa2(
9030 self,
9031 ) -> crate::common::RegisterField<
9032 2,
9033 0x1,
9034 1,
9035 0,
9036 rscsar::Rscsa2,
9037 rscsar::Rscsa2,
9038 Rscsar_SPEC,
9039 crate::common::RW,
9040 > {
9041 crate::common::RegisterField::<
9042 2,
9043 0x1,
9044 1,
9045 0,
9046 rscsar::Rscsa2,
9047 rscsar::Rscsa2,
9048 Rscsar_SPEC,
9049 crate::common::RW,
9050 >::from_register(self, 0)
9051 }
9052
9053 #[doc = "RAM Standby Control Security Attribute bit n (n = 2 to 6)"]
9054 #[inline(always)]
9055 pub fn rscsa3(
9056 self,
9057 ) -> crate::common::RegisterField<
9058 3,
9059 0x1,
9060 1,
9061 0,
9062 rscsar::Rscsa3,
9063 rscsar::Rscsa3,
9064 Rscsar_SPEC,
9065 crate::common::RW,
9066 > {
9067 crate::common::RegisterField::<
9068 3,
9069 0x1,
9070 1,
9071 0,
9072 rscsar::Rscsa3,
9073 rscsar::Rscsa3,
9074 Rscsar_SPEC,
9075 crate::common::RW,
9076 >::from_register(self, 0)
9077 }
9078
9079 #[doc = "RAM Standby Control Security Attribute bit n (n = 2 to 6)"]
9080 #[inline(always)]
9081 pub fn rscsa4(
9082 self,
9083 ) -> crate::common::RegisterField<
9084 4,
9085 0x1,
9086 1,
9087 0,
9088 rscsar::Rscsa4,
9089 rscsar::Rscsa4,
9090 Rscsar_SPEC,
9091 crate::common::RW,
9092 > {
9093 crate::common::RegisterField::<
9094 4,
9095 0x1,
9096 1,
9097 0,
9098 rscsar::Rscsa4,
9099 rscsar::Rscsa4,
9100 Rscsar_SPEC,
9101 crate::common::RW,
9102 >::from_register(self, 0)
9103 }
9104
9105 #[doc = "RAM Standby Control Security Attribute bit n (n = 2 to 6)"]
9106 #[inline(always)]
9107 pub fn rscsa5(
9108 self,
9109 ) -> crate::common::RegisterField<
9110 5,
9111 0x1,
9112 1,
9113 0,
9114 rscsar::Rscsa5,
9115 rscsar::Rscsa5,
9116 Rscsar_SPEC,
9117 crate::common::RW,
9118 > {
9119 crate::common::RegisterField::<
9120 5,
9121 0x1,
9122 1,
9123 0,
9124 rscsar::Rscsa5,
9125 rscsar::Rscsa5,
9126 Rscsar_SPEC,
9127 crate::common::RW,
9128 >::from_register(self, 0)
9129 }
9130
9131 #[doc = "RAM Standby Control Security Attribute bit n (n = 2 to 6)"]
9132 #[inline(always)]
9133 pub fn rscsa6(
9134 self,
9135 ) -> crate::common::RegisterField<
9136 6,
9137 0x1,
9138 1,
9139 0,
9140 rscsar::Rscsa6,
9141 rscsar::Rscsa6,
9142 Rscsar_SPEC,
9143 crate::common::RW,
9144 > {
9145 crate::common::RegisterField::<
9146 6,
9147 0x1,
9148 1,
9149 0,
9150 rscsar::Rscsa6,
9151 rscsar::Rscsa6,
9152 Rscsar_SPEC,
9153 crate::common::RW,
9154 >::from_register(self, 0)
9155 }
9156
9157 #[doc = "RAM Standby Control Security Attribute bit n (n = 16)"]
9158 #[inline(always)]
9159 pub fn rscsa16(
9160 self,
9161 ) -> crate::common::RegisterField<
9162 16,
9163 0x1,
9164 1,
9165 0,
9166 rscsar::Rscsa16,
9167 rscsar::Rscsa16,
9168 Rscsar_SPEC,
9169 crate::common::RW,
9170 > {
9171 crate::common::RegisterField::<
9172 16,
9173 0x1,
9174 1,
9175 0,
9176 rscsar::Rscsa16,
9177 rscsar::Rscsa16,
9178 Rscsar_SPEC,
9179 crate::common::RW,
9180 >::from_register(self, 0)
9181 }
9182}
9183impl ::core::default::Default for Rscsar {
9184 #[inline(always)]
9185 fn default() -> Rscsar {
9186 <crate::RegValueT<Rscsar_SPEC> as RegisterValue<_>>::new(0)
9187 }
9188}
9189pub mod rscsar {
9190
9191 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9192 pub struct Rscsa0_SPEC;
9193 pub type Rscsa0 = crate::EnumBitfieldStruct<u8, Rscsa0_SPEC>;
9194 impl Rscsa0 {
9195 #[doc = "Secure"]
9196 pub const _0: Self = Self::new(0);
9197
9198 #[doc = "Non-secure"]
9199 pub const _1: Self = Self::new(1);
9200 }
9201 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9202 pub struct Rscsa1_SPEC;
9203 pub type Rscsa1 = crate::EnumBitfieldStruct<u8, Rscsa1_SPEC>;
9204 impl Rscsa1 {
9205 #[doc = "Secure"]
9206 pub const _0: Self = Self::new(0);
9207
9208 #[doc = "Non-secure"]
9209 pub const _1: Self = Self::new(1);
9210 }
9211 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9212 pub struct Rscsa2_SPEC;
9213 pub type Rscsa2 = crate::EnumBitfieldStruct<u8, Rscsa2_SPEC>;
9214 impl Rscsa2 {
9215 #[doc = "Secure"]
9216 pub const _0: Self = Self::new(0);
9217
9218 #[doc = "Non-secure"]
9219 pub const _1: Self = Self::new(1);
9220 }
9221 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9222 pub struct Rscsa3_SPEC;
9223 pub type Rscsa3 = crate::EnumBitfieldStruct<u8, Rscsa3_SPEC>;
9224 impl Rscsa3 {
9225 #[doc = "Secure"]
9226 pub const _0: Self = Self::new(0);
9227
9228 #[doc = "Non-secure"]
9229 pub const _1: Self = Self::new(1);
9230 }
9231 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9232 pub struct Rscsa4_SPEC;
9233 pub type Rscsa4 = crate::EnumBitfieldStruct<u8, Rscsa4_SPEC>;
9234 impl Rscsa4 {
9235 #[doc = "Secure"]
9236 pub const _0: Self = Self::new(0);
9237
9238 #[doc = "Non-secure"]
9239 pub const _1: Self = Self::new(1);
9240 }
9241 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9242 pub struct Rscsa5_SPEC;
9243 pub type Rscsa5 = crate::EnumBitfieldStruct<u8, Rscsa5_SPEC>;
9244 impl Rscsa5 {
9245 #[doc = "Secure"]
9246 pub const _0: Self = Self::new(0);
9247
9248 #[doc = "Non-secure"]
9249 pub const _1: Self = Self::new(1);
9250 }
9251 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9252 pub struct Rscsa6_SPEC;
9253 pub type Rscsa6 = crate::EnumBitfieldStruct<u8, Rscsa6_SPEC>;
9254 impl Rscsa6 {
9255 #[doc = "Secure"]
9256 pub const _0: Self = Self::new(0);
9257
9258 #[doc = "Non-secure"]
9259 pub const _1: Self = Self::new(1);
9260 }
9261 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9262 pub struct Rscsa16_SPEC;
9263 pub type Rscsa16 = crate::EnumBitfieldStruct<u8, Rscsa16_SPEC>;
9264 impl Rscsa16 {
9265 #[doc = "Secure"]
9266 pub const _0: Self = Self::new(0);
9267
9268 #[doc = "Non-secure"]
9269 pub const _1: Self = Self::new(1);
9270 }
9271}
9272#[doc(hidden)]
9273#[derive(Copy, Clone, Eq, PartialEq)]
9274pub struct PrcrNs_SPEC;
9275impl crate::sealed::RegSpec for PrcrNs_SPEC {
9276 type DataType = u16;
9277}
9278
9279#[doc = "Protect Register for Non-secure (PRCR_NS)"]
9280pub type PrcrNs = crate::RegValueT<PrcrNs_SPEC>;
9281
9282impl PrcrNs {
9283 #[doc = "Enable writing to the registers related to the clock generation circuit"]
9284 #[inline(always)]
9285 pub fn prc0(
9286 self,
9287 ) -> crate::common::RegisterField<
9288 0,
9289 0x1,
9290 1,
9291 0,
9292 prcr_ns::Prc0,
9293 prcr_ns::Prc0,
9294 PrcrNs_SPEC,
9295 crate::common::RW,
9296 > {
9297 crate::common::RegisterField::<
9298 0,
9299 0x1,
9300 1,
9301 0,
9302 prcr_ns::Prc0,
9303 prcr_ns::Prc0,
9304 PrcrNs_SPEC,
9305 crate::common::RW,
9306 >::from_register(self, 0)
9307 }
9308
9309 #[doc = "Enable writing to the registers related to the low power modes, and the battery backup function"]
9310 #[inline(always)]
9311 pub fn prc1(
9312 self,
9313 ) -> crate::common::RegisterField<
9314 1,
9315 0x1,
9316 1,
9317 0,
9318 prcr_ns::Prc1,
9319 prcr_ns::Prc1,
9320 PrcrNs_SPEC,
9321 crate::common::RW,
9322 > {
9323 crate::common::RegisterField::<
9324 1,
9325 0x1,
9326 1,
9327 0,
9328 prcr_ns::Prc1,
9329 prcr_ns::Prc1,
9330 PrcrNs_SPEC,
9331 crate::common::RW,
9332 >::from_register(self, 0)
9333 }
9334
9335 #[doc = "Enable writing to the registers related to the PVD"]
9336 #[inline(always)]
9337 pub fn prc3(
9338 self,
9339 ) -> crate::common::RegisterField<
9340 3,
9341 0x1,
9342 1,
9343 0,
9344 prcr_ns::Prc3,
9345 prcr_ns::Prc3,
9346 PrcrNs_SPEC,
9347 crate::common::RW,
9348 > {
9349 crate::common::RegisterField::<
9350 3,
9351 0x1,
9352 1,
9353 0,
9354 prcr_ns::Prc3,
9355 prcr_ns::Prc3,
9356 PrcrNs_SPEC,
9357 crate::common::RW,
9358 >::from_register(self, 0)
9359 }
9360
9361 #[inline(always)]
9362 pub fn prc4(
9363 self,
9364 ) -> crate::common::RegisterField<
9365 4,
9366 0x1,
9367 1,
9368 0,
9369 prcr_ns::Prc4,
9370 prcr_ns::Prc4,
9371 PrcrNs_SPEC,
9372 crate::common::RW,
9373 > {
9374 crate::common::RegisterField::<
9375 4,
9376 0x1,
9377 1,
9378 0,
9379 prcr_ns::Prc4,
9380 prcr_ns::Prc4,
9381 PrcrNs_SPEC,
9382 crate::common::RW,
9383 >::from_register(self, 0)
9384 }
9385
9386 #[doc = "0xA5: Enables writing to the PRCR_NS register."]
9387 #[inline(always)]
9388 pub fn prkey(
9389 self,
9390 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, PrcrNs_SPEC, crate::common::W> {
9391 crate::common::RegisterField::<8,0xff,1,0,u8,u8,PrcrNs_SPEC,crate::common::W>::from_register(self,0)
9392 }
9393}
9394impl ::core::default::Default for PrcrNs {
9395 #[inline(always)]
9396 fn default() -> PrcrNs {
9397 <crate::RegValueT<PrcrNs_SPEC> as RegisterValue<_>>::new(0)
9398 }
9399}
9400pub mod prcr_ns {
9401
9402 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9403 pub struct Prc0_SPEC;
9404 pub type Prc0 = crate::EnumBitfieldStruct<u8, Prc0_SPEC>;
9405 impl Prc0 {
9406 #[doc = "Disable writes"]
9407 pub const _0: Self = Self::new(0);
9408
9409 #[doc = "Enable writes"]
9410 pub const _1: Self = Self::new(1);
9411 }
9412 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9413 pub struct Prc1_SPEC;
9414 pub type Prc1 = crate::EnumBitfieldStruct<u8, Prc1_SPEC>;
9415 impl Prc1 {
9416 #[doc = "Disable writes"]
9417 pub const _0: Self = Self::new(0);
9418
9419 #[doc = "Enable writes"]
9420 pub const _1: Self = Self::new(1);
9421 }
9422 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9423 pub struct Prc3_SPEC;
9424 pub type Prc3 = crate::EnumBitfieldStruct<u8, Prc3_SPEC>;
9425 impl Prc3 {
9426 #[doc = "Disable writes"]
9427 pub const _0: Self = Self::new(0);
9428
9429 #[doc = "Enable writes"]
9430 pub const _1: Self = Self::new(1);
9431 }
9432 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9433 pub struct Prc4_SPEC;
9434 pub type Prc4 = crate::EnumBitfieldStruct<u8, Prc4_SPEC>;
9435 impl Prc4 {
9436 #[doc = "Disable writes"]
9437 pub const _0: Self = Self::new(0);
9438
9439 #[doc = "Enable writes"]
9440 pub const _1: Self = Self::new(1);
9441 }
9442}
9443#[doc(hidden)]
9444#[derive(Copy, Clone, Eq, PartialEq)]
9445pub struct Lococr_SPEC;
9446impl crate::sealed::RegSpec for Lococr_SPEC {
9447 type DataType = u8;
9448}
9449
9450#[doc = "Low-Speed On-Chip Oscillator Control Register"]
9451pub type Lococr = crate::RegValueT<Lococr_SPEC>;
9452
9453impl Lococr {
9454 #[doc = "LOCO Stop"]
9455 #[inline(always)]
9456 pub fn lcstp(
9457 self,
9458 ) -> crate::common::RegisterField<
9459 0,
9460 0x1,
9461 1,
9462 0,
9463 lococr::Lcstp,
9464 lococr::Lcstp,
9465 Lococr_SPEC,
9466 crate::common::RW,
9467 > {
9468 crate::common::RegisterField::<
9469 0,
9470 0x1,
9471 1,
9472 0,
9473 lococr::Lcstp,
9474 lococr::Lcstp,
9475 Lococr_SPEC,
9476 crate::common::RW,
9477 >::from_register(self, 0)
9478 }
9479}
9480impl ::core::default::Default for Lococr {
9481 #[inline(always)]
9482 fn default() -> Lococr {
9483 <crate::RegValueT<Lococr_SPEC> as RegisterValue<_>>::new(0)
9484 }
9485}
9486pub mod lococr {
9487
9488 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9489 pub struct Lcstp_SPEC;
9490 pub type Lcstp = crate::EnumBitfieldStruct<u8, Lcstp_SPEC>;
9491 impl Lcstp {
9492 #[doc = "Operate the LOCO clock"]
9493 pub const _0: Self = Self::new(0);
9494
9495 #[doc = "Stop the LOCO clock"]
9496 pub const _1: Self = Self::new(1);
9497 }
9498}
9499#[doc(hidden)]
9500#[derive(Copy, Clone, Eq, PartialEq)]
9501pub struct Locoutcr_SPEC;
9502impl crate::sealed::RegSpec for Locoutcr_SPEC {
9503 type DataType = u8;
9504}
9505
9506#[doc = "LOCO User Trimming Control Register"]
9507pub type Locoutcr = crate::RegValueT<Locoutcr_SPEC>;
9508
9509impl Locoutcr {
9510 #[doc = "LOCO User Trimming"]
9511 #[inline(always)]
9512 pub fn locoutrm(
9513 self,
9514 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Locoutcr_SPEC, crate::common::RW> {
9515 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Locoutcr_SPEC,crate::common::RW>::from_register(self,0)
9516 }
9517}
9518impl ::core::default::Default for Locoutcr {
9519 #[inline(always)]
9520 fn default() -> Locoutcr {
9521 <crate::RegValueT<Locoutcr_SPEC> as RegisterValue<_>>::new(0)
9522 }
9523}
9524
9525#[doc(hidden)]
9526#[derive(Copy, Clone, Eq, PartialEq)]
9527pub struct Dpsbycr_SPEC;
9528impl crate::sealed::RegSpec for Dpsbycr_SPEC {
9529 type DataType = u8;
9530}
9531
9532#[doc = "Deep Software Standby Control Register"]
9533pub type Dpsbycr = crate::RegValueT<Dpsbycr_SPEC>;
9534
9535impl Dpsbycr {
9536 #[inline(always)]
9537 pub fn dcssmode(
9538 self,
9539 ) -> crate::common::RegisterField<
9540 2,
9541 0x1,
9542 1,
9543 0,
9544 dpsbycr::Dcssmode,
9545 dpsbycr::Dcssmode,
9546 Dpsbycr_SPEC,
9547 crate::common::RW,
9548 > {
9549 crate::common::RegisterField::<
9550 2,
9551 0x1,
9552 1,
9553 0,
9554 dpsbycr::Dcssmode,
9555 dpsbycr::Dcssmode,
9556 Dpsbycr_SPEC,
9557 crate::common::RW,
9558 >::from_register(self, 0)
9559 }
9560
9561 #[doc = "Standby SRAM Retention"]
9562 #[inline(always)]
9563 pub fn srkeep(
9564 self,
9565 ) -> crate::common::RegisterField<
9566 4,
9567 0x1,
9568 1,
9569 0,
9570 dpsbycr::Srkeep,
9571 dpsbycr::Srkeep,
9572 Dpsbycr_SPEC,
9573 crate::common::RW,
9574 > {
9575 crate::common::RegisterField::<
9576 4,
9577 0x1,
9578 1,
9579 0,
9580 dpsbycr::Srkeep,
9581 dpsbycr::Srkeep,
9582 Dpsbycr_SPEC,
9583 crate::common::RW,
9584 >::from_register(self, 0)
9585 }
9586
9587 #[doc = "I/O Port Rentention"]
9588 #[inline(always)]
9589 pub fn iokeep(
9590 self,
9591 ) -> crate::common::RegisterField<
9592 6,
9593 0x1,
9594 1,
9595 0,
9596 dpsbycr::Iokeep,
9597 dpsbycr::Iokeep,
9598 Dpsbycr_SPEC,
9599 crate::common::RW,
9600 > {
9601 crate::common::RegisterField::<
9602 6,
9603 0x1,
9604 1,
9605 0,
9606 dpsbycr::Iokeep,
9607 dpsbycr::Iokeep,
9608 Dpsbycr_SPEC,
9609 crate::common::RW,
9610 >::from_register(self, 0)
9611 }
9612}
9613impl ::core::default::Default for Dpsbycr {
9614 #[inline(always)]
9615 fn default() -> Dpsbycr {
9616 <crate::RegValueT<Dpsbycr_SPEC> as RegisterValue<_>>::new(16)
9617 }
9618}
9619pub mod dpsbycr {
9620
9621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9622 pub struct Dcssmode_SPEC;
9623 pub type Dcssmode = crate::EnumBitfieldStruct<u8, Dcssmode_SPEC>;
9624 impl Dcssmode {
9625 #[doc = "When the Deep Software Standby mode is canceled, the time required to recover is the standard time."]
9626 pub const _0: Self = Self::new(0);
9627
9628 #[doc = "When the Deep Software Standby mode is canceled, the time required to recover is shortened."]
9629 pub const _1: Self = Self::new(1);
9630 }
9631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9632 pub struct Srkeep_SPEC;
9633 pub type Srkeep = crate::EnumBitfieldStruct<u8, Srkeep_SPEC>;
9634 impl Srkeep {
9635 #[doc = "When entering the Software Standby mode or the Deep Software Standby mode 1, the contents of Standby SRAM are not kept."]
9636 pub const _0: Self = Self::new(0);
9637
9638 #[doc = "When entering the Software Standby mode or the Deep Software Standby mode 1, the contents of Standby SRAM are kept."]
9639 pub const _1: Self = Self::new(1);
9640 }
9641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9642 pub struct Iokeep_SPEC;
9643 pub type Iokeep = crate::EnumBitfieldStruct<u8, Iokeep_SPEC>;
9644 impl Iokeep {
9645 #[doc = "When the Deep Software Standby mode is canceled, the I/O ports are in the reset state."]
9646 pub const _0: Self = Self::new(0);
9647
9648 #[doc = "When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode."]
9649 pub const _1: Self = Self::new(1);
9650 }
9651}
9652#[doc(hidden)]
9653#[derive(Copy, Clone, Eq, PartialEq)]
9654pub struct Dpswcr_SPEC;
9655impl crate::sealed::RegSpec for Dpswcr_SPEC {
9656 type DataType = u8;
9657}
9658
9659#[doc = "Deep Software Standby Wait Control Register"]
9660pub type Dpswcr = crate::RegValueT<Dpswcr_SPEC>;
9661
9662impl Dpswcr {
9663 #[doc = "Deep Software Wait Standby Time Setting Bit"]
9664 #[inline(always)]
9665 pub fn wtsts(
9666 self,
9667 ) -> crate::common::RegisterField<
9668 0,
9669 0xff,
9670 1,
9671 0,
9672 dpswcr::Wtsts,
9673 dpswcr::Wtsts,
9674 Dpswcr_SPEC,
9675 crate::common::RW,
9676 > {
9677 crate::common::RegisterField::<
9678 0,
9679 0xff,
9680 1,
9681 0,
9682 dpswcr::Wtsts,
9683 dpswcr::Wtsts,
9684 Dpswcr_SPEC,
9685 crate::common::RW,
9686 >::from_register(self, 0)
9687 }
9688}
9689impl ::core::default::Default for Dpswcr {
9690 #[inline(always)]
9691 fn default() -> Dpswcr {
9692 <crate::RegValueT<Dpswcr_SPEC> as RegisterValue<_>>::new(11)
9693 }
9694}
9695pub mod dpswcr {
9696
9697 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9698 pub struct Wtsts_SPEC;
9699 pub type Wtsts = crate::EnumBitfieldStruct<u8, Wtsts_SPEC>;
9700 impl Wtsts {
9701 #[doc = "Wait cycle for fast recovery"]
9702 pub const _0_X_0_B: Self = Self::new(11);
9703
9704 #[doc = "Wait cycle for slow recovery"]
9705 pub const _0_X_9_A: Self = Self::new(154);
9706
9707 #[doc = "Setting prohibited"]
9708 pub const OTHERS: Self = Self::new(0);
9709 }
9710}
9711#[doc(hidden)]
9712#[derive(Copy, Clone, Eq, PartialEq)]
9713pub struct Dpsier0_SPEC;
9714impl crate::sealed::RegSpec for Dpsier0_SPEC {
9715 type DataType = u8;
9716}
9717
9718#[doc = "Deep Software Standby Interrupt Enable Register 0"]
9719pub type Dpsier0 = crate::RegValueT<Dpsier0_SPEC>;
9720
9721impl Dpsier0 {
9722 #[doc = "IRQ0-DS Pin Enable"]
9723 #[inline(always)]
9724 pub fn dirq0e(
9725 self,
9726 ) -> crate::common::RegisterField<
9727 0,
9728 0x1,
9729 1,
9730 0,
9731 dpsier0::Dirq0E,
9732 dpsier0::Dirq0E,
9733 Dpsier0_SPEC,
9734 crate::common::RW,
9735 > {
9736 crate::common::RegisterField::<
9737 0,
9738 0x1,
9739 1,
9740 0,
9741 dpsier0::Dirq0E,
9742 dpsier0::Dirq0E,
9743 Dpsier0_SPEC,
9744 crate::common::RW,
9745 >::from_register(self, 0)
9746 }
9747
9748 #[doc = "IRQ1-DS Pin Enable"]
9749 #[inline(always)]
9750 pub fn dirq1e(
9751 self,
9752 ) -> crate::common::RegisterField<
9753 1,
9754 0x1,
9755 1,
9756 0,
9757 dpsier0::Dirq1E,
9758 dpsier0::Dirq1E,
9759 Dpsier0_SPEC,
9760 crate::common::RW,
9761 > {
9762 crate::common::RegisterField::<
9763 1,
9764 0x1,
9765 1,
9766 0,
9767 dpsier0::Dirq1E,
9768 dpsier0::Dirq1E,
9769 Dpsier0_SPEC,
9770 crate::common::RW,
9771 >::from_register(self, 0)
9772 }
9773
9774 #[doc = "IRQ2-DS Pin Enable"]
9775 #[inline(always)]
9776 pub fn dirq2e(
9777 self,
9778 ) -> crate::common::RegisterField<
9779 2,
9780 0x1,
9781 1,
9782 0,
9783 dpsier0::Dirq2E,
9784 dpsier0::Dirq2E,
9785 Dpsier0_SPEC,
9786 crate::common::RW,
9787 > {
9788 crate::common::RegisterField::<
9789 2,
9790 0x1,
9791 1,
9792 0,
9793 dpsier0::Dirq2E,
9794 dpsier0::Dirq2E,
9795 Dpsier0_SPEC,
9796 crate::common::RW,
9797 >::from_register(self, 0)
9798 }
9799
9800 #[doc = "IRQ3-DS Pin Enable"]
9801 #[inline(always)]
9802 pub fn dirq3e(
9803 self,
9804 ) -> crate::common::RegisterField<
9805 3,
9806 0x1,
9807 1,
9808 0,
9809 dpsier0::Dirq3E,
9810 dpsier0::Dirq3E,
9811 Dpsier0_SPEC,
9812 crate::common::RW,
9813 > {
9814 crate::common::RegisterField::<
9815 3,
9816 0x1,
9817 1,
9818 0,
9819 dpsier0::Dirq3E,
9820 dpsier0::Dirq3E,
9821 Dpsier0_SPEC,
9822 crate::common::RW,
9823 >::from_register(self, 0)
9824 }
9825
9826 #[doc = "IRQ4-DS Pin Enable"]
9827 #[inline(always)]
9828 pub fn dirq4e(
9829 self,
9830 ) -> crate::common::RegisterField<
9831 4,
9832 0x1,
9833 1,
9834 0,
9835 dpsier0::Dirq4E,
9836 dpsier0::Dirq4E,
9837 Dpsier0_SPEC,
9838 crate::common::RW,
9839 > {
9840 crate::common::RegisterField::<
9841 4,
9842 0x1,
9843 1,
9844 0,
9845 dpsier0::Dirq4E,
9846 dpsier0::Dirq4E,
9847 Dpsier0_SPEC,
9848 crate::common::RW,
9849 >::from_register(self, 0)
9850 }
9851
9852 #[doc = "IRQ5-DS Pin Enable"]
9853 #[inline(always)]
9854 pub fn dirq5e(
9855 self,
9856 ) -> crate::common::RegisterField<
9857 5,
9858 0x1,
9859 1,
9860 0,
9861 dpsier0::Dirq5E,
9862 dpsier0::Dirq5E,
9863 Dpsier0_SPEC,
9864 crate::common::RW,
9865 > {
9866 crate::common::RegisterField::<
9867 5,
9868 0x1,
9869 1,
9870 0,
9871 dpsier0::Dirq5E,
9872 dpsier0::Dirq5E,
9873 Dpsier0_SPEC,
9874 crate::common::RW,
9875 >::from_register(self, 0)
9876 }
9877
9878 #[doc = "IRQ6-DS Pin Enable"]
9879 #[inline(always)]
9880 pub fn dirq6e(
9881 self,
9882 ) -> crate::common::RegisterField<
9883 6,
9884 0x1,
9885 1,
9886 0,
9887 dpsier0::Dirq6E,
9888 dpsier0::Dirq6E,
9889 Dpsier0_SPEC,
9890 crate::common::RW,
9891 > {
9892 crate::common::RegisterField::<
9893 6,
9894 0x1,
9895 1,
9896 0,
9897 dpsier0::Dirq6E,
9898 dpsier0::Dirq6E,
9899 Dpsier0_SPEC,
9900 crate::common::RW,
9901 >::from_register(self, 0)
9902 }
9903
9904 #[doc = "IRQ7-DS Pin Enable"]
9905 #[inline(always)]
9906 pub fn dirq7e(
9907 self,
9908 ) -> crate::common::RegisterField<
9909 7,
9910 0x1,
9911 1,
9912 0,
9913 dpsier0::Dirq7E,
9914 dpsier0::Dirq7E,
9915 Dpsier0_SPEC,
9916 crate::common::RW,
9917 > {
9918 crate::common::RegisterField::<
9919 7,
9920 0x1,
9921 1,
9922 0,
9923 dpsier0::Dirq7E,
9924 dpsier0::Dirq7E,
9925 Dpsier0_SPEC,
9926 crate::common::RW,
9927 >::from_register(self, 0)
9928 }
9929}
9930impl ::core::default::Default for Dpsier0 {
9931 #[inline(always)]
9932 fn default() -> Dpsier0 {
9933 <crate::RegValueT<Dpsier0_SPEC> as RegisterValue<_>>::new(0)
9934 }
9935}
9936pub mod dpsier0 {
9937
9938 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9939 pub struct Dirq0E_SPEC;
9940 pub type Dirq0E = crate::EnumBitfieldStruct<u8, Dirq0E_SPEC>;
9941 impl Dirq0E {
9942 #[doc = "Canceling Deep Software Standby mode is disabled"]
9943 pub const _0: Self = Self::new(0);
9944
9945 #[doc = "Canceling Deep Software Standby mode is enabled"]
9946 pub const _1: Self = Self::new(1);
9947 }
9948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9949 pub struct Dirq1E_SPEC;
9950 pub type Dirq1E = crate::EnumBitfieldStruct<u8, Dirq1E_SPEC>;
9951 impl Dirq1E {
9952 #[doc = "Canceling Deep Software Standby mode is disabled"]
9953 pub const _0: Self = Self::new(0);
9954
9955 #[doc = "Canceling Deep Software Standby mode is enabled"]
9956 pub const _1: Self = Self::new(1);
9957 }
9958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9959 pub struct Dirq2E_SPEC;
9960 pub type Dirq2E = crate::EnumBitfieldStruct<u8, Dirq2E_SPEC>;
9961 impl Dirq2E {
9962 #[doc = "Canceling Deep Software Standby mode is disabled"]
9963 pub const _0: Self = Self::new(0);
9964
9965 #[doc = "Canceling Deep Software Standby mode is enabled"]
9966 pub const _1: Self = Self::new(1);
9967 }
9968 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9969 pub struct Dirq3E_SPEC;
9970 pub type Dirq3E = crate::EnumBitfieldStruct<u8, Dirq3E_SPEC>;
9971 impl Dirq3E {
9972 #[doc = "Canceling Deep Software Standby mode is disabled"]
9973 pub const _0: Self = Self::new(0);
9974
9975 #[doc = "Canceling Deep Software Standby mode is enabled"]
9976 pub const _1: Self = Self::new(1);
9977 }
9978 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9979 pub struct Dirq4E_SPEC;
9980 pub type Dirq4E = crate::EnumBitfieldStruct<u8, Dirq4E_SPEC>;
9981 impl Dirq4E {
9982 #[doc = "Canceling Deep Software Standby mode is disabled"]
9983 pub const _0: Self = Self::new(0);
9984
9985 #[doc = "Canceling Deep Software Standby mode is enabled"]
9986 pub const _1: Self = Self::new(1);
9987 }
9988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9989 pub struct Dirq5E_SPEC;
9990 pub type Dirq5E = crate::EnumBitfieldStruct<u8, Dirq5E_SPEC>;
9991 impl Dirq5E {
9992 #[doc = "Canceling Deep Software Standby mode is disabled"]
9993 pub const _0: Self = Self::new(0);
9994
9995 #[doc = "Canceling Deep Software Standby mode is enabled"]
9996 pub const _1: Self = Self::new(1);
9997 }
9998 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9999 pub struct Dirq6E_SPEC;
10000 pub type Dirq6E = crate::EnumBitfieldStruct<u8, Dirq6E_SPEC>;
10001 impl Dirq6E {
10002 #[doc = "Canceling Deep Software Standby mode is disabled"]
10003 pub const _0: Self = Self::new(0);
10004
10005 #[doc = "Canceling Deep Software Standby mode is enabled"]
10006 pub const _1: Self = Self::new(1);
10007 }
10008 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10009 pub struct Dirq7E_SPEC;
10010 pub type Dirq7E = crate::EnumBitfieldStruct<u8, Dirq7E_SPEC>;
10011 impl Dirq7E {
10012 #[doc = "Canceling Deep Software Standby mode is disabled"]
10013 pub const _0: Self = Self::new(0);
10014
10015 #[doc = "Canceling Deep Software Standby mode is enabled"]
10016 pub const _1: Self = Self::new(1);
10017 }
10018}
10019#[doc(hidden)]
10020#[derive(Copy, Clone, Eq, PartialEq)]
10021pub struct Dpsier1_SPEC;
10022impl crate::sealed::RegSpec for Dpsier1_SPEC {
10023 type DataType = u8;
10024}
10025
10026#[doc = "Deep Software Standby Interrupt Enable Register 1"]
10027pub type Dpsier1 = crate::RegValueT<Dpsier1_SPEC>;
10028
10029impl Dpsier1 {
10030 #[doc = "IRQ8-DS Pin Enable"]
10031 #[inline(always)]
10032 pub fn dirq8e(
10033 self,
10034 ) -> crate::common::RegisterField<
10035 0,
10036 0x1,
10037 1,
10038 0,
10039 dpsier1::Dirq8E,
10040 dpsier1::Dirq8E,
10041 Dpsier1_SPEC,
10042 crate::common::RW,
10043 > {
10044 crate::common::RegisterField::<
10045 0,
10046 0x1,
10047 1,
10048 0,
10049 dpsier1::Dirq8E,
10050 dpsier1::Dirq8E,
10051 Dpsier1_SPEC,
10052 crate::common::RW,
10053 >::from_register(self, 0)
10054 }
10055
10056 #[doc = "IRQ9-DS Pin Enable"]
10057 #[inline(always)]
10058 pub fn dirq9e(
10059 self,
10060 ) -> crate::common::RegisterField<
10061 1,
10062 0x1,
10063 1,
10064 0,
10065 dpsier1::Dirq9E,
10066 dpsier1::Dirq9E,
10067 Dpsier1_SPEC,
10068 crate::common::RW,
10069 > {
10070 crate::common::RegisterField::<
10071 1,
10072 0x1,
10073 1,
10074 0,
10075 dpsier1::Dirq9E,
10076 dpsier1::Dirq9E,
10077 Dpsier1_SPEC,
10078 crate::common::RW,
10079 >::from_register(self, 0)
10080 }
10081
10082 #[doc = "IRQ10-DS Pin Enable"]
10083 #[inline(always)]
10084 pub fn dirq10e(
10085 self,
10086 ) -> crate::common::RegisterField<
10087 2,
10088 0x1,
10089 1,
10090 0,
10091 dpsier1::Dirq10E,
10092 dpsier1::Dirq10E,
10093 Dpsier1_SPEC,
10094 crate::common::RW,
10095 > {
10096 crate::common::RegisterField::<
10097 2,
10098 0x1,
10099 1,
10100 0,
10101 dpsier1::Dirq10E,
10102 dpsier1::Dirq10E,
10103 Dpsier1_SPEC,
10104 crate::common::RW,
10105 >::from_register(self, 0)
10106 }
10107
10108 #[doc = "IRQ11-DS Pin Enable"]
10109 #[inline(always)]
10110 pub fn dirq11e(
10111 self,
10112 ) -> crate::common::RegisterField<
10113 3,
10114 0x1,
10115 1,
10116 0,
10117 dpsier1::Dirq11E,
10118 dpsier1::Dirq11E,
10119 Dpsier1_SPEC,
10120 crate::common::RW,
10121 > {
10122 crate::common::RegisterField::<
10123 3,
10124 0x1,
10125 1,
10126 0,
10127 dpsier1::Dirq11E,
10128 dpsier1::Dirq11E,
10129 Dpsier1_SPEC,
10130 crate::common::RW,
10131 >::from_register(self, 0)
10132 }
10133
10134 #[doc = "IRQ12-DS Pin Enable"]
10135 #[inline(always)]
10136 pub fn dirq12e(
10137 self,
10138 ) -> crate::common::RegisterField<
10139 4,
10140 0x1,
10141 1,
10142 0,
10143 dpsier1::Dirq12E,
10144 dpsier1::Dirq12E,
10145 Dpsier1_SPEC,
10146 crate::common::RW,
10147 > {
10148 crate::common::RegisterField::<
10149 4,
10150 0x1,
10151 1,
10152 0,
10153 dpsier1::Dirq12E,
10154 dpsier1::Dirq12E,
10155 Dpsier1_SPEC,
10156 crate::common::RW,
10157 >::from_register(self, 0)
10158 }
10159
10160 #[doc = "IRQ13-DS Pin Enable"]
10161 #[inline(always)]
10162 pub fn dirq13e(
10163 self,
10164 ) -> crate::common::RegisterField<
10165 5,
10166 0x1,
10167 1,
10168 0,
10169 dpsier1::Dirq13E,
10170 dpsier1::Dirq13E,
10171 Dpsier1_SPEC,
10172 crate::common::RW,
10173 > {
10174 crate::common::RegisterField::<
10175 5,
10176 0x1,
10177 1,
10178 0,
10179 dpsier1::Dirq13E,
10180 dpsier1::Dirq13E,
10181 Dpsier1_SPEC,
10182 crate::common::RW,
10183 >::from_register(self, 0)
10184 }
10185
10186 #[doc = "IRQ14-DS Pin Enable"]
10187 #[inline(always)]
10188 pub fn dirq14e(
10189 self,
10190 ) -> crate::common::RegisterField<
10191 6,
10192 0x1,
10193 1,
10194 0,
10195 dpsier1::Dirq14E,
10196 dpsier1::Dirq14E,
10197 Dpsier1_SPEC,
10198 crate::common::RW,
10199 > {
10200 crate::common::RegisterField::<
10201 6,
10202 0x1,
10203 1,
10204 0,
10205 dpsier1::Dirq14E,
10206 dpsier1::Dirq14E,
10207 Dpsier1_SPEC,
10208 crate::common::RW,
10209 >::from_register(self, 0)
10210 }
10211
10212 #[doc = "IRQ15-DS Pin Enable"]
10213 #[inline(always)]
10214 pub fn dirq15e(
10215 self,
10216 ) -> crate::common::RegisterField<
10217 7,
10218 0x1,
10219 1,
10220 0,
10221 dpsier1::Dirq15E,
10222 dpsier1::Dirq15E,
10223 Dpsier1_SPEC,
10224 crate::common::RW,
10225 > {
10226 crate::common::RegisterField::<
10227 7,
10228 0x1,
10229 1,
10230 0,
10231 dpsier1::Dirq15E,
10232 dpsier1::Dirq15E,
10233 Dpsier1_SPEC,
10234 crate::common::RW,
10235 >::from_register(self, 0)
10236 }
10237}
10238impl ::core::default::Default for Dpsier1 {
10239 #[inline(always)]
10240 fn default() -> Dpsier1 {
10241 <crate::RegValueT<Dpsier1_SPEC> as RegisterValue<_>>::new(0)
10242 }
10243}
10244pub mod dpsier1 {
10245
10246 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10247 pub struct Dirq8E_SPEC;
10248 pub type Dirq8E = crate::EnumBitfieldStruct<u8, Dirq8E_SPEC>;
10249 impl Dirq8E {
10250 #[doc = "Canceling Deep Software Standby mode is disabled"]
10251 pub const _0: Self = Self::new(0);
10252
10253 #[doc = "Canceling Deep Software Standby mode is enabled"]
10254 pub const _1: Self = Self::new(1);
10255 }
10256 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10257 pub struct Dirq9E_SPEC;
10258 pub type Dirq9E = crate::EnumBitfieldStruct<u8, Dirq9E_SPEC>;
10259 impl Dirq9E {
10260 #[doc = "Canceling Deep Software Standby mode is disabled"]
10261 pub const _0: Self = Self::new(0);
10262
10263 #[doc = "Canceling Deep Software Standby mode is enabled"]
10264 pub const _1: Self = Self::new(1);
10265 }
10266 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10267 pub struct Dirq10E_SPEC;
10268 pub type Dirq10E = crate::EnumBitfieldStruct<u8, Dirq10E_SPEC>;
10269 impl Dirq10E {
10270 #[doc = "Canceling Deep Software Standby mode is disabled"]
10271 pub const _0: Self = Self::new(0);
10272
10273 #[doc = "Canceling Deep Software Standby mode is enabled"]
10274 pub const _1: Self = Self::new(1);
10275 }
10276 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10277 pub struct Dirq11E_SPEC;
10278 pub type Dirq11E = crate::EnumBitfieldStruct<u8, Dirq11E_SPEC>;
10279 impl Dirq11E {
10280 #[doc = "Canceling Deep Software Standby mode is disabled"]
10281 pub const _0: Self = Self::new(0);
10282
10283 #[doc = "Canceling Deep Software Standby mode is enabled"]
10284 pub const _1: Self = Self::new(1);
10285 }
10286 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10287 pub struct Dirq12E_SPEC;
10288 pub type Dirq12E = crate::EnumBitfieldStruct<u8, Dirq12E_SPEC>;
10289 impl Dirq12E {
10290 #[doc = "Canceling Deep Software Standby mode is disabled"]
10291 pub const _0: Self = Self::new(0);
10292
10293 #[doc = "Canceling Deep Software Standby mode is enabled"]
10294 pub const _1: Self = Self::new(1);
10295 }
10296 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10297 pub struct Dirq13E_SPEC;
10298 pub type Dirq13E = crate::EnumBitfieldStruct<u8, Dirq13E_SPEC>;
10299 impl Dirq13E {
10300 #[doc = "Canceling Deep Software Standby mode is disabled"]
10301 pub const _0: Self = Self::new(0);
10302
10303 #[doc = "Canceling Deep Software Standby mode is enabled"]
10304 pub const _1: Self = Self::new(1);
10305 }
10306 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10307 pub struct Dirq14E_SPEC;
10308 pub type Dirq14E = crate::EnumBitfieldStruct<u8, Dirq14E_SPEC>;
10309 impl Dirq14E {
10310 #[doc = "Canceling Deep Software Standby mode is disabled"]
10311 pub const _0: Self = Self::new(0);
10312
10313 #[doc = "Canceling Deep Software Standby mode is enabled"]
10314 pub const _1: Self = Self::new(1);
10315 }
10316 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10317 pub struct Dirq15E_SPEC;
10318 pub type Dirq15E = crate::EnumBitfieldStruct<u8, Dirq15E_SPEC>;
10319 impl Dirq15E {
10320 #[doc = "Canceling Deep Software Standby mode is disabled"]
10321 pub const _0: Self = Self::new(0);
10322
10323 #[doc = "Canceling Deep Software Standby mode is enabled"]
10324 pub const _1: Self = Self::new(1);
10325 }
10326}
10327#[doc(hidden)]
10328#[derive(Copy, Clone, Eq, PartialEq)]
10329pub struct Dpsier2_SPEC;
10330impl crate::sealed::RegSpec for Dpsier2_SPEC {
10331 type DataType = u8;
10332}
10333
10334#[doc = "Deep Software Standby Interrupt Enable Register 2"]
10335pub type Dpsier2 = crate::RegValueT<Dpsier2_SPEC>;
10336
10337impl Dpsier2 {
10338 #[doc = "PVD1 Deep Software Standby Cancel Signal Enable"]
10339 #[inline(always)]
10340 pub fn dpvd1ie(
10341 self,
10342 ) -> crate::common::RegisterField<
10343 0,
10344 0x1,
10345 1,
10346 0,
10347 dpsier2::Dpvd1Ie,
10348 dpsier2::Dpvd1Ie,
10349 Dpsier2_SPEC,
10350 crate::common::RW,
10351 > {
10352 crate::common::RegisterField::<
10353 0,
10354 0x1,
10355 1,
10356 0,
10357 dpsier2::Dpvd1Ie,
10358 dpsier2::Dpvd1Ie,
10359 Dpsier2_SPEC,
10360 crate::common::RW,
10361 >::from_register(self, 0)
10362 }
10363
10364 #[doc = "PVD2 Deep Software Standby Cancel Signal Enable"]
10365 #[inline(always)]
10366 pub fn dpvd2ie(
10367 self,
10368 ) -> crate::common::RegisterField<
10369 1,
10370 0x1,
10371 1,
10372 0,
10373 dpsier2::Dpvd2Ie,
10374 dpsier2::Dpvd2Ie,
10375 Dpsier2_SPEC,
10376 crate::common::RW,
10377 > {
10378 crate::common::RegisterField::<
10379 1,
10380 0x1,
10381 1,
10382 0,
10383 dpsier2::Dpvd2Ie,
10384 dpsier2::Dpvd2Ie,
10385 Dpsier2_SPEC,
10386 crate::common::RW,
10387 >::from_register(self, 0)
10388 }
10389
10390 #[doc = "RTC Interval interrupt Deep Software Standby Cancel Signal Enable"]
10391 #[inline(always)]
10392 pub fn drtciie(
10393 self,
10394 ) -> crate::common::RegisterField<
10395 2,
10396 0x1,
10397 1,
10398 0,
10399 dpsier2::Drtciie,
10400 dpsier2::Drtciie,
10401 Dpsier2_SPEC,
10402 crate::common::RW,
10403 > {
10404 crate::common::RegisterField::<
10405 2,
10406 0x1,
10407 1,
10408 0,
10409 dpsier2::Drtciie,
10410 dpsier2::Drtciie,
10411 Dpsier2_SPEC,
10412 crate::common::RW,
10413 >::from_register(self, 0)
10414 }
10415
10416 #[doc = "RTC Alarm interrupt Deep Software Standby Cancel Signal Enable"]
10417 #[inline(always)]
10418 pub fn drtcaie(
10419 self,
10420 ) -> crate::common::RegisterField<
10421 3,
10422 0x1,
10423 1,
10424 0,
10425 dpsier2::Drtcaie,
10426 dpsier2::Drtcaie,
10427 Dpsier2_SPEC,
10428 crate::common::RW,
10429 > {
10430 crate::common::RegisterField::<
10431 3,
10432 0x1,
10433 1,
10434 0,
10435 dpsier2::Drtcaie,
10436 dpsier2::Drtcaie,
10437 Dpsier2_SPEC,
10438 crate::common::RW,
10439 >::from_register(self, 0)
10440 }
10441
10442 #[doc = "NMI Pin Deep Software Standby Cancel Signal Enable"]
10443 #[inline(always)]
10444 pub fn dnmie(
10445 self,
10446 ) -> crate::common::RegisterField<
10447 4,
10448 0x1,
10449 1,
10450 0,
10451 dpsier2::Dnmie,
10452 dpsier2::Dnmie,
10453 Dpsier2_SPEC,
10454 crate::common::RW,
10455 > {
10456 crate::common::RegisterField::<
10457 4,
10458 0x1,
10459 1,
10460 0,
10461 dpsier2::Dnmie,
10462 dpsier2::Dnmie,
10463 Dpsier2_SPEC,
10464 crate::common::RW,
10465 >::from_register(self, 0)
10466 }
10467}
10468impl ::core::default::Default for Dpsier2 {
10469 #[inline(always)]
10470 fn default() -> Dpsier2 {
10471 <crate::RegValueT<Dpsier2_SPEC> as RegisterValue<_>>::new(0)
10472 }
10473}
10474pub mod dpsier2 {
10475
10476 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10477 pub struct Dpvd1Ie_SPEC;
10478 pub type Dpvd1Ie = crate::EnumBitfieldStruct<u8, Dpvd1Ie_SPEC>;
10479 impl Dpvd1Ie {
10480 #[doc = "Canceling Deep Software Standby mode is disabled"]
10481 pub const _0: Self = Self::new(0);
10482
10483 #[doc = "Canceling Deep Software Standby mode is enabled"]
10484 pub const _1: Self = Self::new(1);
10485 }
10486 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10487 pub struct Dpvd2Ie_SPEC;
10488 pub type Dpvd2Ie = crate::EnumBitfieldStruct<u8, Dpvd2Ie_SPEC>;
10489 impl Dpvd2Ie {
10490 #[doc = "Canceling Deep Software Standby mode is disabled"]
10491 pub const _0: Self = Self::new(0);
10492
10493 #[doc = "Canceling Deep Software Standby mode is enabled"]
10494 pub const _1: Self = Self::new(1);
10495 }
10496 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10497 pub struct Drtciie_SPEC;
10498 pub type Drtciie = crate::EnumBitfieldStruct<u8, Drtciie_SPEC>;
10499 impl Drtciie {
10500 #[doc = "Canceling Deep Software Standby mode is disabled"]
10501 pub const _0: Self = Self::new(0);
10502
10503 #[doc = "Canceling Deep Software Standby mode is enabled"]
10504 pub const _1: Self = Self::new(1);
10505 }
10506 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10507 pub struct Drtcaie_SPEC;
10508 pub type Drtcaie = crate::EnumBitfieldStruct<u8, Drtcaie_SPEC>;
10509 impl Drtcaie {
10510 #[doc = "Canceling Deep Software Standby mode is disabled"]
10511 pub const _0: Self = Self::new(0);
10512
10513 #[doc = "Canceling Deep Software Standby mode is enabled"]
10514 pub const _1: Self = Self::new(1);
10515 }
10516 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10517 pub struct Dnmie_SPEC;
10518 pub type Dnmie = crate::EnumBitfieldStruct<u8, Dnmie_SPEC>;
10519 impl Dnmie {
10520 #[doc = "Canceling Deep Software Standby mode is disabled"]
10521 pub const _0: Self = Self::new(0);
10522
10523 #[doc = "Canceling Deep Software Standby mode is enabled"]
10524 pub const _1: Self = Self::new(1);
10525 }
10526}
10527#[doc(hidden)]
10528#[derive(Copy, Clone, Eq, PartialEq)]
10529pub struct Dpsier3_SPEC;
10530impl crate::sealed::RegSpec for Dpsier3_SPEC {
10531 type DataType = u8;
10532}
10533
10534#[doc = "Deep Software Standby Interrupt Enable Register 3"]
10535pub type Dpsier3 = crate::RegValueT<Dpsier3_SPEC>;
10536
10537impl Dpsier3 {
10538 #[doc = "USBFS Suspend/Resume Deep Software Standby Cancel Signal Enable"]
10539 #[inline(always)]
10540 pub fn dusbfsie(
10541 self,
10542 ) -> crate::common::RegisterField<
10543 0,
10544 0x1,
10545 1,
10546 0,
10547 dpsier3::Dusbfsie,
10548 dpsier3::Dusbfsie,
10549 Dpsier3_SPEC,
10550 crate::common::RW,
10551 > {
10552 crate::common::RegisterField::<
10553 0,
10554 0x1,
10555 1,
10556 0,
10557 dpsier3::Dusbfsie,
10558 dpsier3::Dusbfsie,
10559 Dpsier3_SPEC,
10560 crate::common::RW,
10561 >::from_register(self, 0)
10562 }
10563
10564 #[doc = "ULPT0 Overflow Deep Software Standby Cancel Signal Enable"]
10565 #[inline(always)]
10566 pub fn dulpt0ie(
10567 self,
10568 ) -> crate::common::RegisterField<
10569 2,
10570 0x1,
10571 1,
10572 0,
10573 dpsier3::Dulpt0Ie,
10574 dpsier3::Dulpt0Ie,
10575 Dpsier3_SPEC,
10576 crate::common::RW,
10577 > {
10578 crate::common::RegisterField::<
10579 2,
10580 0x1,
10581 1,
10582 0,
10583 dpsier3::Dulpt0Ie,
10584 dpsier3::Dulpt0Ie,
10585 Dpsier3_SPEC,
10586 crate::common::RW,
10587 >::from_register(self, 0)
10588 }
10589
10590 #[doc = "ULPT1 Overflow Deep Software Standby Cancel Signal Enable"]
10591 #[inline(always)]
10592 pub fn dulpt1ie(
10593 self,
10594 ) -> crate::common::RegisterField<
10595 3,
10596 0x1,
10597 1,
10598 0,
10599 dpsier3::Dulpt1Ie,
10600 dpsier3::Dulpt1Ie,
10601 Dpsier3_SPEC,
10602 crate::common::RW,
10603 > {
10604 crate::common::RegisterField::<
10605 3,
10606 0x1,
10607 1,
10608 0,
10609 dpsier3::Dulpt1Ie,
10610 dpsier3::Dulpt1Ie,
10611 Dpsier3_SPEC,
10612 crate::common::RW,
10613 >::from_register(self, 0)
10614 }
10615
10616 #[doc = "IWDT Underflow Deep Software Standby Cancel Signal Enable"]
10617 #[inline(always)]
10618 pub fn diwdtie(
10619 self,
10620 ) -> crate::common::RegisterField<
10621 5,
10622 0x1,
10623 1,
10624 0,
10625 dpsier3::Diwdtie,
10626 dpsier3::Diwdtie,
10627 Dpsier3_SPEC,
10628 crate::common::RW,
10629 > {
10630 crate::common::RegisterField::<
10631 5,
10632 0x1,
10633 1,
10634 0,
10635 dpsier3::Diwdtie,
10636 dpsier3::Diwdtie,
10637 Dpsier3_SPEC,
10638 crate::common::RW,
10639 >::from_register(self, 0)
10640 }
10641
10642 #[doc = "VBATT Tamper Detection Deep Software Standby Cancel Signal Enable"]
10643 #[inline(always)]
10644 pub fn dvbattadie(
10645 self,
10646 ) -> crate::common::RegisterField<
10647 7,
10648 0x1,
10649 1,
10650 0,
10651 dpsier3::Dvbattadie,
10652 dpsier3::Dvbattadie,
10653 Dpsier3_SPEC,
10654 crate::common::RW,
10655 > {
10656 crate::common::RegisterField::<
10657 7,
10658 0x1,
10659 1,
10660 0,
10661 dpsier3::Dvbattadie,
10662 dpsier3::Dvbattadie,
10663 Dpsier3_SPEC,
10664 crate::common::RW,
10665 >::from_register(self, 0)
10666 }
10667}
10668impl ::core::default::Default for Dpsier3 {
10669 #[inline(always)]
10670 fn default() -> Dpsier3 {
10671 <crate::RegValueT<Dpsier3_SPEC> as RegisterValue<_>>::new(0)
10672 }
10673}
10674pub mod dpsier3 {
10675
10676 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10677 pub struct Dusbfsie_SPEC;
10678 pub type Dusbfsie = crate::EnumBitfieldStruct<u8, Dusbfsie_SPEC>;
10679 impl Dusbfsie {
10680 #[doc = "Canceling Deep Software Standby mode is disabled"]
10681 pub const _0: Self = Self::new(0);
10682
10683 #[doc = "Canceling Deep Software Standby mode is enabled"]
10684 pub const _1: Self = Self::new(1);
10685 }
10686 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10687 pub struct Dulpt0Ie_SPEC;
10688 pub type Dulpt0Ie = crate::EnumBitfieldStruct<u8, Dulpt0Ie_SPEC>;
10689 impl Dulpt0Ie {
10690 #[doc = "Canceling Deep Software Standby mode is disabled"]
10691 pub const _0: Self = Self::new(0);
10692
10693 #[doc = "Canceling Deep Software Standby mode is enabled"]
10694 pub const _1: Self = Self::new(1);
10695 }
10696 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10697 pub struct Dulpt1Ie_SPEC;
10698 pub type Dulpt1Ie = crate::EnumBitfieldStruct<u8, Dulpt1Ie_SPEC>;
10699 impl Dulpt1Ie {
10700 #[doc = "Canceling Deep Software Standby mode is disabled"]
10701 pub const _0: Self = Self::new(0);
10702
10703 #[doc = "Canceling Deep Software Standby mode is enabled"]
10704 pub const _1: Self = Self::new(1);
10705 }
10706 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10707 pub struct Diwdtie_SPEC;
10708 pub type Diwdtie = crate::EnumBitfieldStruct<u8, Diwdtie_SPEC>;
10709 impl Diwdtie {
10710 #[doc = "Canceling Deep Software Standby mode is disabled"]
10711 pub const _0: Self = Self::new(0);
10712
10713 #[doc = "Canceling Deep Software Standby mode is enabled"]
10714 pub const _1: Self = Self::new(1);
10715 }
10716 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10717 pub struct Dvbattadie_SPEC;
10718 pub type Dvbattadie = crate::EnumBitfieldStruct<u8, Dvbattadie_SPEC>;
10719 impl Dvbattadie {
10720 #[doc = "Canceling Deep Software Standby mode is disabled"]
10721 pub const _0: Self = Self::new(0);
10722
10723 #[doc = "Canceling Deep Software Standby mode is enabled"]
10724 pub const _1: Self = Self::new(1);
10725 }
10726}
10727#[doc(hidden)]
10728#[derive(Copy, Clone, Eq, PartialEq)]
10729pub struct Dpsifr0_SPEC;
10730impl crate::sealed::RegSpec for Dpsifr0_SPEC {
10731 type DataType = u8;
10732}
10733
10734#[doc = "Deep Software Standby Interrupt Flag Register 0"]
10735pub type Dpsifr0 = crate::RegValueT<Dpsifr0_SPEC>;
10736
10737impl Dpsifr0 {
10738 #[doc = "IRQ0-DS Pin Deep Software Standby Cancel Flag"]
10739 #[inline(always)]
10740 pub fn dirq0f(
10741 self,
10742 ) -> crate::common::RegisterField<
10743 0,
10744 0x1,
10745 1,
10746 0,
10747 dpsifr0::Dirq0F,
10748 dpsifr0::Dirq0F,
10749 Dpsifr0_SPEC,
10750 crate::common::RW,
10751 > {
10752 crate::common::RegisterField::<
10753 0,
10754 0x1,
10755 1,
10756 0,
10757 dpsifr0::Dirq0F,
10758 dpsifr0::Dirq0F,
10759 Dpsifr0_SPEC,
10760 crate::common::RW,
10761 >::from_register(self, 0)
10762 }
10763
10764 #[doc = "IRQ1-DS Pin Deep Software Standby Cancel Flag"]
10765 #[inline(always)]
10766 pub fn dirq1f(
10767 self,
10768 ) -> crate::common::RegisterField<
10769 1,
10770 0x1,
10771 1,
10772 0,
10773 dpsifr0::Dirq1F,
10774 dpsifr0::Dirq1F,
10775 Dpsifr0_SPEC,
10776 crate::common::RW,
10777 > {
10778 crate::common::RegisterField::<
10779 1,
10780 0x1,
10781 1,
10782 0,
10783 dpsifr0::Dirq1F,
10784 dpsifr0::Dirq1F,
10785 Dpsifr0_SPEC,
10786 crate::common::RW,
10787 >::from_register(self, 0)
10788 }
10789
10790 #[doc = "IRQ2-DS Pin Deep Software Standby Cancel Flag"]
10791 #[inline(always)]
10792 pub fn dirq2f(
10793 self,
10794 ) -> crate::common::RegisterField<
10795 2,
10796 0x1,
10797 1,
10798 0,
10799 dpsifr0::Dirq2F,
10800 dpsifr0::Dirq2F,
10801 Dpsifr0_SPEC,
10802 crate::common::RW,
10803 > {
10804 crate::common::RegisterField::<
10805 2,
10806 0x1,
10807 1,
10808 0,
10809 dpsifr0::Dirq2F,
10810 dpsifr0::Dirq2F,
10811 Dpsifr0_SPEC,
10812 crate::common::RW,
10813 >::from_register(self, 0)
10814 }
10815
10816 #[doc = "IRQ3-DS Pin Deep Software Standby Cancel Flag"]
10817 #[inline(always)]
10818 pub fn dirq3f(
10819 self,
10820 ) -> crate::common::RegisterField<
10821 3,
10822 0x1,
10823 1,
10824 0,
10825 dpsifr0::Dirq3F,
10826 dpsifr0::Dirq3F,
10827 Dpsifr0_SPEC,
10828 crate::common::RW,
10829 > {
10830 crate::common::RegisterField::<
10831 3,
10832 0x1,
10833 1,
10834 0,
10835 dpsifr0::Dirq3F,
10836 dpsifr0::Dirq3F,
10837 Dpsifr0_SPEC,
10838 crate::common::RW,
10839 >::from_register(self, 0)
10840 }
10841
10842 #[doc = "IRQ4-DS Pin Deep Software Standby Cancel Flag"]
10843 #[inline(always)]
10844 pub fn dirq4f(
10845 self,
10846 ) -> crate::common::RegisterField<
10847 4,
10848 0x1,
10849 1,
10850 0,
10851 dpsifr0::Dirq4F,
10852 dpsifr0::Dirq4F,
10853 Dpsifr0_SPEC,
10854 crate::common::RW,
10855 > {
10856 crate::common::RegisterField::<
10857 4,
10858 0x1,
10859 1,
10860 0,
10861 dpsifr0::Dirq4F,
10862 dpsifr0::Dirq4F,
10863 Dpsifr0_SPEC,
10864 crate::common::RW,
10865 >::from_register(self, 0)
10866 }
10867
10868 #[doc = "IRQ5-DS Pin Deep Software Standby Cancel Flag"]
10869 #[inline(always)]
10870 pub fn dirq5f(
10871 self,
10872 ) -> crate::common::RegisterField<
10873 5,
10874 0x1,
10875 1,
10876 0,
10877 dpsifr0::Dirq5F,
10878 dpsifr0::Dirq5F,
10879 Dpsifr0_SPEC,
10880 crate::common::RW,
10881 > {
10882 crate::common::RegisterField::<
10883 5,
10884 0x1,
10885 1,
10886 0,
10887 dpsifr0::Dirq5F,
10888 dpsifr0::Dirq5F,
10889 Dpsifr0_SPEC,
10890 crate::common::RW,
10891 >::from_register(self, 0)
10892 }
10893
10894 #[doc = "IRQ6-DS Pin Deep Software Standby Cancel Flag"]
10895 #[inline(always)]
10896 pub fn dirq6f(
10897 self,
10898 ) -> crate::common::RegisterField<
10899 6,
10900 0x1,
10901 1,
10902 0,
10903 dpsifr0::Dirq6F,
10904 dpsifr0::Dirq6F,
10905 Dpsifr0_SPEC,
10906 crate::common::RW,
10907 > {
10908 crate::common::RegisterField::<
10909 6,
10910 0x1,
10911 1,
10912 0,
10913 dpsifr0::Dirq6F,
10914 dpsifr0::Dirq6F,
10915 Dpsifr0_SPEC,
10916 crate::common::RW,
10917 >::from_register(self, 0)
10918 }
10919
10920 #[doc = "IRQ7-DS Pin Deep Software Standby Cancel Flag"]
10921 #[inline(always)]
10922 pub fn dirq7f(
10923 self,
10924 ) -> crate::common::RegisterField<
10925 7,
10926 0x1,
10927 1,
10928 0,
10929 dpsifr0::Dirq7F,
10930 dpsifr0::Dirq7F,
10931 Dpsifr0_SPEC,
10932 crate::common::RW,
10933 > {
10934 crate::common::RegisterField::<
10935 7,
10936 0x1,
10937 1,
10938 0,
10939 dpsifr0::Dirq7F,
10940 dpsifr0::Dirq7F,
10941 Dpsifr0_SPEC,
10942 crate::common::RW,
10943 >::from_register(self, 0)
10944 }
10945}
10946impl ::core::default::Default for Dpsifr0 {
10947 #[inline(always)]
10948 fn default() -> Dpsifr0 {
10949 <crate::RegValueT<Dpsifr0_SPEC> as RegisterValue<_>>::new(0)
10950 }
10951}
10952pub mod dpsifr0 {
10953
10954 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10955 pub struct Dirq0F_SPEC;
10956 pub type Dirq0F = crate::EnumBitfieldStruct<u8, Dirq0F_SPEC>;
10957 impl Dirq0F {
10958 #[doc = "The cancel request is not generated"]
10959 pub const _0: Self = Self::new(0);
10960
10961 #[doc = "The cancel request is generated"]
10962 pub const _1: Self = Self::new(1);
10963 }
10964 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10965 pub struct Dirq1F_SPEC;
10966 pub type Dirq1F = crate::EnumBitfieldStruct<u8, Dirq1F_SPEC>;
10967 impl Dirq1F {
10968 #[doc = "The cancel request is not generated"]
10969 pub const _0: Self = Self::new(0);
10970
10971 #[doc = "The cancel request is generated"]
10972 pub const _1: Self = Self::new(1);
10973 }
10974 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10975 pub struct Dirq2F_SPEC;
10976 pub type Dirq2F = crate::EnumBitfieldStruct<u8, Dirq2F_SPEC>;
10977 impl Dirq2F {
10978 #[doc = "The cancel request is not generated"]
10979 pub const _0: Self = Self::new(0);
10980
10981 #[doc = "The cancel request is generated"]
10982 pub const _1: Self = Self::new(1);
10983 }
10984 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10985 pub struct Dirq3F_SPEC;
10986 pub type Dirq3F = crate::EnumBitfieldStruct<u8, Dirq3F_SPEC>;
10987 impl Dirq3F {
10988 #[doc = "The cancel request is not generated"]
10989 pub const _0: Self = Self::new(0);
10990
10991 #[doc = "The cancel request is generated"]
10992 pub const _1: Self = Self::new(1);
10993 }
10994 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10995 pub struct Dirq4F_SPEC;
10996 pub type Dirq4F = crate::EnumBitfieldStruct<u8, Dirq4F_SPEC>;
10997 impl Dirq4F {
10998 #[doc = "The cancel request is not generated"]
10999 pub const _0: Self = Self::new(0);
11000
11001 #[doc = "The cancel request is generated"]
11002 pub const _1: Self = Self::new(1);
11003 }
11004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11005 pub struct Dirq5F_SPEC;
11006 pub type Dirq5F = crate::EnumBitfieldStruct<u8, Dirq5F_SPEC>;
11007 impl Dirq5F {
11008 #[doc = "The cancel request is not generated"]
11009 pub const _0: Self = Self::new(0);
11010
11011 #[doc = "The cancel request is generated"]
11012 pub const _1: Self = Self::new(1);
11013 }
11014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11015 pub struct Dirq6F_SPEC;
11016 pub type Dirq6F = crate::EnumBitfieldStruct<u8, Dirq6F_SPEC>;
11017 impl Dirq6F {
11018 #[doc = "The cancel request is not generated"]
11019 pub const _0: Self = Self::new(0);
11020
11021 #[doc = "The cancel request is generated"]
11022 pub const _1: Self = Self::new(1);
11023 }
11024 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11025 pub struct Dirq7F_SPEC;
11026 pub type Dirq7F = crate::EnumBitfieldStruct<u8, Dirq7F_SPEC>;
11027 impl Dirq7F {
11028 #[doc = "The cancel request is not generated"]
11029 pub const _0: Self = Self::new(0);
11030
11031 #[doc = "The cancel request is generated"]
11032 pub const _1: Self = Self::new(1);
11033 }
11034}
11035#[doc(hidden)]
11036#[derive(Copy, Clone, Eq, PartialEq)]
11037pub struct Dpsifr1_SPEC;
11038impl crate::sealed::RegSpec for Dpsifr1_SPEC {
11039 type DataType = u8;
11040}
11041
11042#[doc = "Deep Software Standby Interrupt Flag Register 1"]
11043pub type Dpsifr1 = crate::RegValueT<Dpsifr1_SPEC>;
11044
11045impl Dpsifr1 {
11046 #[doc = "IRQ8-DS Pin Deep Software Standby Cancel Flag"]
11047 #[inline(always)]
11048 pub fn dirq8f(
11049 self,
11050 ) -> crate::common::RegisterField<
11051 0,
11052 0x1,
11053 1,
11054 0,
11055 dpsifr1::Dirq8F,
11056 dpsifr1::Dirq8F,
11057 Dpsifr1_SPEC,
11058 crate::common::RW,
11059 > {
11060 crate::common::RegisterField::<
11061 0,
11062 0x1,
11063 1,
11064 0,
11065 dpsifr1::Dirq8F,
11066 dpsifr1::Dirq8F,
11067 Dpsifr1_SPEC,
11068 crate::common::RW,
11069 >::from_register(self, 0)
11070 }
11071
11072 #[doc = "IRQ9-DS Pin Deep Software Standby Cancel Flag"]
11073 #[inline(always)]
11074 pub fn dirq9f(
11075 self,
11076 ) -> crate::common::RegisterField<
11077 1,
11078 0x1,
11079 1,
11080 0,
11081 dpsifr1::Dirq9F,
11082 dpsifr1::Dirq9F,
11083 Dpsifr1_SPEC,
11084 crate::common::RW,
11085 > {
11086 crate::common::RegisterField::<
11087 1,
11088 0x1,
11089 1,
11090 0,
11091 dpsifr1::Dirq9F,
11092 dpsifr1::Dirq9F,
11093 Dpsifr1_SPEC,
11094 crate::common::RW,
11095 >::from_register(self, 0)
11096 }
11097
11098 #[doc = "IRQ10-DS Pin Deep Software Standby Cancel Flag"]
11099 #[inline(always)]
11100 pub fn dirq10f(
11101 self,
11102 ) -> crate::common::RegisterField<
11103 2,
11104 0x1,
11105 1,
11106 0,
11107 dpsifr1::Dirq10F,
11108 dpsifr1::Dirq10F,
11109 Dpsifr1_SPEC,
11110 crate::common::RW,
11111 > {
11112 crate::common::RegisterField::<
11113 2,
11114 0x1,
11115 1,
11116 0,
11117 dpsifr1::Dirq10F,
11118 dpsifr1::Dirq10F,
11119 Dpsifr1_SPEC,
11120 crate::common::RW,
11121 >::from_register(self, 0)
11122 }
11123
11124 #[doc = "IRQ11-DS Pin Deep Software Standby Cancel Flag"]
11125 #[inline(always)]
11126 pub fn dirq11f(
11127 self,
11128 ) -> crate::common::RegisterField<
11129 3,
11130 0x1,
11131 1,
11132 0,
11133 dpsifr1::Dirq11F,
11134 dpsifr1::Dirq11F,
11135 Dpsifr1_SPEC,
11136 crate::common::RW,
11137 > {
11138 crate::common::RegisterField::<
11139 3,
11140 0x1,
11141 1,
11142 0,
11143 dpsifr1::Dirq11F,
11144 dpsifr1::Dirq11F,
11145 Dpsifr1_SPEC,
11146 crate::common::RW,
11147 >::from_register(self, 0)
11148 }
11149
11150 #[doc = "IRQ12-DS Pin Deep Software Standby Cancel Flag"]
11151 #[inline(always)]
11152 pub fn dirq12f(
11153 self,
11154 ) -> crate::common::RegisterField<
11155 4,
11156 0x1,
11157 1,
11158 0,
11159 dpsifr1::Dirq12F,
11160 dpsifr1::Dirq12F,
11161 Dpsifr1_SPEC,
11162 crate::common::RW,
11163 > {
11164 crate::common::RegisterField::<
11165 4,
11166 0x1,
11167 1,
11168 0,
11169 dpsifr1::Dirq12F,
11170 dpsifr1::Dirq12F,
11171 Dpsifr1_SPEC,
11172 crate::common::RW,
11173 >::from_register(self, 0)
11174 }
11175
11176 #[doc = "IRQ13-DS Pin Deep Software Standby Cancel Flag"]
11177 #[inline(always)]
11178 pub fn dirq13f(
11179 self,
11180 ) -> crate::common::RegisterField<
11181 5,
11182 0x1,
11183 1,
11184 0,
11185 dpsifr1::Dirq13F,
11186 dpsifr1::Dirq13F,
11187 Dpsifr1_SPEC,
11188 crate::common::RW,
11189 > {
11190 crate::common::RegisterField::<
11191 5,
11192 0x1,
11193 1,
11194 0,
11195 dpsifr1::Dirq13F,
11196 dpsifr1::Dirq13F,
11197 Dpsifr1_SPEC,
11198 crate::common::RW,
11199 >::from_register(self, 0)
11200 }
11201
11202 #[doc = "IRQ14-DS Pin Deep Software Standby Cancel Flag"]
11203 #[inline(always)]
11204 pub fn dirq14f(
11205 self,
11206 ) -> crate::common::RegisterField<
11207 6,
11208 0x1,
11209 1,
11210 0,
11211 dpsifr1::Dirq14F,
11212 dpsifr1::Dirq14F,
11213 Dpsifr1_SPEC,
11214 crate::common::RW,
11215 > {
11216 crate::common::RegisterField::<
11217 6,
11218 0x1,
11219 1,
11220 0,
11221 dpsifr1::Dirq14F,
11222 dpsifr1::Dirq14F,
11223 Dpsifr1_SPEC,
11224 crate::common::RW,
11225 >::from_register(self, 0)
11226 }
11227
11228 #[doc = "IRQ15-DS Pin Deep Software Standby Cancel Flag"]
11229 #[inline(always)]
11230 pub fn dirq15f(
11231 self,
11232 ) -> crate::common::RegisterField<
11233 7,
11234 0x1,
11235 1,
11236 0,
11237 dpsifr1::Dirq15F,
11238 dpsifr1::Dirq15F,
11239 Dpsifr1_SPEC,
11240 crate::common::RW,
11241 > {
11242 crate::common::RegisterField::<
11243 7,
11244 0x1,
11245 1,
11246 0,
11247 dpsifr1::Dirq15F,
11248 dpsifr1::Dirq15F,
11249 Dpsifr1_SPEC,
11250 crate::common::RW,
11251 >::from_register(self, 0)
11252 }
11253}
11254impl ::core::default::Default for Dpsifr1 {
11255 #[inline(always)]
11256 fn default() -> Dpsifr1 {
11257 <crate::RegValueT<Dpsifr1_SPEC> as RegisterValue<_>>::new(0)
11258 }
11259}
11260pub mod dpsifr1 {
11261
11262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11263 pub struct Dirq8F_SPEC;
11264 pub type Dirq8F = crate::EnumBitfieldStruct<u8, Dirq8F_SPEC>;
11265 impl Dirq8F {
11266 #[doc = "The cancel request is not generated"]
11267 pub const _0: Self = Self::new(0);
11268
11269 #[doc = "The cancel request is generated"]
11270 pub const _1: Self = Self::new(1);
11271 }
11272 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11273 pub struct Dirq9F_SPEC;
11274 pub type Dirq9F = crate::EnumBitfieldStruct<u8, Dirq9F_SPEC>;
11275 impl Dirq9F {
11276 #[doc = "The cancel request is not generated"]
11277 pub const _0: Self = Self::new(0);
11278
11279 #[doc = "The cancel request is generated"]
11280 pub const _1: Self = Self::new(1);
11281 }
11282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11283 pub struct Dirq10F_SPEC;
11284 pub type Dirq10F = crate::EnumBitfieldStruct<u8, Dirq10F_SPEC>;
11285 impl Dirq10F {
11286 #[doc = "The cancel request is not generated"]
11287 pub const _0: Self = Self::new(0);
11288
11289 #[doc = "The cancel request is generated"]
11290 pub const _1: Self = Self::new(1);
11291 }
11292 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11293 pub struct Dirq11F_SPEC;
11294 pub type Dirq11F = crate::EnumBitfieldStruct<u8, Dirq11F_SPEC>;
11295 impl Dirq11F {
11296 #[doc = "The cancel request is not generated"]
11297 pub const _0: Self = Self::new(0);
11298
11299 #[doc = "The cancel request is generated"]
11300 pub const _1: Self = Self::new(1);
11301 }
11302 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11303 pub struct Dirq12F_SPEC;
11304 pub type Dirq12F = crate::EnumBitfieldStruct<u8, Dirq12F_SPEC>;
11305 impl Dirq12F {
11306 #[doc = "The cancel request is not generated"]
11307 pub const _0: Self = Self::new(0);
11308
11309 #[doc = "The cancel request is generated"]
11310 pub const _1: Self = Self::new(1);
11311 }
11312 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11313 pub struct Dirq13F_SPEC;
11314 pub type Dirq13F = crate::EnumBitfieldStruct<u8, Dirq13F_SPEC>;
11315 impl Dirq13F {
11316 #[doc = "The cancel request is not generated"]
11317 pub const _0: Self = Self::new(0);
11318
11319 #[doc = "The cancel request is generated"]
11320 pub const _1: Self = Self::new(1);
11321 }
11322 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11323 pub struct Dirq14F_SPEC;
11324 pub type Dirq14F = crate::EnumBitfieldStruct<u8, Dirq14F_SPEC>;
11325 impl Dirq14F {
11326 #[doc = "The cancel request is not generated"]
11327 pub const _0: Self = Self::new(0);
11328
11329 #[doc = "The cancel request is generated"]
11330 pub const _1: Self = Self::new(1);
11331 }
11332 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11333 pub struct Dirq15F_SPEC;
11334 pub type Dirq15F = crate::EnumBitfieldStruct<u8, Dirq15F_SPEC>;
11335 impl Dirq15F {
11336 #[doc = "The cancel request is not generated"]
11337 pub const _0: Self = Self::new(0);
11338
11339 #[doc = "The cancel request is generated"]
11340 pub const _1: Self = Self::new(1);
11341 }
11342}
11343#[doc(hidden)]
11344#[derive(Copy, Clone, Eq, PartialEq)]
11345pub struct Dpsifr2_SPEC;
11346impl crate::sealed::RegSpec for Dpsifr2_SPEC {
11347 type DataType = u8;
11348}
11349
11350#[doc = "Deep Software Standby Interrupt Flag Register 2"]
11351pub type Dpsifr2 = crate::RegValueT<Dpsifr2_SPEC>;
11352
11353impl Dpsifr2 {
11354 #[doc = "PVD1 Deep Software Standby Cancel Flag"]
11355 #[inline(always)]
11356 pub fn dpvd1if(
11357 self,
11358 ) -> crate::common::RegisterField<
11359 0,
11360 0x1,
11361 1,
11362 0,
11363 dpsifr2::Dpvd1If,
11364 dpsifr2::Dpvd1If,
11365 Dpsifr2_SPEC,
11366 crate::common::RW,
11367 > {
11368 crate::common::RegisterField::<
11369 0,
11370 0x1,
11371 1,
11372 0,
11373 dpsifr2::Dpvd1If,
11374 dpsifr2::Dpvd1If,
11375 Dpsifr2_SPEC,
11376 crate::common::RW,
11377 >::from_register(self, 0)
11378 }
11379
11380 #[doc = "PVD2 Deep Software Standby Cancel Flag"]
11381 #[inline(always)]
11382 pub fn dpvd2if(
11383 self,
11384 ) -> crate::common::RegisterField<
11385 1,
11386 0x1,
11387 1,
11388 0,
11389 dpsifr2::Dpvd2If,
11390 dpsifr2::Dpvd2If,
11391 Dpsifr2_SPEC,
11392 crate::common::RW,
11393 > {
11394 crate::common::RegisterField::<
11395 1,
11396 0x1,
11397 1,
11398 0,
11399 dpsifr2::Dpvd2If,
11400 dpsifr2::Dpvd2If,
11401 Dpsifr2_SPEC,
11402 crate::common::RW,
11403 >::from_register(self, 0)
11404 }
11405
11406 #[doc = "RTC Interval Interrupt Deep Software Standby Cancel Flag"]
11407 #[inline(always)]
11408 pub fn drtciif(
11409 self,
11410 ) -> crate::common::RegisterField<
11411 2,
11412 0x1,
11413 1,
11414 0,
11415 dpsifr2::Drtciif,
11416 dpsifr2::Drtciif,
11417 Dpsifr2_SPEC,
11418 crate::common::RW,
11419 > {
11420 crate::common::RegisterField::<
11421 2,
11422 0x1,
11423 1,
11424 0,
11425 dpsifr2::Drtciif,
11426 dpsifr2::Drtciif,
11427 Dpsifr2_SPEC,
11428 crate::common::RW,
11429 >::from_register(self, 0)
11430 }
11431
11432 #[doc = "RTC Alarm Interrupt Deep Software Standby Cancel Flag"]
11433 #[inline(always)]
11434 pub fn drtcaif(
11435 self,
11436 ) -> crate::common::RegisterField<
11437 3,
11438 0x1,
11439 1,
11440 0,
11441 dpsifr2::Drtcaif,
11442 dpsifr2::Drtcaif,
11443 Dpsifr2_SPEC,
11444 crate::common::RW,
11445 > {
11446 crate::common::RegisterField::<
11447 3,
11448 0x1,
11449 1,
11450 0,
11451 dpsifr2::Drtcaif,
11452 dpsifr2::Drtcaif,
11453 Dpsifr2_SPEC,
11454 crate::common::RW,
11455 >::from_register(self, 0)
11456 }
11457
11458 #[doc = "NMI Pin Deep Software Standby Cancel Flag"]
11459 #[inline(always)]
11460 pub fn dnmif(
11461 self,
11462 ) -> crate::common::RegisterField<
11463 4,
11464 0x1,
11465 1,
11466 0,
11467 dpsifr2::Dnmif,
11468 dpsifr2::Dnmif,
11469 Dpsifr2_SPEC,
11470 crate::common::RW,
11471 > {
11472 crate::common::RegisterField::<
11473 4,
11474 0x1,
11475 1,
11476 0,
11477 dpsifr2::Dnmif,
11478 dpsifr2::Dnmif,
11479 Dpsifr2_SPEC,
11480 crate::common::RW,
11481 >::from_register(self, 0)
11482 }
11483}
11484impl ::core::default::Default for Dpsifr2 {
11485 #[inline(always)]
11486 fn default() -> Dpsifr2 {
11487 <crate::RegValueT<Dpsifr2_SPEC> as RegisterValue<_>>::new(0)
11488 }
11489}
11490pub mod dpsifr2 {
11491
11492 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11493 pub struct Dpvd1If_SPEC;
11494 pub type Dpvd1If = crate::EnumBitfieldStruct<u8, Dpvd1If_SPEC>;
11495 impl Dpvd1If {
11496 #[doc = "The cancel request is not generated"]
11497 pub const _0: Self = Self::new(0);
11498
11499 #[doc = "The cancel request is generated"]
11500 pub const _1: Self = Self::new(1);
11501 }
11502 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11503 pub struct Dpvd2If_SPEC;
11504 pub type Dpvd2If = crate::EnumBitfieldStruct<u8, Dpvd2If_SPEC>;
11505 impl Dpvd2If {
11506 #[doc = "The cancel request is not generated"]
11507 pub const _0: Self = Self::new(0);
11508
11509 #[doc = "The cancel request is generated"]
11510 pub const _1: Self = Self::new(1);
11511 }
11512 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11513 pub struct Drtciif_SPEC;
11514 pub type Drtciif = crate::EnumBitfieldStruct<u8, Drtciif_SPEC>;
11515 impl Drtciif {
11516 #[doc = "The cancel request is not generated"]
11517 pub const _0: Self = Self::new(0);
11518
11519 #[doc = "The cancel request is generated"]
11520 pub const _1: Self = Self::new(1);
11521 }
11522 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11523 pub struct Drtcaif_SPEC;
11524 pub type Drtcaif = crate::EnumBitfieldStruct<u8, Drtcaif_SPEC>;
11525 impl Drtcaif {
11526 #[doc = "The cancel request is not generated"]
11527 pub const _0: Self = Self::new(0);
11528
11529 #[doc = "The cancel request is generated"]
11530 pub const _1: Self = Self::new(1);
11531 }
11532 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11533 pub struct Dnmif_SPEC;
11534 pub type Dnmif = crate::EnumBitfieldStruct<u8, Dnmif_SPEC>;
11535 impl Dnmif {
11536 #[doc = "The cancel request is not generated"]
11537 pub const _0: Self = Self::new(0);
11538
11539 #[doc = "The cancel request is generated"]
11540 pub const _1: Self = Self::new(1);
11541 }
11542}
11543#[doc(hidden)]
11544#[derive(Copy, Clone, Eq, PartialEq)]
11545pub struct Dpsifr3_SPEC;
11546impl crate::sealed::RegSpec for Dpsifr3_SPEC {
11547 type DataType = u8;
11548}
11549
11550#[doc = "Deep Software Standby Interrupt Flag Register 3"]
11551pub type Dpsifr3 = crate::RegValueT<Dpsifr3_SPEC>;
11552
11553impl Dpsifr3 {
11554 #[doc = "USBFS Suspend/Resume Deep Software Standby Cancel Flag"]
11555 #[inline(always)]
11556 pub fn dusbfsif(
11557 self,
11558 ) -> crate::common::RegisterField<
11559 0,
11560 0x1,
11561 1,
11562 0,
11563 dpsifr3::Dusbfsif,
11564 dpsifr3::Dusbfsif,
11565 Dpsifr3_SPEC,
11566 crate::common::RW,
11567 > {
11568 crate::common::RegisterField::<
11569 0,
11570 0x1,
11571 1,
11572 0,
11573 dpsifr3::Dusbfsif,
11574 dpsifr3::Dusbfsif,
11575 Dpsifr3_SPEC,
11576 crate::common::RW,
11577 >::from_register(self, 0)
11578 }
11579
11580 #[doc = "ULPT0 Overflow Deep Software Standby Cancel Flag"]
11581 #[inline(always)]
11582 pub fn dulpt0if(
11583 self,
11584 ) -> crate::common::RegisterField<
11585 2,
11586 0x1,
11587 1,
11588 0,
11589 dpsifr3::Dulpt0If,
11590 dpsifr3::Dulpt0If,
11591 Dpsifr3_SPEC,
11592 crate::common::RW,
11593 > {
11594 crate::common::RegisterField::<
11595 2,
11596 0x1,
11597 1,
11598 0,
11599 dpsifr3::Dulpt0If,
11600 dpsifr3::Dulpt0If,
11601 Dpsifr3_SPEC,
11602 crate::common::RW,
11603 >::from_register(self, 0)
11604 }
11605
11606 #[doc = "ULPT1 Overflow Deep Software Standby Cancel Flag"]
11607 #[inline(always)]
11608 pub fn dulpt1if(
11609 self,
11610 ) -> crate::common::RegisterField<
11611 3,
11612 0x1,
11613 1,
11614 0,
11615 dpsifr3::Dulpt1If,
11616 dpsifr3::Dulpt1If,
11617 Dpsifr3_SPEC,
11618 crate::common::RW,
11619 > {
11620 crate::common::RegisterField::<
11621 3,
11622 0x1,
11623 1,
11624 0,
11625 dpsifr3::Dulpt1If,
11626 dpsifr3::Dulpt1If,
11627 Dpsifr3_SPEC,
11628 crate::common::RW,
11629 >::from_register(self, 0)
11630 }
11631
11632 #[doc = "IWDT Underflow Deep Software Standby Cancel Flag"]
11633 #[inline(always)]
11634 pub fn diwdtif(
11635 self,
11636 ) -> crate::common::RegisterField<
11637 5,
11638 0x1,
11639 1,
11640 0,
11641 dpsifr3::Diwdtif,
11642 dpsifr3::Diwdtif,
11643 Dpsifr3_SPEC,
11644 crate::common::RW,
11645 > {
11646 crate::common::RegisterField::<
11647 5,
11648 0x1,
11649 1,
11650 0,
11651 dpsifr3::Diwdtif,
11652 dpsifr3::Diwdtif,
11653 Dpsifr3_SPEC,
11654 crate::common::RW,
11655 >::from_register(self, 0)
11656 }
11657
11658 #[doc = "VBATT Tamper Detection Deep Software Standby Cancel Flag"]
11659 #[inline(always)]
11660 pub fn dvbattadif(
11661 self,
11662 ) -> crate::common::RegisterField<
11663 7,
11664 0x1,
11665 1,
11666 0,
11667 dpsifr3::Dvbattadif,
11668 dpsifr3::Dvbattadif,
11669 Dpsifr3_SPEC,
11670 crate::common::RW,
11671 > {
11672 crate::common::RegisterField::<
11673 7,
11674 0x1,
11675 1,
11676 0,
11677 dpsifr3::Dvbattadif,
11678 dpsifr3::Dvbattadif,
11679 Dpsifr3_SPEC,
11680 crate::common::RW,
11681 >::from_register(self, 0)
11682 }
11683}
11684impl ::core::default::Default for Dpsifr3 {
11685 #[inline(always)]
11686 fn default() -> Dpsifr3 {
11687 <crate::RegValueT<Dpsifr3_SPEC> as RegisterValue<_>>::new(0)
11688 }
11689}
11690pub mod dpsifr3 {
11691
11692 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11693 pub struct Dusbfsif_SPEC;
11694 pub type Dusbfsif = crate::EnumBitfieldStruct<u8, Dusbfsif_SPEC>;
11695 impl Dusbfsif {
11696 #[doc = "The cancel request is not generated"]
11697 pub const _0: Self = Self::new(0);
11698
11699 #[doc = "The cancel request is generated"]
11700 pub const _1: Self = Self::new(1);
11701 }
11702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11703 pub struct Dulpt0If_SPEC;
11704 pub type Dulpt0If = crate::EnumBitfieldStruct<u8, Dulpt0If_SPEC>;
11705 impl Dulpt0If {
11706 #[doc = "The cancel request is not generated"]
11707 pub const _0: Self = Self::new(0);
11708
11709 #[doc = "The cancel request is generated"]
11710 pub const _1: Self = Self::new(1);
11711 }
11712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11713 pub struct Dulpt1If_SPEC;
11714 pub type Dulpt1If = crate::EnumBitfieldStruct<u8, Dulpt1If_SPEC>;
11715 impl Dulpt1If {
11716 #[doc = "The cancel request is not generated"]
11717 pub const _0: Self = Self::new(0);
11718
11719 #[doc = "The cancel request is generated"]
11720 pub const _1: Self = Self::new(1);
11721 }
11722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11723 pub struct Diwdtif_SPEC;
11724 pub type Diwdtif = crate::EnumBitfieldStruct<u8, Diwdtif_SPEC>;
11725 impl Diwdtif {
11726 #[doc = "The cancel request is not generated"]
11727 pub const _0: Self = Self::new(0);
11728
11729 #[doc = "The cancel request is generated"]
11730 pub const _1: Self = Self::new(1);
11731 }
11732 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11733 pub struct Dvbattadif_SPEC;
11734 pub type Dvbattadif = crate::EnumBitfieldStruct<u8, Dvbattadif_SPEC>;
11735 impl Dvbattadif {
11736 #[doc = "The cancel request is not generated"]
11737 pub const _0: Self = Self::new(0);
11738
11739 #[doc = "The cancel request is generated"]
11740 pub const _1: Self = Self::new(1);
11741 }
11742}
11743#[doc(hidden)]
11744#[derive(Copy, Clone, Eq, PartialEq)]
11745pub struct Dpsiegr0_SPEC;
11746impl crate::sealed::RegSpec for Dpsiegr0_SPEC {
11747 type DataType = u8;
11748}
11749
11750#[doc = "Deep Software Standby Interrupt Edge Register 0"]
11751pub type Dpsiegr0 = crate::RegValueT<Dpsiegr0_SPEC>;
11752
11753impl Dpsiegr0 {
11754 #[doc = "IRQ0-DS Pin Edge Select"]
11755 #[inline(always)]
11756 pub fn dirq0eg(
11757 self,
11758 ) -> crate::common::RegisterField<
11759 0,
11760 0x1,
11761 1,
11762 0,
11763 dpsiegr0::Dirq0Eg,
11764 dpsiegr0::Dirq0Eg,
11765 Dpsiegr0_SPEC,
11766 crate::common::RW,
11767 > {
11768 crate::common::RegisterField::<
11769 0,
11770 0x1,
11771 1,
11772 0,
11773 dpsiegr0::Dirq0Eg,
11774 dpsiegr0::Dirq0Eg,
11775 Dpsiegr0_SPEC,
11776 crate::common::RW,
11777 >::from_register(self, 0)
11778 }
11779
11780 #[doc = "IRQ1-DS Pin Edge Select"]
11781 #[inline(always)]
11782 pub fn dirq1eg(
11783 self,
11784 ) -> crate::common::RegisterField<
11785 1,
11786 0x1,
11787 1,
11788 0,
11789 dpsiegr0::Dirq1Eg,
11790 dpsiegr0::Dirq1Eg,
11791 Dpsiegr0_SPEC,
11792 crate::common::RW,
11793 > {
11794 crate::common::RegisterField::<
11795 1,
11796 0x1,
11797 1,
11798 0,
11799 dpsiegr0::Dirq1Eg,
11800 dpsiegr0::Dirq1Eg,
11801 Dpsiegr0_SPEC,
11802 crate::common::RW,
11803 >::from_register(self, 0)
11804 }
11805
11806 #[doc = "IRQ2-DS Pin Edge Select"]
11807 #[inline(always)]
11808 pub fn dirq2eg(
11809 self,
11810 ) -> crate::common::RegisterField<
11811 2,
11812 0x1,
11813 1,
11814 0,
11815 dpsiegr0::Dirq2Eg,
11816 dpsiegr0::Dirq2Eg,
11817 Dpsiegr0_SPEC,
11818 crate::common::RW,
11819 > {
11820 crate::common::RegisterField::<
11821 2,
11822 0x1,
11823 1,
11824 0,
11825 dpsiegr0::Dirq2Eg,
11826 dpsiegr0::Dirq2Eg,
11827 Dpsiegr0_SPEC,
11828 crate::common::RW,
11829 >::from_register(self, 0)
11830 }
11831
11832 #[doc = "IRQ3-DS Pin Edge Select"]
11833 #[inline(always)]
11834 pub fn dirq3eg(
11835 self,
11836 ) -> crate::common::RegisterField<
11837 3,
11838 0x1,
11839 1,
11840 0,
11841 dpsiegr0::Dirq3Eg,
11842 dpsiegr0::Dirq3Eg,
11843 Dpsiegr0_SPEC,
11844 crate::common::RW,
11845 > {
11846 crate::common::RegisterField::<
11847 3,
11848 0x1,
11849 1,
11850 0,
11851 dpsiegr0::Dirq3Eg,
11852 dpsiegr0::Dirq3Eg,
11853 Dpsiegr0_SPEC,
11854 crate::common::RW,
11855 >::from_register(self, 0)
11856 }
11857
11858 #[doc = "IRQ4-DS Pin Edge Select"]
11859 #[inline(always)]
11860 pub fn dirq4eg(
11861 self,
11862 ) -> crate::common::RegisterField<
11863 4,
11864 0x1,
11865 1,
11866 0,
11867 dpsiegr0::Dirq4Eg,
11868 dpsiegr0::Dirq4Eg,
11869 Dpsiegr0_SPEC,
11870 crate::common::RW,
11871 > {
11872 crate::common::RegisterField::<
11873 4,
11874 0x1,
11875 1,
11876 0,
11877 dpsiegr0::Dirq4Eg,
11878 dpsiegr0::Dirq4Eg,
11879 Dpsiegr0_SPEC,
11880 crate::common::RW,
11881 >::from_register(self, 0)
11882 }
11883
11884 #[doc = "IRQ5-DS Pin Edge Select"]
11885 #[inline(always)]
11886 pub fn dirq5eg(
11887 self,
11888 ) -> crate::common::RegisterField<
11889 5,
11890 0x1,
11891 1,
11892 0,
11893 dpsiegr0::Dirq5Eg,
11894 dpsiegr0::Dirq5Eg,
11895 Dpsiegr0_SPEC,
11896 crate::common::RW,
11897 > {
11898 crate::common::RegisterField::<
11899 5,
11900 0x1,
11901 1,
11902 0,
11903 dpsiegr0::Dirq5Eg,
11904 dpsiegr0::Dirq5Eg,
11905 Dpsiegr0_SPEC,
11906 crate::common::RW,
11907 >::from_register(self, 0)
11908 }
11909
11910 #[doc = "IRQ6-DS Pin Edge Select"]
11911 #[inline(always)]
11912 pub fn dirq6eg(
11913 self,
11914 ) -> crate::common::RegisterField<
11915 6,
11916 0x1,
11917 1,
11918 0,
11919 dpsiegr0::Dirq6Eg,
11920 dpsiegr0::Dirq6Eg,
11921 Dpsiegr0_SPEC,
11922 crate::common::RW,
11923 > {
11924 crate::common::RegisterField::<
11925 6,
11926 0x1,
11927 1,
11928 0,
11929 dpsiegr0::Dirq6Eg,
11930 dpsiegr0::Dirq6Eg,
11931 Dpsiegr0_SPEC,
11932 crate::common::RW,
11933 >::from_register(self, 0)
11934 }
11935
11936 #[doc = "IRQ7-DS Pin Edge Select"]
11937 #[inline(always)]
11938 pub fn dirq7eg(
11939 self,
11940 ) -> crate::common::RegisterField<
11941 7,
11942 0x1,
11943 1,
11944 0,
11945 dpsiegr0::Dirq7Eg,
11946 dpsiegr0::Dirq7Eg,
11947 Dpsiegr0_SPEC,
11948 crate::common::RW,
11949 > {
11950 crate::common::RegisterField::<
11951 7,
11952 0x1,
11953 1,
11954 0,
11955 dpsiegr0::Dirq7Eg,
11956 dpsiegr0::Dirq7Eg,
11957 Dpsiegr0_SPEC,
11958 crate::common::RW,
11959 >::from_register(self, 0)
11960 }
11961}
11962impl ::core::default::Default for Dpsiegr0 {
11963 #[inline(always)]
11964 fn default() -> Dpsiegr0 {
11965 <crate::RegValueT<Dpsiegr0_SPEC> as RegisterValue<_>>::new(0)
11966 }
11967}
11968pub mod dpsiegr0 {
11969
11970 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11971 pub struct Dirq0Eg_SPEC;
11972 pub type Dirq0Eg = crate::EnumBitfieldStruct<u8, Dirq0Eg_SPEC>;
11973 impl Dirq0Eg {
11974 #[doc = "A cancel request is generated at a falling edge"]
11975 pub const _0: Self = Self::new(0);
11976
11977 #[doc = "A cancel request is generated at a rising edge"]
11978 pub const _1: Self = Self::new(1);
11979 }
11980 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11981 pub struct Dirq1Eg_SPEC;
11982 pub type Dirq1Eg = crate::EnumBitfieldStruct<u8, Dirq1Eg_SPEC>;
11983 impl Dirq1Eg {
11984 #[doc = "A cancel request is generated at a falling edge"]
11985 pub const _0: Self = Self::new(0);
11986
11987 #[doc = "A cancel request is generated at a rising edge"]
11988 pub const _1: Self = Self::new(1);
11989 }
11990 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11991 pub struct Dirq2Eg_SPEC;
11992 pub type Dirq2Eg = crate::EnumBitfieldStruct<u8, Dirq2Eg_SPEC>;
11993 impl Dirq2Eg {
11994 #[doc = "A cancel request is generated at a falling edge"]
11995 pub const _0: Self = Self::new(0);
11996
11997 #[doc = "A cancel request is generated at a rising edge"]
11998 pub const _1: Self = Self::new(1);
11999 }
12000 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12001 pub struct Dirq3Eg_SPEC;
12002 pub type Dirq3Eg = crate::EnumBitfieldStruct<u8, Dirq3Eg_SPEC>;
12003 impl Dirq3Eg {
12004 #[doc = "A cancel request is generated at a falling edge"]
12005 pub const _0: Self = Self::new(0);
12006
12007 #[doc = "A cancel request is generated at a rising edge"]
12008 pub const _1: Self = Self::new(1);
12009 }
12010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12011 pub struct Dirq4Eg_SPEC;
12012 pub type Dirq4Eg = crate::EnumBitfieldStruct<u8, Dirq4Eg_SPEC>;
12013 impl Dirq4Eg {
12014 #[doc = "A cancel request is generated at a falling edge"]
12015 pub const _0: Self = Self::new(0);
12016
12017 #[doc = "A cancel request is generated at a rising edge"]
12018 pub const _1: Self = Self::new(1);
12019 }
12020 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12021 pub struct Dirq5Eg_SPEC;
12022 pub type Dirq5Eg = crate::EnumBitfieldStruct<u8, Dirq5Eg_SPEC>;
12023 impl Dirq5Eg {
12024 #[doc = "A cancel request is generated at a falling edge"]
12025 pub const _0: Self = Self::new(0);
12026
12027 #[doc = "A cancel request is generated at a rising edge"]
12028 pub const _1: Self = Self::new(1);
12029 }
12030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12031 pub struct Dirq6Eg_SPEC;
12032 pub type Dirq6Eg = crate::EnumBitfieldStruct<u8, Dirq6Eg_SPEC>;
12033 impl Dirq6Eg {
12034 #[doc = "A cancel request is generated at a falling edge"]
12035 pub const _0: Self = Self::new(0);
12036
12037 #[doc = "A cancel request is generated at a rising edge"]
12038 pub const _1: Self = Self::new(1);
12039 }
12040 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12041 pub struct Dirq7Eg_SPEC;
12042 pub type Dirq7Eg = crate::EnumBitfieldStruct<u8, Dirq7Eg_SPEC>;
12043 impl Dirq7Eg {
12044 #[doc = "A cancel request is generated at a falling edge"]
12045 pub const _0: Self = Self::new(0);
12046
12047 #[doc = "A cancel request is generated at a rising edge"]
12048 pub const _1: Self = Self::new(1);
12049 }
12050}
12051#[doc(hidden)]
12052#[derive(Copy, Clone, Eq, PartialEq)]
12053pub struct Dpsiegr1_SPEC;
12054impl crate::sealed::RegSpec for Dpsiegr1_SPEC {
12055 type DataType = u8;
12056}
12057
12058#[doc = "Deep Software Standby Interrupt Edge Register 1"]
12059pub type Dpsiegr1 = crate::RegValueT<Dpsiegr1_SPEC>;
12060
12061impl Dpsiegr1 {
12062 #[doc = "IRQ8-DS Pin Edge Select"]
12063 #[inline(always)]
12064 pub fn dirq8eg(
12065 self,
12066 ) -> crate::common::RegisterField<
12067 0,
12068 0x1,
12069 1,
12070 0,
12071 dpsiegr1::Dirq8Eg,
12072 dpsiegr1::Dirq8Eg,
12073 Dpsiegr1_SPEC,
12074 crate::common::RW,
12075 > {
12076 crate::common::RegisterField::<
12077 0,
12078 0x1,
12079 1,
12080 0,
12081 dpsiegr1::Dirq8Eg,
12082 dpsiegr1::Dirq8Eg,
12083 Dpsiegr1_SPEC,
12084 crate::common::RW,
12085 >::from_register(self, 0)
12086 }
12087
12088 #[doc = "IRQ9-DS Pin Edge Select"]
12089 #[inline(always)]
12090 pub fn dirq9eg(
12091 self,
12092 ) -> crate::common::RegisterField<
12093 1,
12094 0x1,
12095 1,
12096 0,
12097 dpsiegr1::Dirq9Eg,
12098 dpsiegr1::Dirq9Eg,
12099 Dpsiegr1_SPEC,
12100 crate::common::RW,
12101 > {
12102 crate::common::RegisterField::<
12103 1,
12104 0x1,
12105 1,
12106 0,
12107 dpsiegr1::Dirq9Eg,
12108 dpsiegr1::Dirq9Eg,
12109 Dpsiegr1_SPEC,
12110 crate::common::RW,
12111 >::from_register(self, 0)
12112 }
12113
12114 #[doc = "IRQ10-DS Pin Edge Select"]
12115 #[inline(always)]
12116 pub fn dirq10eg(
12117 self,
12118 ) -> crate::common::RegisterField<
12119 2,
12120 0x1,
12121 1,
12122 0,
12123 dpsiegr1::Dirq10Eg,
12124 dpsiegr1::Dirq10Eg,
12125 Dpsiegr1_SPEC,
12126 crate::common::RW,
12127 > {
12128 crate::common::RegisterField::<
12129 2,
12130 0x1,
12131 1,
12132 0,
12133 dpsiegr1::Dirq10Eg,
12134 dpsiegr1::Dirq10Eg,
12135 Dpsiegr1_SPEC,
12136 crate::common::RW,
12137 >::from_register(self, 0)
12138 }
12139
12140 #[doc = "IRQ11-DS Pin Edge Select"]
12141 #[inline(always)]
12142 pub fn dirq11eg(
12143 self,
12144 ) -> crate::common::RegisterField<
12145 3,
12146 0x1,
12147 1,
12148 0,
12149 dpsiegr1::Dirq11Eg,
12150 dpsiegr1::Dirq11Eg,
12151 Dpsiegr1_SPEC,
12152 crate::common::RW,
12153 > {
12154 crate::common::RegisterField::<
12155 3,
12156 0x1,
12157 1,
12158 0,
12159 dpsiegr1::Dirq11Eg,
12160 dpsiegr1::Dirq11Eg,
12161 Dpsiegr1_SPEC,
12162 crate::common::RW,
12163 >::from_register(self, 0)
12164 }
12165
12166 #[doc = "IRQ12-DS Pin Edge Select"]
12167 #[inline(always)]
12168 pub fn dirq12eg(
12169 self,
12170 ) -> crate::common::RegisterField<
12171 4,
12172 0x1,
12173 1,
12174 0,
12175 dpsiegr1::Dirq12Eg,
12176 dpsiegr1::Dirq12Eg,
12177 Dpsiegr1_SPEC,
12178 crate::common::RW,
12179 > {
12180 crate::common::RegisterField::<
12181 4,
12182 0x1,
12183 1,
12184 0,
12185 dpsiegr1::Dirq12Eg,
12186 dpsiegr1::Dirq12Eg,
12187 Dpsiegr1_SPEC,
12188 crate::common::RW,
12189 >::from_register(self, 0)
12190 }
12191
12192 #[doc = "IRQ13-DS Pin Edge Select"]
12193 #[inline(always)]
12194 pub fn dirq13eg(
12195 self,
12196 ) -> crate::common::RegisterField<
12197 5,
12198 0x1,
12199 1,
12200 0,
12201 dpsiegr1::Dirq13Eg,
12202 dpsiegr1::Dirq13Eg,
12203 Dpsiegr1_SPEC,
12204 crate::common::RW,
12205 > {
12206 crate::common::RegisterField::<
12207 5,
12208 0x1,
12209 1,
12210 0,
12211 dpsiegr1::Dirq13Eg,
12212 dpsiegr1::Dirq13Eg,
12213 Dpsiegr1_SPEC,
12214 crate::common::RW,
12215 >::from_register(self, 0)
12216 }
12217
12218 #[doc = "IRQ14-DS Pin Edge Select"]
12219 #[inline(always)]
12220 pub fn dirq14eg(
12221 self,
12222 ) -> crate::common::RegisterField<
12223 6,
12224 0x1,
12225 1,
12226 0,
12227 dpsiegr1::Dirq14Eg,
12228 dpsiegr1::Dirq14Eg,
12229 Dpsiegr1_SPEC,
12230 crate::common::RW,
12231 > {
12232 crate::common::RegisterField::<
12233 6,
12234 0x1,
12235 1,
12236 0,
12237 dpsiegr1::Dirq14Eg,
12238 dpsiegr1::Dirq14Eg,
12239 Dpsiegr1_SPEC,
12240 crate::common::RW,
12241 >::from_register(self, 0)
12242 }
12243
12244 #[doc = "IRQ15-DS Pin Edge Select"]
12245 #[inline(always)]
12246 pub fn dirq15eg(
12247 self,
12248 ) -> crate::common::RegisterField<
12249 7,
12250 0x1,
12251 1,
12252 0,
12253 dpsiegr1::Dirq15Eg,
12254 dpsiegr1::Dirq15Eg,
12255 Dpsiegr1_SPEC,
12256 crate::common::RW,
12257 > {
12258 crate::common::RegisterField::<
12259 7,
12260 0x1,
12261 1,
12262 0,
12263 dpsiegr1::Dirq15Eg,
12264 dpsiegr1::Dirq15Eg,
12265 Dpsiegr1_SPEC,
12266 crate::common::RW,
12267 >::from_register(self, 0)
12268 }
12269}
12270impl ::core::default::Default for Dpsiegr1 {
12271 #[inline(always)]
12272 fn default() -> Dpsiegr1 {
12273 <crate::RegValueT<Dpsiegr1_SPEC> as RegisterValue<_>>::new(0)
12274 }
12275}
12276pub mod dpsiegr1 {
12277
12278 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12279 pub struct Dirq8Eg_SPEC;
12280 pub type Dirq8Eg = crate::EnumBitfieldStruct<u8, Dirq8Eg_SPEC>;
12281 impl Dirq8Eg {
12282 #[doc = "A cancel request is generated at a falling edge."]
12283 pub const _0: Self = Self::new(0);
12284
12285 #[doc = "A cancel request is generated at a rising edge."]
12286 pub const _1: Self = Self::new(1);
12287 }
12288 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12289 pub struct Dirq9Eg_SPEC;
12290 pub type Dirq9Eg = crate::EnumBitfieldStruct<u8, Dirq9Eg_SPEC>;
12291 impl Dirq9Eg {
12292 #[doc = "A cancel request is generated at a falling edge."]
12293 pub const _0: Self = Self::new(0);
12294
12295 #[doc = "A cancel request is generated at a rising edge."]
12296 pub const _1: Self = Self::new(1);
12297 }
12298 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12299 pub struct Dirq10Eg_SPEC;
12300 pub type Dirq10Eg = crate::EnumBitfieldStruct<u8, Dirq10Eg_SPEC>;
12301 impl Dirq10Eg {
12302 #[doc = "A cancel request is generated at a falling edge."]
12303 pub const _0: Self = Self::new(0);
12304
12305 #[doc = "A cancel request is generated at a rising edge"]
12306 pub const _1: Self = Self::new(1);
12307 }
12308 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12309 pub struct Dirq11Eg_SPEC;
12310 pub type Dirq11Eg = crate::EnumBitfieldStruct<u8, Dirq11Eg_SPEC>;
12311 impl Dirq11Eg {
12312 #[doc = "A cancel request is generated at a falling edge."]
12313 pub const _0: Self = Self::new(0);
12314
12315 #[doc = "A cancel request is generated at a rising edge."]
12316 pub const _1: Self = Self::new(1);
12317 }
12318 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12319 pub struct Dirq12Eg_SPEC;
12320 pub type Dirq12Eg = crate::EnumBitfieldStruct<u8, Dirq12Eg_SPEC>;
12321 impl Dirq12Eg {
12322 #[doc = "A cancel request is generated at a falling edge."]
12323 pub const _0: Self = Self::new(0);
12324
12325 #[doc = "A cancel request is generated at a rising edge."]
12326 pub const _1: Self = Self::new(1);
12327 }
12328 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12329 pub struct Dirq13Eg_SPEC;
12330 pub type Dirq13Eg = crate::EnumBitfieldStruct<u8, Dirq13Eg_SPEC>;
12331 impl Dirq13Eg {
12332 #[doc = "A cancel request is generated at a falling edge."]
12333 pub const _0: Self = Self::new(0);
12334
12335 #[doc = "A cancel request is generated at a rising edge."]
12336 pub const _1: Self = Self::new(1);
12337 }
12338 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12339 pub struct Dirq14Eg_SPEC;
12340 pub type Dirq14Eg = crate::EnumBitfieldStruct<u8, Dirq14Eg_SPEC>;
12341 impl Dirq14Eg {
12342 #[doc = "A cancel request is generated at a falling edge."]
12343 pub const _0: Self = Self::new(0);
12344
12345 #[doc = "A cancel request is generated at a rising edge."]
12346 pub const _1: Self = Self::new(1);
12347 }
12348 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12349 pub struct Dirq15Eg_SPEC;
12350 pub type Dirq15Eg = crate::EnumBitfieldStruct<u8, Dirq15Eg_SPEC>;
12351 impl Dirq15Eg {
12352 #[doc = "A cancel request is generated at a falling edge."]
12353 pub const _0: Self = Self::new(0);
12354
12355 #[doc = "A cancel request is generated at a rising edge."]
12356 pub const _1: Self = Self::new(1);
12357 }
12358}
12359#[doc(hidden)]
12360#[derive(Copy, Clone, Eq, PartialEq)]
12361pub struct Dpsiegr2_SPEC;
12362impl crate::sealed::RegSpec for Dpsiegr2_SPEC {
12363 type DataType = u8;
12364}
12365
12366#[doc = "Deep Software Standby Interrupt Edge Register 2"]
12367pub type Dpsiegr2 = crate::RegValueT<Dpsiegr2_SPEC>;
12368
12369impl Dpsiegr2 {
12370 #[doc = "PVD1 Edge Select"]
12371 #[inline(always)]
12372 pub fn dpvd1eg(
12373 self,
12374 ) -> crate::common::RegisterField<
12375 0,
12376 0x1,
12377 1,
12378 0,
12379 dpsiegr2::Dpvd1Eg,
12380 dpsiegr2::Dpvd1Eg,
12381 Dpsiegr2_SPEC,
12382 crate::common::RW,
12383 > {
12384 crate::common::RegisterField::<
12385 0,
12386 0x1,
12387 1,
12388 0,
12389 dpsiegr2::Dpvd1Eg,
12390 dpsiegr2::Dpvd1Eg,
12391 Dpsiegr2_SPEC,
12392 crate::common::RW,
12393 >::from_register(self, 0)
12394 }
12395
12396 #[doc = "PVD2 Edge Select"]
12397 #[inline(always)]
12398 pub fn dpvd2eg(
12399 self,
12400 ) -> crate::common::RegisterField<
12401 1,
12402 0x1,
12403 1,
12404 0,
12405 dpsiegr2::Dpvd2Eg,
12406 dpsiegr2::Dpvd2Eg,
12407 Dpsiegr2_SPEC,
12408 crate::common::RW,
12409 > {
12410 crate::common::RegisterField::<
12411 1,
12412 0x1,
12413 1,
12414 0,
12415 dpsiegr2::Dpvd2Eg,
12416 dpsiegr2::Dpvd2Eg,
12417 Dpsiegr2_SPEC,
12418 crate::common::RW,
12419 >::from_register(self, 0)
12420 }
12421
12422 #[doc = "NMI Pin Edge Select"]
12423 #[inline(always)]
12424 pub fn dnmieg(
12425 self,
12426 ) -> crate::common::RegisterField<
12427 4,
12428 0x1,
12429 1,
12430 0,
12431 dpsiegr2::Dnmieg,
12432 dpsiegr2::Dnmieg,
12433 Dpsiegr2_SPEC,
12434 crate::common::RW,
12435 > {
12436 crate::common::RegisterField::<
12437 4,
12438 0x1,
12439 1,
12440 0,
12441 dpsiegr2::Dnmieg,
12442 dpsiegr2::Dnmieg,
12443 Dpsiegr2_SPEC,
12444 crate::common::RW,
12445 >::from_register(self, 0)
12446 }
12447}
12448impl ::core::default::Default for Dpsiegr2 {
12449 #[inline(always)]
12450 fn default() -> Dpsiegr2 {
12451 <crate::RegValueT<Dpsiegr2_SPEC> as RegisterValue<_>>::new(0)
12452 }
12453}
12454pub mod dpsiegr2 {
12455
12456 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12457 pub struct Dpvd1Eg_SPEC;
12458 pub type Dpvd1Eg = crate::EnumBitfieldStruct<u8, Dpvd1Eg_SPEC>;
12459 impl Dpvd1Eg {
12460 #[doc = "A cancel request is generated when VCC < Vdet1 (fall) is detected"]
12461 pub const _0: Self = Self::new(0);
12462
12463 #[doc = "A cancel request is generated when VCC ≥ Vdet1 (rise) is detected"]
12464 pub const _1: Self = Self::new(1);
12465 }
12466 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12467 pub struct Dpvd2Eg_SPEC;
12468 pub type Dpvd2Eg = crate::EnumBitfieldStruct<u8, Dpvd2Eg_SPEC>;
12469 impl Dpvd2Eg {
12470 #[doc = "A cancel request is generated when VCC < Vdet2 (fall) is detected"]
12471 pub const _0: Self = Self::new(0);
12472
12473 #[doc = "A cancel request is generated when VCC ≥ Vdet2 (rise) is detected"]
12474 pub const _1: Self = Self::new(1);
12475 }
12476 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12477 pub struct Dnmieg_SPEC;
12478 pub type Dnmieg = crate::EnumBitfieldStruct<u8, Dnmieg_SPEC>;
12479 impl Dnmieg {
12480 #[doc = "A cancel request is generated at a falling edge"]
12481 pub const _0: Self = Self::new(0);
12482
12483 #[doc = "A cancel request is generated at a rising edge"]
12484 pub const _1: Self = Self::new(1);
12485 }
12486}
12487#[doc(hidden)]
12488#[derive(Copy, Clone, Eq, PartialEq)]
12489pub struct Syocdcr_SPEC;
12490impl crate::sealed::RegSpec for Syocdcr_SPEC {
12491 type DataType = u8;
12492}
12493
12494#[doc = "System Control OCD Control Register"]
12495pub type Syocdcr = crate::RegValueT<Syocdcr_SPEC>;
12496
12497impl Syocdcr {
12498 #[doc = "Debugger Enable bit"]
12499 #[inline(always)]
12500 pub fn dbgen(
12501 self,
12502 ) -> crate::common::RegisterField<
12503 7,
12504 0x1,
12505 1,
12506 0,
12507 syocdcr::Dbgen,
12508 syocdcr::Dbgen,
12509 Syocdcr_SPEC,
12510 crate::common::RW,
12511 > {
12512 crate::common::RegisterField::<
12513 7,
12514 0x1,
12515 1,
12516 0,
12517 syocdcr::Dbgen,
12518 syocdcr::Dbgen,
12519 Syocdcr_SPEC,
12520 crate::common::RW,
12521 >::from_register(self, 0)
12522 }
12523}
12524impl ::core::default::Default for Syocdcr {
12525 #[inline(always)]
12526 fn default() -> Syocdcr {
12527 <crate::RegValueT<Syocdcr_SPEC> as RegisterValue<_>>::new(128)
12528 }
12529}
12530pub mod syocdcr {
12531
12532 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12533 pub struct Dbgen_SPEC;
12534 pub type Dbgen = crate::EnumBitfieldStruct<u8, Dbgen_SPEC>;
12535 impl Dbgen {
12536 #[doc = "On-chip debugger is disabled"]
12537 pub const _0: Self = Self::new(0);
12538
12539 #[doc = "On-chip debugger is enabled"]
12540 pub const _1: Self = Self::new(1);
12541 }
12542}
12543#[doc(hidden)]
12544#[derive(Copy, Clone, Eq, PartialEq)]
12545pub struct Rstsr0_SPEC;
12546impl crate::sealed::RegSpec for Rstsr0_SPEC {
12547 type DataType = u8;
12548}
12549
12550#[doc = "Reset Status Register 0"]
12551pub type Rstsr0 = crate::RegValueT<Rstsr0_SPEC>;
12552
12553impl Rstsr0 {
12554 #[doc = "Power-On Reset Detect Flag"]
12555 #[inline(always)]
12556 pub fn porf(
12557 self,
12558 ) -> crate::common::RegisterField<
12559 0,
12560 0x1,
12561 1,
12562 0,
12563 rstsr0::Porf,
12564 rstsr0::Porf,
12565 Rstsr0_SPEC,
12566 crate::common::RW,
12567 > {
12568 crate::common::RegisterField::<
12569 0,
12570 0x1,
12571 1,
12572 0,
12573 rstsr0::Porf,
12574 rstsr0::Porf,
12575 Rstsr0_SPEC,
12576 crate::common::RW,
12577 >::from_register(self, 0)
12578 }
12579
12580 #[doc = "Voltage Monitor 0 Reset Detect Flag"]
12581 #[inline(always)]
12582 pub fn pvd0rf(
12583 self,
12584 ) -> crate::common::RegisterField<
12585 1,
12586 0x1,
12587 1,
12588 0,
12589 rstsr0::Pvd0Rf,
12590 rstsr0::Pvd0Rf,
12591 Rstsr0_SPEC,
12592 crate::common::RW,
12593 > {
12594 crate::common::RegisterField::<
12595 1,
12596 0x1,
12597 1,
12598 0,
12599 rstsr0::Pvd0Rf,
12600 rstsr0::Pvd0Rf,
12601 Rstsr0_SPEC,
12602 crate::common::RW,
12603 >::from_register(self, 0)
12604 }
12605
12606 #[doc = "Voltage Monitor 1 Reset Detect Flag"]
12607 #[inline(always)]
12608 pub fn pvd1rf(
12609 self,
12610 ) -> crate::common::RegisterField<
12611 2,
12612 0x1,
12613 1,
12614 0,
12615 rstsr0::Pvd1Rf,
12616 rstsr0::Pvd1Rf,
12617 Rstsr0_SPEC,
12618 crate::common::RW,
12619 > {
12620 crate::common::RegisterField::<
12621 2,
12622 0x1,
12623 1,
12624 0,
12625 rstsr0::Pvd1Rf,
12626 rstsr0::Pvd1Rf,
12627 Rstsr0_SPEC,
12628 crate::common::RW,
12629 >::from_register(self, 0)
12630 }
12631
12632 #[doc = "Voltage Monitor 2 Reset Detect Flag"]
12633 #[inline(always)]
12634 pub fn pvd2rf(
12635 self,
12636 ) -> crate::common::RegisterField<
12637 3,
12638 0x1,
12639 1,
12640 0,
12641 rstsr0::Pvd2Rf,
12642 rstsr0::Pvd2Rf,
12643 Rstsr0_SPEC,
12644 crate::common::RW,
12645 > {
12646 crate::common::RegisterField::<
12647 3,
12648 0x1,
12649 1,
12650 0,
12651 rstsr0::Pvd2Rf,
12652 rstsr0::Pvd2Rf,
12653 Rstsr0_SPEC,
12654 crate::common::RW,
12655 >::from_register(self, 0)
12656 }
12657
12658 #[doc = "Deep Software Standby Reset Flag"]
12659 #[inline(always)]
12660 pub fn dpsrstf(
12661 self,
12662 ) -> crate::common::RegisterField<
12663 7,
12664 0x1,
12665 1,
12666 0,
12667 rstsr0::Dpsrstf,
12668 rstsr0::Dpsrstf,
12669 Rstsr0_SPEC,
12670 crate::common::RW,
12671 > {
12672 crate::common::RegisterField::<
12673 7,
12674 0x1,
12675 1,
12676 0,
12677 rstsr0::Dpsrstf,
12678 rstsr0::Dpsrstf,
12679 Rstsr0_SPEC,
12680 crate::common::RW,
12681 >::from_register(self, 0)
12682 }
12683}
12684impl ::core::default::Default for Rstsr0 {
12685 #[inline(always)]
12686 fn default() -> Rstsr0 {
12687 <crate::RegValueT<Rstsr0_SPEC> as RegisterValue<_>>::new(0)
12688 }
12689}
12690pub mod rstsr0 {
12691
12692 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12693 pub struct Porf_SPEC;
12694 pub type Porf = crate::EnumBitfieldStruct<u8, Porf_SPEC>;
12695 impl Porf {
12696 #[doc = "Power-on reset not detected"]
12697 pub const _0: Self = Self::new(0);
12698
12699 #[doc = "Power-on reset detected"]
12700 pub const _1: Self = Self::new(1);
12701 }
12702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12703 pub struct Pvd0Rf_SPEC;
12704 pub type Pvd0Rf = crate::EnumBitfieldStruct<u8, Pvd0Rf_SPEC>;
12705 impl Pvd0Rf {
12706 #[doc = "Voltage monitor 0 reset not detected"]
12707 pub const _0: Self = Self::new(0);
12708
12709 #[doc = "Voltage monitor 0 reset detected"]
12710 pub const _1: Self = Self::new(1);
12711 }
12712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12713 pub struct Pvd1Rf_SPEC;
12714 pub type Pvd1Rf = crate::EnumBitfieldStruct<u8, Pvd1Rf_SPEC>;
12715 impl Pvd1Rf {
12716 #[doc = "Voltage monitor 1 reset not detected"]
12717 pub const _0: Self = Self::new(0);
12718
12719 #[doc = "Voltage monitor 1 reset detected"]
12720 pub const _1: Self = Self::new(1);
12721 }
12722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12723 pub struct Pvd2Rf_SPEC;
12724 pub type Pvd2Rf = crate::EnumBitfieldStruct<u8, Pvd2Rf_SPEC>;
12725 impl Pvd2Rf {
12726 #[doc = "Voltage monitor 2 reset not detected"]
12727 pub const _0: Self = Self::new(0);
12728
12729 #[doc = "Voltage monitor 2 reset detected"]
12730 pub const _1: Self = Self::new(1);
12731 }
12732 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12733 pub struct Dpsrstf_SPEC;
12734 pub type Dpsrstf = crate::EnumBitfieldStruct<u8, Dpsrstf_SPEC>;
12735 impl Dpsrstf {
12736 #[doc = "Deep Software Standby mode cancellation not requested by an interrupt or a reset."]
12737 pub const _0: Self = Self::new(0);
12738
12739 #[doc = "Deep Software Standby mode cancellation requested by an interrupt or a reset."]
12740 pub const _1: Self = Self::new(1);
12741 }
12742}
12743#[doc(hidden)]
12744#[derive(Copy, Clone, Eq, PartialEq)]
12745pub struct Rstsr2_SPEC;
12746impl crate::sealed::RegSpec for Rstsr2_SPEC {
12747 type DataType = u8;
12748}
12749
12750#[doc = "Reset Status Register 2"]
12751pub type Rstsr2 = crate::RegValueT<Rstsr2_SPEC>;
12752
12753impl Rstsr2 {
12754 #[doc = "Cold/Warm Start Determination Flag"]
12755 #[inline(always)]
12756 pub fn cwsf(
12757 self,
12758 ) -> crate::common::RegisterField<
12759 0,
12760 0x1,
12761 1,
12762 0,
12763 rstsr2::Cwsf,
12764 rstsr2::Cwsf,
12765 Rstsr2_SPEC,
12766 crate::common::RW,
12767 > {
12768 crate::common::RegisterField::<
12769 0,
12770 0x1,
12771 1,
12772 0,
12773 rstsr2::Cwsf,
12774 rstsr2::Cwsf,
12775 Rstsr2_SPEC,
12776 crate::common::RW,
12777 >::from_register(self, 0)
12778 }
12779}
12780impl ::core::default::Default for Rstsr2 {
12781 #[inline(always)]
12782 fn default() -> Rstsr2 {
12783 <crate::RegValueT<Rstsr2_SPEC> as RegisterValue<_>>::new(0)
12784 }
12785}
12786pub mod rstsr2 {
12787
12788 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12789 pub struct Cwsf_SPEC;
12790 pub type Cwsf = crate::EnumBitfieldStruct<u8, Cwsf_SPEC>;
12791 impl Cwsf {
12792 #[doc = "Cold start"]
12793 pub const _0: Self = Self::new(0);
12794
12795 #[doc = "Warm start"]
12796 pub const _1: Self = Self::new(1);
12797 }
12798}
12799#[doc(hidden)]
12800#[derive(Copy, Clone, Eq, PartialEq)]
12801pub struct Momcr_SPEC;
12802impl crate::sealed::RegSpec for Momcr_SPEC {
12803 type DataType = u8;
12804}
12805
12806#[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
12807pub type Momcr = crate::RegValueT<Momcr_SPEC>;
12808
12809impl Momcr {
12810 #[doc = "Main Clock Oscillator Drive Capability 0 Switching"]
12811 #[inline(always)]
12812 pub fn modrv0(
12813 self,
12814 ) -> crate::common::RegisterField<
12815 1,
12816 0x7,
12817 1,
12818 0,
12819 momcr::Modrv0,
12820 momcr::Modrv0,
12821 Momcr_SPEC,
12822 crate::common::RW,
12823 > {
12824 crate::common::RegisterField::<
12825 1,
12826 0x7,
12827 1,
12828 0,
12829 momcr::Modrv0,
12830 momcr::Modrv0,
12831 Momcr_SPEC,
12832 crate::common::RW,
12833 >::from_register(self, 0)
12834 }
12835
12836 #[doc = "Main Clock Oscillator Switching"]
12837 #[inline(always)]
12838 pub fn mosel(
12839 self,
12840 ) -> crate::common::RegisterField<
12841 6,
12842 0x1,
12843 1,
12844 0,
12845 momcr::Mosel,
12846 momcr::Mosel,
12847 Momcr_SPEC,
12848 crate::common::RW,
12849 > {
12850 crate::common::RegisterField::<
12851 6,
12852 0x1,
12853 1,
12854 0,
12855 momcr::Mosel,
12856 momcr::Mosel,
12857 Momcr_SPEC,
12858 crate::common::RW,
12859 >::from_register(self, 0)
12860 }
12861}
12862impl ::core::default::Default for Momcr {
12863 #[inline(always)]
12864 fn default() -> Momcr {
12865 <crate::RegValueT<Momcr_SPEC> as RegisterValue<_>>::new(26)
12866 }
12867}
12868pub mod momcr {
12869
12870 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12871 pub struct Modrv0_SPEC;
12872 pub type Modrv0 = crate::EnumBitfieldStruct<u8, Modrv0_SPEC>;
12873 impl Modrv0 {
12874 #[doc = "8 MHz"]
12875 pub const _000: Self = Self::new(0);
12876
12877 #[doc = "8 MHz to 24 MHz"]
12878 pub const _011: Self = Self::new(3);
12879
12880 #[doc = "8 MHz to 48 MHz"]
12881 pub const _101: Self = Self::new(5);
12882
12883 #[doc = "Setting prohibited"]
12884 pub const OTHERS: Self = Self::new(0);
12885 }
12886 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12887 pub struct Mosel_SPEC;
12888 pub type Mosel = crate::EnumBitfieldStruct<u8, Mosel_SPEC>;
12889 impl Mosel {
12890 #[doc = "Resonator"]
12891 pub const _0: Self = Self::new(0);
12892
12893 #[doc = "External clock input"]
12894 pub const _1: Self = Self::new(1);
12895 }
12896}
12897#[doc(hidden)]
12898#[derive(Copy, Clone, Eq, PartialEq)]
12899pub struct Fwepror_SPEC;
12900impl crate::sealed::RegSpec for Fwepror_SPEC {
12901 type DataType = u8;
12902}
12903
12904#[doc = "Flash P/E Protect Register"]
12905pub type Fwepror = crate::RegValueT<Fwepror_SPEC>;
12906
12907impl Fwepror {
12908 #[doc = "Flash Programming and Erasure"]
12909 #[inline(always)]
12910 pub fn flwe(
12911 self,
12912 ) -> crate::common::RegisterField<
12913 0,
12914 0x3,
12915 1,
12916 0,
12917 fwepror::Flwe,
12918 fwepror::Flwe,
12919 Fwepror_SPEC,
12920 crate::common::RW,
12921 > {
12922 crate::common::RegisterField::<
12923 0,
12924 0x3,
12925 1,
12926 0,
12927 fwepror::Flwe,
12928 fwepror::Flwe,
12929 Fwepror_SPEC,
12930 crate::common::RW,
12931 >::from_register(self, 0)
12932 }
12933}
12934impl ::core::default::Default for Fwepror {
12935 #[inline(always)]
12936 fn default() -> Fwepror {
12937 <crate::RegValueT<Fwepror_SPEC> as RegisterValue<_>>::new(2)
12938 }
12939}
12940pub mod fwepror {
12941
12942 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12943 pub struct Flwe_SPEC;
12944 pub type Flwe = crate::EnumBitfieldStruct<u8, Flwe_SPEC>;
12945 impl Flwe {
12946 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
12947 pub const _00: Self = Self::new(0);
12948
12949 #[doc = "Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
12950 pub const _01: Self = Self::new(1);
12951
12952 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
12953 pub const _10: Self = Self::new(2);
12954
12955 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
12956 pub const _11: Self = Self::new(3);
12957 }
12958}
12959#[doc(hidden)]
12960#[derive(Copy, Clone, Eq, PartialEq)]
12961pub struct Pvdcmpcr_SPEC;
12962impl crate::sealed::RegSpec for Pvdcmpcr_SPEC {
12963 type DataType = u8;
12964}
12965
12966#[doc = "Voltage Monitor %s Comparator Control Register"]
12967pub type Pvdcmpcr = crate::RegValueT<Pvdcmpcr_SPEC>;
12968
12969impl Pvdcmpcr {
12970 #[doc = "Detection Voltage m Level Select"]
12971 #[inline(always)]
12972 pub fn pvdlvl(
12973 self,
12974 ) -> crate::common::RegisterField<
12975 0,
12976 0x1f,
12977 1,
12978 0,
12979 pvdcmpcr::Pvdlvl,
12980 pvdcmpcr::Pvdlvl,
12981 Pvdcmpcr_SPEC,
12982 crate::common::RW,
12983 > {
12984 crate::common::RegisterField::<
12985 0,
12986 0x1f,
12987 1,
12988 0,
12989 pvdcmpcr::Pvdlvl,
12990 pvdcmpcr::Pvdlvl,
12991 Pvdcmpcr_SPEC,
12992 crate::common::RW,
12993 >::from_register(self, 0)
12994 }
12995
12996 #[doc = "Voltage Detection m Enable"]
12997 #[inline(always)]
12998 pub fn pvde(
12999 self,
13000 ) -> crate::common::RegisterField<
13001 7,
13002 0x1,
13003 1,
13004 0,
13005 pvdcmpcr::Pvde,
13006 pvdcmpcr::Pvde,
13007 Pvdcmpcr_SPEC,
13008 crate::common::RW,
13009 > {
13010 crate::common::RegisterField::<
13011 7,
13012 0x1,
13013 1,
13014 0,
13015 pvdcmpcr::Pvde,
13016 pvdcmpcr::Pvde,
13017 Pvdcmpcr_SPEC,
13018 crate::common::RW,
13019 >::from_register(self, 0)
13020 }
13021}
13022impl ::core::default::Default for Pvdcmpcr {
13023 #[inline(always)]
13024 fn default() -> Pvdcmpcr {
13025 <crate::RegValueT<Pvdcmpcr_SPEC> as RegisterValue<_>>::new(15)
13026 }
13027}
13028pub mod pvdcmpcr {
13029
13030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13031 pub struct Pvdlvl_SPEC;
13032 pub type Pvdlvl = crate::EnumBitfieldStruct<u8, Pvdlvl_SPEC>;
13033 impl Pvdlvl {
13034 #[doc = "3.86 V (Vdetm_3)"]
13035 pub const _0_X_03: Self = Self::new(3);
13036
13037 #[doc = "3.14 V (Vdetm_4)"]
13038 pub const _0_X_04: Self = Self::new(4);
13039
13040 #[doc = "3.10 V (Vdetm_5)"]
13041 pub const _0_X_05: Self = Self::new(5);
13042
13043 #[doc = "3.08 V (Vdetm_6)"]
13044 pub const _0_X_06: Self = Self::new(6);
13045
13046 #[doc = "2.85 V (Vdetm_7)"]
13047 pub const _0_X_07: Self = Self::new(7);
13048
13049 #[doc = "2.83 V (Vdetm_8)"]
13050 pub const _0_X_08: Self = Self::new(8);
13051
13052 #[doc = "2.80 V (Vdetm_9)"]
13053 pub const _0_X_09: Self = Self::new(9);
13054
13055 #[doc = "2.62V (Vdetm_10)"]
13056 pub const _0_X_0_A: Self = Self::new(10);
13057
13058 #[doc = "2.33V (Vdetm_11)"]
13059 pub const _0_X_0_B: Self = Self::new(11);
13060
13061 #[doc = "1.90V (Vdetm_12)"]
13062 pub const _0_X_0_C: Self = Self::new(12);
13063
13064 #[doc = "1.86V (Vdetm_13)"]
13065 pub const _0_X_0_D: Self = Self::new(13);
13066
13067 #[doc = "1.74V (Vdetm_14)"]
13068 pub const _0_X_0_E: Self = Self::new(14);
13069
13070 #[doc = "1.71V (Vdetm_15)"]
13071 pub const _0_X_0_F: Self = Self::new(15);
13072
13073 #[doc = "Setting prohibited"]
13074 pub const OTHERS: Self = Self::new(0);
13075 }
13076 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13077 pub struct Pvde_SPEC;
13078 pub type Pvde = crate::EnumBitfieldStruct<u8, Pvde_SPEC>;
13079 impl Pvde {
13080 #[doc = "Voltage detection m circuit disabled"]
13081 pub const _0: Self = Self::new(0);
13082
13083 #[doc = "Voltage detection m circuit enabled"]
13084 pub const _1: Self = Self::new(1);
13085 }
13086}
13087#[doc(hidden)]
13088#[derive(Copy, Clone, Eq, PartialEq)]
13089pub struct Pvdcr0_SPEC;
13090impl crate::sealed::RegSpec for Pvdcr0_SPEC {
13091 type DataType = u8;
13092}
13093
13094#[doc = "Voltage Monitor %s Circuit Control Register 0"]
13095pub type Pvdcr0 = crate::RegValueT<Pvdcr0_SPEC>;
13096
13097impl Pvdcr0 {
13098 #[doc = "Voltage Monitor m Interrupt/Reset Enable"]
13099 #[inline(always)]
13100 pub fn rie(
13101 self,
13102 ) -> crate::common::RegisterField<
13103 0,
13104 0x1,
13105 1,
13106 0,
13107 pvdcr0::Rie,
13108 pvdcr0::Rie,
13109 Pvdcr0_SPEC,
13110 crate::common::RW,
13111 > {
13112 crate::common::RegisterField::<
13113 0,
13114 0x1,
13115 1,
13116 0,
13117 pvdcr0::Rie,
13118 pvdcr0::Rie,
13119 Pvdcr0_SPEC,
13120 crate::common::RW,
13121 >::from_register(self, 0)
13122 }
13123
13124 #[doc = "Voltage monitor m Digital Filter Disabled Mode Select"]
13125 #[inline(always)]
13126 pub fn dfdis(
13127 self,
13128 ) -> crate::common::RegisterField<
13129 1,
13130 0x1,
13131 1,
13132 0,
13133 pvdcr0::Dfdis,
13134 pvdcr0::Dfdis,
13135 Pvdcr0_SPEC,
13136 crate::common::RW,
13137 > {
13138 crate::common::RegisterField::<
13139 1,
13140 0x1,
13141 1,
13142 0,
13143 pvdcr0::Dfdis,
13144 pvdcr0::Dfdis,
13145 Pvdcr0_SPEC,
13146 crate::common::RW,
13147 >::from_register(self, 0)
13148 }
13149
13150 #[doc = "Voltage Monitor m Circuit Comparison Result Output Enable"]
13151 #[inline(always)]
13152 pub fn cmpe(
13153 self,
13154 ) -> crate::common::RegisterField<
13155 2,
13156 0x1,
13157 1,
13158 0,
13159 pvdcr0::Cmpe,
13160 pvdcr0::Cmpe,
13161 Pvdcr0_SPEC,
13162 crate::common::RW,
13163 > {
13164 crate::common::RegisterField::<
13165 2,
13166 0x1,
13167 1,
13168 0,
13169 pvdcr0::Cmpe,
13170 pvdcr0::Cmpe,
13171 Pvdcr0_SPEC,
13172 crate::common::RW,
13173 >::from_register(self, 0)
13174 }
13175
13176 #[doc = "Sampling Clock Select"]
13177 #[inline(always)]
13178 pub fn fsamp(
13179 self,
13180 ) -> crate::common::RegisterField<
13181 4,
13182 0x3,
13183 1,
13184 0,
13185 pvdcr0::Fsamp,
13186 pvdcr0::Fsamp,
13187 Pvdcr0_SPEC,
13188 crate::common::RW,
13189 > {
13190 crate::common::RegisterField::<
13191 4,
13192 0x3,
13193 1,
13194 0,
13195 pvdcr0::Fsamp,
13196 pvdcr0::Fsamp,
13197 Pvdcr0_SPEC,
13198 crate::common::RW,
13199 >::from_register(self, 0)
13200 }
13201
13202 #[doc = "Voltage Monitor m Circuit Mode Select"]
13203 #[inline(always)]
13204 pub fn ri(self) -> crate::common::RegisterFieldBool<6, 1, 0, Pvdcr0_SPEC, crate::common::RW> {
13205 crate::common::RegisterFieldBool::<6, 1, 0, Pvdcr0_SPEC, crate::common::RW>::from_register(
13206 self, 0,
13207 )
13208 }
13209
13210 #[doc = "Voltage Monitor m Reset Negate Select"]
13211 #[inline(always)]
13212 pub fn rn(self) -> crate::common::RegisterFieldBool<7, 1, 0, Pvdcr0_SPEC, crate::common::RW> {
13213 crate::common::RegisterFieldBool::<7, 1, 0, Pvdcr0_SPEC, crate::common::RW>::from_register(
13214 self, 0,
13215 )
13216 }
13217}
13218impl ::core::default::Default for Pvdcr0 {
13219 #[inline(always)]
13220 fn default() -> Pvdcr0 {
13221 <crate::RegValueT<Pvdcr0_SPEC> as RegisterValue<_>>::new(130)
13222 }
13223}
13224pub mod pvdcr0 {
13225
13226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13227 pub struct Rie_SPEC;
13228 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
13229 impl Rie {
13230 #[doc = "Disable"]
13231 pub const _0: Self = Self::new(0);
13232
13233 #[doc = "Enable"]
13234 pub const _1: Self = Self::new(1);
13235 }
13236 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13237 pub struct Dfdis_SPEC;
13238 pub type Dfdis = crate::EnumBitfieldStruct<u8, Dfdis_SPEC>;
13239 impl Dfdis {
13240 #[doc = "Enable the digital filter"]
13241 pub const _0: Self = Self::new(0);
13242
13243 #[doc = "Disable the digital filter"]
13244 pub const _1: Self = Self::new(1);
13245 }
13246 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13247 pub struct Cmpe_SPEC;
13248 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
13249 impl Cmpe {
13250 #[doc = "Voltage monitor m circuit comparison result output disabled"]
13251 pub const _0: Self = Self::new(0);
13252
13253 #[doc = "Voltage monitor m circuit comparison result output enabled"]
13254 pub const _1: Self = Self::new(1);
13255 }
13256 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13257 pub struct Fsamp_SPEC;
13258 pub type Fsamp = crate::EnumBitfieldStruct<u8, Fsamp_SPEC>;
13259 impl Fsamp {
13260 #[doc = "1/2 LOCO frequency"]
13261 pub const _00: Self = Self::new(0);
13262
13263 #[doc = "1/4 LOCO frequency"]
13264 pub const _01: Self = Self::new(1);
13265
13266 #[doc = "1/8 LOCO frequency"]
13267 pub const _10: Self = Self::new(2);
13268
13269 #[doc = "1/16 LOCO frequency"]
13270 pub const _11: Self = Self::new(3);
13271 }
13272}
13273#[doc(hidden)]
13274#[derive(Copy, Clone, Eq, PartialEq)]
13275pub struct Vbattmnselr_SPEC;
13276impl crate::sealed::RegSpec for Vbattmnselr_SPEC {
13277 type DataType = u8;
13278}
13279
13280#[doc = "Battery Backup Voltage Monitor Function Select Register"]
13281pub type Vbattmnselr = crate::RegValueT<Vbattmnselr_SPEC>;
13282
13283impl Vbattmnselr {
13284 #[doc = "VBATT Voltage Monitor Function Select Bit"]
13285 #[inline(always)]
13286 pub fn vbtmnsel(
13287 self,
13288 ) -> crate::common::RegisterField<
13289 0,
13290 0x1,
13291 1,
13292 0,
13293 vbattmnselr::Vbtmnsel,
13294 vbattmnselr::Vbtmnsel,
13295 Vbattmnselr_SPEC,
13296 crate::common::RW,
13297 > {
13298 crate::common::RegisterField::<
13299 0,
13300 0x1,
13301 1,
13302 0,
13303 vbattmnselr::Vbtmnsel,
13304 vbattmnselr::Vbtmnsel,
13305 Vbattmnselr_SPEC,
13306 crate::common::RW,
13307 >::from_register(self, 0)
13308 }
13309}
13310impl ::core::default::Default for Vbattmnselr {
13311 #[inline(always)]
13312 fn default() -> Vbattmnselr {
13313 <crate::RegValueT<Vbattmnselr_SPEC> as RegisterValue<_>>::new(0)
13314 }
13315}
13316pub mod vbattmnselr {
13317
13318 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13319 pub struct Vbtmnsel_SPEC;
13320 pub type Vbtmnsel = crate::EnumBitfieldStruct<u8, Vbtmnsel_SPEC>;
13321 impl Vbtmnsel {
13322 #[doc = "Disables VBATT voltage monitor function"]
13323 pub const _0: Self = Self::new(0);
13324
13325 #[doc = "Enables VBATT voltage monitor function"]
13326 pub const _1: Self = Self::new(1);
13327 }
13328}
13329#[doc(hidden)]
13330#[derive(Copy, Clone, Eq, PartialEq)]
13331pub struct Vbtbpcr1_SPEC;
13332impl crate::sealed::RegSpec for Vbtbpcr1_SPEC {
13333 type DataType = u8;
13334}
13335
13336#[doc = "VBATT Battery Power Supply Control Register 1"]
13337pub type Vbtbpcr1 = crate::RegValueT<Vbtbpcr1_SPEC>;
13338
13339impl Vbtbpcr1 {
13340 #[doc = "Battery Power Supply Switch Stop"]
13341 #[inline(always)]
13342 pub fn bpwswstp(
13343 self,
13344 ) -> crate::common::RegisterField<
13345 0,
13346 0x1,
13347 1,
13348 0,
13349 vbtbpcr1::Bpwswstp,
13350 vbtbpcr1::Bpwswstp,
13351 Vbtbpcr1_SPEC,
13352 crate::common::RW,
13353 > {
13354 crate::common::RegisterField::<
13355 0,
13356 0x1,
13357 1,
13358 0,
13359 vbtbpcr1::Bpwswstp,
13360 vbtbpcr1::Bpwswstp,
13361 Vbtbpcr1_SPEC,
13362 crate::common::RW,
13363 >::from_register(self, 0)
13364 }
13365}
13366impl ::core::default::Default for Vbtbpcr1 {
13367 #[inline(always)]
13368 fn default() -> Vbtbpcr1 {
13369 <crate::RegValueT<Vbtbpcr1_SPEC> as RegisterValue<_>>::new(0)
13370 }
13371}
13372pub mod vbtbpcr1 {
13373
13374 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13375 pub struct Bpwswstp_SPEC;
13376 pub type Bpwswstp = crate::EnumBitfieldStruct<u8, Bpwswstp_SPEC>;
13377 impl Bpwswstp {
13378 #[doc = "Battery power supply switch enable"]
13379 pub const _0: Self = Self::new(0);
13380
13381 #[doc = "Battery power supply switch stop"]
13382 pub const _1: Self = Self::new(1);
13383 }
13384}
13385#[doc(hidden)]
13386#[derive(Copy, Clone, Eq, PartialEq)]
13387pub struct Lpscr_SPEC;
13388impl crate::sealed::RegSpec for Lpscr_SPEC {
13389 type DataType = u8;
13390}
13391
13392#[doc = "Low Power State Control Register"]
13393pub type Lpscr = crate::RegValueT<Lpscr_SPEC>;
13394
13395impl Lpscr {
13396 #[doc = "Low power mode setting bit"]
13397 #[inline(always)]
13398 pub fn lpmd(
13399 self,
13400 ) -> crate::common::RegisterField<
13401 0,
13402 0xf,
13403 1,
13404 0,
13405 lpscr::Lpmd,
13406 lpscr::Lpmd,
13407 Lpscr_SPEC,
13408 crate::common::RW,
13409 > {
13410 crate::common::RegisterField::<
13411 0,
13412 0xf,
13413 1,
13414 0,
13415 lpscr::Lpmd,
13416 lpscr::Lpmd,
13417 Lpscr_SPEC,
13418 crate::common::RW,
13419 >::from_register(self, 0)
13420 }
13421}
13422impl ::core::default::Default for Lpscr {
13423 #[inline(always)]
13424 fn default() -> Lpscr {
13425 <crate::RegValueT<Lpscr_SPEC> as RegisterValue<_>>::new(4)
13426 }
13427}
13428pub mod lpscr {
13429
13430 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13431 pub struct Lpmd_SPEC;
13432 pub type Lpmd = crate::EnumBitfieldStruct<u8, Lpmd_SPEC>;
13433 impl Lpmd {
13434 #[doc = "System Active"]
13435 pub const _0_X_0: Self = Self::new(0);
13436
13437 #[doc = "Software Standby mode"]
13438 pub const _0_X_4: Self = Self::new(4);
13439
13440 #[doc = "Deep Software Standby mode 1"]
13441 pub const _0_X_8: Self = Self::new(8);
13442
13443 #[doc = "Deep Software Standby mode 2"]
13444 pub const _0_X_9: Self = Self::new(9);
13445
13446 #[doc = "Deep Software Standby mode 3"]
13447 pub const _0_X_A: Self = Self::new(10);
13448
13449 #[doc = "Setting prohibited"]
13450 pub const OTHERS: Self = Self::new(0);
13451 }
13452}
13453#[doc(hidden)]
13454#[derive(Copy, Clone, Eq, PartialEq)]
13455pub struct Sscr1_SPEC;
13456impl crate::sealed::RegSpec for Sscr1_SPEC {
13457 type DataType = u8;
13458}
13459
13460#[doc = "Software Standby Control Register 1"]
13461pub type Sscr1 = crate::RegValueT<Sscr1_SPEC>;
13462
13463impl Sscr1 {
13464 #[doc = "Software Standby Fast Return"]
13465 #[inline(always)]
13466 pub fn ss1fr(
13467 self,
13468 ) -> crate::common::RegisterField<
13469 0,
13470 0x1,
13471 1,
13472 0,
13473 sscr1::Ss1Fr,
13474 sscr1::Ss1Fr,
13475 Sscr1_SPEC,
13476 crate::common::RW,
13477 > {
13478 crate::common::RegisterField::<
13479 0,
13480 0x1,
13481 1,
13482 0,
13483 sscr1::Ss1Fr,
13484 sscr1::Ss1Fr,
13485 Sscr1_SPEC,
13486 crate::common::RW,
13487 >::from_register(self, 0)
13488 }
13489}
13490impl ::core::default::Default for Sscr1 {
13491 #[inline(always)]
13492 fn default() -> Sscr1 {
13493 <crate::RegValueT<Sscr1_SPEC> as RegisterValue<_>>::new(0)
13494 }
13495}
13496pub mod sscr1 {
13497
13498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13499 pub struct Ss1Fr_SPEC;
13500 pub type Ss1Fr = crate::EnumBitfieldStruct<u8, Ss1Fr_SPEC>;
13501 impl Ss1Fr {
13502 #[doc = "When returning from Software Standby mode, fast return function is disabled"]
13503 pub const _0: Self = Self::new(0);
13504
13505 #[doc = "When returning from Software Standby mode, fast return function is enabled"]
13506 pub const _1: Self = Self::new(1);
13507 }
13508}
13509#[doc(hidden)]
13510#[derive(Copy, Clone, Eq, PartialEq)]
13511pub struct Lvocr_SPEC;
13512impl crate::sealed::RegSpec for Lvocr_SPEC {
13513 type DataType = u8;
13514}
13515
13516#[doc = "Low Voltage Operation Control register"]
13517pub type Lvocr = crate::RegValueT<Lvocr_SPEC>;
13518
13519impl Lvocr {
13520 #[doc = "Low Voltage Operation 0 Enable"]
13521 #[inline(always)]
13522 pub fn lvo0e(
13523 self,
13524 ) -> crate::common::RegisterField<
13525 0,
13526 0x1,
13527 1,
13528 0,
13529 lvocr::Lvo0E,
13530 lvocr::Lvo0E,
13531 Lvocr_SPEC,
13532 crate::common::RW,
13533 > {
13534 crate::common::RegisterField::<
13535 0,
13536 0x1,
13537 1,
13538 0,
13539 lvocr::Lvo0E,
13540 lvocr::Lvo0E,
13541 Lvocr_SPEC,
13542 crate::common::RW,
13543 >::from_register(self, 0)
13544 }
13545
13546 #[doc = "Low Voltage Operation 1 Enable"]
13547 #[inline(always)]
13548 pub fn lvo1e(
13549 self,
13550 ) -> crate::common::RegisterField<
13551 1,
13552 0x1,
13553 1,
13554 0,
13555 lvocr::Lvo1E,
13556 lvocr::Lvo1E,
13557 Lvocr_SPEC,
13558 crate::common::RW,
13559 > {
13560 crate::common::RegisterField::<
13561 1,
13562 0x1,
13563 1,
13564 0,
13565 lvocr::Lvo1E,
13566 lvocr::Lvo1E,
13567 Lvocr_SPEC,
13568 crate::common::RW,
13569 >::from_register(self, 0)
13570 }
13571}
13572impl ::core::default::Default for Lvocr {
13573 #[inline(always)]
13574 fn default() -> Lvocr {
13575 <crate::RegValueT<Lvocr_SPEC> as RegisterValue<_>>::new(3)
13576 }
13577}
13578pub mod lvocr {
13579
13580 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13581 pub struct Lvo0E_SPEC;
13582 pub type Lvo0E = crate::EnumBitfieldStruct<u8, Lvo0E_SPEC>;
13583 impl Lvo0E {
13584 #[doc = "Disable"]
13585 pub const _0: Self = Self::new(0);
13586
13587 #[doc = "Enable"]
13588 pub const _1: Self = Self::new(1);
13589 }
13590 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13591 pub struct Lvo1E_SPEC;
13592 pub type Lvo1E = crate::EnumBitfieldStruct<u8, Lvo1E_SPEC>;
13593 impl Lvo1E {
13594 #[doc = "Disable"]
13595 pub const _0: Self = Self::new(0);
13596
13597 #[doc = "Enable"]
13598 pub const _1: Self = Self::new(1);
13599 }
13600}
13601#[doc(hidden)]
13602#[derive(Copy, Clone, Eq, PartialEq)]
13603pub struct Pll1Ldocr_SPEC;
13604impl crate::sealed::RegSpec for Pll1Ldocr_SPEC {
13605 type DataType = u8;
13606}
13607
13608#[doc = "PLL1-LDO Control Register"]
13609pub type Pll1Ldocr = crate::RegValueT<Pll1Ldocr_SPEC>;
13610
13611impl Pll1Ldocr {
13612 #[doc = "LDO Stop"]
13613 #[inline(always)]
13614 pub fn ldostp(
13615 self,
13616 ) -> crate::common::RegisterField<
13617 0,
13618 0x1,
13619 1,
13620 0,
13621 pll1ldocr::Ldostp,
13622 pll1ldocr::Ldostp,
13623 Pll1Ldocr_SPEC,
13624 crate::common::RW,
13625 > {
13626 crate::common::RegisterField::<
13627 0,
13628 0x1,
13629 1,
13630 0,
13631 pll1ldocr::Ldostp,
13632 pll1ldocr::Ldostp,
13633 Pll1Ldocr_SPEC,
13634 crate::common::RW,
13635 >::from_register(self, 0)
13636 }
13637
13638 #[doc = "STBY Keep"]
13639 #[inline(always)]
13640 pub fn skeep(
13641 self,
13642 ) -> crate::common::RegisterField<
13643 1,
13644 0x1,
13645 1,
13646 0,
13647 pll1ldocr::Skeep,
13648 pll1ldocr::Skeep,
13649 Pll1Ldocr_SPEC,
13650 crate::common::RW,
13651 > {
13652 crate::common::RegisterField::<
13653 1,
13654 0x1,
13655 1,
13656 0,
13657 pll1ldocr::Skeep,
13658 pll1ldocr::Skeep,
13659 Pll1Ldocr_SPEC,
13660 crate::common::RW,
13661 >::from_register(self, 0)
13662 }
13663}
13664impl ::core::default::Default for Pll1Ldocr {
13665 #[inline(always)]
13666 fn default() -> Pll1Ldocr {
13667 <crate::RegValueT<Pll1Ldocr_SPEC> as RegisterValue<_>>::new(0)
13668 }
13669}
13670pub mod pll1ldocr {
13671
13672 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13673 pub struct Ldostp_SPEC;
13674 pub type Ldostp = crate::EnumBitfieldStruct<u8, Ldostp_SPEC>;
13675 impl Ldostp {
13676 #[doc = "PLL1-LDO is enabled"]
13677 pub const _0: Self = Self::new(0);
13678
13679 #[doc = "PLL1-LDO is stopped"]
13680 pub const _1: Self = Self::new(1);
13681 }
13682 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13683 pub struct Skeep_SPEC;
13684 pub type Skeep = crate::EnumBitfieldStruct<u8, Skeep_SPEC>;
13685 impl Skeep {
13686 #[doc = "PLL1-LDO is stopped during Software Standby mode."]
13687 pub const _0: Self = Self::new(0);
13688
13689 #[doc = "PLL1-LDO state before Software Standby mode is retained during Software Standby mode."]
13690 pub const _1: Self = Self::new(1);
13691 }
13692}
13693#[doc(hidden)]
13694#[derive(Copy, Clone, Eq, PartialEq)]
13695pub struct Pll2Ldocr_SPEC;
13696impl crate::sealed::RegSpec for Pll2Ldocr_SPEC {
13697 type DataType = u8;
13698}
13699
13700#[doc = "PLL2-LDO Control Register"]
13701pub type Pll2Ldocr = crate::RegValueT<Pll2Ldocr_SPEC>;
13702
13703impl Pll2Ldocr {
13704 #[doc = "LDO Stop"]
13705 #[inline(always)]
13706 pub fn ldostp(
13707 self,
13708 ) -> crate::common::RegisterField<
13709 0,
13710 0x1,
13711 1,
13712 0,
13713 pll2ldocr::Ldostp,
13714 pll2ldocr::Ldostp,
13715 Pll2Ldocr_SPEC,
13716 crate::common::RW,
13717 > {
13718 crate::common::RegisterField::<
13719 0,
13720 0x1,
13721 1,
13722 0,
13723 pll2ldocr::Ldostp,
13724 pll2ldocr::Ldostp,
13725 Pll2Ldocr_SPEC,
13726 crate::common::RW,
13727 >::from_register(self, 0)
13728 }
13729
13730 #[doc = "STBY Keep"]
13731 #[inline(always)]
13732 pub fn skeep(
13733 self,
13734 ) -> crate::common::RegisterField<
13735 1,
13736 0x1,
13737 1,
13738 0,
13739 pll2ldocr::Skeep,
13740 pll2ldocr::Skeep,
13741 Pll2Ldocr_SPEC,
13742 crate::common::RW,
13743 > {
13744 crate::common::RegisterField::<
13745 1,
13746 0x1,
13747 1,
13748 0,
13749 pll2ldocr::Skeep,
13750 pll2ldocr::Skeep,
13751 Pll2Ldocr_SPEC,
13752 crate::common::RW,
13753 >::from_register(self, 0)
13754 }
13755}
13756impl ::core::default::Default for Pll2Ldocr {
13757 #[inline(always)]
13758 fn default() -> Pll2Ldocr {
13759 <crate::RegValueT<Pll2Ldocr_SPEC> as RegisterValue<_>>::new(0)
13760 }
13761}
13762pub mod pll2ldocr {
13763
13764 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13765 pub struct Ldostp_SPEC;
13766 pub type Ldostp = crate::EnumBitfieldStruct<u8, Ldostp_SPEC>;
13767 impl Ldostp {
13768 #[doc = "PLL2-LDO is enabled"]
13769 pub const _0: Self = Self::new(0);
13770
13771 #[doc = "PLL2-LDO is stopped"]
13772 pub const _1: Self = Self::new(1);
13773 }
13774 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13775 pub struct Skeep_SPEC;
13776 pub type Skeep = crate::EnumBitfieldStruct<u8, Skeep_SPEC>;
13777 impl Skeep {
13778 #[doc = "PLL2-LDO is stopped during Software Standby mode."]
13779 pub const _0: Self = Self::new(0);
13780
13781 #[doc = "PLL2-LDO state before Software Standby mode is retained during Software Standby mode."]
13782 pub const _1: Self = Self::new(1);
13783 }
13784}
13785#[doc(hidden)]
13786#[derive(Copy, Clone, Eq, PartialEq)]
13787pub struct Hocoldocr_SPEC;
13788impl crate::sealed::RegSpec for Hocoldocr_SPEC {
13789 type DataType = u8;
13790}
13791
13792#[doc = "HOCO-LDO Control Register"]
13793pub type Hocoldocr = crate::RegValueT<Hocoldocr_SPEC>;
13794
13795impl Hocoldocr {
13796 #[doc = "LDO Stop"]
13797 #[inline(always)]
13798 pub fn ldostp(
13799 self,
13800 ) -> crate::common::RegisterField<
13801 0,
13802 0x1,
13803 1,
13804 0,
13805 hocoldocr::Ldostp,
13806 hocoldocr::Ldostp,
13807 Hocoldocr_SPEC,
13808 crate::common::RW,
13809 > {
13810 crate::common::RegisterField::<
13811 0,
13812 0x1,
13813 1,
13814 0,
13815 hocoldocr::Ldostp,
13816 hocoldocr::Ldostp,
13817 Hocoldocr_SPEC,
13818 crate::common::RW,
13819 >::from_register(self, 0)
13820 }
13821
13822 #[doc = "STBY Keep"]
13823 #[inline(always)]
13824 pub fn skeep(
13825 self,
13826 ) -> crate::common::RegisterField<
13827 1,
13828 0x1,
13829 1,
13830 0,
13831 hocoldocr::Skeep,
13832 hocoldocr::Skeep,
13833 Hocoldocr_SPEC,
13834 crate::common::RW,
13835 > {
13836 crate::common::RegisterField::<
13837 1,
13838 0x1,
13839 1,
13840 0,
13841 hocoldocr::Skeep,
13842 hocoldocr::Skeep,
13843 Hocoldocr_SPEC,
13844 crate::common::RW,
13845 >::from_register(self, 0)
13846 }
13847}
13848impl ::core::default::Default for Hocoldocr {
13849 #[inline(always)]
13850 fn default() -> Hocoldocr {
13851 <crate::RegValueT<Hocoldocr_SPEC> as RegisterValue<_>>::new(0)
13852 }
13853}
13854pub mod hocoldocr {
13855
13856 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13857 pub struct Ldostp_SPEC;
13858 pub type Ldostp = crate::EnumBitfieldStruct<u8, Ldostp_SPEC>;
13859 impl Ldostp {
13860 #[doc = "HOCO-LDO is enabled"]
13861 pub const _0: Self = Self::new(0);
13862
13863 #[doc = "HOCO-LDO is stopped"]
13864 pub const _1: Self = Self::new(1);
13865 }
13866 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13867 pub struct Skeep_SPEC;
13868 pub type Skeep = crate::EnumBitfieldStruct<u8, Skeep_SPEC>;
13869 impl Skeep {
13870 #[doc = "HOCO-LDO is stopped during Software Standby mode."]
13871 pub const _0: Self = Self::new(0);
13872
13873 #[doc = "HOCO-LDO state before Software Standby mode is retained during Software Standby mode."]
13874 pub const _1: Self = Self::new(1);
13875 }
13876}
13877#[doc(hidden)]
13878#[derive(Copy, Clone, Eq, PartialEq)]
13879pub struct Pvdfcr_SPEC;
13880impl crate::sealed::RegSpec for Pvdfcr_SPEC {
13881 type DataType = u8;
13882}
13883
13884#[doc = "Voltage Monitor %s Function Control Register"]
13885pub type Pvdfcr = crate::RegValueT<Pvdfcr_SPEC>;
13886
13887impl Pvdfcr {
13888 #[doc = "Rise Hysteresis Select"]
13889 #[inline(always)]
13890 pub fn rhsel(
13891 self,
13892 ) -> crate::common::RegisterField<
13893 0,
13894 0x1,
13895 1,
13896 0,
13897 pvdfcr::Rhsel,
13898 pvdfcr::Rhsel,
13899 Pvdfcr_SPEC,
13900 crate::common::RW,
13901 > {
13902 crate::common::RegisterField::<
13903 0,
13904 0x1,
13905 1,
13906 0,
13907 pvdfcr::Rhsel,
13908 pvdfcr::Rhsel,
13909 Pvdfcr_SPEC,
13910 crate::common::RW,
13911 >::from_register(self, 0)
13912 }
13913}
13914impl ::core::default::Default for Pvdfcr {
13915 #[inline(always)]
13916 fn default() -> Pvdfcr {
13917 <crate::RegValueT<Pvdfcr_SPEC> as RegisterValue<_>>::new(0)
13918 }
13919}
13920pub mod pvdfcr {
13921
13922 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13923 pub struct Rhsel_SPEC;
13924 pub type Rhsel = crate::EnumBitfieldStruct<u8, Rhsel_SPEC>;
13925 impl Rhsel {
13926 #[doc = "Hysteresis level for VCC-fall detection is selected."]
13927 pub const _0: Self = Self::new(0);
13928
13929 #[doc = "Hysteresis level for VCC-rise detection is selected."]
13930 pub const _1: Self = Self::new(1);
13931 }
13932}
13933#[doc(hidden)]
13934#[derive(Copy, Clone, Eq, PartialEq)]
13935pub struct Sosccr_SPEC;
13936impl crate::sealed::RegSpec for Sosccr_SPEC {
13937 type DataType = u8;
13938}
13939
13940#[doc = "Sub-Clock Oscillator Control Register"]
13941pub type Sosccr = crate::RegValueT<Sosccr_SPEC>;
13942
13943impl Sosccr {
13944 #[doc = "Sub-Clock Oscillator Stop"]
13945 #[inline(always)]
13946 pub fn sostp(
13947 self,
13948 ) -> crate::common::RegisterField<
13949 0,
13950 0x1,
13951 1,
13952 0,
13953 sosccr::Sostp,
13954 sosccr::Sostp,
13955 Sosccr_SPEC,
13956 crate::common::RW,
13957 > {
13958 crate::common::RegisterField::<
13959 0,
13960 0x1,
13961 1,
13962 0,
13963 sosccr::Sostp,
13964 sosccr::Sostp,
13965 Sosccr_SPEC,
13966 crate::common::RW,
13967 >::from_register(self, 0)
13968 }
13969}
13970impl ::core::default::Default for Sosccr {
13971 #[inline(always)]
13972 fn default() -> Sosccr {
13973 <crate::RegValueT<Sosccr_SPEC> as RegisterValue<_>>::new(1)
13974 }
13975}
13976pub mod sosccr {
13977
13978 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13979 pub struct Sostp_SPEC;
13980 pub type Sostp = crate::EnumBitfieldStruct<u8, Sostp_SPEC>;
13981 impl Sostp {
13982 #[doc = "Operate the sub-clock oscillator"]
13983 pub const _0: Self = Self::new(0);
13984
13985 #[doc = "Stop the sub-clock oscillator"]
13986 pub const _1: Self = Self::new(1);
13987 }
13988}
13989#[doc(hidden)]
13990#[derive(Copy, Clone, Eq, PartialEq)]
13991pub struct Somcr_SPEC;
13992impl crate::sealed::RegSpec for Somcr_SPEC {
13993 type DataType = u8;
13994}
13995
13996#[doc = "Sub-Clock Oscillator Mode Control Register"]
13997pub type Somcr = crate::RegValueT<Somcr_SPEC>;
13998
13999impl Somcr {
14000 #[doc = "Sub-Clock Oscillator Drive Capability Switching"]
14001 #[inline(always)]
14002 pub fn sodrv(
14003 self,
14004 ) -> crate::common::RegisterField<
14005 0,
14006 0x3,
14007 1,
14008 0,
14009 somcr::Sodrv,
14010 somcr::Sodrv,
14011 Somcr_SPEC,
14012 crate::common::RW,
14013 > {
14014 crate::common::RegisterField::<
14015 0,
14016 0x3,
14017 1,
14018 0,
14019 somcr::Sodrv,
14020 somcr::Sodrv,
14021 Somcr_SPEC,
14022 crate::common::RW,
14023 >::from_register(self, 0)
14024 }
14025
14026 #[doc = "Sub-Clock Oscillator Switching"]
14027 #[inline(always)]
14028 pub fn sosel(
14029 self,
14030 ) -> crate::common::RegisterField<
14031 6,
14032 0x1,
14033 1,
14034 0,
14035 somcr::Sosel,
14036 somcr::Sosel,
14037 Somcr_SPEC,
14038 crate::common::RW,
14039 > {
14040 crate::common::RegisterField::<
14041 6,
14042 0x1,
14043 1,
14044 0,
14045 somcr::Sosel,
14046 somcr::Sosel,
14047 Somcr_SPEC,
14048 crate::common::RW,
14049 >::from_register(self, 0)
14050 }
14051}
14052impl ::core::default::Default for Somcr {
14053 #[inline(always)]
14054 fn default() -> Somcr {
14055 <crate::RegValueT<Somcr_SPEC> as RegisterValue<_>>::new(0)
14056 }
14057}
14058pub mod somcr {
14059
14060 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14061 pub struct Sodrv_SPEC;
14062 pub type Sodrv = crate::EnumBitfieldStruct<u8, Sodrv_SPEC>;
14063 impl Sodrv {
14064 #[doc = "Standard (12.5pf)"]
14065 pub const _00: Self = Self::new(0);
14066
14067 #[doc = "Lowpower mode 1 (9pf)"]
14068 pub const _01: Self = Self::new(1);
14069
14070 #[doc = "Lowpower mode 2 (7pf)"]
14071 pub const _10: Self = Self::new(2);
14072
14073 #[doc = "Lowpower mode 3 (4pf)"]
14074 pub const _11: Self = Self::new(3);
14075 }
14076 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14077 pub struct Sosel_SPEC;
14078 pub type Sosel = crate::EnumBitfieldStruct<u8, Sosel_SPEC>;
14079 impl Sosel {
14080 #[doc = "Resonator"]
14081 pub const _0: Self = Self::new(0);
14082
14083 #[doc = "External clock input"]
14084 pub const _1: Self = Self::new(1);
14085 }
14086}
14087#[doc(hidden)]
14088#[derive(Copy, Clone, Eq, PartialEq)]
14089pub struct Vbtber_SPEC;
14090impl crate::sealed::RegSpec for Vbtber_SPEC {
14091 type DataType = u8;
14092}
14093
14094#[doc = "VBATT Backup Enable Register"]
14095pub type Vbtber = crate::RegValueT<Vbtber_SPEC>;
14096
14097impl Vbtber {
14098 #[doc = "VBATT backup register access enable bit"]
14099 #[inline(always)]
14100 pub fn vbae(
14101 self,
14102 ) -> crate::common::RegisterField<
14103 3,
14104 0x1,
14105 1,
14106 0,
14107 vbtber::Vbae,
14108 vbtber::Vbae,
14109 Vbtber_SPEC,
14110 crate::common::RW,
14111 > {
14112 crate::common::RegisterField::<
14113 3,
14114 0x1,
14115 1,
14116 0,
14117 vbtber::Vbae,
14118 vbtber::Vbae,
14119 Vbtber_SPEC,
14120 crate::common::RW,
14121 >::from_register(self, 0)
14122 }
14123}
14124impl ::core::default::Default for Vbtber {
14125 #[inline(always)]
14126 fn default() -> Vbtber {
14127 <crate::RegValueT<Vbtber_SPEC> as RegisterValue<_>>::new(8)
14128 }
14129}
14130pub mod vbtber {
14131
14132 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14133 pub struct Vbae_SPEC;
14134 pub type Vbae = crate::EnumBitfieldStruct<u8, Vbae_SPEC>;
14135 impl Vbae {
14136 #[doc = "Disable to access VBTBKR\\[n\\]"]
14137 pub const _0: Self = Self::new(0);
14138
14139 #[doc = "Enable to access VBTBKR\\[n\\]"]
14140 pub const _1: Self = Self::new(1);
14141 }
14142}
14143#[doc(hidden)]
14144#[derive(Copy, Clone, Eq, PartialEq)]
14145pub struct Vbtbpcr2_SPEC;
14146impl crate::sealed::RegSpec for Vbtbpcr2_SPEC {
14147 type DataType = u8;
14148}
14149
14150#[doc = "VBATT Battery Power Supply Control Register 2"]
14151pub type Vbtbpcr2 = crate::RegValueT<Vbtbpcr2_SPEC>;
14152
14153impl Vbtbpcr2 {
14154 #[doc = "VDETBAT Level Select"]
14155 #[inline(always)]
14156 pub fn vdetlvl(
14157 self,
14158 ) -> crate::common::RegisterField<
14159 0,
14160 0x7,
14161 1,
14162 0,
14163 vbtbpcr2::Vdetlvl,
14164 vbtbpcr2::Vdetlvl,
14165 Vbtbpcr2_SPEC,
14166 crate::common::RW,
14167 > {
14168 crate::common::RegisterField::<
14169 0,
14170 0x7,
14171 1,
14172 0,
14173 vbtbpcr2::Vdetlvl,
14174 vbtbpcr2::Vdetlvl,
14175 Vbtbpcr2_SPEC,
14176 crate::common::RW,
14177 >::from_register(self, 0)
14178 }
14179
14180 #[doc = "Voltage drop detection enable"]
14181 #[inline(always)]
14182 pub fn vdete(
14183 self,
14184 ) -> crate::common::RegisterField<
14185 4,
14186 0x1,
14187 1,
14188 0,
14189 vbtbpcr2::Vdete,
14190 vbtbpcr2::Vdete,
14191 Vbtbpcr2_SPEC,
14192 crate::common::RW,
14193 > {
14194 crate::common::RegisterField::<
14195 4,
14196 0x1,
14197 1,
14198 0,
14199 vbtbpcr2::Vdete,
14200 vbtbpcr2::Vdete,
14201 Vbtbpcr2_SPEC,
14202 crate::common::RW,
14203 >::from_register(self, 0)
14204 }
14205}
14206impl ::core::default::Default for Vbtbpcr2 {
14207 #[inline(always)]
14208 fn default() -> Vbtbpcr2 {
14209 <crate::RegValueT<Vbtbpcr2_SPEC> as RegisterValue<_>>::new(6)
14210 }
14211}
14212pub mod vbtbpcr2 {
14213
14214 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14215 pub struct Vdetlvl_SPEC;
14216 pub type Vdetlvl = crate::EnumBitfieldStruct<u8, Vdetlvl_SPEC>;
14217 impl Vdetlvl {
14218 #[doc = "2.80 V"]
14219 pub const _000: Self = Self::new(0);
14220
14221 #[doc = "2.53 V"]
14222 pub const _001: Self = Self::new(1);
14223
14224 #[doc = "2.10 V"]
14225 pub const _010: Self = Self::new(2);
14226
14227 #[doc = "1.95 V"]
14228 pub const _011: Self = Self::new(3);
14229
14230 #[doc = "1.85 V"]
14231 pub const _100: Self = Self::new(4);
14232
14233 #[doc = "1.75 V"]
14234 pub const _101: Self = Self::new(5);
14235
14236 #[doc = "setting prohibited"]
14237 pub const _110: Self = Self::new(6);
14238
14239 #[doc = "setting prohibited"]
14240 pub const _111: Self = Self::new(7);
14241 }
14242 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14243 pub struct Vdete_SPEC;
14244 pub type Vdete = crate::EnumBitfieldStruct<u8, Vdete_SPEC>;
14245 impl Vdete {
14246 #[doc = "VCC Voltage drop detection disable"]
14247 pub const _0: Self = Self::new(0);
14248
14249 #[doc = "VCC Voltage drop detection enable"]
14250 pub const _1: Self = Self::new(1);
14251 }
14252}
14253#[doc(hidden)]
14254#[derive(Copy, Clone, Eq, PartialEq)]
14255pub struct Vbtbpsr_SPEC;
14256impl crate::sealed::RegSpec for Vbtbpsr_SPEC {
14257 type DataType = u8;
14258}
14259
14260#[doc = "VBATT Battery Power Supply Status Register"]
14261pub type Vbtbpsr = crate::RegValueT<Vbtbpsr_SPEC>;
14262
14263impl Vbtbpsr {
14264 #[doc = "VBATT_POR Flag"]
14265 #[inline(always)]
14266 pub fn vbporf(
14267 self,
14268 ) -> crate::common::RegisterField<
14269 0,
14270 0x1,
14271 1,
14272 0,
14273 vbtbpsr::Vbporf,
14274 vbtbpsr::Vbporf,
14275 Vbtbpsr_SPEC,
14276 crate::common::RW,
14277 > {
14278 crate::common::RegisterField::<
14279 0,
14280 0x1,
14281 1,
14282 0,
14283 vbtbpsr::Vbporf,
14284 vbtbpsr::Vbporf,
14285 Vbtbpsr_SPEC,
14286 crate::common::RW,
14287 >::from_register(self, 0)
14288 }
14289
14290 #[doc = "VBATT_POR Monitor"]
14291 #[inline(always)]
14292 pub fn vbporm(
14293 self,
14294 ) -> crate::common::RegisterField<
14295 4,
14296 0x1,
14297 1,
14298 0,
14299 vbtbpsr::Vbporm,
14300 vbtbpsr::Vbporm,
14301 Vbtbpsr_SPEC,
14302 crate::common::R,
14303 > {
14304 crate::common::RegisterField::<
14305 4,
14306 0x1,
14307 1,
14308 0,
14309 vbtbpsr::Vbporm,
14310 vbtbpsr::Vbporm,
14311 Vbtbpsr_SPEC,
14312 crate::common::R,
14313 >::from_register(self, 0)
14314 }
14315
14316 #[doc = "Battery Power Supply Switch Status Monitor"]
14317 #[inline(always)]
14318 pub fn bpwswm(
14319 self,
14320 ) -> crate::common::RegisterField<
14321 5,
14322 0x1,
14323 1,
14324 0,
14325 vbtbpsr::Bpwswm,
14326 vbtbpsr::Bpwswm,
14327 Vbtbpsr_SPEC,
14328 crate::common::R,
14329 > {
14330 crate::common::RegisterField::<
14331 5,
14332 0x1,
14333 1,
14334 0,
14335 vbtbpsr::Bpwswm,
14336 vbtbpsr::Bpwswm,
14337 Vbtbpsr_SPEC,
14338 crate::common::R,
14339 >::from_register(self, 0)
14340 }
14341}
14342impl ::core::default::Default for Vbtbpsr {
14343 #[inline(always)]
14344 fn default() -> Vbtbpsr {
14345 <crate::RegValueT<Vbtbpsr_SPEC> as RegisterValue<_>>::new(0)
14346 }
14347}
14348pub mod vbtbpsr {
14349
14350 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14351 pub struct Vbporf_SPEC;
14352 pub type Vbporf = crate::EnumBitfieldStruct<u8, Vbporf_SPEC>;
14353 impl Vbporf {
14354 #[doc = "VBATT_R voltage drop is not detected"]
14355 pub const _0: Self = Self::new(0);
14356
14357 #[doc = "VBATT_R voltage drop is detected"]
14358 pub const _1: Self = Self::new(1);
14359 }
14360 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14361 pub struct Vbporm_SPEC;
14362 pub type Vbporm = crate::EnumBitfieldStruct<u8, Vbporm_SPEC>;
14363 impl Vbporm {
14364 #[doc = "VBATT_R voltage < VPDR (BATR)"]
14365 pub const _0: Self = Self::new(0);
14366
14367 #[doc = "VBATT_R voltage > VPDR (BATR)"]
14368 pub const _1: Self = Self::new(1);
14369 }
14370 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14371 pub struct Bpwswm_SPEC;
14372 pub type Bpwswm = crate::EnumBitfieldStruct<u8, Bpwswm_SPEC>;
14373 impl Bpwswm {
14374 #[doc = "VCC voltage < VDETBATT_m"]
14375 pub const _0: Self = Self::new(0);
14376
14377 #[doc = "VCC voltage > VDETBATT_m"]
14378 pub const _1: Self = Self::new(1);
14379 }
14380}
14381#[doc(hidden)]
14382#[derive(Copy, Clone, Eq, PartialEq)]
14383pub struct Vbtadsr_SPEC;
14384impl crate::sealed::RegSpec for Vbtadsr_SPEC {
14385 type DataType = u8;
14386}
14387
14388#[doc = "VBATT Tamper detection Status Register"]
14389pub type Vbtadsr = crate::RegValueT<Vbtadsr_SPEC>;
14390
14391impl Vbtadsr {
14392 #[doc = "VBATT Tamper Detection flag 0"]
14393 #[inline(always)]
14394 pub fn vbtadf0(
14395 self,
14396 ) -> crate::common::RegisterField<
14397 0,
14398 0x1,
14399 1,
14400 0,
14401 vbtadsr::Vbtadf0,
14402 vbtadsr::Vbtadf0,
14403 Vbtadsr_SPEC,
14404 crate::common::RW,
14405 > {
14406 crate::common::RegisterField::<
14407 0,
14408 0x1,
14409 1,
14410 0,
14411 vbtadsr::Vbtadf0,
14412 vbtadsr::Vbtadf0,
14413 Vbtadsr_SPEC,
14414 crate::common::RW,
14415 >::from_register(self, 0)
14416 }
14417
14418 #[doc = "VBATT Tamper Detection flag 1"]
14419 #[inline(always)]
14420 pub fn vbtadf1(
14421 self,
14422 ) -> crate::common::RegisterField<
14423 1,
14424 0x1,
14425 1,
14426 0,
14427 vbtadsr::Vbtadf1,
14428 vbtadsr::Vbtadf1,
14429 Vbtadsr_SPEC,
14430 crate::common::RW,
14431 > {
14432 crate::common::RegisterField::<
14433 1,
14434 0x1,
14435 1,
14436 0,
14437 vbtadsr::Vbtadf1,
14438 vbtadsr::Vbtadf1,
14439 Vbtadsr_SPEC,
14440 crate::common::RW,
14441 >::from_register(self, 0)
14442 }
14443
14444 #[doc = "VBATT Tamper Detection flag 2"]
14445 #[inline(always)]
14446 pub fn vbtadf2(
14447 self,
14448 ) -> crate::common::RegisterField<
14449 2,
14450 0x1,
14451 1,
14452 0,
14453 vbtadsr::Vbtadf2,
14454 vbtadsr::Vbtadf2,
14455 Vbtadsr_SPEC,
14456 crate::common::RW,
14457 > {
14458 crate::common::RegisterField::<
14459 2,
14460 0x1,
14461 1,
14462 0,
14463 vbtadsr::Vbtadf2,
14464 vbtadsr::Vbtadf2,
14465 Vbtadsr_SPEC,
14466 crate::common::RW,
14467 >::from_register(self, 0)
14468 }
14469}
14470impl ::core::default::Default for Vbtadsr {
14471 #[inline(always)]
14472 fn default() -> Vbtadsr {
14473 <crate::RegValueT<Vbtadsr_SPEC> as RegisterValue<_>>::new(0)
14474 }
14475}
14476pub mod vbtadsr {
14477
14478 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14479 pub struct Vbtadf0_SPEC;
14480 pub type Vbtadf0 = crate::EnumBitfieldStruct<u8, Vbtadf0_SPEC>;
14481 impl Vbtadf0 {
14482 #[doc = "RTCIC0 input edge is not detected"]
14483 pub const _0: Self = Self::new(0);
14484
14485 #[doc = "RTCIC0 input edge is detected"]
14486 pub const _1: Self = Self::new(1);
14487 }
14488 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14489 pub struct Vbtadf1_SPEC;
14490 pub type Vbtadf1 = crate::EnumBitfieldStruct<u8, Vbtadf1_SPEC>;
14491 impl Vbtadf1 {
14492 #[doc = "RTCIC1 input edge is not detected"]
14493 pub const _0: Self = Self::new(0);
14494
14495 #[doc = "RTCIC1 input edge is detected"]
14496 pub const _1: Self = Self::new(1);
14497 }
14498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14499 pub struct Vbtadf2_SPEC;
14500 pub type Vbtadf2 = crate::EnumBitfieldStruct<u8, Vbtadf2_SPEC>;
14501 impl Vbtadf2 {
14502 #[doc = "RTCIC2 input edge is not detected"]
14503 pub const _0: Self = Self::new(0);
14504
14505 #[doc = "RTCIC2 input edge is detected"]
14506 pub const _1: Self = Self::new(1);
14507 }
14508}
14509#[doc(hidden)]
14510#[derive(Copy, Clone, Eq, PartialEq)]
14511pub struct Vbtadcr1_SPEC;
14512impl crate::sealed::RegSpec for Vbtadcr1_SPEC {
14513 type DataType = u8;
14514}
14515
14516#[doc = "VBATT Tamper detection Control Register 1"]
14517pub type Vbtadcr1 = crate::RegValueT<Vbtadcr1_SPEC>;
14518
14519impl Vbtadcr1 {
14520 #[doc = "VBATT Tamper Detection Interrupt Enable 0"]
14521 #[inline(always)]
14522 pub fn vbtadie0(
14523 self,
14524 ) -> crate::common::RegisterField<
14525 0,
14526 0x1,
14527 1,
14528 0,
14529 vbtadcr1::Vbtadie0,
14530 vbtadcr1::Vbtadie0,
14531 Vbtadcr1_SPEC,
14532 crate::common::RW,
14533 > {
14534 crate::common::RegisterField::<
14535 0,
14536 0x1,
14537 1,
14538 0,
14539 vbtadcr1::Vbtadie0,
14540 vbtadcr1::Vbtadie0,
14541 Vbtadcr1_SPEC,
14542 crate::common::RW,
14543 >::from_register(self, 0)
14544 }
14545
14546 #[doc = "VBATT Tamper Detection Interrupt Enable 1"]
14547 #[inline(always)]
14548 pub fn vbtadie1(
14549 self,
14550 ) -> crate::common::RegisterField<
14551 1,
14552 0x1,
14553 1,
14554 0,
14555 vbtadcr1::Vbtadie1,
14556 vbtadcr1::Vbtadie1,
14557 Vbtadcr1_SPEC,
14558 crate::common::RW,
14559 > {
14560 crate::common::RegisterField::<
14561 1,
14562 0x1,
14563 1,
14564 0,
14565 vbtadcr1::Vbtadie1,
14566 vbtadcr1::Vbtadie1,
14567 Vbtadcr1_SPEC,
14568 crate::common::RW,
14569 >::from_register(self, 0)
14570 }
14571
14572 #[doc = "VBATT Tamper Detection Interrupt Enable 2"]
14573 #[inline(always)]
14574 pub fn vbtadie2(
14575 self,
14576 ) -> crate::common::RegisterField<
14577 2,
14578 0x1,
14579 1,
14580 0,
14581 vbtadcr1::Vbtadie2,
14582 vbtadcr1::Vbtadie2,
14583 Vbtadcr1_SPEC,
14584 crate::common::RW,
14585 > {
14586 crate::common::RegisterField::<
14587 2,
14588 0x1,
14589 1,
14590 0,
14591 vbtadcr1::Vbtadie2,
14592 vbtadcr1::Vbtadie2,
14593 Vbtadcr1_SPEC,
14594 crate::common::RW,
14595 >::from_register(self, 0)
14596 }
14597
14598 #[doc = "VBATT Tamper Detection Backup Register Clear Enable 0"]
14599 #[inline(always)]
14600 pub fn vbtadce0(
14601 self,
14602 ) -> crate::common::RegisterField<
14603 4,
14604 0x1,
14605 1,
14606 0,
14607 vbtadcr1::Vbtadce0,
14608 vbtadcr1::Vbtadce0,
14609 Vbtadcr1_SPEC,
14610 crate::common::RW,
14611 > {
14612 crate::common::RegisterField::<
14613 4,
14614 0x1,
14615 1,
14616 0,
14617 vbtadcr1::Vbtadce0,
14618 vbtadcr1::Vbtadce0,
14619 Vbtadcr1_SPEC,
14620 crate::common::RW,
14621 >::from_register(self, 0)
14622 }
14623
14624 #[doc = "VBATT Tamper Detection Backup Register Clear Enable 1"]
14625 #[inline(always)]
14626 pub fn vbtadce1(
14627 self,
14628 ) -> crate::common::RegisterField<
14629 5,
14630 0x1,
14631 1,
14632 0,
14633 vbtadcr1::Vbtadce1,
14634 vbtadcr1::Vbtadce1,
14635 Vbtadcr1_SPEC,
14636 crate::common::RW,
14637 > {
14638 crate::common::RegisterField::<
14639 5,
14640 0x1,
14641 1,
14642 0,
14643 vbtadcr1::Vbtadce1,
14644 vbtadcr1::Vbtadce1,
14645 Vbtadcr1_SPEC,
14646 crate::common::RW,
14647 >::from_register(self, 0)
14648 }
14649
14650 #[doc = "VBATT Tamper Detection Backup Register Clear Enable 2"]
14651 #[inline(always)]
14652 pub fn vbtadce2(
14653 self,
14654 ) -> crate::common::RegisterField<
14655 6,
14656 0x1,
14657 1,
14658 0,
14659 vbtadcr1::Vbtadce2,
14660 vbtadcr1::Vbtadce2,
14661 Vbtadcr1_SPEC,
14662 crate::common::RW,
14663 > {
14664 crate::common::RegisterField::<
14665 6,
14666 0x1,
14667 1,
14668 0,
14669 vbtadcr1::Vbtadce2,
14670 vbtadcr1::Vbtadce2,
14671 Vbtadcr1_SPEC,
14672 crate::common::RW,
14673 >::from_register(self, 0)
14674 }
14675}
14676impl ::core::default::Default for Vbtadcr1 {
14677 #[inline(always)]
14678 fn default() -> Vbtadcr1 {
14679 <crate::RegValueT<Vbtadcr1_SPEC> as RegisterValue<_>>::new(0)
14680 }
14681}
14682pub mod vbtadcr1 {
14683
14684 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14685 pub struct Vbtadie0_SPEC;
14686 pub type Vbtadie0 = crate::EnumBitfieldStruct<u8, Vbtadie0_SPEC>;
14687 impl Vbtadie0 {
14688 #[doc = "Interrupt by VBTADF0 flag is disable"]
14689 pub const _0: Self = Self::new(0);
14690
14691 #[doc = "Interrupt by VBTADF0 flag is enable"]
14692 pub const _1: Self = Self::new(1);
14693 }
14694 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14695 pub struct Vbtadie1_SPEC;
14696 pub type Vbtadie1 = crate::EnumBitfieldStruct<u8, Vbtadie1_SPEC>;
14697 impl Vbtadie1 {
14698 #[doc = "Interrupt by VBTADF1 flag is disable"]
14699 pub const _0: Self = Self::new(0);
14700
14701 #[doc = "Interrupt by VBTADF1 flag is enable"]
14702 pub const _1: Self = Self::new(1);
14703 }
14704 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14705 pub struct Vbtadie2_SPEC;
14706 pub type Vbtadie2 = crate::EnumBitfieldStruct<u8, Vbtadie2_SPEC>;
14707 impl Vbtadie2 {
14708 #[doc = "Interrupt by VBTADF2 flag is disable"]
14709 pub const _0: Self = Self::new(0);
14710
14711 #[doc = "Interrupt by VBTADF2 flag is enable"]
14712 pub const _1: Self = Self::new(1);
14713 }
14714 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14715 pub struct Vbtadce0_SPEC;
14716 pub type Vbtadce0 = crate::EnumBitfieldStruct<u8, Vbtadce0_SPEC>;
14717 impl Vbtadce0 {
14718 #[doc = "Clear Backup Register by VBTADF0 flag is disable"]
14719 pub const _0: Self = Self::new(0);
14720
14721 #[doc = "Clear Backup Register by VBTADF0 flag is enable"]
14722 pub const _1: Self = Self::new(1);
14723 }
14724 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14725 pub struct Vbtadce1_SPEC;
14726 pub type Vbtadce1 = crate::EnumBitfieldStruct<u8, Vbtadce1_SPEC>;
14727 impl Vbtadce1 {
14728 #[doc = "Clear Backup Register by VBTADF1 flag is disable"]
14729 pub const _0: Self = Self::new(0);
14730
14731 #[doc = "Clear Backup Register by VBTADF1 flag is enable"]
14732 pub const _1: Self = Self::new(1);
14733 }
14734 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14735 pub struct Vbtadce2_SPEC;
14736 pub type Vbtadce2 = crate::EnumBitfieldStruct<u8, Vbtadce2_SPEC>;
14737 impl Vbtadce2 {
14738 #[doc = "Clear Backup Register by VBTADF2 flag is disable"]
14739 pub const _0: Self = Self::new(0);
14740
14741 #[doc = "Clear Backup Register by VBTADF2 flag is enable"]
14742 pub const _1: Self = Self::new(1);
14743 }
14744}
14745#[doc(hidden)]
14746#[derive(Copy, Clone, Eq, PartialEq)]
14747pub struct Vbtadcr2_SPEC;
14748impl crate::sealed::RegSpec for Vbtadcr2_SPEC {
14749 type DataType = u8;
14750}
14751
14752#[doc = "VBATT Tamper detection Control Register 2"]
14753pub type Vbtadcr2 = crate::RegValueT<Vbtadcr2_SPEC>;
14754
14755impl Vbtadcr2 {
14756 #[doc = "VBATT RTC Time Capture Event Source Select 0"]
14757 #[inline(always)]
14758 pub fn vbrtces0(
14759 self,
14760 ) -> crate::common::RegisterField<
14761 0,
14762 0x1,
14763 1,
14764 0,
14765 vbtadcr2::Vbrtces0,
14766 vbtadcr2::Vbrtces0,
14767 Vbtadcr2_SPEC,
14768 crate::common::RW,
14769 > {
14770 crate::common::RegisterField::<
14771 0,
14772 0x1,
14773 1,
14774 0,
14775 vbtadcr2::Vbrtces0,
14776 vbtadcr2::Vbrtces0,
14777 Vbtadcr2_SPEC,
14778 crate::common::RW,
14779 >::from_register(self, 0)
14780 }
14781
14782 #[doc = "VBATT RTC Time Capture Event Source Select 1"]
14783 #[inline(always)]
14784 pub fn vbrtces1(
14785 self,
14786 ) -> crate::common::RegisterField<
14787 1,
14788 0x1,
14789 1,
14790 0,
14791 vbtadcr2::Vbrtces1,
14792 vbtadcr2::Vbrtces1,
14793 Vbtadcr2_SPEC,
14794 crate::common::RW,
14795 > {
14796 crate::common::RegisterField::<
14797 1,
14798 0x1,
14799 1,
14800 0,
14801 vbtadcr2::Vbrtces1,
14802 vbtadcr2::Vbrtces1,
14803 Vbtadcr2_SPEC,
14804 crate::common::RW,
14805 >::from_register(self, 0)
14806 }
14807
14808 #[doc = "VBATT RTC Time Capture Event Source Select 2"]
14809 #[inline(always)]
14810 pub fn vbrtces2(
14811 self,
14812 ) -> crate::common::RegisterField<
14813 2,
14814 0x1,
14815 1,
14816 0,
14817 vbtadcr2::Vbrtces2,
14818 vbtadcr2::Vbrtces2,
14819 Vbtadcr2_SPEC,
14820 crate::common::RW,
14821 > {
14822 crate::common::RegisterField::<
14823 2,
14824 0x1,
14825 1,
14826 0,
14827 vbtadcr2::Vbrtces2,
14828 vbtadcr2::Vbrtces2,
14829 Vbtadcr2_SPEC,
14830 crate::common::RW,
14831 >::from_register(self, 0)
14832 }
14833}
14834impl ::core::default::Default for Vbtadcr2 {
14835 #[inline(always)]
14836 fn default() -> Vbtadcr2 {
14837 <crate::RegValueT<Vbtadcr2_SPEC> as RegisterValue<_>>::new(0)
14838 }
14839}
14840pub mod vbtadcr2 {
14841
14842 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14843 pub struct Vbrtces0_SPEC;
14844 pub type Vbrtces0 = crate::EnumBitfieldStruct<u8, Vbrtces0_SPEC>;
14845 impl Vbrtces0 {
14846 #[doc = "RTCIC0"]
14847 pub const _0: Self = Self::new(0);
14848
14849 #[doc = "VBTADF0"]
14850 pub const _1: Self = Self::new(1);
14851 }
14852 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14853 pub struct Vbrtces1_SPEC;
14854 pub type Vbrtces1 = crate::EnumBitfieldStruct<u8, Vbrtces1_SPEC>;
14855 impl Vbrtces1 {
14856 #[doc = "RTCIC1"]
14857 pub const _0: Self = Self::new(0);
14858
14859 #[doc = "VBTADF1"]
14860 pub const _1: Self = Self::new(1);
14861 }
14862 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14863 pub struct Vbrtces2_SPEC;
14864 pub type Vbrtces2 = crate::EnumBitfieldStruct<u8, Vbrtces2_SPEC>;
14865 impl Vbrtces2 {
14866 #[doc = "RTCIC2"]
14867 pub const _0: Self = Self::new(0);
14868
14869 #[doc = "VBTADF2"]
14870 pub const _1: Self = Self::new(1);
14871 }
14872}
14873#[doc(hidden)]
14874#[derive(Copy, Clone, Eq, PartialEq)]
14875pub struct Vbtictlr_SPEC;
14876impl crate::sealed::RegSpec for Vbtictlr_SPEC {
14877 type DataType = u8;
14878}
14879
14880#[doc = "VBATT Input Control Register"]
14881pub type Vbtictlr = crate::RegValueT<Vbtictlr_SPEC>;
14882
14883impl Vbtictlr {
14884 #[doc = "VBATT CH0 Input Enable"]
14885 #[inline(always)]
14886 pub fn vch0inen(
14887 self,
14888 ) -> crate::common::RegisterField<
14889 0,
14890 0x1,
14891 1,
14892 0,
14893 vbtictlr::Vch0Inen,
14894 vbtictlr::Vch0Inen,
14895 Vbtictlr_SPEC,
14896 crate::common::RW,
14897 > {
14898 crate::common::RegisterField::<
14899 0,
14900 0x1,
14901 1,
14902 0,
14903 vbtictlr::Vch0Inen,
14904 vbtictlr::Vch0Inen,
14905 Vbtictlr_SPEC,
14906 crate::common::RW,
14907 >::from_register(self, 0)
14908 }
14909
14910 #[doc = "VBATT CH1 Input Enable"]
14911 #[inline(always)]
14912 pub fn vch1inen(
14913 self,
14914 ) -> crate::common::RegisterField<
14915 1,
14916 0x1,
14917 1,
14918 0,
14919 vbtictlr::Vch1Inen,
14920 vbtictlr::Vch1Inen,
14921 Vbtictlr_SPEC,
14922 crate::common::RW,
14923 > {
14924 crate::common::RegisterField::<
14925 1,
14926 0x1,
14927 1,
14928 0,
14929 vbtictlr::Vch1Inen,
14930 vbtictlr::Vch1Inen,
14931 Vbtictlr_SPEC,
14932 crate::common::RW,
14933 >::from_register(self, 0)
14934 }
14935
14936 #[doc = "VBATT CH2 Input Enable"]
14937 #[inline(always)]
14938 pub fn vch2inen(
14939 self,
14940 ) -> crate::common::RegisterField<
14941 2,
14942 0x1,
14943 1,
14944 0,
14945 vbtictlr::Vch2Inen,
14946 vbtictlr::Vch2Inen,
14947 Vbtictlr_SPEC,
14948 crate::common::RW,
14949 > {
14950 crate::common::RegisterField::<
14951 2,
14952 0x1,
14953 1,
14954 0,
14955 vbtictlr::Vch2Inen,
14956 vbtictlr::Vch2Inen,
14957 Vbtictlr_SPEC,
14958 crate::common::RW,
14959 >::from_register(self, 0)
14960 }
14961}
14962impl ::core::default::Default for Vbtictlr {
14963 #[inline(always)]
14964 fn default() -> Vbtictlr {
14965 <crate::RegValueT<Vbtictlr_SPEC> as RegisterValue<_>>::new(0)
14966 }
14967}
14968pub mod vbtictlr {
14969
14970 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14971 pub struct Vch0Inen_SPEC;
14972 pub type Vch0Inen = crate::EnumBitfieldStruct<u8, Vch0Inen_SPEC>;
14973 impl Vch0Inen {
14974 #[doc = "RTCIC0 input disable"]
14975 pub const _0: Self = Self::new(0);
14976
14977 #[doc = "RTCIC0 input enable"]
14978 pub const _1: Self = Self::new(1);
14979 }
14980 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14981 pub struct Vch1Inen_SPEC;
14982 pub type Vch1Inen = crate::EnumBitfieldStruct<u8, Vch1Inen_SPEC>;
14983 impl Vch1Inen {
14984 #[doc = "RTCIC1 input disable"]
14985 pub const _0: Self = Self::new(0);
14986
14987 #[doc = "RTCIC1 input enable"]
14988 pub const _1: Self = Self::new(1);
14989 }
14990 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14991 pub struct Vch2Inen_SPEC;
14992 pub type Vch2Inen = crate::EnumBitfieldStruct<u8, Vch2Inen_SPEC>;
14993 impl Vch2Inen {
14994 #[doc = "RTCIC2 input disable"]
14995 pub const _0: Self = Self::new(0);
14996
14997 #[doc = "RTCIC2 input enable"]
14998 pub const _1: Self = Self::new(1);
14999 }
15000}
15001#[doc(hidden)]
15002#[derive(Copy, Clone, Eq, PartialEq)]
15003pub struct Vbtictlr2_SPEC;
15004impl crate::sealed::RegSpec for Vbtictlr2_SPEC {
15005 type DataType = u8;
15006}
15007
15008#[doc = "VBATT Input Control Register 2"]
15009pub type Vbtictlr2 = crate::RegValueT<Vbtictlr2_SPEC>;
15010
15011impl Vbtictlr2 {
15012 #[doc = "VBATT CH0 Input Noise Canceler Enable"]
15013 #[inline(always)]
15014 pub fn vch0nce(
15015 self,
15016 ) -> crate::common::RegisterField<
15017 0,
15018 0x1,
15019 1,
15020 0,
15021 vbtictlr2::Vch0Nce,
15022 vbtictlr2::Vch0Nce,
15023 Vbtictlr2_SPEC,
15024 crate::common::RW,
15025 > {
15026 crate::common::RegisterField::<
15027 0,
15028 0x1,
15029 1,
15030 0,
15031 vbtictlr2::Vch0Nce,
15032 vbtictlr2::Vch0Nce,
15033 Vbtictlr2_SPEC,
15034 crate::common::RW,
15035 >::from_register(self, 0)
15036 }
15037
15038 #[doc = "VBATT CH1 Input Noise Canceler Enable"]
15039 #[inline(always)]
15040 pub fn vch1nce(
15041 self,
15042 ) -> crate::common::RegisterField<
15043 1,
15044 0x1,
15045 1,
15046 0,
15047 vbtictlr2::Vch1Nce,
15048 vbtictlr2::Vch1Nce,
15049 Vbtictlr2_SPEC,
15050 crate::common::RW,
15051 > {
15052 crate::common::RegisterField::<
15053 1,
15054 0x1,
15055 1,
15056 0,
15057 vbtictlr2::Vch1Nce,
15058 vbtictlr2::Vch1Nce,
15059 Vbtictlr2_SPEC,
15060 crate::common::RW,
15061 >::from_register(self, 0)
15062 }
15063
15064 #[doc = "VBATT CH2 Input Noise Canceler Enable"]
15065 #[inline(always)]
15066 pub fn vch2nce(
15067 self,
15068 ) -> crate::common::RegisterField<
15069 2,
15070 0x1,
15071 1,
15072 0,
15073 vbtictlr2::Vch2Nce,
15074 vbtictlr2::Vch2Nce,
15075 Vbtictlr2_SPEC,
15076 crate::common::RW,
15077 > {
15078 crate::common::RegisterField::<
15079 2,
15080 0x1,
15081 1,
15082 0,
15083 vbtictlr2::Vch2Nce,
15084 vbtictlr2::Vch2Nce,
15085 Vbtictlr2_SPEC,
15086 crate::common::RW,
15087 >::from_register(self, 0)
15088 }
15089
15090 #[doc = "VBATT CH0 Input Edge Select"]
15091 #[inline(always)]
15092 pub fn vch0eg(
15093 self,
15094 ) -> crate::common::RegisterField<
15095 4,
15096 0x1,
15097 1,
15098 0,
15099 vbtictlr2::Vch0Eg,
15100 vbtictlr2::Vch0Eg,
15101 Vbtictlr2_SPEC,
15102 crate::common::RW,
15103 > {
15104 crate::common::RegisterField::<
15105 4,
15106 0x1,
15107 1,
15108 0,
15109 vbtictlr2::Vch0Eg,
15110 vbtictlr2::Vch0Eg,
15111 Vbtictlr2_SPEC,
15112 crate::common::RW,
15113 >::from_register(self, 0)
15114 }
15115
15116 #[doc = "VBATT CH1 Input Edge Select"]
15117 #[inline(always)]
15118 pub fn vch1eg(
15119 self,
15120 ) -> crate::common::RegisterField<
15121 5,
15122 0x1,
15123 1,
15124 0,
15125 vbtictlr2::Vch1Eg,
15126 vbtictlr2::Vch1Eg,
15127 Vbtictlr2_SPEC,
15128 crate::common::RW,
15129 > {
15130 crate::common::RegisterField::<
15131 5,
15132 0x1,
15133 1,
15134 0,
15135 vbtictlr2::Vch1Eg,
15136 vbtictlr2::Vch1Eg,
15137 Vbtictlr2_SPEC,
15138 crate::common::RW,
15139 >::from_register(self, 0)
15140 }
15141
15142 #[doc = "VBATT CH2 Input Edge Select"]
15143 #[inline(always)]
15144 pub fn vch2eg(
15145 self,
15146 ) -> crate::common::RegisterField<
15147 6,
15148 0x1,
15149 1,
15150 0,
15151 vbtictlr2::Vch2Eg,
15152 vbtictlr2::Vch2Eg,
15153 Vbtictlr2_SPEC,
15154 crate::common::RW,
15155 > {
15156 crate::common::RegisterField::<
15157 6,
15158 0x1,
15159 1,
15160 0,
15161 vbtictlr2::Vch2Eg,
15162 vbtictlr2::Vch2Eg,
15163 Vbtictlr2_SPEC,
15164 crate::common::RW,
15165 >::from_register(self, 0)
15166 }
15167}
15168impl ::core::default::Default for Vbtictlr2 {
15169 #[inline(always)]
15170 fn default() -> Vbtictlr2 {
15171 <crate::RegValueT<Vbtictlr2_SPEC> as RegisterValue<_>>::new(112)
15172 }
15173}
15174pub mod vbtictlr2 {
15175
15176 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15177 pub struct Vch0Nce_SPEC;
15178 pub type Vch0Nce = crate::EnumBitfieldStruct<u8, Vch0Nce_SPEC>;
15179 impl Vch0Nce {
15180 #[doc = "RTCIC0 pin input noise canceler disable"]
15181 pub const _0: Self = Self::new(0);
15182
15183 #[doc = "RTCIC0 pin input noise canceler enable"]
15184 pub const _1: Self = Self::new(1);
15185 }
15186 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15187 pub struct Vch1Nce_SPEC;
15188 pub type Vch1Nce = crate::EnumBitfieldStruct<u8, Vch1Nce_SPEC>;
15189 impl Vch1Nce {
15190 #[doc = "RTCIC1 pin input noise canceler disable"]
15191 pub const _0: Self = Self::new(0);
15192
15193 #[doc = "RTCIC1 pin input noise canceler enable"]
15194 pub const _1: Self = Self::new(1);
15195 }
15196 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15197 pub struct Vch2Nce_SPEC;
15198 pub type Vch2Nce = crate::EnumBitfieldStruct<u8, Vch2Nce_SPEC>;
15199 impl Vch2Nce {
15200 #[doc = "RTCIC2 pin input noise canceler disable"]
15201 pub const _0: Self = Self::new(0);
15202
15203 #[doc = "RTCIC2 pin input noise canceler enable"]
15204 pub const _1: Self = Self::new(1);
15205 }
15206 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15207 pub struct Vch0Eg_SPEC;
15208 pub type Vch0Eg = crate::EnumBitfieldStruct<u8, Vch0Eg_SPEC>;
15209 impl Vch0Eg {
15210 #[doc = "RTCIC0 pin input event is detected on falling edge"]
15211 pub const _0: Self = Self::new(0);
15212
15213 #[doc = "RTCIC0 pin input event is detected on rising edge"]
15214 pub const _1: Self = Self::new(1);
15215 }
15216 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15217 pub struct Vch1Eg_SPEC;
15218 pub type Vch1Eg = crate::EnumBitfieldStruct<u8, Vch1Eg_SPEC>;
15219 impl Vch1Eg {
15220 #[doc = "RTCIC1 pin input event is detected on falling edge"]
15221 pub const _0: Self = Self::new(0);
15222
15223 #[doc = "RTCIC1 pin input event is detected on rising edge"]
15224 pub const _1: Self = Self::new(1);
15225 }
15226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15227 pub struct Vch2Eg_SPEC;
15228 pub type Vch2Eg = crate::EnumBitfieldStruct<u8, Vch2Eg_SPEC>;
15229 impl Vch2Eg {
15230 #[doc = "RTCIC2 pin input event is detected on falling edge"]
15231 pub const _0: Self = Self::new(0);
15232
15233 #[doc = "RTCIC2 pin input event is detected on rising edge"]
15234 pub const _1: Self = Self::new(1);
15235 }
15236}
15237#[doc(hidden)]
15238#[derive(Copy, Clone, Eq, PartialEq)]
15239pub struct Vbtimonr_SPEC;
15240impl crate::sealed::RegSpec for Vbtimonr_SPEC {
15241 type DataType = u8;
15242}
15243
15244#[doc = "VBATT Input Monitor Register"]
15245pub type Vbtimonr = crate::RegValueT<Vbtimonr_SPEC>;
15246
15247impl Vbtimonr {
15248 #[doc = "VBATT CH0 Input monitor"]
15249 #[inline(always)]
15250 pub fn vch0mon(
15251 self,
15252 ) -> crate::common::RegisterField<
15253 0,
15254 0x1,
15255 1,
15256 0,
15257 vbtimonr::Vch0Mon,
15258 vbtimonr::Vch0Mon,
15259 Vbtimonr_SPEC,
15260 crate::common::R,
15261 > {
15262 crate::common::RegisterField::<
15263 0,
15264 0x1,
15265 1,
15266 0,
15267 vbtimonr::Vch0Mon,
15268 vbtimonr::Vch0Mon,
15269 Vbtimonr_SPEC,
15270 crate::common::R,
15271 >::from_register(self, 0)
15272 }
15273
15274 #[doc = "VBATT CH1 Input monitor"]
15275 #[inline(always)]
15276 pub fn vch1mon(
15277 self,
15278 ) -> crate::common::RegisterField<
15279 1,
15280 0x1,
15281 1,
15282 0,
15283 vbtimonr::Vch1Mon,
15284 vbtimonr::Vch1Mon,
15285 Vbtimonr_SPEC,
15286 crate::common::R,
15287 > {
15288 crate::common::RegisterField::<
15289 1,
15290 0x1,
15291 1,
15292 0,
15293 vbtimonr::Vch1Mon,
15294 vbtimonr::Vch1Mon,
15295 Vbtimonr_SPEC,
15296 crate::common::R,
15297 >::from_register(self, 0)
15298 }
15299
15300 #[doc = "VBATT CH2 Input monitor"]
15301 #[inline(always)]
15302 pub fn vch2mon(
15303 self,
15304 ) -> crate::common::RegisterField<
15305 2,
15306 0x1,
15307 1,
15308 0,
15309 vbtimonr::Vch2Mon,
15310 vbtimonr::Vch2Mon,
15311 Vbtimonr_SPEC,
15312 crate::common::R,
15313 > {
15314 crate::common::RegisterField::<
15315 2,
15316 0x1,
15317 1,
15318 0,
15319 vbtimonr::Vch2Mon,
15320 vbtimonr::Vch2Mon,
15321 Vbtimonr_SPEC,
15322 crate::common::R,
15323 >::from_register(self, 0)
15324 }
15325}
15326impl ::core::default::Default for Vbtimonr {
15327 #[inline(always)]
15328 fn default() -> Vbtimonr {
15329 <crate::RegValueT<Vbtimonr_SPEC> as RegisterValue<_>>::new(0)
15330 }
15331}
15332pub mod vbtimonr {
15333
15334 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15335 pub struct Vch0Mon_SPEC;
15336 pub type Vch0Mon = crate::EnumBitfieldStruct<u8, Vch0Mon_SPEC>;
15337 impl Vch0Mon {
15338 #[doc = "RTCIC0 pin input is low level"]
15339 pub const _0: Self = Self::new(0);
15340
15341 #[doc = "RTCIC0 pin input is high level."]
15342 pub const _1: Self = Self::new(1);
15343 }
15344 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15345 pub struct Vch1Mon_SPEC;
15346 pub type Vch1Mon = crate::EnumBitfieldStruct<u8, Vch1Mon_SPEC>;
15347 impl Vch1Mon {
15348 #[doc = "RTCIC1 pin input is low level"]
15349 pub const _0: Self = Self::new(0);
15350
15351 #[doc = "RTCIC1 pin input is high level"]
15352 pub const _1: Self = Self::new(1);
15353 }
15354 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15355 pub struct Vch2Mon_SPEC;
15356 pub type Vch2Mon = crate::EnumBitfieldStruct<u8, Vch2Mon_SPEC>;
15357 impl Vch2Mon {
15358 #[doc = "RTCIC2 pin input is low level"]
15359 pub const _0: Self = Self::new(0);
15360
15361 #[doc = "RTCIC2 pin input is high level."]
15362 pub const _1: Self = Self::new(1);
15363 }
15364}
15365#[doc(hidden)]
15366#[derive(Copy, Clone, Eq, PartialEq)]
15367pub struct Vbtbkr_SPEC;
15368impl crate::sealed::RegSpec for Vbtbkr_SPEC {
15369 type DataType = u8;
15370}
15371
15372#[doc = "VBATT Backup Register"]
15373pub type Vbtbkr = crate::RegValueT<Vbtbkr_SPEC>;
15374
15375impl NoBitfieldReg<Vbtbkr_SPEC> for Vbtbkr {}
15376impl ::core::default::Default for Vbtbkr {
15377 #[inline(always)]
15378 fn default() -> Vbtbkr {
15379 <crate::RegValueT<Vbtbkr_SPEC> as RegisterValue<_>>::new(0)
15380 }
15381}