ra6t2/sci_b0/
ccr3.rs

1#[doc = "Register `CCR3` reader"]
2pub struct R(crate::R<CCR3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCR3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCR3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCR3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CCR3` writer"]
17pub struct W(crate::W<CCR3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCR3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCR3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCR3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CPHA` reader - Clock Phase Select"]
38pub type CPHA_R = crate::BitReader<CPHA_A>;
39#[doc = "Clock Phase Select\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum CPHA_A {
42    #[doc = "0: Data is sampled at an odd edge and changes at an even edge. (Clock is delayed.)"]
43    _0 = 0,
44    #[doc = "1: Data changes at an odd edge and is sampled at an even edge. (Clock is not delayed)"]
45    _1 = 1,
46}
47impl From<CPHA_A> for bool {
48    #[inline(always)]
49    fn from(variant: CPHA_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl CPHA_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> CPHA_A {
57        match self.bits {
58            false => CPHA_A::_0,
59            true => CPHA_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == CPHA_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == CPHA_A::_1
71    }
72}
73#[doc = "Field `CPHA` writer - Clock Phase Select"]
74pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, CPHA_A, O>;
75impl<'a, const O: u8> CPHA_W<'a, O> {
76    #[doc = "Data is sampled at an odd edge and changes at an even edge. (Clock is delayed.)"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(CPHA_A::_0)
80    }
81    #[doc = "Data changes at an odd edge and is sampled at an even edge. (Clock is not delayed)"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(CPHA_A::_1)
85    }
86}
87#[doc = "Field `CPOL` reader - Clock Polarity Select"]
88pub type CPOL_R = crate::BitReader<CPOL_A>;
89#[doc = "Clock Polarity Select\n\nValue on reset: 1"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CPOL_A {
92    #[doc = "0: SCKn in idle state is 0."]
93    _0 = 0,
94    #[doc = "1: SCKn in idle state is 1."]
95    _1 = 1,
96}
97impl From<CPOL_A> for bool {
98    #[inline(always)]
99    fn from(variant: CPOL_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CPOL_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CPOL_A {
107        match self.bits {
108            false => CPOL_A::_0,
109            true => CPOL_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == CPOL_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == CPOL_A::_1
121    }
122}
123#[doc = "Field `CPOL` writer - Clock Polarity Select"]
124pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, CPOL_A, O>;
125impl<'a, const O: u8> CPOL_W<'a, O> {
126    #[doc = "SCKn in idle state is 0."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(CPOL_A::_0)
130    }
131    #[doc = "SCKn in idle state is 1."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(CPOL_A::_1)
135    }
136}
137#[doc = "Field `BPEN` reader - Synchronizer bypass enable"]
138pub type BPEN_R = crate::BitReader<BPEN_A>;
139#[doc = "Synchronizer bypass enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum BPEN_A {
142    #[doc = "0: Synchronizer circuit is not bypassed."]
143    _0 = 0,
144    #[doc = "1: Synchronizer circuit is bypassed."]
145    _1 = 1,
146}
147impl From<BPEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: BPEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl BPEN_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> BPEN_A {
157        match self.bits {
158            false => BPEN_A::_0,
159            true => BPEN_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == BPEN_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == BPEN_A::_1
171    }
172}
173#[doc = "Field `BPEN` writer - Synchronizer bypass enable"]
174pub type BPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, BPEN_A, O>;
175impl<'a, const O: u8> BPEN_W<'a, O> {
176    #[doc = "Synchronizer circuit is not bypassed."]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(BPEN_A::_0)
180    }
181    #[doc = "Synchronizer circuit is bypassed."]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(BPEN_A::_1)
185    }
186}
187#[doc = "Field `CHR` reader - Character Length"]
188pub type CHR_R = crate::FieldReader<u8, CHR_A>;
189#[doc = "Character Length\n\nValue on reset: 2"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191#[repr(u8)]
192pub enum CHR_A {
193    #[doc = "0: Transmit/receive in 9-bit data length"]
194    _00 = 0,
195    #[doc = "1: Transmit/receive in 9-bit data length"]
196    _01 = 1,
197    #[doc = "2: Transmit/receive in 8-bit data length (initial value)"]
198    _10 = 2,
199    #[doc = "3: Transmit/receive in 7-bit data length"]
200    _11 = 3,
201}
202impl From<CHR_A> for u8 {
203    #[inline(always)]
204    fn from(variant: CHR_A) -> Self {
205        variant as _
206    }
207}
208impl CHR_R {
209    #[doc = "Get enumerated values variant"]
210    #[inline(always)]
211    pub fn variant(&self) -> CHR_A {
212        match self.bits {
213            0 => CHR_A::_00,
214            1 => CHR_A::_01,
215            2 => CHR_A::_10,
216            3 => CHR_A::_11,
217            _ => unreachable!(),
218        }
219    }
220    #[doc = "Checks if the value of the field is `_00`"]
221    #[inline(always)]
222    pub fn is_00(&self) -> bool {
223        *self == CHR_A::_00
224    }
225    #[doc = "Checks if the value of the field is `_01`"]
226    #[inline(always)]
227    pub fn is_01(&self) -> bool {
228        *self == CHR_A::_01
229    }
230    #[doc = "Checks if the value of the field is `_10`"]
231    #[inline(always)]
232    pub fn is_10(&self) -> bool {
233        *self == CHR_A::_10
234    }
235    #[doc = "Checks if the value of the field is `_11`"]
236    #[inline(always)]
237    pub fn is_11(&self) -> bool {
238        *self == CHR_A::_11
239    }
240}
241#[doc = "Field `CHR` writer - Character Length"]
242pub type CHR_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CCR3_SPEC, u8, CHR_A, 2, O>;
243impl<'a, const O: u8> CHR_W<'a, O> {
244    #[doc = "Transmit/receive in 9-bit data length"]
245    #[inline(always)]
246    pub fn _00(self) -> &'a mut W {
247        self.variant(CHR_A::_00)
248    }
249    #[doc = "Transmit/receive in 9-bit data length"]
250    #[inline(always)]
251    pub fn _01(self) -> &'a mut W {
252        self.variant(CHR_A::_01)
253    }
254    #[doc = "Transmit/receive in 8-bit data length (initial value)"]
255    #[inline(always)]
256    pub fn _10(self) -> &'a mut W {
257        self.variant(CHR_A::_10)
258    }
259    #[doc = "Transmit/receive in 7-bit data length"]
260    #[inline(always)]
261    pub fn _11(self) -> &'a mut W {
262        self.variant(CHR_A::_11)
263    }
264}
265#[doc = "Field `LSBF` reader - LSB First select"]
266pub type LSBF_R = crate::BitReader<LSBF_A>;
267#[doc = "LSB First select\n\nValue on reset: 1"]
268#[derive(Clone, Copy, Debug, PartialEq, Eq)]
269pub enum LSBF_A {
270    #[doc = "0: MSB first"]
271    _0 = 0,
272    #[doc = "1: LSB first"]
273    _1 = 1,
274}
275impl From<LSBF_A> for bool {
276    #[inline(always)]
277    fn from(variant: LSBF_A) -> Self {
278        variant as u8 != 0
279    }
280}
281impl LSBF_R {
282    #[doc = "Get enumerated values variant"]
283    #[inline(always)]
284    pub fn variant(&self) -> LSBF_A {
285        match self.bits {
286            false => LSBF_A::_0,
287            true => LSBF_A::_1,
288        }
289    }
290    #[doc = "Checks if the value of the field is `_0`"]
291    #[inline(always)]
292    pub fn is_0(&self) -> bool {
293        *self == LSBF_A::_0
294    }
295    #[doc = "Checks if the value of the field is `_1`"]
296    #[inline(always)]
297    pub fn is_1(&self) -> bool {
298        *self == LSBF_A::_1
299    }
300}
301#[doc = "Field `LSBF` writer - LSB First select"]
302pub type LSBF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, LSBF_A, O>;
303impl<'a, const O: u8> LSBF_W<'a, O> {
304    #[doc = "MSB first"]
305    #[inline(always)]
306    pub fn _0(self) -> &'a mut W {
307        self.variant(LSBF_A::_0)
308    }
309    #[doc = "LSB first"]
310    #[inline(always)]
311    pub fn _1(self) -> &'a mut W {
312        self.variant(LSBF_A::_1)
313    }
314}
315#[doc = "Field `SINV` reader - Transmitted/Received Data Invert"]
316pub type SINV_R = crate::BitReader<SINV_A>;
317#[doc = "Transmitted/Received Data Invert\n\nValue on reset: 0"]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum SINV_A {
320    #[doc = "0: TDR contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are."]
321    _0 = 0,
322    #[doc = "1: TDR contents are inverted before being transmitted to TSR. RSR contents are inverted and stored to RDR."]
323    _1 = 1,
324}
325impl From<SINV_A> for bool {
326    #[inline(always)]
327    fn from(variant: SINV_A) -> Self {
328        variant as u8 != 0
329    }
330}
331impl SINV_R {
332    #[doc = "Get enumerated values variant"]
333    #[inline(always)]
334    pub fn variant(&self) -> SINV_A {
335        match self.bits {
336            false => SINV_A::_0,
337            true => SINV_A::_1,
338        }
339    }
340    #[doc = "Checks if the value of the field is `_0`"]
341    #[inline(always)]
342    pub fn is_0(&self) -> bool {
343        *self == SINV_A::_0
344    }
345    #[doc = "Checks if the value of the field is `_1`"]
346    #[inline(always)]
347    pub fn is_1(&self) -> bool {
348        *self == SINV_A::_1
349    }
350}
351#[doc = "Field `SINV` writer - Transmitted/Received Data Invert"]
352pub type SINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, SINV_A, O>;
353impl<'a, const O: u8> SINV_W<'a, O> {
354    #[doc = "TDR contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are."]
355    #[inline(always)]
356    pub fn _0(self) -> &'a mut W {
357        self.variant(SINV_A::_0)
358    }
359    #[doc = "TDR contents are inverted before being transmitted to TSR. RSR contents are inverted and stored to RDR."]
360    #[inline(always)]
361    pub fn _1(self) -> &'a mut W {
362        self.variant(SINV_A::_1)
363    }
364}
365#[doc = "Field `STP` reader - Stop Bit Length"]
366pub type STP_R = crate::BitReader<STP_A>;
367#[doc = "Stop Bit Length\n\nValue on reset: 0"]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum STP_A {
370    #[doc = "0: 1 stop bit / Break Delimiter length is 1bit"]
371    _0 = 0,
372    #[doc = "1: 2 stop bits / Break Delimiter length is 2bits"]
373    _1 = 1,
374}
375impl From<STP_A> for bool {
376    #[inline(always)]
377    fn from(variant: STP_A) -> Self {
378        variant as u8 != 0
379    }
380}
381impl STP_R {
382    #[doc = "Get enumerated values variant"]
383    #[inline(always)]
384    pub fn variant(&self) -> STP_A {
385        match self.bits {
386            false => STP_A::_0,
387            true => STP_A::_1,
388        }
389    }
390    #[doc = "Checks if the value of the field is `_0`"]
391    #[inline(always)]
392    pub fn is_0(&self) -> bool {
393        *self == STP_A::_0
394    }
395    #[doc = "Checks if the value of the field is `_1`"]
396    #[inline(always)]
397    pub fn is_1(&self) -> bool {
398        *self == STP_A::_1
399    }
400}
401#[doc = "Field `STP` writer - Stop Bit Length"]
402pub type STP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, STP_A, O>;
403impl<'a, const O: u8> STP_W<'a, O> {
404    #[doc = "1 stop bit / Break Delimiter length is 1bit"]
405    #[inline(always)]
406    pub fn _0(self) -> &'a mut W {
407        self.variant(STP_A::_0)
408    }
409    #[doc = "2 stop bits / Break Delimiter length is 2bits"]
410    #[inline(always)]
411    pub fn _1(self) -> &'a mut W {
412        self.variant(STP_A::_1)
413    }
414}
415#[doc = "Field `RXDESEL` reader - Asynchronous Start Bit Edge Detection Select"]
416pub type RXDESEL_R = crate::BitReader<RXDESEL_A>;
417#[doc = "Asynchronous Start Bit Edge Detection Select\n\nValue on reset: 0"]
418#[derive(Clone, Copy, Debug, PartialEq, Eq)]
419pub enum RXDESEL_A {
420    #[doc = "0: The low level on the RXDn pin is detected as the start bit."]
421    _0 = 0,
422    #[doc = "1: A falling edge on the RXDn pin is detected as the start bit."]
423    _1 = 1,
424}
425impl From<RXDESEL_A> for bool {
426    #[inline(always)]
427    fn from(variant: RXDESEL_A) -> Self {
428        variant as u8 != 0
429    }
430}
431impl RXDESEL_R {
432    #[doc = "Get enumerated values variant"]
433    #[inline(always)]
434    pub fn variant(&self) -> RXDESEL_A {
435        match self.bits {
436            false => RXDESEL_A::_0,
437            true => RXDESEL_A::_1,
438        }
439    }
440    #[doc = "Checks if the value of the field is `_0`"]
441    #[inline(always)]
442    pub fn is_0(&self) -> bool {
443        *self == RXDESEL_A::_0
444    }
445    #[doc = "Checks if the value of the field is `_1`"]
446    #[inline(always)]
447    pub fn is_1(&self) -> bool {
448        *self == RXDESEL_A::_1
449    }
450}
451#[doc = "Field `RXDESEL` writer - Asynchronous Start Bit Edge Detection Select"]
452pub type RXDESEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, RXDESEL_A, O>;
453impl<'a, const O: u8> RXDESEL_W<'a, O> {
454    #[doc = "The low level on the RXDn pin is detected as the start bit."]
455    #[inline(always)]
456    pub fn _0(self) -> &'a mut W {
457        self.variant(RXDESEL_A::_0)
458    }
459    #[doc = "A falling edge on the RXDn pin is detected as the start bit."]
460    #[inline(always)]
461    pub fn _1(self) -> &'a mut W {
462        self.variant(RXDESEL_A::_1)
463    }
464}
465#[doc = "Field `MOD` reader - Communication mode select"]
466pub type MOD_R = crate::FieldReader<u8, MOD_A>;
467#[doc = "Communication mode select\n\nValue on reset: 0"]
468#[derive(Clone, Copy, Debug, PartialEq, Eq)]
469#[repr(u8)]
470pub enum MOD_A {
471    #[doc = "0: Asynchronous mode (Multi-processor mode)"]
472    _000 = 0,
473    #[doc = "1: Smart card interface mode"]
474    _001 = 1,
475    #[doc = "2: Clock synchronous mode"]
476    _010 = 2,
477    #[doc = "3: Simple SPI mode"]
478    _011 = 3,
479    #[doc = "4: Simple IIC mode"]
480    _100 = 4,
481    #[doc = "5: Manchester mode"]
482    _101 = 5,
483    #[doc = "6: Simple LIN mode"]
484    _110 = 6,
485    #[doc = "7: Setting prohibited"]
486    _111 = 7,
487}
488impl From<MOD_A> for u8 {
489    #[inline(always)]
490    fn from(variant: MOD_A) -> Self {
491        variant as _
492    }
493}
494impl MOD_R {
495    #[doc = "Get enumerated values variant"]
496    #[inline(always)]
497    pub fn variant(&self) -> MOD_A {
498        match self.bits {
499            0 => MOD_A::_000,
500            1 => MOD_A::_001,
501            2 => MOD_A::_010,
502            3 => MOD_A::_011,
503            4 => MOD_A::_100,
504            5 => MOD_A::_101,
505            6 => MOD_A::_110,
506            7 => MOD_A::_111,
507            _ => unreachable!(),
508        }
509    }
510    #[doc = "Checks if the value of the field is `_000`"]
511    #[inline(always)]
512    pub fn is_000(&self) -> bool {
513        *self == MOD_A::_000
514    }
515    #[doc = "Checks if the value of the field is `_001`"]
516    #[inline(always)]
517    pub fn is_001(&self) -> bool {
518        *self == MOD_A::_001
519    }
520    #[doc = "Checks if the value of the field is `_010`"]
521    #[inline(always)]
522    pub fn is_010(&self) -> bool {
523        *self == MOD_A::_010
524    }
525    #[doc = "Checks if the value of the field is `_011`"]
526    #[inline(always)]
527    pub fn is_011(&self) -> bool {
528        *self == MOD_A::_011
529    }
530    #[doc = "Checks if the value of the field is `_100`"]
531    #[inline(always)]
532    pub fn is_100(&self) -> bool {
533        *self == MOD_A::_100
534    }
535    #[doc = "Checks if the value of the field is `_101`"]
536    #[inline(always)]
537    pub fn is_101(&self) -> bool {
538        *self == MOD_A::_101
539    }
540    #[doc = "Checks if the value of the field is `_110`"]
541    #[inline(always)]
542    pub fn is_110(&self) -> bool {
543        *self == MOD_A::_110
544    }
545    #[doc = "Checks if the value of the field is `_111`"]
546    #[inline(always)]
547    pub fn is_111(&self) -> bool {
548        *self == MOD_A::_111
549    }
550}
551#[doc = "Field `MOD` writer - Communication mode select"]
552pub type MOD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CCR3_SPEC, u8, MOD_A, 3, O>;
553impl<'a, const O: u8> MOD_W<'a, O> {
554    #[doc = "Asynchronous mode (Multi-processor mode)"]
555    #[inline(always)]
556    pub fn _000(self) -> &'a mut W {
557        self.variant(MOD_A::_000)
558    }
559    #[doc = "Smart card interface mode"]
560    #[inline(always)]
561    pub fn _001(self) -> &'a mut W {
562        self.variant(MOD_A::_001)
563    }
564    #[doc = "Clock synchronous mode"]
565    #[inline(always)]
566    pub fn _010(self) -> &'a mut W {
567        self.variant(MOD_A::_010)
568    }
569    #[doc = "Simple SPI mode"]
570    #[inline(always)]
571    pub fn _011(self) -> &'a mut W {
572        self.variant(MOD_A::_011)
573    }
574    #[doc = "Simple IIC mode"]
575    #[inline(always)]
576    pub fn _100(self) -> &'a mut W {
577        self.variant(MOD_A::_100)
578    }
579    #[doc = "Manchester mode"]
580    #[inline(always)]
581    pub fn _101(self) -> &'a mut W {
582        self.variant(MOD_A::_101)
583    }
584    #[doc = "Simple LIN mode"]
585    #[inline(always)]
586    pub fn _110(self) -> &'a mut W {
587        self.variant(MOD_A::_110)
588    }
589    #[doc = "Setting prohibited"]
590    #[inline(always)]
591    pub fn _111(self) -> &'a mut W {
592        self.variant(MOD_A::_111)
593    }
594}
595#[doc = "Field `MP` reader - Multi-Processor Mode"]
596pub type MP_R = crate::BitReader<MP_A>;
597#[doc = "Multi-Processor Mode\n\nValue on reset: 0"]
598#[derive(Clone, Copy, Debug, PartialEq, Eq)]
599pub enum MP_A {
600    #[doc = "0: Multi-processor communications function is disabled"]
601    _0 = 0,
602    #[doc = "1: Multi-processor communications function is enabled"]
603    _1 = 1,
604}
605impl From<MP_A> for bool {
606    #[inline(always)]
607    fn from(variant: MP_A) -> Self {
608        variant as u8 != 0
609    }
610}
611impl MP_R {
612    #[doc = "Get enumerated values variant"]
613    #[inline(always)]
614    pub fn variant(&self) -> MP_A {
615        match self.bits {
616            false => MP_A::_0,
617            true => MP_A::_1,
618        }
619    }
620    #[doc = "Checks if the value of the field is `_0`"]
621    #[inline(always)]
622    pub fn is_0(&self) -> bool {
623        *self == MP_A::_0
624    }
625    #[doc = "Checks if the value of the field is `_1`"]
626    #[inline(always)]
627    pub fn is_1(&self) -> bool {
628        *self == MP_A::_1
629    }
630}
631#[doc = "Field `MP` writer - Multi-Processor Mode"]
632pub type MP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, MP_A, O>;
633impl<'a, const O: u8> MP_W<'a, O> {
634    #[doc = "Multi-processor communications function is disabled"]
635    #[inline(always)]
636    pub fn _0(self) -> &'a mut W {
637        self.variant(MP_A::_0)
638    }
639    #[doc = "Multi-processor communications function is enabled"]
640    #[inline(always)]
641    pub fn _1(self) -> &'a mut W {
642        self.variant(MP_A::_1)
643    }
644}
645#[doc = "Field `FM` reader - FIFO Mode select"]
646pub type FM_R = crate::BitReader<FM_A>;
647#[doc = "FIFO Mode select\n\nValue on reset: 0"]
648#[derive(Clone, Copy, Debug, PartialEq, Eq)]
649pub enum FM_A {
650    #[doc = "0: TDR register, RDR register is non-FIFO buffer configuration"]
651    _0 = 0,
652    #[doc = "1: TDR register, RDR register is FIFO buffer configuration"]
653    _1 = 1,
654}
655impl From<FM_A> for bool {
656    #[inline(always)]
657    fn from(variant: FM_A) -> Self {
658        variant as u8 != 0
659    }
660}
661impl FM_R {
662    #[doc = "Get enumerated values variant"]
663    #[inline(always)]
664    pub fn variant(&self) -> FM_A {
665        match self.bits {
666            false => FM_A::_0,
667            true => FM_A::_1,
668        }
669    }
670    #[doc = "Checks if the value of the field is `_0`"]
671    #[inline(always)]
672    pub fn is_0(&self) -> bool {
673        *self == FM_A::_0
674    }
675    #[doc = "Checks if the value of the field is `_1`"]
676    #[inline(always)]
677    pub fn is_1(&self) -> bool {
678        *self == FM_A::_1
679    }
680}
681#[doc = "Field `FM` writer - FIFO Mode select"]
682pub type FM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, FM_A, O>;
683impl<'a, const O: u8> FM_W<'a, O> {
684    #[doc = "TDR register, RDR register is non-FIFO buffer configuration"]
685    #[inline(always)]
686    pub fn _0(self) -> &'a mut W {
687        self.variant(FM_A::_0)
688    }
689    #[doc = "TDR register, RDR register is FIFO buffer configuration"]
690    #[inline(always)]
691    pub fn _1(self) -> &'a mut W {
692        self.variant(FM_A::_1)
693    }
694}
695#[doc = "Field `DEN` reader - Driver enable"]
696pub type DEN_R = crate::BitReader<DEN_A>;
697#[doc = "Driver enable\n\nValue on reset: 0"]
698#[derive(Clone, Copy, Debug, PartialEq, Eq)]
699pub enum DEN_A {
700    #[doc = "0: RS-485 Driver control function disable."]
701    _0 = 0,
702    #[doc = "1: RS-485 Driver control function enable."]
703    _1 = 1,
704}
705impl From<DEN_A> for bool {
706    #[inline(always)]
707    fn from(variant: DEN_A) -> Self {
708        variant as u8 != 0
709    }
710}
711impl DEN_R {
712    #[doc = "Get enumerated values variant"]
713    #[inline(always)]
714    pub fn variant(&self) -> DEN_A {
715        match self.bits {
716            false => DEN_A::_0,
717            true => DEN_A::_1,
718        }
719    }
720    #[doc = "Checks if the value of the field is `_0`"]
721    #[inline(always)]
722    pub fn is_0(&self) -> bool {
723        *self == DEN_A::_0
724    }
725    #[doc = "Checks if the value of the field is `_1`"]
726    #[inline(always)]
727    pub fn is_1(&self) -> bool {
728        *self == DEN_A::_1
729    }
730}
731#[doc = "Field `DEN` writer - Driver enable"]
732pub type DEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, DEN_A, O>;
733impl<'a, const O: u8> DEN_W<'a, O> {
734    #[doc = "RS-485 Driver control function disable."]
735    #[inline(always)]
736    pub fn _0(self) -> &'a mut W {
737        self.variant(DEN_A::_0)
738    }
739    #[doc = "RS-485 Driver control function enable."]
740    #[inline(always)]
741    pub fn _1(self) -> &'a mut W {
742        self.variant(DEN_A::_1)
743    }
744}
745#[doc = "Field `CKE` reader - Clock enable"]
746pub type CKE_R = crate::FieldReader<u8, CKE_A>;
747#[doc = "Clock enable\n\nValue on reset: 0"]
748#[derive(Clone, Copy, Debug, PartialEq, Eq)]
749#[repr(u8)]
750pub enum CKE_A {
751    #[doc = "0: In the case of Asynchronous modeOn-chip baud rate generatorThe SCKn pin is available for use as an I/O port in accord with the I/O port settings. In the case of Manchester mode and Simple LIN modeOn-chip baud rate generatorThe SCKn pin functions as I/O port. In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Output disabled (The SCKn pin is available for use as an I/O port in accord with the I/O port settings.) In the case of Smart card interface mode and CCR3.GM = 1Output fixed low"]
752    _00 = 0,
753    #[doc = "1: In the case of Asynchronous modeOn-chip baud rate generatorThe clock with the same frequency as the bit rate is output from the SCKn pin. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Clock output In the case of Smart card interface mode and CCR3.GM = 1Clock output"]
754    _01 = 1,
755    #[doc = "2: In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Output fixed high"]
756    _10 = 2,
757    #[doc = "3: In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Clock output"]
758    _11 = 3,
759}
760impl From<CKE_A> for u8 {
761    #[inline(always)]
762    fn from(variant: CKE_A) -> Self {
763        variant as _
764    }
765}
766impl CKE_R {
767    #[doc = "Get enumerated values variant"]
768    #[inline(always)]
769    pub fn variant(&self) -> CKE_A {
770        match self.bits {
771            0 => CKE_A::_00,
772            1 => CKE_A::_01,
773            2 => CKE_A::_10,
774            3 => CKE_A::_11,
775            _ => unreachable!(),
776        }
777    }
778    #[doc = "Checks if the value of the field is `_00`"]
779    #[inline(always)]
780    pub fn is_00(&self) -> bool {
781        *self == CKE_A::_00
782    }
783    #[doc = "Checks if the value of the field is `_01`"]
784    #[inline(always)]
785    pub fn is_01(&self) -> bool {
786        *self == CKE_A::_01
787    }
788    #[doc = "Checks if the value of the field is `_10`"]
789    #[inline(always)]
790    pub fn is_10(&self) -> bool {
791        *self == CKE_A::_10
792    }
793    #[doc = "Checks if the value of the field is `_11`"]
794    #[inline(always)]
795    pub fn is_11(&self) -> bool {
796        *self == CKE_A::_11
797    }
798}
799#[doc = "Field `CKE` writer - Clock enable"]
800pub type CKE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CCR3_SPEC, u8, CKE_A, 2, O>;
801impl<'a, const O: u8> CKE_W<'a, O> {
802    #[doc = "In the case of Asynchronous modeOn-chip baud rate generatorThe SCKn pin is available for use as an I/O port in accord with the I/O port settings. In the case of Manchester mode and Simple LIN modeOn-chip baud rate generatorThe SCKn pin functions as I/O port. In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Output disabled (The SCKn pin is available for use as an I/O port in accord with the I/O port settings.) In the case of Smart card interface mode and CCR3.GM = 1Output fixed low"]
803    #[inline(always)]
804    pub fn _00(self) -> &'a mut W {
805        self.variant(CKE_A::_00)
806    }
807    #[doc = "In the case of Asynchronous modeOn-chip baud rate generatorThe clock with the same frequency as the bit rate is output from the SCKn pin. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Clock output In the case of Smart card interface mode and CCR3.GM = 1Clock output"]
808    #[inline(always)]
809    pub fn _01(self) -> &'a mut W {
810        self.variant(CKE_A::_01)
811    }
812    #[doc = "In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Output fixed high"]
813    #[inline(always)]
814    pub fn _10(self) -> &'a mut W {
815        self.variant(CKE_A::_10)
816    }
817    #[doc = "In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Clock output"]
818    #[inline(always)]
819    pub fn _11(self) -> &'a mut W {
820        self.variant(CKE_A::_11)
821    }
822}
823#[doc = "Field `GM` reader - GSM Mode"]
824pub type GM_R = crate::BitReader<GM_A>;
825#[doc = "GSM Mode\n\nValue on reset: 0"]
826#[derive(Clone, Copy, Debug, PartialEq, Eq)]
827pub enum GM_A {
828    #[doc = "0: Non-GSM mode operation"]
829    _0 = 0,
830    #[doc = "1: GSM mode operation"]
831    _1 = 1,
832}
833impl From<GM_A> for bool {
834    #[inline(always)]
835    fn from(variant: GM_A) -> Self {
836        variant as u8 != 0
837    }
838}
839impl GM_R {
840    #[doc = "Get enumerated values variant"]
841    #[inline(always)]
842    pub fn variant(&self) -> GM_A {
843        match self.bits {
844            false => GM_A::_0,
845            true => GM_A::_1,
846        }
847    }
848    #[doc = "Checks if the value of the field is `_0`"]
849    #[inline(always)]
850    pub fn is_0(&self) -> bool {
851        *self == GM_A::_0
852    }
853    #[doc = "Checks if the value of the field is `_1`"]
854    #[inline(always)]
855    pub fn is_1(&self) -> bool {
856        *self == GM_A::_1
857    }
858}
859#[doc = "Field `GM` writer - GSM Mode"]
860pub type GM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, GM_A, O>;
861impl<'a, const O: u8> GM_W<'a, O> {
862    #[doc = "Non-GSM mode operation"]
863    #[inline(always)]
864    pub fn _0(self) -> &'a mut W {
865        self.variant(GM_A::_0)
866    }
867    #[doc = "GSM mode operation"]
868    #[inline(always)]
869    pub fn _1(self) -> &'a mut W {
870        self.variant(GM_A::_1)
871    }
872}
873#[doc = "Field `BLK` reader - Block Transfer Mode"]
874pub type BLK_R = crate::BitReader<BLK_A>;
875#[doc = "Block Transfer Mode\n\nValue on reset: 0"]
876#[derive(Clone, Copy, Debug, PartialEq, Eq)]
877pub enum BLK_A {
878    #[doc = "0: Non-block transfer mode operation"]
879    _0 = 0,
880    #[doc = "1: Block transfer mode operation"]
881    _1 = 1,
882}
883impl From<BLK_A> for bool {
884    #[inline(always)]
885    fn from(variant: BLK_A) -> Self {
886        variant as u8 != 0
887    }
888}
889impl BLK_R {
890    #[doc = "Get enumerated values variant"]
891    #[inline(always)]
892    pub fn variant(&self) -> BLK_A {
893        match self.bits {
894            false => BLK_A::_0,
895            true => BLK_A::_1,
896        }
897    }
898    #[doc = "Checks if the value of the field is `_0`"]
899    #[inline(always)]
900    pub fn is_0(&self) -> bool {
901        *self == BLK_A::_0
902    }
903    #[doc = "Checks if the value of the field is `_1`"]
904    #[inline(always)]
905    pub fn is_1(&self) -> bool {
906        *self == BLK_A::_1
907    }
908}
909#[doc = "Field `BLK` writer - Block Transfer Mode"]
910pub type BLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR3_SPEC, BLK_A, O>;
911impl<'a, const O: u8> BLK_W<'a, O> {
912    #[doc = "Non-block transfer mode operation"]
913    #[inline(always)]
914    pub fn _0(self) -> &'a mut W {
915        self.variant(BLK_A::_0)
916    }
917    #[doc = "Block transfer mode operation"]
918    #[inline(always)]
919    pub fn _1(self) -> &'a mut W {
920        self.variant(BLK_A::_1)
921    }
922}
923impl R {
924    #[doc = "Bit 0 - Clock Phase Select"]
925    #[inline(always)]
926    pub fn cpha(&self) -> CPHA_R {
927        CPHA_R::new((self.bits & 1) != 0)
928    }
929    #[doc = "Bit 1 - Clock Polarity Select"]
930    #[inline(always)]
931    pub fn cpol(&self) -> CPOL_R {
932        CPOL_R::new(((self.bits >> 1) & 1) != 0)
933    }
934    #[doc = "Bit 7 - Synchronizer bypass enable"]
935    #[inline(always)]
936    pub fn bpen(&self) -> BPEN_R {
937        BPEN_R::new(((self.bits >> 7) & 1) != 0)
938    }
939    #[doc = "Bits 8:9 - Character Length"]
940    #[inline(always)]
941    pub fn chr(&self) -> CHR_R {
942        CHR_R::new(((self.bits >> 8) & 3) as u8)
943    }
944    #[doc = "Bit 12 - LSB First select"]
945    #[inline(always)]
946    pub fn lsbf(&self) -> LSBF_R {
947        LSBF_R::new(((self.bits >> 12) & 1) != 0)
948    }
949    #[doc = "Bit 13 - Transmitted/Received Data Invert"]
950    #[inline(always)]
951    pub fn sinv(&self) -> SINV_R {
952        SINV_R::new(((self.bits >> 13) & 1) != 0)
953    }
954    #[doc = "Bit 14 - Stop Bit Length"]
955    #[inline(always)]
956    pub fn stp(&self) -> STP_R {
957        STP_R::new(((self.bits >> 14) & 1) != 0)
958    }
959    #[doc = "Bit 15 - Asynchronous Start Bit Edge Detection Select"]
960    #[inline(always)]
961    pub fn rxdesel(&self) -> RXDESEL_R {
962        RXDESEL_R::new(((self.bits >> 15) & 1) != 0)
963    }
964    #[doc = "Bits 16:18 - Communication mode select"]
965    #[inline(always)]
966    pub fn mod_(&self) -> MOD_R {
967        MOD_R::new(((self.bits >> 16) & 7) as u8)
968    }
969    #[doc = "Bit 19 - Multi-Processor Mode"]
970    #[inline(always)]
971    pub fn mp(&self) -> MP_R {
972        MP_R::new(((self.bits >> 19) & 1) != 0)
973    }
974    #[doc = "Bit 20 - FIFO Mode select"]
975    #[inline(always)]
976    pub fn fm(&self) -> FM_R {
977        FM_R::new(((self.bits >> 20) & 1) != 0)
978    }
979    #[doc = "Bit 21 - Driver enable"]
980    #[inline(always)]
981    pub fn den(&self) -> DEN_R {
982        DEN_R::new(((self.bits >> 21) & 1) != 0)
983    }
984    #[doc = "Bits 24:25 - Clock enable"]
985    #[inline(always)]
986    pub fn cke(&self) -> CKE_R {
987        CKE_R::new(((self.bits >> 24) & 3) as u8)
988    }
989    #[doc = "Bit 28 - GSM Mode"]
990    #[inline(always)]
991    pub fn gm(&self) -> GM_R {
992        GM_R::new(((self.bits >> 28) & 1) != 0)
993    }
994    #[doc = "Bit 29 - Block Transfer Mode"]
995    #[inline(always)]
996    pub fn blk(&self) -> BLK_R {
997        BLK_R::new(((self.bits >> 29) & 1) != 0)
998    }
999}
1000impl W {
1001    #[doc = "Bit 0 - Clock Phase Select"]
1002    #[inline(always)]
1003    #[must_use]
1004    pub fn cpha(&mut self) -> CPHA_W<0> {
1005        CPHA_W::new(self)
1006    }
1007    #[doc = "Bit 1 - Clock Polarity Select"]
1008    #[inline(always)]
1009    #[must_use]
1010    pub fn cpol(&mut self) -> CPOL_W<1> {
1011        CPOL_W::new(self)
1012    }
1013    #[doc = "Bit 7 - Synchronizer bypass enable"]
1014    #[inline(always)]
1015    #[must_use]
1016    pub fn bpen(&mut self) -> BPEN_W<7> {
1017        BPEN_W::new(self)
1018    }
1019    #[doc = "Bits 8:9 - Character Length"]
1020    #[inline(always)]
1021    #[must_use]
1022    pub fn chr(&mut self) -> CHR_W<8> {
1023        CHR_W::new(self)
1024    }
1025    #[doc = "Bit 12 - LSB First select"]
1026    #[inline(always)]
1027    #[must_use]
1028    pub fn lsbf(&mut self) -> LSBF_W<12> {
1029        LSBF_W::new(self)
1030    }
1031    #[doc = "Bit 13 - Transmitted/Received Data Invert"]
1032    #[inline(always)]
1033    #[must_use]
1034    pub fn sinv(&mut self) -> SINV_W<13> {
1035        SINV_W::new(self)
1036    }
1037    #[doc = "Bit 14 - Stop Bit Length"]
1038    #[inline(always)]
1039    #[must_use]
1040    pub fn stp(&mut self) -> STP_W<14> {
1041        STP_W::new(self)
1042    }
1043    #[doc = "Bit 15 - Asynchronous Start Bit Edge Detection Select"]
1044    #[inline(always)]
1045    #[must_use]
1046    pub fn rxdesel(&mut self) -> RXDESEL_W<15> {
1047        RXDESEL_W::new(self)
1048    }
1049    #[doc = "Bits 16:18 - Communication mode select"]
1050    #[inline(always)]
1051    #[must_use]
1052    pub fn mod_(&mut self) -> MOD_W<16> {
1053        MOD_W::new(self)
1054    }
1055    #[doc = "Bit 19 - Multi-Processor Mode"]
1056    #[inline(always)]
1057    #[must_use]
1058    pub fn mp(&mut self) -> MP_W<19> {
1059        MP_W::new(self)
1060    }
1061    #[doc = "Bit 20 - FIFO Mode select"]
1062    #[inline(always)]
1063    #[must_use]
1064    pub fn fm(&mut self) -> FM_W<20> {
1065        FM_W::new(self)
1066    }
1067    #[doc = "Bit 21 - Driver enable"]
1068    #[inline(always)]
1069    #[must_use]
1070    pub fn den(&mut self) -> DEN_W<21> {
1071        DEN_W::new(self)
1072    }
1073    #[doc = "Bits 24:25 - Clock enable"]
1074    #[inline(always)]
1075    #[must_use]
1076    pub fn cke(&mut self) -> CKE_W<24> {
1077        CKE_W::new(self)
1078    }
1079    #[doc = "Bit 28 - GSM Mode"]
1080    #[inline(always)]
1081    #[must_use]
1082    pub fn gm(&mut self) -> GM_W<28> {
1083        GM_W::new(self)
1084    }
1085    #[doc = "Bit 29 - Block Transfer Mode"]
1086    #[inline(always)]
1087    #[must_use]
1088    pub fn blk(&mut self) -> BLK_W<29> {
1089        BLK_W::new(self)
1090    }
1091    #[doc = "Writes raw bits to the register."]
1092    #[inline(always)]
1093    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1094        self.0.bits(bits);
1095        self
1096    }
1097}
1098#[doc = "Common Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr3](index.html) module"]
1099pub struct CCR3_SPEC;
1100impl crate::RegisterSpec for CCR3_SPEC {
1101    type Ux = u32;
1102}
1103#[doc = "`read()` method returns [ccr3::R](R) reader structure"]
1104impl crate::Readable for CCR3_SPEC {
1105    type Reader = R;
1106}
1107#[doc = "`write(|w| ..)` method takes [ccr3::W](W) writer structure"]
1108impl crate::Writable for CCR3_SPEC {
1109    type Writer = W;
1110    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1111    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1112}
1113#[doc = "`reset()` method sets CCR3 to value 0x1203"]
1114impl crate::Resettable for CCR3_SPEC {
1115    const RESET_VALUE: Self::Ux = 0x1203;
1116}
ra6t2/sci_b0/ccr3.rs

ra6t2/sci_b0/
ccr3.rs
