ra6t1/iic1/
icmr2.rs

1#[doc = "Register `ICMR2` reader"]
2pub struct R(crate::R<ICMR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ICMR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ICMR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ICMR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ICMR2` writer"]
17pub struct W(crate::W<ICMR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ICMR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ICMR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ICMR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TMOS` reader - Timeout Detection Time Selection"]
38pub type TMOS_R = crate::BitReader<TMOS_A>;
39#[doc = "Timeout Detection Time Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum TMOS_A {
42    #[doc = "0: Long mode is selected."]
43    _0 = 0,
44    #[doc = "1: Short mode is selected."]
45    _1 = 1,
46}
47impl From<TMOS_A> for bool {
48    #[inline(always)]
49    fn from(variant: TMOS_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl TMOS_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> TMOS_A {
57        match self.bits {
58            false => TMOS_A::_0,
59            true => TMOS_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == TMOS_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == TMOS_A::_1
71    }
72}
73#[doc = "Field `TMOS` writer - Timeout Detection Time Selection"]
74pub type TMOS_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICMR2_SPEC, TMOS_A, O>;
75impl<'a, const O: u8> TMOS_W<'a, O> {
76    #[doc = "Long mode is selected."]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(TMOS_A::_0)
80    }
81    #[doc = "Short mode is selected."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(TMOS_A::_1)
85    }
86}
87#[doc = "Field `TMOL` reader - Timeout L Count Control"]
88pub type TMOL_R = crate::BitReader<TMOL_A>;
89#[doc = "Timeout L Count Control\n\nValue on reset: 1"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum TMOL_A {
92    #[doc = "0: Count is disabled while the SCLn line is at a low level."]
93    _0 = 0,
94    #[doc = "1: Count is enabled while the SCLn line is at a low level."]
95    _1 = 1,
96}
97impl From<TMOL_A> for bool {
98    #[inline(always)]
99    fn from(variant: TMOL_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl TMOL_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> TMOL_A {
107        match self.bits {
108            false => TMOL_A::_0,
109            true => TMOL_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == TMOL_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == TMOL_A::_1
121    }
122}
123#[doc = "Field `TMOL` writer - Timeout L Count Control"]
124pub type TMOL_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICMR2_SPEC, TMOL_A, O>;
125impl<'a, const O: u8> TMOL_W<'a, O> {
126    #[doc = "Count is disabled while the SCLn line is at a low level."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(TMOL_A::_0)
130    }
131    #[doc = "Count is enabled while the SCLn line is at a low level."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(TMOL_A::_1)
135    }
136}
137#[doc = "Field `TMOH` reader - Timeout H Count Control"]
138pub type TMOH_R = crate::BitReader<TMOH_A>;
139#[doc = "Timeout H Count Control\n\nValue on reset: 1"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum TMOH_A {
142    #[doc = "0: Count is disabled while the SCLn line is at a high level."]
143    _0 = 0,
144    #[doc = "1: Count is enabled while the SCLn line is at a high level."]
145    _1 = 1,
146}
147impl From<TMOH_A> for bool {
148    #[inline(always)]
149    fn from(variant: TMOH_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl TMOH_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> TMOH_A {
157        match self.bits {
158            false => TMOH_A::_0,
159            true => TMOH_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == TMOH_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == TMOH_A::_1
171    }
172}
173#[doc = "Field `TMOH` writer - Timeout H Count Control"]
174pub type TMOH_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICMR2_SPEC, TMOH_A, O>;
175impl<'a, const O: u8> TMOH_W<'a, O> {
176    #[doc = "Count is disabled while the SCLn line is at a high level."]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(TMOH_A::_0)
180    }
181    #[doc = "Count is enabled while the SCLn line is at a high level."]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(TMOH_A::_1)
185    }
186}
187#[doc = "Field `SDDL` reader - SDA Output Delay Counter"]
188pub type SDDL_R = crate::FieldReader<u8, SDDL_A>;
189#[doc = "SDA Output Delay Counter\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191#[repr(u8)]
192pub enum SDDL_A {
193    #[doc = "0: No output delay"]
194    _000 = 0,
195    #[doc = "1: 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1)"]
196    _001 = 1,
197    #[doc = "2: 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
198    _010 = 2,
199    #[doc = "3: 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
200    _011 = 3,
201    #[doc = "4: 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
202    _100 = 4,
203    #[doc = "5: 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
204    _101 = 5,
205    #[doc = "6: 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
206    _110 = 6,
207    #[doc = "7: 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
208    _111 = 7,
209}
210impl From<SDDL_A> for u8 {
211    #[inline(always)]
212    fn from(variant: SDDL_A) -> Self {
213        variant as _
214    }
215}
216impl SDDL_R {
217    #[doc = "Get enumerated values variant"]
218    #[inline(always)]
219    pub fn variant(&self) -> SDDL_A {
220        match self.bits {
221            0 => SDDL_A::_000,
222            1 => SDDL_A::_001,
223            2 => SDDL_A::_010,
224            3 => SDDL_A::_011,
225            4 => SDDL_A::_100,
226            5 => SDDL_A::_101,
227            6 => SDDL_A::_110,
228            7 => SDDL_A::_111,
229            _ => unreachable!(),
230        }
231    }
232    #[doc = "Checks if the value of the field is `_000`"]
233    #[inline(always)]
234    pub fn is_000(&self) -> bool {
235        *self == SDDL_A::_000
236    }
237    #[doc = "Checks if the value of the field is `_001`"]
238    #[inline(always)]
239    pub fn is_001(&self) -> bool {
240        *self == SDDL_A::_001
241    }
242    #[doc = "Checks if the value of the field is `_010`"]
243    #[inline(always)]
244    pub fn is_010(&self) -> bool {
245        *self == SDDL_A::_010
246    }
247    #[doc = "Checks if the value of the field is `_011`"]
248    #[inline(always)]
249    pub fn is_011(&self) -> bool {
250        *self == SDDL_A::_011
251    }
252    #[doc = "Checks if the value of the field is `_100`"]
253    #[inline(always)]
254    pub fn is_100(&self) -> bool {
255        *self == SDDL_A::_100
256    }
257    #[doc = "Checks if the value of the field is `_101`"]
258    #[inline(always)]
259    pub fn is_101(&self) -> bool {
260        *self == SDDL_A::_101
261    }
262    #[doc = "Checks if the value of the field is `_110`"]
263    #[inline(always)]
264    pub fn is_110(&self) -> bool {
265        *self == SDDL_A::_110
266    }
267    #[doc = "Checks if the value of the field is `_111`"]
268    #[inline(always)]
269    pub fn is_111(&self) -> bool {
270        *self == SDDL_A::_111
271    }
272}
273#[doc = "Field `SDDL` writer - SDA Output Delay Counter"]
274pub type SDDL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, ICMR2_SPEC, u8, SDDL_A, 3, O>;
275impl<'a, const O: u8> SDDL_W<'a, O> {
276    #[doc = "No output delay"]
277    #[inline(always)]
278    pub fn _000(self) -> &'a mut W {
279        self.variant(SDDL_A::_000)
280    }
281    #[doc = "1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1)"]
282    #[inline(always)]
283    pub fn _001(self) -> &'a mut W {
284        self.variant(SDDL_A::_001)
285    }
286    #[doc = "2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
287    #[inline(always)]
288    pub fn _010(self) -> &'a mut W {
289        self.variant(SDDL_A::_010)
290    }
291    #[doc = "3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
292    #[inline(always)]
293    pub fn _011(self) -> &'a mut W {
294        self.variant(SDDL_A::_011)
295    }
296    #[doc = "4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
297    #[inline(always)]
298    pub fn _100(self) -> &'a mut W {
299        self.variant(SDDL_A::_100)
300    }
301    #[doc = "5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
302    #[inline(always)]
303    pub fn _101(self) -> &'a mut W {
304        self.variant(SDDL_A::_101)
305    }
306    #[doc = "6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
307    #[inline(always)]
308    pub fn _110(self) -> &'a mut W {
309        self.variant(SDDL_A::_110)
310    }
311    #[doc = "7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
312    #[inline(always)]
313    pub fn _111(self) -> &'a mut W {
314        self.variant(SDDL_A::_111)
315    }
316}
317#[doc = "Field `DLCS` reader - SDA Output Delay Clock Source Selection"]
318pub type DLCS_R = crate::BitReader<DLCS_A>;
319#[doc = "SDA Output Delay Clock Source Selection\n\nValue on reset: 0"]
320#[derive(Clone, Copy, Debug, PartialEq, Eq)]
321pub enum DLCS_A {
322    #[doc = "0: The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
323    _0 = 0,
324    #[doc = "1: The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
325    _1 = 1,
326}
327impl From<DLCS_A> for bool {
328    #[inline(always)]
329    fn from(variant: DLCS_A) -> Self {
330        variant as u8 != 0
331    }
332}
333impl DLCS_R {
334    #[doc = "Get enumerated values variant"]
335    #[inline(always)]
336    pub fn variant(&self) -> DLCS_A {
337        match self.bits {
338            false => DLCS_A::_0,
339            true => DLCS_A::_1,
340        }
341    }
342    #[doc = "Checks if the value of the field is `_0`"]
343    #[inline(always)]
344    pub fn is_0(&self) -> bool {
345        *self == DLCS_A::_0
346    }
347    #[doc = "Checks if the value of the field is `_1`"]
348    #[inline(always)]
349    pub fn is_1(&self) -> bool {
350        *self == DLCS_A::_1
351    }
352}
353#[doc = "Field `DLCS` writer - SDA Output Delay Clock Source Selection"]
354pub type DLCS_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICMR2_SPEC, DLCS_A, O>;
355impl<'a, const O: u8> DLCS_W<'a, O> {
356    #[doc = "The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
357    #[inline(always)]
358    pub fn _0(self) -> &'a mut W {
359        self.variant(DLCS_A::_0)
360    }
361    #[doc = "The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
362    #[inline(always)]
363    pub fn _1(self) -> &'a mut W {
364        self.variant(DLCS_A::_1)
365    }
366}
367impl R {
368    #[doc = "Bit 0 - Timeout Detection Time Selection"]
369    #[inline(always)]
370    pub fn tmos(&self) -> TMOS_R {
371        TMOS_R::new((self.bits & 1) != 0)
372    }
373    #[doc = "Bit 1 - Timeout L Count Control"]
374    #[inline(always)]
375    pub fn tmol(&self) -> TMOL_R {
376        TMOL_R::new(((self.bits >> 1) & 1) != 0)
377    }
378    #[doc = "Bit 2 - Timeout H Count Control"]
379    #[inline(always)]
380    pub fn tmoh(&self) -> TMOH_R {
381        TMOH_R::new(((self.bits >> 2) & 1) != 0)
382    }
383    #[doc = "Bits 4:6 - SDA Output Delay Counter"]
384    #[inline(always)]
385    pub fn sddl(&self) -> SDDL_R {
386        SDDL_R::new((self.bits >> 4) & 7)
387    }
388    #[doc = "Bit 7 - SDA Output Delay Clock Source Selection"]
389    #[inline(always)]
390    pub fn dlcs(&self) -> DLCS_R {
391        DLCS_R::new(((self.bits >> 7) & 1) != 0)
392    }
393}
394impl W {
395    #[doc = "Bit 0 - Timeout Detection Time Selection"]
396    #[inline(always)]
397    #[must_use]
398    pub fn tmos(&mut self) -> TMOS_W<0> {
399        TMOS_W::new(self)
400    }
401    #[doc = "Bit 1 - Timeout L Count Control"]
402    #[inline(always)]
403    #[must_use]
404    pub fn tmol(&mut self) -> TMOL_W<1> {
405        TMOL_W::new(self)
406    }
407    #[doc = "Bit 2 - Timeout H Count Control"]
408    #[inline(always)]
409    #[must_use]
410    pub fn tmoh(&mut self) -> TMOH_W<2> {
411        TMOH_W::new(self)
412    }
413    #[doc = "Bits 4:6 - SDA Output Delay Counter"]
414    #[inline(always)]
415    #[must_use]
416    pub fn sddl(&mut self) -> SDDL_W<4> {
417        SDDL_W::new(self)
418    }
419    #[doc = "Bit 7 - SDA Output Delay Clock Source Selection"]
420    #[inline(always)]
421    #[must_use]
422    pub fn dlcs(&mut self) -> DLCS_W<7> {
423        DLCS_W::new(self)
424    }
425    #[doc = "Writes raw bits to the register."]
426    #[inline(always)]
427    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
428        self.0.bits(bits);
429        self
430    }
431}
432#[doc = "I2C Bus Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icmr2](index.html) module"]
433pub struct ICMR2_SPEC;
434impl crate::RegisterSpec for ICMR2_SPEC {
435    type Ux = u8;
436}
437#[doc = "`read()` method returns [icmr2::R](R) reader structure"]
438impl crate::Readable for ICMR2_SPEC {
439    type Reader = R;
440}
441#[doc = "`write(|w| ..)` method takes [icmr2::W](W) writer structure"]
442impl crate::Writable for ICMR2_SPEC {
443    type Writer = W;
444    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
445    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
446}
447#[doc = "`reset()` method sets ICMR2 to value 0x06"]
448impl crate::Resettable for ICMR2_SPEC {
449    const RESET_VALUE: Self::Ux = 0x06;
450}
ra6t1/iic1/icmr2.rs

ra6t1/iic1/
icmr2.rs
