ra6m4/sci3/
scr_smci.rs

1#[doc = "Register `SCR_SMCI` reader"]
2pub struct R(crate::R<SCR_SMCI_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCR_SMCI_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCR_SMCI_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCR_SMCI_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCR_SMCI` writer"]
17pub struct W(crate::W<SCR_SMCI_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCR_SMCI_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCR_SMCI_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCR_SMCI_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CKE` reader - Clock Enable"]
38pub type CKE_R = crate::FieldReader<u8, CKE_A>;
39#[doc = "Clock Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CKE_A {
43    #[doc = "0: When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low"]
44    _00 = 0,
45    #[doc = "1: When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock"]
46    _01 = 1,
47    #[doc = "2: When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high"]
48    _10 = 2,
49    #[doc = "3: When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock"]
50    _11 = 3,
51}
52impl From<CKE_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CKE_A) -> Self {
55        variant as _
56    }
57}
58impl CKE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> CKE_A {
62        match self.bits {
63            0 => CKE_A::_00,
64            1 => CKE_A::_01,
65            2 => CKE_A::_10,
66            3 => CKE_A::_11,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_00`"]
71    #[inline(always)]
72    pub fn is_00(&self) -> bool {
73        *self == CKE_A::_00
74    }
75    #[doc = "Checks if the value of the field is `_01`"]
76    #[inline(always)]
77    pub fn is_01(&self) -> bool {
78        *self == CKE_A::_01
79    }
80    #[doc = "Checks if the value of the field is `_10`"]
81    #[inline(always)]
82    pub fn is_10(&self) -> bool {
83        *self == CKE_A::_10
84    }
85    #[doc = "Checks if the value of the field is `_11`"]
86    #[inline(always)]
87    pub fn is_11(&self) -> bool {
88        *self == CKE_A::_11
89    }
90}
91#[doc = "Field `CKE` writer - Clock Enable"]
92pub type CKE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, SCR_SMCI_SPEC, u8, CKE_A, 2, O>;
93impl<'a, const O: u8> CKE_W<'a, O> {
94    #[doc = "When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low"]
95    #[inline(always)]
96    pub fn _00(self) -> &'a mut W {
97        self.variant(CKE_A::_00)
98    }
99    #[doc = "When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock"]
100    #[inline(always)]
101    pub fn _01(self) -> &'a mut W {
102        self.variant(CKE_A::_01)
103    }
104    #[doc = "When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high"]
105    #[inline(always)]
106    pub fn _10(self) -> &'a mut W {
107        self.variant(CKE_A::_10)
108    }
109    #[doc = "When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock"]
110    #[inline(always)]
111    pub fn _11(self) -> &'a mut W {
112        self.variant(CKE_A::_11)
113    }
114}
115#[doc = "Field `TEIE` reader - Transmit End Interrupt Enable"]
116pub type TEIE_R = crate::BitReader<bool>;
117#[doc = "Field `TEIE` writer - Transmit End Interrupt Enable"]
118pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, bool, O>;
119#[doc = "Field `MPIE` reader - Multi-Processor Interrupt Enable"]
120pub type MPIE_R = crate::BitReader<bool>;
121#[doc = "Field `MPIE` writer - Multi-Processor Interrupt Enable"]
122pub type MPIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, bool, O>;
123#[doc = "Field `RE` reader - Receive Enable"]
124pub type RE_R = crate::BitReader<RE_A>;
125#[doc = "Receive Enable\n\nValue on reset: 0"]
126#[derive(Clone, Copy, Debug, PartialEq, Eq)]
127pub enum RE_A {
128    #[doc = "0: Disable serial reception"]
129    _0 = 0,
130    #[doc = "1: Enable serial reception"]
131    _1 = 1,
132}
133impl From<RE_A> for bool {
134    #[inline(always)]
135    fn from(variant: RE_A) -> Self {
136        variant as u8 != 0
137    }
138}
139impl RE_R {
140    #[doc = "Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> RE_A {
143        match self.bits {
144            false => RE_A::_0,
145            true => RE_A::_1,
146        }
147    }
148    #[doc = "Checks if the value of the field is `_0`"]
149    #[inline(always)]
150    pub fn is_0(&self) -> bool {
151        *self == RE_A::_0
152    }
153    #[doc = "Checks if the value of the field is `_1`"]
154    #[inline(always)]
155    pub fn is_1(&self) -> bool {
156        *self == RE_A::_1
157    }
158}
159#[doc = "Field `RE` writer - Receive Enable"]
160pub type RE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, RE_A, O>;
161impl<'a, const O: u8> RE_W<'a, O> {
162    #[doc = "Disable serial reception"]
163    #[inline(always)]
164    pub fn _0(self) -> &'a mut W {
165        self.variant(RE_A::_0)
166    }
167    #[doc = "Enable serial reception"]
168    #[inline(always)]
169    pub fn _1(self) -> &'a mut W {
170        self.variant(RE_A::_1)
171    }
172}
173#[doc = "Field `TE` reader - Transmit Enable"]
174pub type TE_R = crate::BitReader<TE_A>;
175#[doc = "Transmit Enable\n\nValue on reset: 0"]
176#[derive(Clone, Copy, Debug, PartialEq, Eq)]
177pub enum TE_A {
178    #[doc = "0: Disable serial transmission"]
179    _0 = 0,
180    #[doc = "1: Enable serial transmission"]
181    _1 = 1,
182}
183impl From<TE_A> for bool {
184    #[inline(always)]
185    fn from(variant: TE_A) -> Self {
186        variant as u8 != 0
187    }
188}
189impl TE_R {
190    #[doc = "Get enumerated values variant"]
191    #[inline(always)]
192    pub fn variant(&self) -> TE_A {
193        match self.bits {
194            false => TE_A::_0,
195            true => TE_A::_1,
196        }
197    }
198    #[doc = "Checks if the value of the field is `_0`"]
199    #[inline(always)]
200    pub fn is_0(&self) -> bool {
201        *self == TE_A::_0
202    }
203    #[doc = "Checks if the value of the field is `_1`"]
204    #[inline(always)]
205    pub fn is_1(&self) -> bool {
206        *self == TE_A::_1
207    }
208}
209#[doc = "Field `TE` writer - Transmit Enable"]
210pub type TE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, TE_A, O>;
211impl<'a, const O: u8> TE_W<'a, O> {
212    #[doc = "Disable serial transmission"]
213    #[inline(always)]
214    pub fn _0(self) -> &'a mut W {
215        self.variant(TE_A::_0)
216    }
217    #[doc = "Enable serial transmission"]
218    #[inline(always)]
219    pub fn _1(self) -> &'a mut W {
220        self.variant(TE_A::_1)
221    }
222}
223#[doc = "Field `RIE` reader - Receive Interrupt Enable"]
224pub type RIE_R = crate::BitReader<RIE_A>;
225#[doc = "Receive Interrupt Enable\n\nValue on reset: 0"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum RIE_A {
228    #[doc = "0: Disable SCIn_RXI and SCIn_ERI interrupt requests"]
229    _0 = 0,
230    #[doc = "1: Enable SCIn_RXI and SCIn_ERI interrupt requests"]
231    _1 = 1,
232}
233impl From<RIE_A> for bool {
234    #[inline(always)]
235    fn from(variant: RIE_A) -> Self {
236        variant as u8 != 0
237    }
238}
239impl RIE_R {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub fn variant(&self) -> RIE_A {
243        match self.bits {
244            false => RIE_A::_0,
245            true => RIE_A::_1,
246        }
247    }
248    #[doc = "Checks if the value of the field is `_0`"]
249    #[inline(always)]
250    pub fn is_0(&self) -> bool {
251        *self == RIE_A::_0
252    }
253    #[doc = "Checks if the value of the field is `_1`"]
254    #[inline(always)]
255    pub fn is_1(&self) -> bool {
256        *self == RIE_A::_1
257    }
258}
259#[doc = "Field `RIE` writer - Receive Interrupt Enable"]
260pub type RIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, RIE_A, O>;
261impl<'a, const O: u8> RIE_W<'a, O> {
262    #[doc = "Disable SCIn_RXI and SCIn_ERI interrupt requests"]
263    #[inline(always)]
264    pub fn _0(self) -> &'a mut W {
265        self.variant(RIE_A::_0)
266    }
267    #[doc = "Enable SCIn_RXI and SCIn_ERI interrupt requests"]
268    #[inline(always)]
269    pub fn _1(self) -> &'a mut W {
270        self.variant(RIE_A::_1)
271    }
272}
273#[doc = "Field `TIE` reader - Transmit Interrupt Enable"]
274pub type TIE_R = crate::BitReader<TIE_A>;
275#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"]
276#[derive(Clone, Copy, Debug, PartialEq, Eq)]
277pub enum TIE_A {
278    #[doc = "0: Disable SCIn_TXI interrupt requests"]
279    _0 = 0,
280    #[doc = "1: Enable SCIn_TXI interrupt requests"]
281    _1 = 1,
282}
283impl From<TIE_A> for bool {
284    #[inline(always)]
285    fn from(variant: TIE_A) -> Self {
286        variant as u8 != 0
287    }
288}
289impl TIE_R {
290    #[doc = "Get enumerated values variant"]
291    #[inline(always)]
292    pub fn variant(&self) -> TIE_A {
293        match self.bits {
294            false => TIE_A::_0,
295            true => TIE_A::_1,
296        }
297    }
298    #[doc = "Checks if the value of the field is `_0`"]
299    #[inline(always)]
300    pub fn is_0(&self) -> bool {
301        *self == TIE_A::_0
302    }
303    #[doc = "Checks if the value of the field is `_1`"]
304    #[inline(always)]
305    pub fn is_1(&self) -> bool {
306        *self == TIE_A::_1
307    }
308}
309#[doc = "Field `TIE` writer - Transmit Interrupt Enable"]
310pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SMCI_SPEC, TIE_A, O>;
311impl<'a, const O: u8> TIE_W<'a, O> {
312    #[doc = "Disable SCIn_TXI interrupt requests"]
313    #[inline(always)]
314    pub fn _0(self) -> &'a mut W {
315        self.variant(TIE_A::_0)
316    }
317    #[doc = "Enable SCIn_TXI interrupt requests"]
318    #[inline(always)]
319    pub fn _1(self) -> &'a mut W {
320        self.variant(TIE_A::_1)
321    }
322}
323impl R {
324    #[doc = "Bits 0:1 - Clock Enable"]
325    #[inline(always)]
326    pub fn cke(&self) -> CKE_R {
327        CKE_R::new(self.bits & 3)
328    }
329    #[doc = "Bit 2 - Transmit End Interrupt Enable"]
330    #[inline(always)]
331    pub fn teie(&self) -> TEIE_R {
332        TEIE_R::new(((self.bits >> 2) & 1) != 0)
333    }
334    #[doc = "Bit 3 - Multi-Processor Interrupt Enable"]
335    #[inline(always)]
336    pub fn mpie(&self) -> MPIE_R {
337        MPIE_R::new(((self.bits >> 3) & 1) != 0)
338    }
339    #[doc = "Bit 4 - Receive Enable"]
340    #[inline(always)]
341    pub fn re(&self) -> RE_R {
342        RE_R::new(((self.bits >> 4) & 1) != 0)
343    }
344    #[doc = "Bit 5 - Transmit Enable"]
345    #[inline(always)]
346    pub fn te(&self) -> TE_R {
347        TE_R::new(((self.bits >> 5) & 1) != 0)
348    }
349    #[doc = "Bit 6 - Receive Interrupt Enable"]
350    #[inline(always)]
351    pub fn rie(&self) -> RIE_R {
352        RIE_R::new(((self.bits >> 6) & 1) != 0)
353    }
354    #[doc = "Bit 7 - Transmit Interrupt Enable"]
355    #[inline(always)]
356    pub fn tie(&self) -> TIE_R {
357        TIE_R::new(((self.bits >> 7) & 1) != 0)
358    }
359}
360impl W {
361    #[doc = "Bits 0:1 - Clock Enable"]
362    #[inline(always)]
363    #[must_use]
364    pub fn cke(&mut self) -> CKE_W<0> {
365        CKE_W::new(self)
366    }
367    #[doc = "Bit 2 - Transmit End Interrupt Enable"]
368    #[inline(always)]
369    #[must_use]
370    pub fn teie(&mut self) -> TEIE_W<2> {
371        TEIE_W::new(self)
372    }
373    #[doc = "Bit 3 - Multi-Processor Interrupt Enable"]
374    #[inline(always)]
375    #[must_use]
376    pub fn mpie(&mut self) -> MPIE_W<3> {
377        MPIE_W::new(self)
378    }
379    #[doc = "Bit 4 - Receive Enable"]
380    #[inline(always)]
381    #[must_use]
382    pub fn re(&mut self) -> RE_W<4> {
383        RE_W::new(self)
384    }
385    #[doc = "Bit 5 - Transmit Enable"]
386    #[inline(always)]
387    #[must_use]
388    pub fn te(&mut self) -> TE_W<5> {
389        TE_W::new(self)
390    }
391    #[doc = "Bit 6 - Receive Interrupt Enable"]
392    #[inline(always)]
393    #[must_use]
394    pub fn rie(&mut self) -> RIE_W<6> {
395        RIE_W::new(self)
396    }
397    #[doc = "Bit 7 - Transmit Interrupt Enable"]
398    #[inline(always)]
399    #[must_use]
400    pub fn tie(&mut self) -> TIE_W<7> {
401        TIE_W::new(self)
402    }
403    #[doc = "Writes raw bits to the register."]
404    #[inline(always)]
405    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
406        self.0.bits(bits);
407        self
408    }
409}
410#[doc = "Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr_smci](index.html) module"]
411pub struct SCR_SMCI_SPEC;
412impl crate::RegisterSpec for SCR_SMCI_SPEC {
413    type Ux = u8;
414}
415#[doc = "`read()` method returns [scr_smci::R](R) reader structure"]
416impl crate::Readable for SCR_SMCI_SPEC {
417    type Reader = R;
418}
419#[doc = "`write(|w| ..)` method takes [scr_smci::W](W) writer structure"]
420impl crate::Writable for SCR_SMCI_SPEC {
421    type Writer = W;
422    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
423    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
424}
425#[doc = "`reset()` method sets SCR_SMCI to value 0"]
426impl crate::Resettable for SCR_SMCI_SPEC {
427    const RESET_VALUE: Self::Ux = 0;
428}
ra6m4/sci3/scr_smci.rs

ra6m4/sci3/
scr_smci.rs
