ra6m4/sci3/
scr.rs

1#[doc = "Register `SCR` reader"]
2pub struct R(crate::R<SCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCR` writer"]
17pub struct W(crate::W<SCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CKE` reader - Clock Enable"]
38pub type CKE_R = crate::FieldReader<u8, CKE_A>;
39#[doc = "Clock Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CKE_A {
43    #[doc = "0: In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
44    _00 = 0,
45    #[doc = "1: In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
46    _01 = 1,
47}
48impl From<CKE_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CKE_A) -> Self {
51        variant as _
52    }
53}
54impl CKE_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<CKE_A> {
58        match self.bits {
59            0 => Some(CKE_A::_00),
60            1 => Some(CKE_A::_01),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `_00`"]
65    #[inline(always)]
66    pub fn is_00(&self) -> bool {
67        *self == CKE_A::_00
68    }
69    #[doc = "Checks if the value of the field is `_01`"]
70    #[inline(always)]
71    pub fn is_01(&self) -> bool {
72        *self == CKE_A::_01
73    }
74}
75#[doc = "Field `CKE` writer - Clock Enable"]
76pub type CKE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, SCR_SPEC, u8, CKE_A, 2, O>;
77impl<'a, const O: u8> CKE_W<'a, O> {
78    #[doc = "In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
79    #[inline(always)]
80    pub fn _00(self) -> &'a mut W {
81        self.variant(CKE_A::_00)
82    }
83    #[doc = "In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
84    #[inline(always)]
85    pub fn _01(self) -> &'a mut W {
86        self.variant(CKE_A::_01)
87    }
88}
89#[doc = "Field `TEIE` reader - Transmit End Interrupt Enable"]
90pub type TEIE_R = crate::BitReader<TEIE_A>;
91#[doc = "Transmit End Interrupt Enable\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum TEIE_A {
94    #[doc = "0: Disable SCIn_TEI interrupt requests"]
95    _0 = 0,
96    #[doc = "1: Enable SCIn_TEI interrupt requests"]
97    _1 = 1,
98}
99impl From<TEIE_A> for bool {
100    #[inline(always)]
101    fn from(variant: TEIE_A) -> Self {
102        variant as u8 != 0
103    }
104}
105impl TEIE_R {
106    #[doc = "Get enumerated values variant"]
107    #[inline(always)]
108    pub fn variant(&self) -> TEIE_A {
109        match self.bits {
110            false => TEIE_A::_0,
111            true => TEIE_A::_1,
112        }
113    }
114    #[doc = "Checks if the value of the field is `_0`"]
115    #[inline(always)]
116    pub fn is_0(&self) -> bool {
117        *self == TEIE_A::_0
118    }
119    #[doc = "Checks if the value of the field is `_1`"]
120    #[inline(always)]
121    pub fn is_1(&self) -> bool {
122        *self == TEIE_A::_1
123    }
124}
125#[doc = "Field `TEIE` writer - Transmit End Interrupt Enable"]
126pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, TEIE_A, O>;
127impl<'a, const O: u8> TEIE_W<'a, O> {
128    #[doc = "Disable SCIn_TEI interrupt requests"]
129    #[inline(always)]
130    pub fn _0(self) -> &'a mut W {
131        self.variant(TEIE_A::_0)
132    }
133    #[doc = "Enable SCIn_TEI interrupt requests"]
134    #[inline(always)]
135    pub fn _1(self) -> &'a mut W {
136        self.variant(TEIE_A::_1)
137    }
138}
139#[doc = "Field `MPIE` reader - Multi-Processor Interrupt Enable"]
140pub type MPIE_R = crate::BitReader<MPIE_A>;
141#[doc = "Multi-Processor Interrupt Enable\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum MPIE_A {
144    #[doc = "0: Normal reception"]
145    _0 = 0,
146    #[doc = "1: When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed."]
147    _1 = 1,
148}
149impl From<MPIE_A> for bool {
150    #[inline(always)]
151    fn from(variant: MPIE_A) -> Self {
152        variant as u8 != 0
153    }
154}
155impl MPIE_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> MPIE_A {
159        match self.bits {
160            false => MPIE_A::_0,
161            true => MPIE_A::_1,
162        }
163    }
164    #[doc = "Checks if the value of the field is `_0`"]
165    #[inline(always)]
166    pub fn is_0(&self) -> bool {
167        *self == MPIE_A::_0
168    }
169    #[doc = "Checks if the value of the field is `_1`"]
170    #[inline(always)]
171    pub fn is_1(&self) -> bool {
172        *self == MPIE_A::_1
173    }
174}
175#[doc = "Field `MPIE` writer - Multi-Processor Interrupt Enable"]
176pub type MPIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, MPIE_A, O>;
177impl<'a, const O: u8> MPIE_W<'a, O> {
178    #[doc = "Normal reception"]
179    #[inline(always)]
180    pub fn _0(self) -> &'a mut W {
181        self.variant(MPIE_A::_0)
182    }
183    #[doc = "When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed."]
184    #[inline(always)]
185    pub fn _1(self) -> &'a mut W {
186        self.variant(MPIE_A::_1)
187    }
188}
189#[doc = "Field `RE` reader - Receive Enable"]
190pub type RE_R = crate::BitReader<RE_A>;
191#[doc = "Receive Enable\n\nValue on reset: 0"]
192#[derive(Clone, Copy, Debug, PartialEq, Eq)]
193pub enum RE_A {
194    #[doc = "0: Disable serial reception"]
195    _0 = 0,
196    #[doc = "1: Enable serial reception"]
197    _1 = 1,
198}
199impl From<RE_A> for bool {
200    #[inline(always)]
201    fn from(variant: RE_A) -> Self {
202        variant as u8 != 0
203    }
204}
205impl RE_R {
206    #[doc = "Get enumerated values variant"]
207    #[inline(always)]
208    pub fn variant(&self) -> RE_A {
209        match self.bits {
210            false => RE_A::_0,
211            true => RE_A::_1,
212        }
213    }
214    #[doc = "Checks if the value of the field is `_0`"]
215    #[inline(always)]
216    pub fn is_0(&self) -> bool {
217        *self == RE_A::_0
218    }
219    #[doc = "Checks if the value of the field is `_1`"]
220    #[inline(always)]
221    pub fn is_1(&self) -> bool {
222        *self == RE_A::_1
223    }
224}
225#[doc = "Field `RE` writer - Receive Enable"]
226pub type RE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, RE_A, O>;
227impl<'a, const O: u8> RE_W<'a, O> {
228    #[doc = "Disable serial reception"]
229    #[inline(always)]
230    pub fn _0(self) -> &'a mut W {
231        self.variant(RE_A::_0)
232    }
233    #[doc = "Enable serial reception"]
234    #[inline(always)]
235    pub fn _1(self) -> &'a mut W {
236        self.variant(RE_A::_1)
237    }
238}
239#[doc = "Field `TE` reader - Transmit Enable"]
240pub type TE_R = crate::BitReader<TE_A>;
241#[doc = "Transmit Enable\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243pub enum TE_A {
244    #[doc = "0: Disable serial transmission"]
245    _0 = 0,
246    #[doc = "1: Enable serial transmission"]
247    _1 = 1,
248}
249impl From<TE_A> for bool {
250    #[inline(always)]
251    fn from(variant: TE_A) -> Self {
252        variant as u8 != 0
253    }
254}
255impl TE_R {
256    #[doc = "Get enumerated values variant"]
257    #[inline(always)]
258    pub fn variant(&self) -> TE_A {
259        match self.bits {
260            false => TE_A::_0,
261            true => TE_A::_1,
262        }
263    }
264    #[doc = "Checks if the value of the field is `_0`"]
265    #[inline(always)]
266    pub fn is_0(&self) -> bool {
267        *self == TE_A::_0
268    }
269    #[doc = "Checks if the value of the field is `_1`"]
270    #[inline(always)]
271    pub fn is_1(&self) -> bool {
272        *self == TE_A::_1
273    }
274}
275#[doc = "Field `TE` writer - Transmit Enable"]
276pub type TE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, TE_A, O>;
277impl<'a, const O: u8> TE_W<'a, O> {
278    #[doc = "Disable serial transmission"]
279    #[inline(always)]
280    pub fn _0(self) -> &'a mut W {
281        self.variant(TE_A::_0)
282    }
283    #[doc = "Enable serial transmission"]
284    #[inline(always)]
285    pub fn _1(self) -> &'a mut W {
286        self.variant(TE_A::_1)
287    }
288}
289#[doc = "Field `RIE` reader - Receive Interrupt Enable"]
290pub type RIE_R = crate::BitReader<RIE_A>;
291#[doc = "Receive Interrupt Enable\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum RIE_A {
294    #[doc = "0: Disable SCIn_RXI and SCIn_ERI interrupt requests"]
295    _0 = 0,
296    #[doc = "1: Enable SCIn_RXI and SCIn_ERI interrupt requests"]
297    _1 = 1,
298}
299impl From<RIE_A> for bool {
300    #[inline(always)]
301    fn from(variant: RIE_A) -> Self {
302        variant as u8 != 0
303    }
304}
305impl RIE_R {
306    #[doc = "Get enumerated values variant"]
307    #[inline(always)]
308    pub fn variant(&self) -> RIE_A {
309        match self.bits {
310            false => RIE_A::_0,
311            true => RIE_A::_1,
312        }
313    }
314    #[doc = "Checks if the value of the field is `_0`"]
315    #[inline(always)]
316    pub fn is_0(&self) -> bool {
317        *self == RIE_A::_0
318    }
319    #[doc = "Checks if the value of the field is `_1`"]
320    #[inline(always)]
321    pub fn is_1(&self) -> bool {
322        *self == RIE_A::_1
323    }
324}
325#[doc = "Field `RIE` writer - Receive Interrupt Enable"]
326pub type RIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, RIE_A, O>;
327impl<'a, const O: u8> RIE_W<'a, O> {
328    #[doc = "Disable SCIn_RXI and SCIn_ERI interrupt requests"]
329    #[inline(always)]
330    pub fn _0(self) -> &'a mut W {
331        self.variant(RIE_A::_0)
332    }
333    #[doc = "Enable SCIn_RXI and SCIn_ERI interrupt requests"]
334    #[inline(always)]
335    pub fn _1(self) -> &'a mut W {
336        self.variant(RIE_A::_1)
337    }
338}
339#[doc = "Field `TIE` reader - Transmit Interrupt Enable"]
340pub type TIE_R = crate::BitReader<TIE_A>;
341#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"]
342#[derive(Clone, Copy, Debug, PartialEq, Eq)]
343pub enum TIE_A {
344    #[doc = "0: Disable SCIn_TXI interrupt requests"]
345    _0 = 0,
346    #[doc = "1: Enable SCIn_TXI interrupt requests"]
347    _1 = 1,
348}
349impl From<TIE_A> for bool {
350    #[inline(always)]
351    fn from(variant: TIE_A) -> Self {
352        variant as u8 != 0
353    }
354}
355impl TIE_R {
356    #[doc = "Get enumerated values variant"]
357    #[inline(always)]
358    pub fn variant(&self) -> TIE_A {
359        match self.bits {
360            false => TIE_A::_0,
361            true => TIE_A::_1,
362        }
363    }
364    #[doc = "Checks if the value of the field is `_0`"]
365    #[inline(always)]
366    pub fn is_0(&self) -> bool {
367        *self == TIE_A::_0
368    }
369    #[doc = "Checks if the value of the field is `_1`"]
370    #[inline(always)]
371    pub fn is_1(&self) -> bool {
372        *self == TIE_A::_1
373    }
374}
375#[doc = "Field `TIE` writer - Transmit Interrupt Enable"]
376pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SCR_SPEC, TIE_A, O>;
377impl<'a, const O: u8> TIE_W<'a, O> {
378    #[doc = "Disable SCIn_TXI interrupt requests"]
379    #[inline(always)]
380    pub fn _0(self) -> &'a mut W {
381        self.variant(TIE_A::_0)
382    }
383    #[doc = "Enable SCIn_TXI interrupt requests"]
384    #[inline(always)]
385    pub fn _1(self) -> &'a mut W {
386        self.variant(TIE_A::_1)
387    }
388}
389impl R {
390    #[doc = "Bits 0:1 - Clock Enable"]
391    #[inline(always)]
392    pub fn cke(&self) -> CKE_R {
393        CKE_R::new(self.bits & 3)
394    }
395    #[doc = "Bit 2 - Transmit End Interrupt Enable"]
396    #[inline(always)]
397    pub fn teie(&self) -> TEIE_R {
398        TEIE_R::new(((self.bits >> 2) & 1) != 0)
399    }
400    #[doc = "Bit 3 - Multi-Processor Interrupt Enable"]
401    #[inline(always)]
402    pub fn mpie(&self) -> MPIE_R {
403        MPIE_R::new(((self.bits >> 3) & 1) != 0)
404    }
405    #[doc = "Bit 4 - Receive Enable"]
406    #[inline(always)]
407    pub fn re(&self) -> RE_R {
408        RE_R::new(((self.bits >> 4) & 1) != 0)
409    }
410    #[doc = "Bit 5 - Transmit Enable"]
411    #[inline(always)]
412    pub fn te(&self) -> TE_R {
413        TE_R::new(((self.bits >> 5) & 1) != 0)
414    }
415    #[doc = "Bit 6 - Receive Interrupt Enable"]
416    #[inline(always)]
417    pub fn rie(&self) -> RIE_R {
418        RIE_R::new(((self.bits >> 6) & 1) != 0)
419    }
420    #[doc = "Bit 7 - Transmit Interrupt Enable"]
421    #[inline(always)]
422    pub fn tie(&self) -> TIE_R {
423        TIE_R::new(((self.bits >> 7) & 1) != 0)
424    }
425}
426impl W {
427    #[doc = "Bits 0:1 - Clock Enable"]
428    #[inline(always)]
429    #[must_use]
430    pub fn cke(&mut self) -> CKE_W<0> {
431        CKE_W::new(self)
432    }
433    #[doc = "Bit 2 - Transmit End Interrupt Enable"]
434    #[inline(always)]
435    #[must_use]
436    pub fn teie(&mut self) -> TEIE_W<2> {
437        TEIE_W::new(self)
438    }
439    #[doc = "Bit 3 - Multi-Processor Interrupt Enable"]
440    #[inline(always)]
441    #[must_use]
442    pub fn mpie(&mut self) -> MPIE_W<3> {
443        MPIE_W::new(self)
444    }
445    #[doc = "Bit 4 - Receive Enable"]
446    #[inline(always)]
447    #[must_use]
448    pub fn re(&mut self) -> RE_W<4> {
449        RE_W::new(self)
450    }
451    #[doc = "Bit 5 - Transmit Enable"]
452    #[inline(always)]
453    #[must_use]
454    pub fn te(&mut self) -> TE_W<5> {
455        TE_W::new(self)
456    }
457    #[doc = "Bit 6 - Receive Interrupt Enable"]
458    #[inline(always)]
459    #[must_use]
460    pub fn rie(&mut self) -> RIE_W<6> {
461        RIE_W::new(self)
462    }
463    #[doc = "Bit 7 - Transmit Interrupt Enable"]
464    #[inline(always)]
465    #[must_use]
466    pub fn tie(&mut self) -> TIE_W<7> {
467        TIE_W::new(self)
468    }
469    #[doc = "Writes raw bits to the register."]
470    #[inline(always)]
471    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
472        self.0.bits(bits);
473        self
474    }
475}
476#[doc = "Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"]
477pub struct SCR_SPEC;
478impl crate::RegisterSpec for SCR_SPEC {
479    type Ux = u8;
480}
481#[doc = "`read()` method returns [scr::R](R) reader structure"]
482impl crate::Readable for SCR_SPEC {
483    type Reader = R;
484}
485#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"]
486impl crate::Writable for SCR_SPEC {
487    type Writer = W;
488    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
489    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
490}
491#[doc = "`reset()` method sets SCR to value 0"]
492impl crate::Resettable for SCR_SPEC {
493    const RESET_VALUE: Self::Ux = 0;
494}
ra6m4/sci3/scr.rs

ra6m4/sci3/
scr.rs
