ra6m3/usbhs/
d0fifosel.rs

1#[doc = "Register `D0FIFOSEL` reader"]
2pub struct R(crate::R<D0FIFOSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<D0FIFOSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<D0FIFOSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<D0FIFOSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `D0FIFOSEL` writer"]
17pub struct W(crate::W<D0FIFOSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<D0FIFOSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<D0FIFOSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<D0FIFOSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CURPIPE` reader - FIFO Port Access Pipe Specification"]
38pub type CURPIPE_R = crate::FieldReader<u8, CURPIPE_A>;
39#[doc = "FIFO Port Access Pipe Specification\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CURPIPE_A {
43    #[doc = "0: No pipe specified"]
44    _0000 = 0,
45    #[doc = "1: Pipe1"]
46    _0001 = 1,
47    #[doc = "2: Pipe 2"]
48    _0010 = 2,
49    #[doc = "3: Pipe 3"]
50    _0011 = 3,
51    #[doc = "4: Pipe 4"]
52    _0100 = 4,
53    #[doc = "5: Pipe 5"]
54    _0101 = 5,
55    #[doc = "6: Pipe 6"]
56    _0110 = 6,
57    #[doc = "7: Pipe 7"]
58    _0111 = 7,
59    #[doc = "8: Pipe 8"]
60    _1000 = 8,
61    #[doc = "9: Pipe 9"]
62    _1001 = 9,
63}
64impl From<CURPIPE_A> for u8 {
65    #[inline(always)]
66    fn from(variant: CURPIPE_A) -> Self {
67        variant as _
68    }
69}
70impl CURPIPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<CURPIPE_A> {
74        match self.bits {
75            0 => Some(CURPIPE_A::_0000),
76            1 => Some(CURPIPE_A::_0001),
77            2 => Some(CURPIPE_A::_0010),
78            3 => Some(CURPIPE_A::_0011),
79            4 => Some(CURPIPE_A::_0100),
80            5 => Some(CURPIPE_A::_0101),
81            6 => Some(CURPIPE_A::_0110),
82            7 => Some(CURPIPE_A::_0111),
83            8 => Some(CURPIPE_A::_1000),
84            9 => Some(CURPIPE_A::_1001),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `_0000`"]
89    #[inline(always)]
90    pub fn is_0000(&self) -> bool {
91        *self == CURPIPE_A::_0000
92    }
93    #[doc = "Checks if the value of the field is `_0001`"]
94    #[inline(always)]
95    pub fn is_0001(&self) -> bool {
96        *self == CURPIPE_A::_0001
97    }
98    #[doc = "Checks if the value of the field is `_0010`"]
99    #[inline(always)]
100    pub fn is_0010(&self) -> bool {
101        *self == CURPIPE_A::_0010
102    }
103    #[doc = "Checks if the value of the field is `_0011`"]
104    #[inline(always)]
105    pub fn is_0011(&self) -> bool {
106        *self == CURPIPE_A::_0011
107    }
108    #[doc = "Checks if the value of the field is `_0100`"]
109    #[inline(always)]
110    pub fn is_0100(&self) -> bool {
111        *self == CURPIPE_A::_0100
112    }
113    #[doc = "Checks if the value of the field is `_0101`"]
114    #[inline(always)]
115    pub fn is_0101(&self) -> bool {
116        *self == CURPIPE_A::_0101
117    }
118    #[doc = "Checks if the value of the field is `_0110`"]
119    #[inline(always)]
120    pub fn is_0110(&self) -> bool {
121        *self == CURPIPE_A::_0110
122    }
123    #[doc = "Checks if the value of the field is `_0111`"]
124    #[inline(always)]
125    pub fn is_0111(&self) -> bool {
126        *self == CURPIPE_A::_0111
127    }
128    #[doc = "Checks if the value of the field is `_1000`"]
129    #[inline(always)]
130    pub fn is_1000(&self) -> bool {
131        *self == CURPIPE_A::_1000
132    }
133    #[doc = "Checks if the value of the field is `_1001`"]
134    #[inline(always)]
135    pub fn is_1001(&self) -> bool {
136        *self == CURPIPE_A::_1001
137    }
138}
139#[doc = "Field `CURPIPE` writer - FIFO Port Access Pipe Specification"]
140pub type CURPIPE_W<'a, const O: u8> =
141    crate::FieldWriter<'a, u16, D0FIFOSEL_SPEC, u8, CURPIPE_A, 4, O>;
142impl<'a, const O: u8> CURPIPE_W<'a, O> {
143    #[doc = "No pipe specified"]
144    #[inline(always)]
145    pub fn _0000(self) -> &'a mut W {
146        self.variant(CURPIPE_A::_0000)
147    }
148    #[doc = "Pipe1"]
149    #[inline(always)]
150    pub fn _0001(self) -> &'a mut W {
151        self.variant(CURPIPE_A::_0001)
152    }
153    #[doc = "Pipe 2"]
154    #[inline(always)]
155    pub fn _0010(self) -> &'a mut W {
156        self.variant(CURPIPE_A::_0010)
157    }
158    #[doc = "Pipe 3"]
159    #[inline(always)]
160    pub fn _0011(self) -> &'a mut W {
161        self.variant(CURPIPE_A::_0011)
162    }
163    #[doc = "Pipe 4"]
164    #[inline(always)]
165    pub fn _0100(self) -> &'a mut W {
166        self.variant(CURPIPE_A::_0100)
167    }
168    #[doc = "Pipe 5"]
169    #[inline(always)]
170    pub fn _0101(self) -> &'a mut W {
171        self.variant(CURPIPE_A::_0101)
172    }
173    #[doc = "Pipe 6"]
174    #[inline(always)]
175    pub fn _0110(self) -> &'a mut W {
176        self.variant(CURPIPE_A::_0110)
177    }
178    #[doc = "Pipe 7"]
179    #[inline(always)]
180    pub fn _0111(self) -> &'a mut W {
181        self.variant(CURPIPE_A::_0111)
182    }
183    #[doc = "Pipe 8"]
184    #[inline(always)]
185    pub fn _1000(self) -> &'a mut W {
186        self.variant(CURPIPE_A::_1000)
187    }
188    #[doc = "Pipe 9"]
189    #[inline(always)]
190    pub fn _1001(self) -> &'a mut W {
191        self.variant(CURPIPE_A::_1001)
192    }
193}
194#[doc = "Field `BIGEND` reader - FIFO Port Endian Control"]
195pub type BIGEND_R = crate::BitReader<BIGEND_A>;
196#[doc = "FIFO Port Endian Control\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum BIGEND_A {
199    #[doc = "0: Little endian"]
200    _0 = 0,
201    #[doc = "1: Big endian"]
202    _1 = 1,
203}
204impl From<BIGEND_A> for bool {
205    #[inline(always)]
206    fn from(variant: BIGEND_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl BIGEND_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> BIGEND_A {
214        match self.bits {
215            false => BIGEND_A::_0,
216            true => BIGEND_A::_1,
217        }
218    }
219    #[doc = "Checks if the value of the field is `_0`"]
220    #[inline(always)]
221    pub fn is_0(&self) -> bool {
222        *self == BIGEND_A::_0
223    }
224    #[doc = "Checks if the value of the field is `_1`"]
225    #[inline(always)]
226    pub fn is_1(&self) -> bool {
227        *self == BIGEND_A::_1
228    }
229}
230#[doc = "Field `BIGEND` writer - FIFO Port Endian Control"]
231pub type BIGEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, D0FIFOSEL_SPEC, BIGEND_A, O>;
232impl<'a, const O: u8> BIGEND_W<'a, O> {
233    #[doc = "Little endian"]
234    #[inline(always)]
235    pub fn _0(self) -> &'a mut W {
236        self.variant(BIGEND_A::_0)
237    }
238    #[doc = "Big endian"]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut W {
241        self.variant(BIGEND_A::_1)
242    }
243}
244#[doc = "Field `MBW` reader - FIFO Port Access Bit Width"]
245pub type MBW_R = crate::FieldReader<u8, MBW_A>;
246#[doc = "FIFO Port Access Bit Width\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248#[repr(u8)]
249pub enum MBW_A {
250    #[doc = "0: 8-bit width"]
251    _00 = 0,
252    #[doc = "1: 16-bit width"]
253    _01 = 1,
254    #[doc = "2: 32-bit width"]
255    _10 = 2,
256    #[doc = "3: Setting prohibited"]
257    _11 = 3,
258}
259impl From<MBW_A> for u8 {
260    #[inline(always)]
261    fn from(variant: MBW_A) -> Self {
262        variant as _
263    }
264}
265impl MBW_R {
266    #[doc = "Get enumerated values variant"]
267    #[inline(always)]
268    pub fn variant(&self) -> MBW_A {
269        match self.bits {
270            0 => MBW_A::_00,
271            1 => MBW_A::_01,
272            2 => MBW_A::_10,
273            3 => MBW_A::_11,
274            _ => unreachable!(),
275        }
276    }
277    #[doc = "Checks if the value of the field is `_00`"]
278    #[inline(always)]
279    pub fn is_00(&self) -> bool {
280        *self == MBW_A::_00
281    }
282    #[doc = "Checks if the value of the field is `_01`"]
283    #[inline(always)]
284    pub fn is_01(&self) -> bool {
285        *self == MBW_A::_01
286    }
287    #[doc = "Checks if the value of the field is `_10`"]
288    #[inline(always)]
289    pub fn is_10(&self) -> bool {
290        *self == MBW_A::_10
291    }
292    #[doc = "Checks if the value of the field is `_11`"]
293    #[inline(always)]
294    pub fn is_11(&self) -> bool {
295        *self == MBW_A::_11
296    }
297}
298#[doc = "Field `MBW` writer - FIFO Port Access Bit Width"]
299pub type MBW_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u16, D0FIFOSEL_SPEC, u8, MBW_A, 2, O>;
300impl<'a, const O: u8> MBW_W<'a, O> {
301    #[doc = "8-bit width"]
302    #[inline(always)]
303    pub fn _00(self) -> &'a mut W {
304        self.variant(MBW_A::_00)
305    }
306    #[doc = "16-bit width"]
307    #[inline(always)]
308    pub fn _01(self) -> &'a mut W {
309        self.variant(MBW_A::_01)
310    }
311    #[doc = "32-bit width"]
312    #[inline(always)]
313    pub fn _10(self) -> &'a mut W {
314        self.variant(MBW_A::_10)
315    }
316    #[doc = "Setting prohibited"]
317    #[inline(always)]
318    pub fn _11(self) -> &'a mut W {
319        self.variant(MBW_A::_11)
320    }
321}
322#[doc = "Field `DREQE` reader - UCL_Dx_DREQ Signal Output Enable"]
323pub type DREQE_R = crate::BitReader<DREQE_A>;
324#[doc = "UCL_Dx_DREQ Signal Output Enable\n\nValue on reset: 0"]
325#[derive(Clone, Copy, Debug, PartialEq, Eq)]
326pub enum DREQE_A {
327    #[doc = "0: Disables the output"]
328    _0 = 0,
329    #[doc = "1: Enables the output"]
330    _1 = 1,
331}
332impl From<DREQE_A> for bool {
333    #[inline(always)]
334    fn from(variant: DREQE_A) -> Self {
335        variant as u8 != 0
336    }
337}
338impl DREQE_R {
339    #[doc = "Get enumerated values variant"]
340    #[inline(always)]
341    pub fn variant(&self) -> DREQE_A {
342        match self.bits {
343            false => DREQE_A::_0,
344            true => DREQE_A::_1,
345        }
346    }
347    #[doc = "Checks if the value of the field is `_0`"]
348    #[inline(always)]
349    pub fn is_0(&self) -> bool {
350        *self == DREQE_A::_0
351    }
352    #[doc = "Checks if the value of the field is `_1`"]
353    #[inline(always)]
354    pub fn is_1(&self) -> bool {
355        *self == DREQE_A::_1
356    }
357}
358#[doc = "Field `DREQE` writer - UCL_Dx_DREQ Signal Output Enable"]
359pub type DREQE_W<'a, const O: u8> = crate::BitWriter<'a, u16, D0FIFOSEL_SPEC, DREQE_A, O>;
360impl<'a, const O: u8> DREQE_W<'a, O> {
361    #[doc = "Disables the output"]
362    #[inline(always)]
363    pub fn _0(self) -> &'a mut W {
364        self.variant(DREQE_A::_0)
365    }
366    #[doc = "Enables the output"]
367    #[inline(always)]
368    pub fn _1(self) -> &'a mut W {
369        self.variant(DREQE_A::_1)
370    }
371}
372#[doc = "Field `DCLRM` reader - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
373pub type DCLRM_R = crate::BitReader<DCLRM_A>;
374#[doc = "Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read\n\nValue on reset: 0"]
375#[derive(Clone, Copy, Debug, PartialEq, Eq)]
376pub enum DCLRM_A {
377    #[doc = "0: Auto buffer clear mode is disabled"]
378    _0 = 0,
379    #[doc = "1: Auto buffer clear mode is enabled"]
380    _1 = 1,
381}
382impl From<DCLRM_A> for bool {
383    #[inline(always)]
384    fn from(variant: DCLRM_A) -> Self {
385        variant as u8 != 0
386    }
387}
388impl DCLRM_R {
389    #[doc = "Get enumerated values variant"]
390    #[inline(always)]
391    pub fn variant(&self) -> DCLRM_A {
392        match self.bits {
393            false => DCLRM_A::_0,
394            true => DCLRM_A::_1,
395        }
396    }
397    #[doc = "Checks if the value of the field is `_0`"]
398    #[inline(always)]
399    pub fn is_0(&self) -> bool {
400        *self == DCLRM_A::_0
401    }
402    #[doc = "Checks if the value of the field is `_1`"]
403    #[inline(always)]
404    pub fn is_1(&self) -> bool {
405        *self == DCLRM_A::_1
406    }
407}
408#[doc = "Field `DCLRM` writer - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
409pub type DCLRM_W<'a, const O: u8> = crate::BitWriter<'a, u16, D0FIFOSEL_SPEC, DCLRM_A, O>;
410impl<'a, const O: u8> DCLRM_W<'a, O> {
411    #[doc = "Auto buffer clear mode is disabled"]
412    #[inline(always)]
413    pub fn _0(self) -> &'a mut W {
414        self.variant(DCLRM_A::_0)
415    }
416    #[doc = "Auto buffer clear mode is enabled"]
417    #[inline(always)]
418    pub fn _1(self) -> &'a mut W {
419        self.variant(DCLRM_A::_1)
420    }
421}
422#[doc = "Buffer Pointer Rewind\n\nValue on reset: 0"]
423#[derive(Clone, Copy, Debug, PartialEq, Eq)]
424pub enum REW_AW {
425    #[doc = "0: The buffer pointer is not rewound"]
426    _0 = 0,
427    #[doc = "1: The buffer pointer is rewound"]
428    _1 = 1,
429}
430impl From<REW_AW> for bool {
431    #[inline(always)]
432    fn from(variant: REW_AW) -> Self {
433        variant as u8 != 0
434    }
435}
436#[doc = "Field `REW` writer - Buffer Pointer Rewind"]
437pub type REW_W<'a, const O: u8> = crate::BitWriter<'a, u16, D0FIFOSEL_SPEC, REW_AW, O>;
438impl<'a, const O: u8> REW_W<'a, O> {
439    #[doc = "The buffer pointer is not rewound"]
440    #[inline(always)]
441    pub fn _0(self) -> &'a mut W {
442        self.variant(REW_AW::_0)
443    }
444    #[doc = "The buffer pointer is rewound"]
445    #[inline(always)]
446    pub fn _1(self) -> &'a mut W {
447        self.variant(REW_AW::_1)
448    }
449}
450#[doc = "Field `RCNT` reader - Read Count Mode"]
451pub type RCNT_R = crate::BitReader<RCNT_A>;
452#[doc = "Read Count Mode\n\nValue on reset: 0"]
453#[derive(Clone, Copy, Debug, PartialEq, Eq)]
454pub enum RCNT_A {
455    #[doc = "0: The DTLN bits are cleared when all of the receive data has been read from the CFIFO"]
456    _0 = 0,
457    #[doc = "1: The DTLN bits are decremented each time the receive data is read from the CFIFO"]
458    _1 = 1,
459}
460impl From<RCNT_A> for bool {
461    #[inline(always)]
462    fn from(variant: RCNT_A) -> Self {
463        variant as u8 != 0
464    }
465}
466impl RCNT_R {
467    #[doc = "Get enumerated values variant"]
468    #[inline(always)]
469    pub fn variant(&self) -> RCNT_A {
470        match self.bits {
471            false => RCNT_A::_0,
472            true => RCNT_A::_1,
473        }
474    }
475    #[doc = "Checks if the value of the field is `_0`"]
476    #[inline(always)]
477    pub fn is_0(&self) -> bool {
478        *self == RCNT_A::_0
479    }
480    #[doc = "Checks if the value of the field is `_1`"]
481    #[inline(always)]
482    pub fn is_1(&self) -> bool {
483        *self == RCNT_A::_1
484    }
485}
486#[doc = "Field `RCNT` writer - Read Count Mode"]
487pub type RCNT_W<'a, const O: u8> = crate::BitWriter<'a, u16, D0FIFOSEL_SPEC, RCNT_A, O>;
488impl<'a, const O: u8> RCNT_W<'a, O> {
489    #[doc = "The DTLN bits are cleared when all of the receive data has been read from the CFIFO"]
490    #[inline(always)]
491    pub fn _0(self) -> &'a mut W {
492        self.variant(RCNT_A::_0)
493    }
494    #[doc = "The DTLN bits are decremented each time the receive data is read from the CFIFO"]
495    #[inline(always)]
496    pub fn _1(self) -> &'a mut W {
497        self.variant(RCNT_A::_1)
498    }
499}
500impl R {
501    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
502    #[inline(always)]
503    pub fn curpipe(&self) -> CURPIPE_R {
504        CURPIPE_R::new((self.bits & 0x0f) as u8)
505    }
506    #[doc = "Bit 8 - FIFO Port Endian Control"]
507    #[inline(always)]
508    pub fn bigend(&self) -> BIGEND_R {
509        BIGEND_R::new(((self.bits >> 8) & 1) != 0)
510    }
511    #[doc = "Bits 10:11 - FIFO Port Access Bit Width"]
512    #[inline(always)]
513    pub fn mbw(&self) -> MBW_R {
514        MBW_R::new(((self.bits >> 10) & 3) as u8)
515    }
516    #[doc = "Bit 12 - UCL_Dx_DREQ Signal Output Enable"]
517    #[inline(always)]
518    pub fn dreqe(&self) -> DREQE_R {
519        DREQE_R::new(((self.bits >> 12) & 1) != 0)
520    }
521    #[doc = "Bit 13 - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
522    #[inline(always)]
523    pub fn dclrm(&self) -> DCLRM_R {
524        DCLRM_R::new(((self.bits >> 13) & 1) != 0)
525    }
526    #[doc = "Bit 15 - Read Count Mode"]
527    #[inline(always)]
528    pub fn rcnt(&self) -> RCNT_R {
529        RCNT_R::new(((self.bits >> 15) & 1) != 0)
530    }
531}
532impl W {
533    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
534    #[inline(always)]
535    #[must_use]
536    pub fn curpipe(&mut self) -> CURPIPE_W<0> {
537        CURPIPE_W::new(self)
538    }
539    #[doc = "Bit 8 - FIFO Port Endian Control"]
540    #[inline(always)]
541    #[must_use]
542    pub fn bigend(&mut self) -> BIGEND_W<8> {
543        BIGEND_W::new(self)
544    }
545    #[doc = "Bits 10:11 - FIFO Port Access Bit Width"]
546    #[inline(always)]
547    #[must_use]
548    pub fn mbw(&mut self) -> MBW_W<10> {
549        MBW_W::new(self)
550    }
551    #[doc = "Bit 12 - UCL_Dx_DREQ Signal Output Enable"]
552    #[inline(always)]
553    #[must_use]
554    pub fn dreqe(&mut self) -> DREQE_W<12> {
555        DREQE_W::new(self)
556    }
557    #[doc = "Bit 13 - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
558    #[inline(always)]
559    #[must_use]
560    pub fn dclrm(&mut self) -> DCLRM_W<13> {
561        DCLRM_W::new(self)
562    }
563    #[doc = "Bit 14 - Buffer Pointer Rewind"]
564    #[inline(always)]
565    #[must_use]
566    pub fn rew(&mut self) -> REW_W<14> {
567        REW_W::new(self)
568    }
569    #[doc = "Bit 15 - Read Count Mode"]
570    #[inline(always)]
571    #[must_use]
572    pub fn rcnt(&mut self) -> RCNT_W<15> {
573        RCNT_W::new(self)
574    }
575    #[doc = "Writes raw bits to the register."]
576    #[inline(always)]
577    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
578        self.0.bits(bits);
579        self
580    }
581}
582#[doc = "D0FIFO Port Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [d0fifosel](index.html) module"]
583pub struct D0FIFOSEL_SPEC;
584impl crate::RegisterSpec for D0FIFOSEL_SPEC {
585    type Ux = u16;
586}
587#[doc = "`read()` method returns [d0fifosel::R](R) reader structure"]
588impl crate::Readable for D0FIFOSEL_SPEC {
589    type Reader = R;
590}
591#[doc = "`write(|w| ..)` method takes [d0fifosel::W](W) writer structure"]
592impl crate::Writable for D0FIFOSEL_SPEC {
593    type Writer = W;
594    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
595    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
596}
597#[doc = "`reset()` method sets D0FIFOSEL to value 0"]
598impl crate::Resettable for D0FIFOSEL_SPEC {
599    const RESET_VALUE: Self::Ux = 0;
600}
ra6m3/usbhs/d0fifosel.rs

ra6m3/usbhs/
d0fifosel.rs
