ra6m3_fsp_pac/src/
srcidctrl.rs

1///Register `SRCIDCTRL` reader
2pub type R = crate::R<SRCIDCTRL_SPEC>;
3///Register `SRCIDCTRL` writer
4pub type W = crate::W<SRCIDCTRL_SPEC>;
5/**Input FIFO Data Triggering Number
6
7Value on reset: 0*/
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum IFTRG_A {
11    ///0: 0
12    _00 = 0,
13    ///1: 2
14    _01 = 1,
15    ///2: 4
16    _10 = 2,
17    ///3: 6
18    _11 = 3,
19}
20impl From<IFTRG_A> for u8 {
21    #[inline(always)]
22    fn from(variant: IFTRG_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for IFTRG_A {
27    type Ux = u8;
28}
29impl crate::IsEnum for IFTRG_A {}
30///Field `IFTRG` reader - Input FIFO Data Triggering Number
31pub type IFTRG_R = crate::FieldReader<IFTRG_A>;
32impl IFTRG_R {
33    ///Get enumerated values variant
34    #[inline(always)]
35    pub const fn variant(&self) -> IFTRG_A {
36        match self.bits {
37            0 => IFTRG_A::_00,
38            1 => IFTRG_A::_01,
39            2 => IFTRG_A::_10,
40            3 => IFTRG_A::_11,
41            _ => unreachable!(),
42        }
43    }
44    ///0
45    #[inline(always)]
46    pub fn is_00(&self) -> bool {
47        *self == IFTRG_A::_00
48    }
49    ///2
50    #[inline(always)]
51    pub fn is_01(&self) -> bool {
52        *self == IFTRG_A::_01
53    }
54    ///4
55    #[inline(always)]
56    pub fn is_10(&self) -> bool {
57        *self == IFTRG_A::_10
58    }
59    ///6
60    #[inline(always)]
61    pub fn is_11(&self) -> bool {
62        *self == IFTRG_A::_11
63    }
64}
65///Field `IFTRG` writer - Input FIFO Data Triggering Number
66pub type IFTRG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IFTRG_A, crate::Safe>;
67impl<'a, REG> IFTRG_W<'a, REG>
68where
69    REG: crate::Writable + crate::RegisterSpec,
70    REG::Ux: From<u8>,
71{
72    ///0
73    #[inline(always)]
74    pub fn _00(self) -> &'a mut crate::W<REG> {
75        self.variant(IFTRG_A::_00)
76    }
77    ///2
78    #[inline(always)]
79    pub fn _01(self) -> &'a mut crate::W<REG> {
80        self.variant(IFTRG_A::_01)
81    }
82    ///4
83    #[inline(always)]
84    pub fn _10(self) -> &'a mut crate::W<REG> {
85        self.variant(IFTRG_A::_10)
86    }
87    ///6
88    #[inline(always)]
89    pub fn _11(self) -> &'a mut crate::W<REG> {
90        self.variant(IFTRG_A::_11)
91    }
92}
93/**Input FIFO Empty Interrupt Enable
94
95Value on reset: 0*/
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97pub enum IEN_A {
98    ///0: Input FIFO empty interrupt is disabled.
99    _0 = 0,
100    ///1: Input FIFO empty interrupt is enabled.
101    _1 = 1,
102}
103impl From<IEN_A> for bool {
104    #[inline(always)]
105    fn from(variant: IEN_A) -> Self {
106        variant as u8 != 0
107    }
108}
109///Field `IEN` reader - Input FIFO Empty Interrupt Enable
110pub type IEN_R = crate::BitReader<IEN_A>;
111impl IEN_R {
112    ///Get enumerated values variant
113    #[inline(always)]
114    pub const fn variant(&self) -> IEN_A {
115        match self.bits {
116            false => IEN_A::_0,
117            true => IEN_A::_1,
118        }
119    }
120    ///Input FIFO empty interrupt is disabled.
121    #[inline(always)]
122    pub fn is_0(&self) -> bool {
123        *self == IEN_A::_0
124    }
125    ///Input FIFO empty interrupt is enabled.
126    #[inline(always)]
127    pub fn is_1(&self) -> bool {
128        *self == IEN_A::_1
129    }
130}
131///Field `IEN` writer - Input FIFO Empty Interrupt Enable
132pub type IEN_W<'a, REG> = crate::BitWriter<'a, REG, IEN_A>;
133impl<'a, REG> IEN_W<'a, REG>
134where
135    REG: crate::Writable + crate::RegisterSpec,
136{
137    ///Input FIFO empty interrupt is disabled.
138    #[inline(always)]
139    pub fn _0(self) -> &'a mut crate::W<REG> {
140        self.variant(IEN_A::_0)
141    }
142    ///Input FIFO empty interrupt is enabled.
143    #[inline(always)]
144    pub fn _1(self) -> &'a mut crate::W<REG> {
145        self.variant(IEN_A::_1)
146    }
147}
148/**Input Data Endian
149
150Value on reset: 0*/
151#[derive(Clone, Copy, Debug, PartialEq, Eq)]
152pub enum IED_A {
153    ///0: Endian formats 1 are the same between the CPU and input data.
154    _0 = 0,
155    ///1: Endian formats 1 are different between the CPU and input data.
156    _1 = 1,
157}
158impl From<IED_A> for bool {
159    #[inline(always)]
160    fn from(variant: IED_A) -> Self {
161        variant as u8 != 0
162    }
163}
164///Field `IED` reader - Input Data Endian
165pub type IED_R = crate::BitReader<IED_A>;
166impl IED_R {
167    ///Get enumerated values variant
168    #[inline(always)]
169    pub const fn variant(&self) -> IED_A {
170        match self.bits {
171            false => IED_A::_0,
172            true => IED_A::_1,
173        }
174    }
175    ///Endian formats 1 are the same between the CPU and input data.
176    #[inline(always)]
177    pub fn is_0(&self) -> bool {
178        *self == IED_A::_0
179    }
180    ///Endian formats 1 are different between the CPU and input data.
181    #[inline(always)]
182    pub fn is_1(&self) -> bool {
183        *self == IED_A::_1
184    }
185}
186///Field `IED` writer - Input Data Endian
187pub type IED_W<'a, REG> = crate::BitWriter<'a, REG, IED_A>;
188impl<'a, REG> IED_W<'a, REG>
189where
190    REG: crate::Writable + crate::RegisterSpec,
191{
192    ///Endian formats 1 are the same between the CPU and input data.
193    #[inline(always)]
194    pub fn _0(self) -> &'a mut crate::W<REG> {
195        self.variant(IED_A::_0)
196    }
197    ///Endian formats 1 are different between the CPU and input data.
198    #[inline(always)]
199    pub fn _1(self) -> &'a mut crate::W<REG> {
200        self.variant(IED_A::_1)
201    }
202}
203impl R {
204    ///Bits 0:1 - Input FIFO Data Triggering Number
205    #[inline(always)]
206    pub fn iftrg(&self) -> IFTRG_R {
207        IFTRG_R::new((self.bits & 3) as u8)
208    }
209    ///Bit 8 - Input FIFO Empty Interrupt Enable
210    #[inline(always)]
211    pub fn ien(&self) -> IEN_R {
212        IEN_R::new(((self.bits >> 8) & 1) != 0)
213    }
214    ///Bit 9 - Input Data Endian
215    #[inline(always)]
216    pub fn ied(&self) -> IED_R {
217        IED_R::new(((self.bits >> 9) & 1) != 0)
218    }
219}
220impl W {
221    ///Bits 0:1 - Input FIFO Data Triggering Number
222    #[inline(always)]
223    pub fn iftrg(&mut self) -> IFTRG_W<'_, SRCIDCTRL_SPEC> {
224        IFTRG_W::new(self, 0)
225    }
226    ///Bit 8 - Input FIFO Empty Interrupt Enable
227    #[inline(always)]
228    pub fn ien(&mut self) -> IEN_W<'_, SRCIDCTRL_SPEC> {
229        IEN_W::new(self, 8)
230    }
231    ///Bit 9 - Input Data Endian
232    #[inline(always)]
233    pub fn ied(&mut self) -> IED_W<'_, SRCIDCTRL_SPEC> {
234        IED_W::new(self, 9)
235    }
236}
237/**Input Data Control Register
238
239You can [`read`](crate::Reg::read) this register and get [`srcidctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srcidctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
240pub struct SRCIDCTRL_SPEC;
241impl crate::RegisterSpec for SRCIDCTRL_SPEC {
242    type Ux = u16;
243}
244///`read()` method returns [`srcidctrl::R`](R) reader structure
245impl crate::Readable for SRCIDCTRL_SPEC {}
246///`write(|w| ..)` method takes [`srcidctrl::W`](W) writer structure
247impl crate::Writable for SRCIDCTRL_SPEC {
248    type Safety = crate::Unsafe;
249}
250///`reset()` method sets SRCIDCTRL to value 0
251impl crate::Resettable for SRCIDCTRL_SPEC {}
ra6m3_fsp_pac/src/srcidctrl.rs

ra6m3_fsp_pac/src/
srcidctrl.rs
