ra6m2/usbhs/
buswait.rs

1#[doc = "Register `BUSWAIT` reader"]
2pub struct R(crate::R<BUSWAIT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<BUSWAIT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<BUSWAIT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<BUSWAIT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `BUSWAIT` writer"]
17pub struct W(crate::W<BUSWAIT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<BUSWAIT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<BUSWAIT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<BUSWAIT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `BWAIT` reader - CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)"]
38pub type BWAIT_R = crate::FieldReader<u8, BWAIT_A>;
39#[doc = "CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)\n\nValue on reset: 15"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub struct BWAIT_A(u8);
42impl From<BWAIT_A> for u8 {
43    #[inline(always)]
44    fn from(val: BWAIT_A) -> Self {
45        val.0 as _
46    }
47}
48#[doc = "Field `BWAIT` writer - CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)"]
49pub type BWAIT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, BUSWAIT_SPEC, u8, BWAIT_A, 4, O>;
50impl R {
51    #[doc = "Bits 0:3 - CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)"]
52    #[inline(always)]
53    pub fn bwait(&self) -> BWAIT_R {
54        BWAIT_R::new((self.bits & 0x0f) as u8)
55    }
56}
57impl W {
58    #[doc = "Bits 0:3 - CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)"]
59    #[inline(always)]
60    #[must_use]
61    pub fn bwait(&mut self) -> BWAIT_W<0> {
62        BWAIT_W::new(self)
63    }
64    #[doc = "Writes raw bits to the register."]
65    #[inline(always)]
66    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
67        self.0.bits(bits);
68        self
69    }
70}
71#[doc = "CPU Bus Wait Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [buswait](index.html) module"]
72pub struct BUSWAIT_SPEC;
73impl crate::RegisterSpec for BUSWAIT_SPEC {
74    type Ux = u16;
75}
76#[doc = "`read()` method returns [buswait::R](R) reader structure"]
77impl crate::Readable for BUSWAIT_SPEC {
78    type Reader = R;
79}
80#[doc = "`write(|w| ..)` method takes [buswait::W](W) writer structure"]
81impl crate::Writable for BUSWAIT_SPEC {
82    type Writer = W;
83    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
84    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
85}
86#[doc = "`reset()` method sets BUSWAIT to value 0x0f"]
87impl crate::Resettable for BUSWAIT_SPEC {
88    const RESET_VALUE: Self::Ux = 0x0f;
89}
ra6m2/usbhs/buswait.rs

ra6m2/usbhs/
buswait.rs
