ra6m2/usbhs/
cfifosel.rs

1#[doc = "Register `CFIFOSEL` reader"]
2pub struct R(crate::R<CFIFOSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFIFOSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFIFOSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFIFOSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFIFOSEL` writer"]
17pub struct W(crate::W<CFIFOSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFIFOSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFIFOSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFIFOSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CURPIPE` reader - FIFO Port Access Pipe Specification"]
38pub type CURPIPE_R = crate::FieldReader<u8, CURPIPE_A>;
39#[doc = "FIFO Port Access Pipe Specification\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CURPIPE_A {
43    #[doc = "0: DCP"]
44    _0000 = 0,
45    #[doc = "1: PIPE1"]
46    _0001 = 1,
47    #[doc = "2: PIPE2"]
48    _0010 = 2,
49    #[doc = "3: PIPE3"]
50    _0011 = 3,
51    #[doc = "4: PIPE4"]
52    _0100 = 4,
53    #[doc = "5: PIPE5"]
54    _0101 = 5,
55    #[doc = "6: PIPE6"]
56    _0110 = 6,
57    #[doc = "7: PIPE7"]
58    _0111 = 7,
59    #[doc = "8: PIPE8"]
60    _1000 = 8,
61    #[doc = "9: PIPE9"]
62    _1001 = 9,
63}
64impl From<CURPIPE_A> for u8 {
65    #[inline(always)]
66    fn from(variant: CURPIPE_A) -> Self {
67        variant as _
68    }
69}
70impl CURPIPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<CURPIPE_A> {
74        match self.bits {
75            0 => Some(CURPIPE_A::_0000),
76            1 => Some(CURPIPE_A::_0001),
77            2 => Some(CURPIPE_A::_0010),
78            3 => Some(CURPIPE_A::_0011),
79            4 => Some(CURPIPE_A::_0100),
80            5 => Some(CURPIPE_A::_0101),
81            6 => Some(CURPIPE_A::_0110),
82            7 => Some(CURPIPE_A::_0111),
83            8 => Some(CURPIPE_A::_1000),
84            9 => Some(CURPIPE_A::_1001),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `_0000`"]
89    #[inline(always)]
90    pub fn is_0000(&self) -> bool {
91        *self == CURPIPE_A::_0000
92    }
93    #[doc = "Checks if the value of the field is `_0001`"]
94    #[inline(always)]
95    pub fn is_0001(&self) -> bool {
96        *self == CURPIPE_A::_0001
97    }
98    #[doc = "Checks if the value of the field is `_0010`"]
99    #[inline(always)]
100    pub fn is_0010(&self) -> bool {
101        *self == CURPIPE_A::_0010
102    }
103    #[doc = "Checks if the value of the field is `_0011`"]
104    #[inline(always)]
105    pub fn is_0011(&self) -> bool {
106        *self == CURPIPE_A::_0011
107    }
108    #[doc = "Checks if the value of the field is `_0100`"]
109    #[inline(always)]
110    pub fn is_0100(&self) -> bool {
111        *self == CURPIPE_A::_0100
112    }
113    #[doc = "Checks if the value of the field is `_0101`"]
114    #[inline(always)]
115    pub fn is_0101(&self) -> bool {
116        *self == CURPIPE_A::_0101
117    }
118    #[doc = "Checks if the value of the field is `_0110`"]
119    #[inline(always)]
120    pub fn is_0110(&self) -> bool {
121        *self == CURPIPE_A::_0110
122    }
123    #[doc = "Checks if the value of the field is `_0111`"]
124    #[inline(always)]
125    pub fn is_0111(&self) -> bool {
126        *self == CURPIPE_A::_0111
127    }
128    #[doc = "Checks if the value of the field is `_1000`"]
129    #[inline(always)]
130    pub fn is_1000(&self) -> bool {
131        *self == CURPIPE_A::_1000
132    }
133    #[doc = "Checks if the value of the field is `_1001`"]
134    #[inline(always)]
135    pub fn is_1001(&self) -> bool {
136        *self == CURPIPE_A::_1001
137    }
138}
139#[doc = "Field `CURPIPE` writer - FIFO Port Access Pipe Specification"]
140pub type CURPIPE_W<'a, const O: u8> =
141    crate::FieldWriter<'a, u16, CFIFOSEL_SPEC, u8, CURPIPE_A, 4, O>;
142impl<'a, const O: u8> CURPIPE_W<'a, O> {
143    #[doc = "DCP"]
144    #[inline(always)]
145    pub fn _0000(self) -> &'a mut W {
146        self.variant(CURPIPE_A::_0000)
147    }
148    #[doc = "PIPE1"]
149    #[inline(always)]
150    pub fn _0001(self) -> &'a mut W {
151        self.variant(CURPIPE_A::_0001)
152    }
153    #[doc = "PIPE2"]
154    #[inline(always)]
155    pub fn _0010(self) -> &'a mut W {
156        self.variant(CURPIPE_A::_0010)
157    }
158    #[doc = "PIPE3"]
159    #[inline(always)]
160    pub fn _0011(self) -> &'a mut W {
161        self.variant(CURPIPE_A::_0011)
162    }
163    #[doc = "PIPE4"]
164    #[inline(always)]
165    pub fn _0100(self) -> &'a mut W {
166        self.variant(CURPIPE_A::_0100)
167    }
168    #[doc = "PIPE5"]
169    #[inline(always)]
170    pub fn _0101(self) -> &'a mut W {
171        self.variant(CURPIPE_A::_0101)
172    }
173    #[doc = "PIPE6"]
174    #[inline(always)]
175    pub fn _0110(self) -> &'a mut W {
176        self.variant(CURPIPE_A::_0110)
177    }
178    #[doc = "PIPE7"]
179    #[inline(always)]
180    pub fn _0111(self) -> &'a mut W {
181        self.variant(CURPIPE_A::_0111)
182    }
183    #[doc = "PIPE8"]
184    #[inline(always)]
185    pub fn _1000(self) -> &'a mut W {
186        self.variant(CURPIPE_A::_1000)
187    }
188    #[doc = "PIPE9"]
189    #[inline(always)]
190    pub fn _1001(self) -> &'a mut W {
191        self.variant(CURPIPE_A::_1001)
192    }
193}
194#[doc = "Field `ISEL` reader - FIFO Port Access Direction when DCP is Selected"]
195pub type ISEL_R = crate::BitReader<ISEL_A>;
196#[doc = "FIFO Port Access Direction when DCP is Selected\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum ISEL_A {
199    #[doc = "0: Select reading from the FIFO buffer"]
200    _0 = 0,
201    #[doc = "1: Select writing to the FIFO buffer."]
202    _1 = 1,
203}
204impl From<ISEL_A> for bool {
205    #[inline(always)]
206    fn from(variant: ISEL_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl ISEL_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> ISEL_A {
214        match self.bits {
215            false => ISEL_A::_0,
216            true => ISEL_A::_1,
217        }
218    }
219    #[doc = "Checks if the value of the field is `_0`"]
220    #[inline(always)]
221    pub fn is_0(&self) -> bool {
222        *self == ISEL_A::_0
223    }
224    #[doc = "Checks if the value of the field is `_1`"]
225    #[inline(always)]
226    pub fn is_1(&self) -> bool {
227        *self == ISEL_A::_1
228    }
229}
230#[doc = "Field `ISEL` writer - FIFO Port Access Direction when DCP is Selected"]
231pub type ISEL_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, ISEL_A, O>;
232impl<'a, const O: u8> ISEL_W<'a, O> {
233    #[doc = "Select reading from the FIFO buffer"]
234    #[inline(always)]
235    pub fn _0(self) -> &'a mut W {
236        self.variant(ISEL_A::_0)
237    }
238    #[doc = "Select writing to the FIFO buffer."]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut W {
241        self.variant(ISEL_A::_1)
242    }
243}
244#[doc = "Field `BIGEND` reader - FIFO Port Endian Control"]
245pub type BIGEND_R = crate::BitReader<BIGEND_A>;
246#[doc = "FIFO Port Endian Control\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum BIGEND_A {
249    #[doc = "0: Little endian"]
250    _0 = 0,
251    #[doc = "1: Big endian"]
252    _1 = 1,
253}
254impl From<BIGEND_A> for bool {
255    #[inline(always)]
256    fn from(variant: BIGEND_A) -> Self {
257        variant as u8 != 0
258    }
259}
260impl BIGEND_R {
261    #[doc = "Get enumerated values variant"]
262    #[inline(always)]
263    pub fn variant(&self) -> BIGEND_A {
264        match self.bits {
265            false => BIGEND_A::_0,
266            true => BIGEND_A::_1,
267        }
268    }
269    #[doc = "Checks if the value of the field is `_0`"]
270    #[inline(always)]
271    pub fn is_0(&self) -> bool {
272        *self == BIGEND_A::_0
273    }
274    #[doc = "Checks if the value of the field is `_1`"]
275    #[inline(always)]
276    pub fn is_1(&self) -> bool {
277        *self == BIGEND_A::_1
278    }
279}
280#[doc = "Field `BIGEND` writer - FIFO Port Endian Control"]
281pub type BIGEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, BIGEND_A, O>;
282impl<'a, const O: u8> BIGEND_W<'a, O> {
283    #[doc = "Little endian"]
284    #[inline(always)]
285    pub fn _0(self) -> &'a mut W {
286        self.variant(BIGEND_A::_0)
287    }
288    #[doc = "Big endian"]
289    #[inline(always)]
290    pub fn _1(self) -> &'a mut W {
291        self.variant(BIGEND_A::_1)
292    }
293}
294#[doc = "Field `MBW` reader - CFIFO Port Access Bit Width"]
295pub type MBW_R = crate::FieldReader<u8, MBW_A>;
296#[doc = "CFIFO Port Access Bit Width\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq, Eq)]
298#[repr(u8)]
299pub enum MBW_A {
300    #[doc = "0: 8-bit width"]
301    _00 = 0,
302    #[doc = "1: 16-bit width"]
303    _01 = 1,
304    #[doc = "2: 32-bit width"]
305    _10 = 2,
306    #[doc = "3: Setting prohibited"]
307    _11 = 3,
308}
309impl From<MBW_A> for u8 {
310    #[inline(always)]
311    fn from(variant: MBW_A) -> Self {
312        variant as _
313    }
314}
315impl MBW_R {
316    #[doc = "Get enumerated values variant"]
317    #[inline(always)]
318    pub fn variant(&self) -> MBW_A {
319        match self.bits {
320            0 => MBW_A::_00,
321            1 => MBW_A::_01,
322            2 => MBW_A::_10,
323            3 => MBW_A::_11,
324            _ => unreachable!(),
325        }
326    }
327    #[doc = "Checks if the value of the field is `_00`"]
328    #[inline(always)]
329    pub fn is_00(&self) -> bool {
330        *self == MBW_A::_00
331    }
332    #[doc = "Checks if the value of the field is `_01`"]
333    #[inline(always)]
334    pub fn is_01(&self) -> bool {
335        *self == MBW_A::_01
336    }
337    #[doc = "Checks if the value of the field is `_10`"]
338    #[inline(always)]
339    pub fn is_10(&self) -> bool {
340        *self == MBW_A::_10
341    }
342    #[doc = "Checks if the value of the field is `_11`"]
343    #[inline(always)]
344    pub fn is_11(&self) -> bool {
345        *self == MBW_A::_11
346    }
347}
348#[doc = "Field `MBW` writer - CFIFO Port Access Bit Width"]
349pub type MBW_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u16, CFIFOSEL_SPEC, u8, MBW_A, 2, O>;
350impl<'a, const O: u8> MBW_W<'a, O> {
351    #[doc = "8-bit width"]
352    #[inline(always)]
353    pub fn _00(self) -> &'a mut W {
354        self.variant(MBW_A::_00)
355    }
356    #[doc = "16-bit width"]
357    #[inline(always)]
358    pub fn _01(self) -> &'a mut W {
359        self.variant(MBW_A::_01)
360    }
361    #[doc = "32-bit width"]
362    #[inline(always)]
363    pub fn _10(self) -> &'a mut W {
364        self.variant(MBW_A::_10)
365    }
366    #[doc = "Setting prohibited"]
367    #[inline(always)]
368    pub fn _11(self) -> &'a mut W {
369        self.variant(MBW_A::_11)
370    }
371}
372#[doc = "Buffer Pointer Rewind\n\nValue on reset: 0"]
373#[derive(Clone, Copy, Debug, PartialEq, Eq)]
374pub enum REW_AW {
375    #[doc = "0: Do not rewind buffer pointer (Writing 0 has no effect.)"]
376    _0 = 0,
377    #[doc = "1: Rewind buffer pointer."]
378    _1 = 1,
379}
380impl From<REW_AW> for bool {
381    #[inline(always)]
382    fn from(variant: REW_AW) -> Self {
383        variant as u8 != 0
384    }
385}
386#[doc = "Field `REW` writer - Buffer Pointer Rewind"]
387pub type REW_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, REW_AW, O>;
388impl<'a, const O: u8> REW_W<'a, O> {
389    #[doc = "Do not rewind buffer pointer (Writing 0 has no effect.)"]
390    #[inline(always)]
391    pub fn _0(self) -> &'a mut W {
392        self.variant(REW_AW::_0)
393    }
394    #[doc = "Rewind buffer pointer."]
395    #[inline(always)]
396    pub fn _1(self) -> &'a mut W {
397        self.variant(REW_AW::_1)
398    }
399}
400#[doc = "Field `RCNT` reader - Read Count Mode"]
401pub type RCNT_R = crate::BitReader<RCNT_A>;
402#[doc = "Read Count Mode\n\nValue on reset: 0"]
403#[derive(Clone, Copy, Debug, PartialEq, Eq)]
404pub enum RCNT_A {
405    #[doc = "0: Clear DTLN\\[11:0\\]
406flags in the FIFO port control register to 000h when all receive data is read from CFIFO"]
407    _0 = 0,
408    #[doc = "1: Decrement DTLN\\[11:0\\]
409flags each time receive data is read from CFIFO."]
410    _1 = 1,
411}
412impl From<RCNT_A> for bool {
413    #[inline(always)]
414    fn from(variant: RCNT_A) -> Self {
415        variant as u8 != 0
416    }
417}
418impl RCNT_R {
419    #[doc = "Get enumerated values variant"]
420    #[inline(always)]
421    pub fn variant(&self) -> RCNT_A {
422        match self.bits {
423            false => RCNT_A::_0,
424            true => RCNT_A::_1,
425        }
426    }
427    #[doc = "Checks if the value of the field is `_0`"]
428    #[inline(always)]
429    pub fn is_0(&self) -> bool {
430        *self == RCNT_A::_0
431    }
432    #[doc = "Checks if the value of the field is `_1`"]
433    #[inline(always)]
434    pub fn is_1(&self) -> bool {
435        *self == RCNT_A::_1
436    }
437}
438#[doc = "Field `RCNT` writer - Read Count Mode"]
439pub type RCNT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CFIFOSEL_SPEC, RCNT_A, O>;
440impl<'a, const O: u8> RCNT_W<'a, O> {
441    #[doc = "Clear DTLN\\[11:0\\]
442flags in the FIFO port control register to 000h when all receive data is read from CFIFO"]
443    #[inline(always)]
444    pub fn _0(self) -> &'a mut W {
445        self.variant(RCNT_A::_0)
446    }
447    #[doc = "Decrement DTLN\\[11:0\\]
448flags each time receive data is read from CFIFO."]
449    #[inline(always)]
450    pub fn _1(self) -> &'a mut W {
451        self.variant(RCNT_A::_1)
452    }
453}
454impl R {
455    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
456    #[inline(always)]
457    pub fn curpipe(&self) -> CURPIPE_R {
458        CURPIPE_R::new((self.bits & 0x0f) as u8)
459    }
460    #[doc = "Bit 5 - FIFO Port Access Direction when DCP is Selected"]
461    #[inline(always)]
462    pub fn isel(&self) -> ISEL_R {
463        ISEL_R::new(((self.bits >> 5) & 1) != 0)
464    }
465    #[doc = "Bit 8 - FIFO Port Endian Control"]
466    #[inline(always)]
467    pub fn bigend(&self) -> BIGEND_R {
468        BIGEND_R::new(((self.bits >> 8) & 1) != 0)
469    }
470    #[doc = "Bits 10:11 - CFIFO Port Access Bit Width"]
471    #[inline(always)]
472    pub fn mbw(&self) -> MBW_R {
473        MBW_R::new(((self.bits >> 10) & 3) as u8)
474    }
475    #[doc = "Bit 15 - Read Count Mode"]
476    #[inline(always)]
477    pub fn rcnt(&self) -> RCNT_R {
478        RCNT_R::new(((self.bits >> 15) & 1) != 0)
479    }
480}
481impl W {
482    #[doc = "Bits 0:3 - FIFO Port Access Pipe Specification"]
483    #[inline(always)]
484    #[must_use]
485    pub fn curpipe(&mut self) -> CURPIPE_W<0> {
486        CURPIPE_W::new(self)
487    }
488    #[doc = "Bit 5 - FIFO Port Access Direction when DCP is Selected"]
489    #[inline(always)]
490    #[must_use]
491    pub fn isel(&mut self) -> ISEL_W<5> {
492        ISEL_W::new(self)
493    }
494    #[doc = "Bit 8 - FIFO Port Endian Control"]
495    #[inline(always)]
496    #[must_use]
497    pub fn bigend(&mut self) -> BIGEND_W<8> {
498        BIGEND_W::new(self)
499    }
500    #[doc = "Bits 10:11 - CFIFO Port Access Bit Width"]
501    #[inline(always)]
502    #[must_use]
503    pub fn mbw(&mut self) -> MBW_W<10> {
504        MBW_W::new(self)
505    }
506    #[doc = "Bit 14 - Buffer Pointer Rewind"]
507    #[inline(always)]
508    #[must_use]
509    pub fn rew(&mut self) -> REW_W<14> {
510        REW_W::new(self)
511    }
512    #[doc = "Bit 15 - Read Count Mode"]
513    #[inline(always)]
514    #[must_use]
515    pub fn rcnt(&mut self) -> RCNT_W<15> {
516        RCNT_W::new(self)
517    }
518    #[doc = "Writes raw bits to the register."]
519    #[inline(always)]
520    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
521        self.0.bits(bits);
522        self
523    }
524}
525#[doc = "CFIFO Port Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfifosel](index.html) module"]
526pub struct CFIFOSEL_SPEC;
527impl crate::RegisterSpec for CFIFOSEL_SPEC {
528    type Ux = u16;
529}
530#[doc = "`read()` method returns [cfifosel::R](R) reader structure"]
531impl crate::Readable for CFIFOSEL_SPEC {
532    type Reader = R;
533}
534#[doc = "`write(|w| ..)` method takes [cfifosel::W](W) writer structure"]
535impl crate::Writable for CFIFOSEL_SPEC {
536    type Writer = W;
537    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
538    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
539}
540#[doc = "`reset()` method sets CFIFOSEL to value 0"]
541impl crate::Resettable for CFIFOSEL_SPEC {
542    const RESET_VALUE: Self::Ux = 0;
543}
ra6m2/usbhs/cfifosel.rs

ra6m2/usbhs/
cfifosel.rs
