1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Sound Interface Enhanced (SSIE)"]
28unsafe impl ::core::marker::Send for super::Ssie0 {}
29unsafe impl ::core::marker::Sync for super::Ssie0 {}
30impl super::Ssie0 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Control Register"]
38 #[inline(always)]
39 pub const fn ssicr(&self) -> &'static crate::common::Reg<self::Ssicr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Ssicr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "Status Register"]
48 #[inline(always)]
49 pub const fn ssisr(&self) -> &'static crate::common::Reg<self::Ssisr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Ssisr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "FIFO Control Register"]
58 #[inline(always)]
59 pub const fn ssifcr(
60 &self,
61 ) -> &'static crate::common::Reg<self::Ssifcr_SPEC, crate::common::RW> {
62 unsafe {
63 crate::common::Reg::<self::Ssifcr_SPEC, crate::common::RW>::from_ptr(
64 self._svd2pac_as_ptr().add(16usize),
65 )
66 }
67 }
68
69 #[doc = "FIFO Status Register"]
70 #[inline(always)]
71 pub const fn ssifsr(
72 &self,
73 ) -> &'static crate::common::Reg<self::Ssifsr_SPEC, crate::common::RW> {
74 unsafe {
75 crate::common::Reg::<self::Ssifsr_SPEC, crate::common::RW>::from_ptr(
76 self._svd2pac_as_ptr().add(20usize),
77 )
78 }
79 }
80
81 #[doc = "Transmit FIFO Data Register"]
82 #[inline(always)]
83 pub const fn ssiftdr(
84 &self,
85 ) -> &'static crate::common::Reg<self::Ssiftdr_SPEC, crate::common::W> {
86 unsafe {
87 crate::common::Reg::<self::Ssiftdr_SPEC, crate::common::W>::from_ptr(
88 self._svd2pac_as_ptr().add(24usize),
89 )
90 }
91 }
92
93 #[doc = "Receive FIFO Data Register"]
94 #[inline(always)]
95 pub const fn ssifrdr(
96 &self,
97 ) -> &'static crate::common::Reg<self::Ssifrdr_SPEC, crate::common::R> {
98 unsafe {
99 crate::common::Reg::<self::Ssifrdr_SPEC, crate::common::R>::from_ptr(
100 self._svd2pac_as_ptr().add(28usize),
101 )
102 }
103 }
104
105 #[doc = "Audio Format Register"]
106 #[inline(always)]
107 pub const fn ssiofr(
108 &self,
109 ) -> &'static crate::common::Reg<self::Ssiofr_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::Ssiofr_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(32usize),
113 )
114 }
115 }
116
117 #[doc = "Status Control Register"]
118 #[inline(always)]
119 pub const fn ssiscr(
120 &self,
121 ) -> &'static crate::common::Reg<self::Ssiscr_SPEC, crate::common::RW> {
122 unsafe {
123 crate::common::Reg::<self::Ssiscr_SPEC, crate::common::RW>::from_ptr(
124 self._svd2pac_as_ptr().add(36usize),
125 )
126 }
127 }
128}
129#[doc(hidden)]
130#[derive(Copy, Clone, Eq, PartialEq)]
131pub struct Ssicr_SPEC;
132impl crate::sealed::RegSpec for Ssicr_SPEC {
133 type DataType = u32;
134}
135
136#[doc = "Control Register"]
137pub type Ssicr = crate::RegValueT<Ssicr_SPEC>;
138
139impl Ssicr {
140 #[doc = "Oversampling Clock Select"]
141 #[inline(always)]
142 pub fn cks(
143 self,
144 ) -> crate::common::RegisterField<
145 30,
146 0x1,
147 1,
148 0,
149 ssicr::Cks,
150 ssicr::Cks,
151 Ssicr_SPEC,
152 crate::common::RW,
153 > {
154 crate::common::RegisterField::<
155 30,
156 0x1,
157 1,
158 0,
159 ssicr::Cks,
160 ssicr::Cks,
161 Ssicr_SPEC,
162 crate::common::RW,
163 >::from_register(self, 0)
164 }
165
166 #[doc = "Transmit Underflow Interrupt Enable"]
167 #[inline(always)]
168 pub fn tuien(
169 self,
170 ) -> crate::common::RegisterField<
171 29,
172 0x1,
173 1,
174 0,
175 ssicr::Tuien,
176 ssicr::Tuien,
177 Ssicr_SPEC,
178 crate::common::RW,
179 > {
180 crate::common::RegisterField::<
181 29,
182 0x1,
183 1,
184 0,
185 ssicr::Tuien,
186 ssicr::Tuien,
187 Ssicr_SPEC,
188 crate::common::RW,
189 >::from_register(self, 0)
190 }
191
192 #[doc = "Transmit Overflow Interrupt Enable"]
193 #[inline(always)]
194 pub fn toien(
195 self,
196 ) -> crate::common::RegisterField<
197 28,
198 0x1,
199 1,
200 0,
201 ssicr::Toien,
202 ssicr::Toien,
203 Ssicr_SPEC,
204 crate::common::RW,
205 > {
206 crate::common::RegisterField::<
207 28,
208 0x1,
209 1,
210 0,
211 ssicr::Toien,
212 ssicr::Toien,
213 Ssicr_SPEC,
214 crate::common::RW,
215 >::from_register(self, 0)
216 }
217
218 #[doc = "Receive Underflow Interrupt Enable"]
219 #[inline(always)]
220 pub fn ruien(
221 self,
222 ) -> crate::common::RegisterField<
223 27,
224 0x1,
225 1,
226 0,
227 ssicr::Ruien,
228 ssicr::Ruien,
229 Ssicr_SPEC,
230 crate::common::RW,
231 > {
232 crate::common::RegisterField::<
233 27,
234 0x1,
235 1,
236 0,
237 ssicr::Ruien,
238 ssicr::Ruien,
239 Ssicr_SPEC,
240 crate::common::RW,
241 >::from_register(self, 0)
242 }
243
244 #[doc = "Receive Overflow Interrupt Enable"]
245 #[inline(always)]
246 pub fn roien(
247 self,
248 ) -> crate::common::RegisterField<
249 26,
250 0x1,
251 1,
252 0,
253 ssicr::Roien,
254 ssicr::Roien,
255 Ssicr_SPEC,
256 crate::common::RW,
257 > {
258 crate::common::RegisterField::<
259 26,
260 0x1,
261 1,
262 0,
263 ssicr::Roien,
264 ssicr::Roien,
265 Ssicr_SPEC,
266 crate::common::RW,
267 >::from_register(self, 0)
268 }
269
270 #[doc = "Idle Mode Interrupt Enable"]
271 #[inline(always)]
272 pub fn iien(
273 self,
274 ) -> crate::common::RegisterField<
275 25,
276 0x1,
277 1,
278 0,
279 ssicr::Iien,
280 ssicr::Iien,
281 Ssicr_SPEC,
282 crate::common::RW,
283 > {
284 crate::common::RegisterField::<
285 25,
286 0x1,
287 1,
288 0,
289 ssicr::Iien,
290 ssicr::Iien,
291 Ssicr_SPEC,
292 crate::common::RW,
293 >::from_register(self, 0)
294 }
295
296 #[doc = "Channels"]
297 #[inline(always)]
298 pub fn chnl(
299 self,
300 ) -> crate::common::RegisterField<
301 22,
302 0x3,
303 1,
304 0,
305 ssicr::Chnl,
306 ssicr::Chnl,
307 Ssicr_SPEC,
308 crate::common::RW,
309 > {
310 crate::common::RegisterField::<
311 22,
312 0x3,
313 1,
314 0,
315 ssicr::Chnl,
316 ssicr::Chnl,
317 Ssicr_SPEC,
318 crate::common::RW,
319 >::from_register(self, 0)
320 }
321
322 #[doc = "Data Word Length"]
323 #[inline(always)]
324 pub fn dwl(
325 self,
326 ) -> crate::common::RegisterField<
327 19,
328 0x7,
329 1,
330 0,
331 ssicr::Dwl,
332 ssicr::Dwl,
333 Ssicr_SPEC,
334 crate::common::RW,
335 > {
336 crate::common::RegisterField::<
337 19,
338 0x7,
339 1,
340 0,
341 ssicr::Dwl,
342 ssicr::Dwl,
343 Ssicr_SPEC,
344 crate::common::RW,
345 >::from_register(self, 0)
346 }
347
348 #[doc = "System Word LengthSet the system word length to the bit clock frequency/2 fs."]
349 #[inline(always)]
350 pub fn swl(
351 self,
352 ) -> crate::common::RegisterField<
353 16,
354 0x7,
355 1,
356 0,
357 ssicr::Swl,
358 ssicr::Swl,
359 Ssicr_SPEC,
360 crate::common::RW,
361 > {
362 crate::common::RegisterField::<
363 16,
364 0x7,
365 1,
366 0,
367 ssicr::Swl,
368 ssicr::Swl,
369 Ssicr_SPEC,
370 crate::common::RW,
371 >::from_register(self, 0)
372 }
373
374 #[doc = "Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited."]
375 #[inline(always)]
376 pub fn swsd(
377 self,
378 ) -> crate::common::RegisterField<
379 14,
380 0x1,
381 1,
382 0,
383 ssicr::Swsd,
384 ssicr::Swsd,
385 Ssicr_SPEC,
386 crate::common::RW,
387 > {
388 crate::common::RegisterField::<
389 14,
390 0x1,
391 1,
392 0,
393 ssicr::Swsd,
394 ssicr::Swsd,
395 Ssicr_SPEC,
396 crate::common::RW,
397 >::from_register(self, 0)
398 }
399
400 #[doc = "Serial Bit Clock Polarity"]
401 #[inline(always)]
402 pub fn sckp(
403 self,
404 ) -> crate::common::RegisterField<
405 13,
406 0x1,
407 1,
408 0,
409 ssicr::Sckp,
410 ssicr::Sckp,
411 Ssicr_SPEC,
412 crate::common::RW,
413 > {
414 crate::common::RegisterField::<
415 13,
416 0x1,
417 1,
418 0,
419 ssicr::Sckp,
420 ssicr::Sckp,
421 Ssicr_SPEC,
422 crate::common::RW,
423 >::from_register(self, 0)
424 }
425
426 #[doc = "Serial WS Polarity"]
427 #[inline(always)]
428 pub fn swsp(
429 self,
430 ) -> crate::common::RegisterField<
431 12,
432 0x1,
433 1,
434 0,
435 ssicr::Swsp,
436 ssicr::Swsp,
437 Ssicr_SPEC,
438 crate::common::RW,
439 > {
440 crate::common::RegisterField::<
441 12,
442 0x1,
443 1,
444 0,
445 ssicr::Swsp,
446 ssicr::Swsp,
447 Ssicr_SPEC,
448 crate::common::RW,
449 >::from_register(self, 0)
450 }
451
452 #[doc = "Serial Padding Polarity"]
453 #[inline(always)]
454 pub fn spdp(
455 self,
456 ) -> crate::common::RegisterField<
457 11,
458 0x1,
459 1,
460 0,
461 ssicr::Spdp,
462 ssicr::Spdp,
463 Ssicr_SPEC,
464 crate::common::RW,
465 > {
466 crate::common::RegisterField::<
467 11,
468 0x1,
469 1,
470 0,
471 ssicr::Spdp,
472 ssicr::Spdp,
473 Ssicr_SPEC,
474 crate::common::RW,
475 >::from_register(self, 0)
476 }
477
478 #[doc = "Serial Data Alignment"]
479 #[inline(always)]
480 pub fn sdta(
481 self,
482 ) -> crate::common::RegisterField<
483 10,
484 0x1,
485 1,
486 0,
487 ssicr::Sdta,
488 ssicr::Sdta,
489 Ssicr_SPEC,
490 crate::common::RW,
491 > {
492 crate::common::RegisterField::<
493 10,
494 0x1,
495 1,
496 0,
497 ssicr::Sdta,
498 ssicr::Sdta,
499 Ssicr_SPEC,
500 crate::common::RW,
501 >::from_register(self, 0)
502 }
503
504 #[doc = "Parallel Data Alignment"]
505 #[inline(always)]
506 pub fn pdta(
507 self,
508 ) -> crate::common::RegisterField<
509 9,
510 0x1,
511 1,
512 0,
513 ssicr::Pdta,
514 ssicr::Pdta,
515 Ssicr_SPEC,
516 crate::common::RW,
517 > {
518 crate::common::RegisterField::<
519 9,
520 0x1,
521 1,
522 0,
523 ssicr::Pdta,
524 ssicr::Pdta,
525 Ssicr_SPEC,
526 crate::common::RW,
527 >::from_register(self, 0)
528 }
529
530 #[doc = "Serial Data Delay"]
531 #[inline(always)]
532 pub fn del(
533 self,
534 ) -> crate::common::RegisterField<
535 8,
536 0x1,
537 1,
538 0,
539 ssicr::Del,
540 ssicr::Del,
541 Ssicr_SPEC,
542 crate::common::RW,
543 > {
544 crate::common::RegisterField::<
545 8,
546 0x1,
547 1,
548 0,
549 ssicr::Del,
550 ssicr::Del,
551 Ssicr_SPEC,
552 crate::common::RW,
553 >::from_register(self, 0)
554 }
555
556 #[doc = "Serial Oversampling Clock Division Ratio"]
557 #[inline(always)]
558 pub fn ckdv(
559 self,
560 ) -> crate::common::RegisterField<
561 4,
562 0xf,
563 1,
564 0,
565 ssicr::Ckdv,
566 ssicr::Ckdv,
567 Ssicr_SPEC,
568 crate::common::RW,
569 > {
570 crate::common::RegisterField::<
571 4,
572 0xf,
573 1,
574 0,
575 ssicr::Ckdv,
576 ssicr::Ckdv,
577 Ssicr_SPEC,
578 crate::common::RW,
579 >::from_register(self, 0)
580 }
581
582 #[doc = "Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing."]
583 #[inline(always)]
584 pub fn muen(
585 self,
586 ) -> crate::common::RegisterField<
587 3,
588 0x1,
589 1,
590 0,
591 ssicr::Muen,
592 ssicr::Muen,
593 Ssicr_SPEC,
594 crate::common::RW,
595 > {
596 crate::common::RegisterField::<
597 3,
598 0x1,
599 1,
600 0,
601 ssicr::Muen,
602 ssicr::Muen,
603 Ssicr_SPEC,
604 crate::common::RW,
605 >::from_register(self, 0)
606 }
607
608 #[doc = "Transmit Enable"]
609 #[inline(always)]
610 pub fn ten(
611 self,
612 ) -> crate::common::RegisterField<
613 1,
614 0x1,
615 1,
616 0,
617 ssicr::Ten,
618 ssicr::Ten,
619 Ssicr_SPEC,
620 crate::common::RW,
621 > {
622 crate::common::RegisterField::<
623 1,
624 0x1,
625 1,
626 0,
627 ssicr::Ten,
628 ssicr::Ten,
629 Ssicr_SPEC,
630 crate::common::RW,
631 >::from_register(self, 0)
632 }
633
634 #[doc = "Receive Enable"]
635 #[inline(always)]
636 pub fn ren(
637 self,
638 ) -> crate::common::RegisterField<
639 0,
640 0x1,
641 1,
642 0,
643 ssicr::Ren,
644 ssicr::Ren,
645 Ssicr_SPEC,
646 crate::common::RW,
647 > {
648 crate::common::RegisterField::<
649 0,
650 0x1,
651 1,
652 0,
653 ssicr::Ren,
654 ssicr::Ren,
655 Ssicr_SPEC,
656 crate::common::RW,
657 >::from_register(self, 0)
658 }
659}
660impl ::core::default::Default for Ssicr {
661 #[inline(always)]
662 fn default() -> Ssicr {
663 <crate::RegValueT<Ssicr_SPEC> as RegisterValue<_>>::new(0)
664 }
665}
666pub mod ssicr {
667
668 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
669 pub struct Cks_SPEC;
670 pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
671 impl Cks {
672 #[doc = "AUDIO_CLK input"]
673 pub const _0: Self = Self::new(0);
674
675 #[doc = "Setting prohibited"]
676 pub const _1: Self = Self::new(1);
677 }
678 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
679 pub struct Tuien_SPEC;
680 pub type Tuien = crate::EnumBitfieldStruct<u8, Tuien_SPEC>;
681 impl Tuien {
682 #[doc = "Disables an underflow interrupt."]
683 pub const _0: Self = Self::new(0);
684
685 #[doc = "Enables an underflow interrupt."]
686 pub const _1: Self = Self::new(1);
687 }
688 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
689 pub struct Toien_SPEC;
690 pub type Toien = crate::EnumBitfieldStruct<u8, Toien_SPEC>;
691 impl Toien {
692 #[doc = "Disables an overflow interrupt."]
693 pub const _0: Self = Self::new(0);
694
695 #[doc = "Enables an overflow interrupt."]
696 pub const _1: Self = Self::new(1);
697 }
698 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
699 pub struct Ruien_SPEC;
700 pub type Ruien = crate::EnumBitfieldStruct<u8, Ruien_SPEC>;
701 impl Ruien {
702 #[doc = "Disables an underflow interrupt."]
703 pub const _0: Self = Self::new(0);
704
705 #[doc = "Enables an underflow interrupt."]
706 pub const _1: Self = Self::new(1);
707 }
708 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
709 pub struct Roien_SPEC;
710 pub type Roien = crate::EnumBitfieldStruct<u8, Roien_SPEC>;
711 impl Roien {
712 #[doc = "Disables an overflow interrupt."]
713 pub const _0: Self = Self::new(0);
714
715 #[doc = "Enables an overflow interrupt."]
716 pub const _1: Self = Self::new(1);
717 }
718 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
719 pub struct Iien_SPEC;
720 pub type Iien = crate::EnumBitfieldStruct<u8, Iien_SPEC>;
721 impl Iien {
722 #[doc = "Disables an idle mode interrupt."]
723 pub const _0: Self = Self::new(0);
724
725 #[doc = "Enables an idle mode interrupt."]
726 pub const _1: Self = Self::new(1);
727 }
728 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
729 pub struct Chnl_SPEC;
730 pub type Chnl = crate::EnumBitfieldStruct<u8, Chnl_SPEC>;
731 impl Chnl {
732 #[doc = "One channel"]
733 pub const _00: Self = Self::new(0);
734 }
735 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
736 pub struct Dwl_SPEC;
737 pub type Dwl = crate::EnumBitfieldStruct<u8, Dwl_SPEC>;
738 impl Dwl {
739 #[doc = "8 bits"]
740 pub const _000: Self = Self::new(0);
741
742 #[doc = "16 bits"]
743 pub const _001: Self = Self::new(1);
744
745 #[doc = "18 bits"]
746 pub const _010: Self = Self::new(2);
747
748 #[doc = "20 bits"]
749 pub const _011: Self = Self::new(3);
750
751 #[doc = "22 bits"]
752 pub const _100: Self = Self::new(4);
753
754 #[doc = "24 bits"]
755 pub const _101: Self = Self::new(5);
756 }
757 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
758 pub struct Swl_SPEC;
759 pub type Swl = crate::EnumBitfieldStruct<u8, Swl_SPEC>;
760 impl Swl {
761 #[doc = "8 bits (serial bit clock frequency = 16fs )"]
762 pub const _000: Self = Self::new(0);
763
764 #[doc = "16 bits (serial bit clock frequency = 32fs )"]
765 pub const _001: Self = Self::new(1);
766
767 #[doc = "24 bits (serial bit clock frequency = 48fs )"]
768 pub const _010: Self = Self::new(2);
769
770 #[doc = "32 bits (serial bit clock frequency = 64fs )"]
771 pub const _011: Self = Self::new(3);
772 }
773 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
774 pub struct Swsd_SPEC;
775 pub type Swsd = crate::EnumBitfieldStruct<u8, Swsd_SPEC>;
776 impl Swsd {
777 #[doc = "Serial word select is input, slave mode."]
778 pub const _0: Self = Self::new(0);
779
780 #[doc = "Serial word select is output, master mode."]
781 pub const _1: Self = Self::new(1);
782 }
783 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
784 pub struct Sckp_SPEC;
785 pub type Sckp = crate::EnumBitfieldStruct<u8, Sckp_SPEC>;
786 impl Sckp {
787 #[doc = "SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge)."]
788 pub const _0: Self = Self::new(0);
789
790 #[doc = "SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge)."]
791 pub const _1: Self = Self::new(1);
792 }
793 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
794 pub struct Swsp_SPEC;
795 pub type Swsp = crate::EnumBitfieldStruct<u8, Swsp_SPEC>;
796 impl Swsp {
797 #[doc = "SSIWS is low for 1st channel, high for 2nd channel."]
798 pub const _0: Self = Self::new(0);
799
800 #[doc = "SSIWS is high for 1st channel, low for 2nd channel."]
801 pub const _1: Self = Self::new(1);
802 }
803 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
804 pub struct Spdp_SPEC;
805 pub type Spdp = crate::EnumBitfieldStruct<u8, Spdp_SPEC>;
806 impl Spdp {
807 #[doc = "Padding bits are low."]
808 pub const _0: Self = Self::new(0);
809
810 #[doc = "Padding bits are high."]
811 pub const _1: Self = Self::new(1);
812 }
813 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
814 pub struct Sdta_SPEC;
815 pub type Sdta = crate::EnumBitfieldStruct<u8, Sdta_SPEC>;
816 impl Sdta {
817 #[doc = "Transmitting and receiving in the order of serial data and padding bits"]
818 pub const _0: Self = Self::new(0);
819
820 #[doc = "Transmitting and receiving in the order of padding bits and serial data"]
821 pub const _1: Self = Self::new(1);
822 }
823 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
824 pub struct Pdta_SPEC;
825 pub type Pdta = crate::EnumBitfieldStruct<u8, Pdta_SPEC>;
826 impl Pdta {
827 #[doc = "The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits)"]
828 pub const _0: Self = Self::new(0);
829
830 #[doc = "The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits)"]
831 pub const _1: Self = Self::new(1);
832 }
833 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
834 pub struct Del_SPEC;
835 pub type Del = crate::EnumBitfieldStruct<u8, Del_SPEC>;
836 impl Del {
837 #[doc = "1 clock cycle delay between SSIWS and SSIDATA"]
838 pub const _0: Self = Self::new(0);
839
840 #[doc = "No delay between SSIWS and SSIDATA"]
841 pub const _1: Self = Self::new(1);
842 }
843 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
844 pub struct Ckdv_SPEC;
845 pub type Ckdv = crate::EnumBitfieldStruct<u8, Ckdv_SPEC>;
846 impl Ckdv {
847 #[doc = "CLK"]
848 pub const _0_X_0: Self = Self::new(0);
849
850 #[doc = "CLK/2"]
851 pub const _0_X_1: Self = Self::new(1);
852
853 #[doc = "CLK/4"]
854 pub const _0_X_2: Self = Self::new(2);
855
856 #[doc = "CLK/8"]
857 pub const _0_X_3: Self = Self::new(3);
858
859 #[doc = "CLK/16"]
860 pub const _0_X_4: Self = Self::new(4);
861
862 #[doc = "CLK/32"]
863 pub const _0_X_5: Self = Self::new(5);
864
865 #[doc = "CLK/64"]
866 pub const _0_X_6: Self = Self::new(6);
867
868 #[doc = "CLK/128"]
869 pub const _0_X_7: Self = Self::new(7);
870
871 #[doc = "CLK/6"]
872 pub const _0_X_8: Self = Self::new(8);
873
874 #[doc = "CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)"]
875 pub const _0_X_9: Self = Self::new(9);
876
877 #[doc = "CLK/24"]
878 pub const _0_X_A: Self = Self::new(10);
879
880 #[doc = "CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)"]
881 pub const _0_X_B: Self = Self::new(11);
882
883 #[doc = "CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)"]
884 pub const _0_X_C: Self = Self::new(12);
885 }
886 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
887 pub struct Muen_SPEC;
888 pub type Muen = crate::EnumBitfieldStruct<u8, Muen_SPEC>;
889 impl Muen {
890 #[doc = "This module is not muted."]
891 pub const _0: Self = Self::new(0);
892
893 #[doc = "This module is muted."]
894 pub const _1: Self = Self::new(1);
895 }
896 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
897 pub struct Ten_SPEC;
898 pub type Ten = crate::EnumBitfieldStruct<u8, Ten_SPEC>;
899 impl Ten {
900 #[doc = "Disables the transmit operation."]
901 pub const _0: Self = Self::new(0);
902
903 #[doc = "Enables the transmit operation."]
904 pub const _1: Self = Self::new(1);
905 }
906 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
907 pub struct Ren_SPEC;
908 pub type Ren = crate::EnumBitfieldStruct<u8, Ren_SPEC>;
909 impl Ren {
910 #[doc = "Disables the receive operation."]
911 pub const _0: Self = Self::new(0);
912
913 #[doc = "Enables the receive operation."]
914 pub const _1: Self = Self::new(1);
915 }
916}
917#[doc(hidden)]
918#[derive(Copy, Clone, Eq, PartialEq)]
919pub struct Ssisr_SPEC;
920impl crate::sealed::RegSpec for Ssisr_SPEC {
921 type DataType = u32;
922}
923
924#[doc = "Status Register"]
925pub type Ssisr = crate::RegValueT<Ssisr_SPEC>;
926
927impl Ssisr {
928 #[doc = "Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0."]
929 #[inline(always)]
930 pub fn tuirq(
931 self,
932 ) -> crate::common::RegisterField<
933 29,
934 0x1,
935 1,
936 0,
937 ssisr::Tuirq,
938 ssisr::Tuirq,
939 Ssisr_SPEC,
940 crate::common::RW,
941 > {
942 crate::common::RegisterField::<
943 29,
944 0x1,
945 1,
946 0,
947 ssisr::Tuirq,
948 ssisr::Tuirq,
949 Ssisr_SPEC,
950 crate::common::RW,
951 >::from_register(self, 0)
952 }
953
954 #[doc = "Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0."]
955 #[inline(always)]
956 pub fn toirq(
957 self,
958 ) -> crate::common::RegisterField<
959 28,
960 0x1,
961 1,
962 0,
963 ssisr::Toirq,
964 ssisr::Toirq,
965 Ssisr_SPEC,
966 crate::common::RW,
967 > {
968 crate::common::RegisterField::<
969 28,
970 0x1,
971 1,
972 0,
973 ssisr::Toirq,
974 ssisr::Toirq,
975 Ssisr_SPEC,
976 crate::common::RW,
977 >::from_register(self, 0)
978 }
979
980 #[doc = "Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0."]
981 #[inline(always)]
982 pub fn ruirq(
983 self,
984 ) -> crate::common::RegisterField<
985 27,
986 0x1,
987 1,
988 0,
989 ssisr::Ruirq,
990 ssisr::Ruirq,
991 Ssisr_SPEC,
992 crate::common::RW,
993 > {
994 crate::common::RegisterField::<
995 27,
996 0x1,
997 1,
998 0,
999 ssisr::Ruirq,
1000 ssisr::Ruirq,
1001 Ssisr_SPEC,
1002 crate::common::RW,
1003 >::from_register(self, 0)
1004 }
1005
1006 #[doc = "Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0."]
1007 #[inline(always)]
1008 pub fn roirq(
1009 self,
1010 ) -> crate::common::RegisterField<
1011 26,
1012 0x1,
1013 1,
1014 0,
1015 ssisr::Roirq,
1016 ssisr::Roirq,
1017 Ssisr_SPEC,
1018 crate::common::RW,
1019 > {
1020 crate::common::RegisterField::<
1021 26,
1022 0x1,
1023 1,
1024 0,
1025 ssisr::Roirq,
1026 ssisr::Roirq,
1027 Ssisr_SPEC,
1028 crate::common::RW,
1029 >::from_register(self, 0)
1030 }
1031
1032 #[doc = "Idle Mode Interrupt Status Flag"]
1033 #[inline(always)]
1034 pub fn iirq(
1035 self,
1036 ) -> crate::common::RegisterField<
1037 25,
1038 0x1,
1039 1,
1040 0,
1041 ssisr::Iirq,
1042 ssisr::Iirq,
1043 Ssisr_SPEC,
1044 crate::common::R,
1045 > {
1046 crate::common::RegisterField::<
1047 25,
1048 0x1,
1049 1,
1050 0,
1051 ssisr::Iirq,
1052 ssisr::Iirq,
1053 Ssisr_SPEC,
1054 crate::common::R,
1055 >::from_register(self, 0)
1056 }
1057
1058 #[doc = "Transmit Channel Number"]
1059 #[inline(always)]
1060 pub fn tchno(
1061 self,
1062 ) -> crate::common::RegisterField<5, 0x3, 1, 0, u8, u8, Ssisr_SPEC, crate::common::R> {
1063 crate::common::RegisterField::<5,0x3,1,0,u8,u8,Ssisr_SPEC,crate::common::R>::from_register(self,0)
1064 }
1065
1066 #[doc = "Transmit Serial Word Number"]
1067 #[inline(always)]
1068 pub fn tswno(self) -> crate::common::RegisterFieldBool<4, 1, 0, Ssisr_SPEC, crate::common::R> {
1069 crate::common::RegisterFieldBool::<4, 1, 0, Ssisr_SPEC, crate::common::R>::from_register(
1070 self, 0,
1071 )
1072 }
1073
1074 #[doc = "Receive Channel Number.These bits are read as 00b."]
1075 #[inline(always)]
1076 pub fn rchno(
1077 self,
1078 ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, Ssisr_SPEC, crate::common::R> {
1079 crate::common::RegisterField::<2,0x3,1,0,u8,u8,Ssisr_SPEC,crate::common::R>::from_register(self,0)
1080 }
1081
1082 #[doc = "Receive Serial Word Number"]
1083 #[inline(always)]
1084 pub fn rswno(self) -> crate::common::RegisterFieldBool<1, 1, 0, Ssisr_SPEC, crate::common::R> {
1085 crate::common::RegisterFieldBool::<1, 1, 0, Ssisr_SPEC, crate::common::R>::from_register(
1086 self, 0,
1087 )
1088 }
1089
1090 #[doc = "Idle Mode Status Flag"]
1091 #[inline(always)]
1092 pub fn idst(
1093 self,
1094 ) -> crate::common::RegisterField<
1095 0,
1096 0x1,
1097 1,
1098 0,
1099 ssisr::Idst,
1100 ssisr::Idst,
1101 Ssisr_SPEC,
1102 crate::common::R,
1103 > {
1104 crate::common::RegisterField::<
1105 0,
1106 0x1,
1107 1,
1108 0,
1109 ssisr::Idst,
1110 ssisr::Idst,
1111 Ssisr_SPEC,
1112 crate::common::R,
1113 >::from_register(self, 0)
1114 }
1115}
1116impl ::core::default::Default for Ssisr {
1117 #[inline(always)]
1118 fn default() -> Ssisr {
1119 <crate::RegValueT<Ssisr_SPEC> as RegisterValue<_>>::new(33554451)
1120 }
1121}
1122pub mod ssisr {
1123
1124 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1125 pub struct Tuirq_SPEC;
1126 pub type Tuirq = crate::EnumBitfieldStruct<u8, Tuirq_SPEC>;
1127 impl Tuirq {
1128 #[doc = "No transmit underflow has occurred."]
1129 pub const _0: Self = Self::new(0);
1130
1131 #[doc = "A transmit underflow has occurred."]
1132 pub const _1: Self = Self::new(1);
1133 }
1134 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1135 pub struct Toirq_SPEC;
1136 pub type Toirq = crate::EnumBitfieldStruct<u8, Toirq_SPEC>;
1137 impl Toirq {
1138 #[doc = "No transmit overflow has occurred."]
1139 pub const _0: Self = Self::new(0);
1140
1141 #[doc = "A transmit overflow has occurred."]
1142 pub const _1: Self = Self::new(1);
1143 }
1144 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1145 pub struct Ruirq_SPEC;
1146 pub type Ruirq = crate::EnumBitfieldStruct<u8, Ruirq_SPEC>;
1147 impl Ruirq {
1148 #[doc = "No receive underflow has occurred."]
1149 pub const _0: Self = Self::new(0);
1150
1151 #[doc = "A receive underflow has occurred."]
1152 pub const _1: Self = Self::new(1);
1153 }
1154 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1155 pub struct Roirq_SPEC;
1156 pub type Roirq = crate::EnumBitfieldStruct<u8, Roirq_SPEC>;
1157 impl Roirq {
1158 #[doc = "No receive overflow has occurred."]
1159 pub const _0: Self = Self::new(0);
1160
1161 #[doc = "A receive overflow has occurred."]
1162 pub const _1: Self = Self::new(1);
1163 }
1164 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1165 pub struct Iirq_SPEC;
1166 pub type Iirq = crate::EnumBitfieldStruct<u8, Iirq_SPEC>;
1167 impl Iirq {
1168 #[doc = "This module is not in idle state."]
1169 pub const _0: Self = Self::new(0);
1170
1171 #[doc = "This module is in idle state."]
1172 pub const _1: Self = Self::new(1);
1173 }
1174 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1175 pub struct Idst_SPEC;
1176 pub type Idst = crate::EnumBitfieldStruct<u8, Idst_SPEC>;
1177 impl Idst {
1178 #[doc = "Serial bus is operating."]
1179 pub const _0: Self = Self::new(0);
1180
1181 #[doc = "The current communication is stopped."]
1182 pub const _1: Self = Self::new(1);
1183 }
1184}
1185#[doc(hidden)]
1186#[derive(Copy, Clone, Eq, PartialEq)]
1187pub struct Ssifcr_SPEC;
1188impl crate::sealed::RegSpec for Ssifcr_SPEC {
1189 type DataType = u32;
1190}
1191
1192#[doc = "FIFO Control Register"]
1193pub type Ssifcr = crate::RegValueT<Ssifcr_SPEC>;
1194
1195impl Ssifcr {
1196 #[doc = "Oversampling Clock Enable"]
1197 #[inline(always)]
1198 pub fn aucke(
1199 self,
1200 ) -> crate::common::RegisterField<
1201 31,
1202 0x1,
1203 1,
1204 0,
1205 ssifcr::Aucke,
1206 ssifcr::Aucke,
1207 Ssifcr_SPEC,
1208 crate::common::RW,
1209 > {
1210 crate::common::RegisterField::<
1211 31,
1212 0x1,
1213 1,
1214 0,
1215 ssifcr::Aucke,
1216 ssifcr::Aucke,
1217 Ssifcr_SPEC,
1218 crate::common::RW,
1219 >::from_register(self, 0)
1220 }
1221
1222 #[doc = "SSI soft ware reset"]
1223 #[inline(always)]
1224 pub fn ssirst(
1225 self,
1226 ) -> crate::common::RegisterField<
1227 16,
1228 0x1,
1229 1,
1230 0,
1231 ssifcr::Ssirst,
1232 ssifcr::Ssirst,
1233 Ssifcr_SPEC,
1234 crate::common::RW,
1235 > {
1236 crate::common::RegisterField::<
1237 16,
1238 0x1,
1239 1,
1240 0,
1241 ssifcr::Ssirst,
1242 ssifcr::Ssirst,
1243 Ssifcr_SPEC,
1244 crate::common::RW,
1245 >::from_register(self, 0)
1246 }
1247
1248 #[doc = "Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set."]
1249 #[inline(always)]
1250 pub fn ttrg(
1251 self,
1252 ) -> crate::common::RegisterField<
1253 6,
1254 0x3,
1255 1,
1256 0,
1257 ssifcr::Ttrg,
1258 ssifcr::Ttrg,
1259 Ssifcr_SPEC,
1260 crate::common::RW,
1261 > {
1262 crate::common::RegisterField::<
1263 6,
1264 0x3,
1265 1,
1266 0,
1267 ssifcr::Ttrg,
1268 ssifcr::Ttrg,
1269 Ssifcr_SPEC,
1270 crate::common::RW,
1271 >::from_register(self, 0)
1272 }
1273
1274 #[doc = "Receive Data Trigger Number"]
1275 #[inline(always)]
1276 pub fn rtrg(
1277 self,
1278 ) -> crate::common::RegisterField<
1279 4,
1280 0x3,
1281 1,
1282 0,
1283 ssifcr::Rtrg,
1284 ssifcr::Rtrg,
1285 Ssifcr_SPEC,
1286 crate::common::RW,
1287 > {
1288 crate::common::RegisterField::<
1289 4,
1290 0x3,
1291 1,
1292 0,
1293 ssifcr::Rtrg,
1294 ssifcr::Rtrg,
1295 Ssifcr_SPEC,
1296 crate::common::RW,
1297 >::from_register(self, 0)
1298 }
1299
1300 #[doc = "Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit."]
1301 #[inline(always)]
1302 pub fn tie(
1303 self,
1304 ) -> crate::common::RegisterField<
1305 3,
1306 0x1,
1307 1,
1308 0,
1309 ssifcr::Tie,
1310 ssifcr::Tie,
1311 Ssifcr_SPEC,
1312 crate::common::RW,
1313 > {
1314 crate::common::RegisterField::<
1315 3,
1316 0x1,
1317 1,
1318 0,
1319 ssifcr::Tie,
1320 ssifcr::Tie,
1321 Ssifcr_SPEC,
1322 crate::common::RW,
1323 >::from_register(self, 0)
1324 }
1325
1326 #[doc = "Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit."]
1327 #[inline(always)]
1328 pub fn rie(
1329 self,
1330 ) -> crate::common::RegisterField<
1331 2,
1332 0x1,
1333 1,
1334 0,
1335 ssifcr::Rie,
1336 ssifcr::Rie,
1337 Ssifcr_SPEC,
1338 crate::common::RW,
1339 > {
1340 crate::common::RegisterField::<
1341 2,
1342 0x1,
1343 1,
1344 0,
1345 ssifcr::Rie,
1346 ssifcr::Rie,
1347 Ssifcr_SPEC,
1348 crate::common::RW,
1349 >::from_register(self, 0)
1350 }
1351
1352 #[doc = "Transmit FIFO Data Register Reset"]
1353 #[inline(always)]
1354 pub fn tfrst(
1355 self,
1356 ) -> crate::common::RegisterField<
1357 1,
1358 0x1,
1359 1,
1360 0,
1361 ssifcr::Tfrst,
1362 ssifcr::Tfrst,
1363 Ssifcr_SPEC,
1364 crate::common::RW,
1365 > {
1366 crate::common::RegisterField::<
1367 1,
1368 0x1,
1369 1,
1370 0,
1371 ssifcr::Tfrst,
1372 ssifcr::Tfrst,
1373 Ssifcr_SPEC,
1374 crate::common::RW,
1375 >::from_register(self, 0)
1376 }
1377
1378 #[doc = "Receive FIFO Data Register Reset"]
1379 #[inline(always)]
1380 pub fn rfrst(
1381 self,
1382 ) -> crate::common::RegisterField<
1383 0,
1384 0x1,
1385 1,
1386 0,
1387 ssifcr::Rfrst,
1388 ssifcr::Rfrst,
1389 Ssifcr_SPEC,
1390 crate::common::RW,
1391 > {
1392 crate::common::RegisterField::<
1393 0,
1394 0x1,
1395 1,
1396 0,
1397 ssifcr::Rfrst,
1398 ssifcr::Rfrst,
1399 Ssifcr_SPEC,
1400 crate::common::RW,
1401 >::from_register(self, 0)
1402 }
1403}
1404impl ::core::default::Default for Ssifcr {
1405 #[inline(always)]
1406 fn default() -> Ssifcr {
1407 <crate::RegValueT<Ssifcr_SPEC> as RegisterValue<_>>::new(0)
1408 }
1409}
1410pub mod ssifcr {
1411
1412 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1413 pub struct Aucke_SPEC;
1414 pub type Aucke = crate::EnumBitfieldStruct<u8, Aucke_SPEC>;
1415 impl Aucke {
1416 #[doc = "The oversampling clock is disabled."]
1417 pub const _0: Self = Self::new(0);
1418
1419 #[doc = "The oversampling clock is enabled."]
1420 pub const _1: Self = Self::new(1);
1421 }
1422 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1423 pub struct Ssirst_SPEC;
1424 pub type Ssirst = crate::EnumBitfieldStruct<u8, Ssirst_SPEC>;
1425 impl Ssirst {
1426 #[doc = "Clears the SSI software reset."]
1427 pub const _0: Self = Self::new(0);
1428
1429 #[doc = "initiates the SSI software reset."]
1430 pub const _1: Self = Self::new(1);
1431 }
1432 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1433 pub struct Ttrg_SPEC;
1434 pub type Ttrg = crate::EnumBitfieldStruct<u8, Ttrg_SPEC>;
1435 impl Ttrg {
1436 #[doc = "7 (1)"]
1437 pub const _00: Self = Self::new(0);
1438
1439 #[doc = "6 (2)"]
1440 pub const _01: Self = Self::new(1);
1441
1442 #[doc = "4 (4)"]
1443 pub const _10: Self = Self::new(2);
1444
1445 #[doc = "2 (6)"]
1446 pub const _11: Self = Self::new(3);
1447 }
1448 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1449 pub struct Rtrg_SPEC;
1450 pub type Rtrg = crate::EnumBitfieldStruct<u8, Rtrg_SPEC>;
1451 impl Rtrg {
1452 #[doc = "1"]
1453 pub const _00: Self = Self::new(0);
1454
1455 #[doc = "2"]
1456 pub const _01: Self = Self::new(1);
1457
1458 #[doc = "4"]
1459 pub const _10: Self = Self::new(2);
1460
1461 #[doc = "6"]
1462 pub const _11: Self = Self::new(3);
1463 }
1464 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1465 pub struct Tie_SPEC;
1466 pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
1467 impl Tie {
1468 #[doc = "Transmit data empty interrupt (TXI) request is disabled"]
1469 pub const _0: Self = Self::new(0);
1470
1471 #[doc = "Transmit data empty interrupt (TXI) request is enabled"]
1472 pub const _1: Self = Self::new(1);
1473 }
1474 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1475 pub struct Rie_SPEC;
1476 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
1477 impl Rie {
1478 #[doc = "Receive data full interrupt (RXI) request is disabled"]
1479 pub const _0: Self = Self::new(0);
1480
1481 #[doc = "Receive data full interrupt (RXI) request is enabled"]
1482 pub const _1: Self = Self::new(1);
1483 }
1484 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1485 pub struct Tfrst_SPEC;
1486 pub type Tfrst = crate::EnumBitfieldStruct<u8, Tfrst_SPEC>;
1487 impl Tfrst {
1488 #[doc = "Clears the transmit data FIFO reset."]
1489 pub const _0: Self = Self::new(0);
1490
1491 #[doc = "Initiates the transmit data FIFO reset."]
1492 pub const _1: Self = Self::new(1);
1493 }
1494 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1495 pub struct Rfrst_SPEC;
1496 pub type Rfrst = crate::EnumBitfieldStruct<u8, Rfrst_SPEC>;
1497 impl Rfrst {
1498 #[doc = "Clears the receive data FIFO reset."]
1499 pub const _0: Self = Self::new(0);
1500
1501 #[doc = "Initiates the receive data FIFO reset."]
1502 pub const _1: Self = Self::new(1);
1503 }
1504}
1505#[doc(hidden)]
1506#[derive(Copy, Clone, Eq, PartialEq)]
1507pub struct Ssifsr_SPEC;
1508impl crate::sealed::RegSpec for Ssifsr_SPEC {
1509 type DataType = u32;
1510}
1511
1512#[doc = "FIFO Status Register"]
1513pub type Ssifsr = crate::RegValueT<Ssifsr_SPEC>;
1514
1515impl Ssifsr {
1516 #[doc = "Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR)"]
1517 #[inline(always)]
1518 pub fn tdc(
1519 self,
1520 ) -> crate::common::RegisterField<24, 0xf, 1, 0, u8, u8, Ssifsr_SPEC, crate::common::R> {
1521 crate::common::RegisterField::<24,0xf,1,0,u8,u8,Ssifsr_SPEC,crate::common::R>::from_register(self,0)
1522 }
1523
1524 #[doc = "Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC\\[3:0\\]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs."]
1525 #[inline(always)]
1526 pub fn tde(
1527 self,
1528 ) -> crate::common::RegisterField<
1529 16,
1530 0x1,
1531 1,
1532 0,
1533 ssifsr::Tde,
1534 ssifsr::Tde,
1535 Ssifsr_SPEC,
1536 crate::common::RW,
1537 > {
1538 crate::common::RegisterField::<
1539 16,
1540 0x1,
1541 1,
1542 0,
1543 ssifsr::Tde,
1544 ssifsr::Tde,
1545 Ssifsr_SPEC,
1546 crate::common::RW,
1547 >::from_register(self, 0)
1548 }
1549
1550 #[doc = "Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR)"]
1551 #[inline(always)]
1552 pub fn rdc(
1553 self,
1554 ) -> crate::common::RegisterField<8, 0xf, 1, 0, u8, u8, Ssifsr_SPEC, crate::common::R> {
1555 crate::common::RegisterField::<8,0xf,1,0,u8,u8,Ssifsr_SPEC,crate::common::R>::from_register(self,0)
1556 }
1557
1558 #[doc = "Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC\\[3:0\\] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read."]
1559 #[inline(always)]
1560 pub fn rdf(
1561 self,
1562 ) -> crate::common::RegisterField<
1563 0,
1564 0x1,
1565 1,
1566 0,
1567 ssifsr::Rdf,
1568 ssifsr::Rdf,
1569 Ssifsr_SPEC,
1570 crate::common::RW,
1571 > {
1572 crate::common::RegisterField::<
1573 0,
1574 0x1,
1575 1,
1576 0,
1577 ssifsr::Rdf,
1578 ssifsr::Rdf,
1579 Ssifsr_SPEC,
1580 crate::common::RW,
1581 >::from_register(self, 0)
1582 }
1583}
1584impl ::core::default::Default for Ssifsr {
1585 #[inline(always)]
1586 fn default() -> Ssifsr {
1587 <crate::RegValueT<Ssifsr_SPEC> as RegisterValue<_>>::new(65536)
1588 }
1589}
1590pub mod ssifsr {
1591
1592 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1593 pub struct Tde_SPEC;
1594 pub type Tde = crate::EnumBitfieldStruct<u8, Tde_SPEC>;
1595 impl Tde {
1596 #[doc = "Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number."]
1597 pub const _0: Self = Self::new(0);
1598
1599 #[doc = "Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number."]
1600 pub const _1: Self = Self::new(1);
1601 }
1602 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1603 pub struct Rdf_SPEC;
1604 pub type Rdf = crate::EnumBitfieldStruct<u8, Rdf_SPEC>;
1605 impl Rdf {
1606 #[doc = "Number of received data bytes in SSIFRDR is less than the set receive trigger number."]
1607 pub const _0: Self = Self::new(0);
1608
1609 #[doc = "Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number."]
1610 pub const _1: Self = Self::new(1);
1611 }
1612}
1613#[doc(hidden)]
1614#[derive(Copy, Clone, Eq, PartialEq)]
1615pub struct Ssiftdr_SPEC;
1616impl crate::sealed::RegSpec for Ssiftdr_SPEC {
1617 type DataType = u32;
1618}
1619
1620#[doc = "Transmit FIFO Data Register"]
1621pub type Ssiftdr = crate::RegValueT<Ssiftdr_SPEC>;
1622
1623impl Ssiftdr {
1624 #[doc = "SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs."]
1625 #[inline(always)]
1626 pub fn ssiftdr(
1627 self,
1628 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Ssiftdr_SPEC, crate::common::W>
1629 {
1630 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Ssiftdr_SPEC,crate::common::W>::from_register(self,0)
1631 }
1632}
1633impl ::core::default::Default for Ssiftdr {
1634 #[inline(always)]
1635 fn default() -> Ssiftdr {
1636 <crate::RegValueT<Ssiftdr_SPEC> as RegisterValue<_>>::new(0)
1637 }
1638}
1639
1640#[doc(hidden)]
1641#[derive(Copy, Clone, Eq, PartialEq)]
1642pub struct Ssifrdr_SPEC;
1643impl crate::sealed::RegSpec for Ssifrdr_SPEC {
1644 type DataType = u32;
1645}
1646
1647#[doc = "Receive FIFO Data Register"]
1648pub type Ssifrdr = crate::RegValueT<Ssifrdr_SPEC>;
1649
1650impl Ssifrdr {
1651 #[doc = "SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data."]
1652 #[inline(always)]
1653 pub fn ssifrdr(
1654 self,
1655 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Ssifrdr_SPEC, crate::common::R>
1656 {
1657 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Ssifrdr_SPEC,crate::common::R>::from_register(self,0)
1658 }
1659}
1660impl ::core::default::Default for Ssifrdr {
1661 #[inline(always)]
1662 fn default() -> Ssifrdr {
1663 <crate::RegValueT<Ssifrdr_SPEC> as RegisterValue<_>>::new(0)
1664 }
1665}
1666
1667#[doc(hidden)]
1668#[derive(Copy, Clone, Eq, PartialEq)]
1669pub struct Ssiofr_SPEC;
1670impl crate::sealed::RegSpec for Ssiofr_SPEC {
1671 type DataType = u32;
1672}
1673
1674#[doc = "Audio Format Register"]
1675pub type Ssiofr = crate::RegValueT<Ssiofr_SPEC>;
1676
1677impl Ssiofr {
1678 #[doc = "Whether to Enable Stopping BCK Output When SSIE is in Idle Status"]
1679 #[inline(always)]
1680 pub fn bckastp(
1681 self,
1682 ) -> crate::common::RegisterField<
1683 9,
1684 0x1,
1685 1,
1686 0,
1687 ssiofr::Bckastp,
1688 ssiofr::Bckastp,
1689 Ssiofr_SPEC,
1690 crate::common::RW,
1691 > {
1692 crate::common::RegisterField::<
1693 9,
1694 0x1,
1695 1,
1696 0,
1697 ssiofr::Bckastp,
1698 ssiofr::Bckastp,
1699 Ssiofr_SPEC,
1700 crate::common::RW,
1701 >::from_register(self, 0)
1702 }
1703
1704 #[doc = "Whether to Enable LRCK/FS Continuation"]
1705 #[inline(always)]
1706 pub fn lrcont(
1707 self,
1708 ) -> crate::common::RegisterField<
1709 8,
1710 0x1,
1711 1,
1712 0,
1713 ssiofr::Lrcont,
1714 ssiofr::Lrcont,
1715 Ssiofr_SPEC,
1716 crate::common::RW,
1717 > {
1718 crate::common::RegisterField::<
1719 8,
1720 0x1,
1721 1,
1722 0,
1723 ssiofr::Lrcont,
1724 ssiofr::Lrcont,
1725 Ssiofr_SPEC,
1726 crate::common::RW,
1727 >::from_register(self, 0)
1728 }
1729
1730 #[doc = "Audio Format Select"]
1731 #[inline(always)]
1732 pub fn omod(
1733 self,
1734 ) -> crate::common::RegisterField<
1735 0,
1736 0x3,
1737 1,
1738 0,
1739 ssiofr::Omod,
1740 ssiofr::Omod,
1741 Ssiofr_SPEC,
1742 crate::common::RW,
1743 > {
1744 crate::common::RegisterField::<
1745 0,
1746 0x3,
1747 1,
1748 0,
1749 ssiofr::Omod,
1750 ssiofr::Omod,
1751 Ssiofr_SPEC,
1752 crate::common::RW,
1753 >::from_register(self, 0)
1754 }
1755}
1756impl ::core::default::Default for Ssiofr {
1757 #[inline(always)]
1758 fn default() -> Ssiofr {
1759 <crate::RegValueT<Ssiofr_SPEC> as RegisterValue<_>>::new(0)
1760 }
1761}
1762pub mod ssiofr {
1763
1764 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1765 pub struct Bckastp_SPEC;
1766 pub type Bckastp = crate::EnumBitfieldStruct<u8, Bckastp_SPEC>;
1767 impl Bckastp {
1768 #[doc = "Always outputs BCK to the SSIBCK pin."]
1769 pub const _0: Self = Self::new(0);
1770
1771 #[doc = "Automatically controls output of BCK to the SSIBCK pin."]
1772 pub const _1: Self = Self::new(1);
1773 }
1774 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1775 pub struct Lrcont_SPEC;
1776 pub type Lrcont = crate::EnumBitfieldStruct<u8, Lrcont_SPEC>;
1777 impl Lrcont {
1778 #[doc = "Disables LRCK/FS continuation."]
1779 pub const _0: Self = Self::new(0);
1780
1781 #[doc = "Enables LRCK/FS continuation."]
1782 pub const _1: Self = Self::new(1);
1783 }
1784 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1785 pub struct Omod_SPEC;
1786 pub type Omod = crate::EnumBitfieldStruct<u8, Omod_SPEC>;
1787 impl Omod {
1788 #[doc = "I2S format"]
1789 pub const _00: Self = Self::new(0);
1790
1791 #[doc = "TDM format"]
1792 pub const _01: Self = Self::new(1);
1793
1794 #[doc = "Monaural format"]
1795 pub const _10: Self = Self::new(2);
1796
1797 #[doc = "Setting prohibited."]
1798 pub const _11: Self = Self::new(3);
1799 }
1800}
1801#[doc(hidden)]
1802#[derive(Copy, Clone, Eq, PartialEq)]
1803pub struct Ssiscr_SPEC;
1804impl crate::sealed::RegSpec for Ssiscr_SPEC {
1805 type DataType = u32;
1806}
1807
1808#[doc = "Status Control Register"]
1809pub type Ssiscr = crate::RegValueT<Ssiscr_SPEC>;
1810
1811impl Ssiscr {
1812 #[doc = "TDE Setting Condition Select"]
1813 #[inline(always)]
1814 pub fn tdes(
1815 self,
1816 ) -> crate::common::RegisterField<
1817 8,
1818 0x1f,
1819 1,
1820 0,
1821 ssiscr::Tdes,
1822 ssiscr::Tdes,
1823 Ssiscr_SPEC,
1824 crate::common::RW,
1825 > {
1826 crate::common::RegisterField::<
1827 8,
1828 0x1f,
1829 1,
1830 0,
1831 ssiscr::Tdes,
1832 ssiscr::Tdes,
1833 Ssiscr_SPEC,
1834 crate::common::RW,
1835 >::from_register(self, 0)
1836 }
1837
1838 #[doc = "RDF Setting Condition Select"]
1839 #[inline(always)]
1840 pub fn rdfs(
1841 self,
1842 ) -> crate::common::RegisterField<
1843 0,
1844 0x1f,
1845 1,
1846 0,
1847 ssiscr::Rdfs,
1848 ssiscr::Rdfs,
1849 Ssiscr_SPEC,
1850 crate::common::RW,
1851 > {
1852 crate::common::RegisterField::<
1853 0,
1854 0x1f,
1855 1,
1856 0,
1857 ssiscr::Rdfs,
1858 ssiscr::Rdfs,
1859 Ssiscr_SPEC,
1860 crate::common::RW,
1861 >::from_register(self, 0)
1862 }
1863}
1864impl ::core::default::Default for Ssiscr {
1865 #[inline(always)]
1866 fn default() -> Ssiscr {
1867 <crate::RegValueT<Ssiscr_SPEC> as RegisterValue<_>>::new(0)
1868 }
1869}
1870pub mod ssiscr {
1871
1872 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1873 pub struct Tdes_SPEC;
1874 pub type Tdes = crate::EnumBitfieldStruct<u8, Tdes_SPEC>;
1875 impl Tdes {
1876 #[doc = "SSIFTDR has one stage or more free space"]
1877 pub const _00000: Self = Self::new(0);
1878
1879 #[doc = "SSIFTDR has two stages or more free space (snip)"]
1880 pub const _00001: Self = Self::new(1);
1881
1882 #[doc = "SSIFTDR has thirty-one stages or more free space"]
1883 pub const _11110: Self = Self::new(30);
1884
1885 #[doc = "SSIFTDR has thirty-two stages or more free space."]
1886 pub const _11111: Self = Self::new(31);
1887 }
1888 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1889 pub struct Rdfs_SPEC;
1890 pub type Rdfs = crate::EnumBitfieldStruct<u8, Rdfs_SPEC>;
1891 impl Rdfs {
1892 #[doc = "SSIFRDR has one stage or more data size"]
1893 pub const _00000: Self = Self::new(0);
1894
1895 #[doc = "SSIFRDR has two stages or more data size (snip)"]
1896 pub const _00001: Self = Self::new(1);
1897
1898 #[doc = "SSIFRDR has thirty-one stages or more data size"]
1899 pub const _11110: Self = Self::new(30);
1900
1901 #[doc = "SSIFRDR has thirty-two stages or more data size."]
1902 pub const _11111: Self = Self::new(31);
1903 }
1904}