ra6m2_pac/
gpt_odc.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"PWM Delay Generation Circuit"]
28unsafe impl ::core::marker::Send for super::GptOdc {}
29unsafe impl ::core::marker::Sync for super::GptOdc {}
30impl super::GptOdc {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "PWM Output Delay Control Register"]
38    #[inline(always)]
39    pub const fn gtdlycr(
40        &self,
41    ) -> &'static crate::common::Reg<self::Gtdlycr_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Gtdlycr_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "PWM Output Delay Control Register2"]
50    #[inline(always)]
51    pub const fn gtdlycr2(
52        &self,
53    ) -> &'static crate::common::Reg<self::Gtdlycr2_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::Gtdlycr2_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(2usize),
57            )
58        }
59    }
60
61    #[doc = "GTIOC%sA Rising Output Delay Register"]
62    #[inline(always)]
63    pub const fn gtdlyra(
64        &self,
65    ) -> &'static crate::common::ClusterRegisterArray<
66        crate::common::Reg<self::Gtdlyra_SPEC, crate::common::RW>,
67        4,
68        0x4,
69    > {
70        unsafe {
71            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x18usize))
72        }
73    }
74    #[inline(always)]
75    pub const fn gtdlyr0a(
76        &self,
77    ) -> &'static crate::common::Reg<self::Gtdlyra_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::Gtdlyra_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(0x18usize),
81            )
82        }
83    }
84    #[inline(always)]
85    pub const fn gtdlyr1a(
86        &self,
87    ) -> &'static crate::common::Reg<self::Gtdlyra_SPEC, crate::common::RW> {
88        unsafe {
89            crate::common::Reg::<self::Gtdlyra_SPEC, crate::common::RW>::from_ptr(
90                self._svd2pac_as_ptr().add(0x1cusize),
91            )
92        }
93    }
94    #[inline(always)]
95    pub const fn gtdlyr2a(
96        &self,
97    ) -> &'static crate::common::Reg<self::Gtdlyra_SPEC, crate::common::RW> {
98        unsafe {
99            crate::common::Reg::<self::Gtdlyra_SPEC, crate::common::RW>::from_ptr(
100                self._svd2pac_as_ptr().add(0x20usize),
101            )
102        }
103    }
104    #[inline(always)]
105    pub const fn gtdlyr3a(
106        &self,
107    ) -> &'static crate::common::Reg<self::Gtdlyra_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::Gtdlyra_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(0x24usize),
111            )
112        }
113    }
114
115    #[doc = "GTIOC%sB Rising Output Delay Register"]
116    #[inline(always)]
117    pub const fn gtdlyrb(
118        &self,
119    ) -> &'static crate::common::ClusterRegisterArray<
120        crate::common::Reg<self::Gtdlyrb_SPEC, crate::common::RW>,
121        4,
122        0x4,
123    > {
124        unsafe {
125            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1ausize))
126        }
127    }
128    #[inline(always)]
129    pub const fn gtdlyr0b(
130        &self,
131    ) -> &'static crate::common::Reg<self::Gtdlyrb_SPEC, crate::common::RW> {
132        unsafe {
133            crate::common::Reg::<self::Gtdlyrb_SPEC, crate::common::RW>::from_ptr(
134                self._svd2pac_as_ptr().add(0x1ausize),
135            )
136        }
137    }
138    #[inline(always)]
139    pub const fn gtdlyr1b(
140        &self,
141    ) -> &'static crate::common::Reg<self::Gtdlyrb_SPEC, crate::common::RW> {
142        unsafe {
143            crate::common::Reg::<self::Gtdlyrb_SPEC, crate::common::RW>::from_ptr(
144                self._svd2pac_as_ptr().add(0x1eusize),
145            )
146        }
147    }
148    #[inline(always)]
149    pub const fn gtdlyr2b(
150        &self,
151    ) -> &'static crate::common::Reg<self::Gtdlyrb_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Gtdlyrb_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0x22usize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn gtdlyr3b(
160        &self,
161    ) -> &'static crate::common::Reg<self::Gtdlyrb_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::Gtdlyrb_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(0x26usize),
165            )
166        }
167    }
168
169    #[doc = "GTIOC%sA Falling Output Delay Register"]
170    #[inline(always)]
171    pub const fn gtdlyfa(
172        &self,
173    ) -> &'static crate::common::ClusterRegisterArray<
174        crate::common::Reg<self::Gtdlyfa_SPEC, crate::common::RW>,
175        4,
176        0x4,
177    > {
178        unsafe {
179            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x28usize))
180        }
181    }
182    #[inline(always)]
183    pub const fn gtdlyf0a(
184        &self,
185    ) -> &'static crate::common::Reg<self::Gtdlyfa_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::Gtdlyfa_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(0x28usize),
189            )
190        }
191    }
192    #[inline(always)]
193    pub const fn gtdlyf1a(
194        &self,
195    ) -> &'static crate::common::Reg<self::Gtdlyfa_SPEC, crate::common::RW> {
196        unsafe {
197            crate::common::Reg::<self::Gtdlyfa_SPEC, crate::common::RW>::from_ptr(
198                self._svd2pac_as_ptr().add(0x2cusize),
199            )
200        }
201    }
202    #[inline(always)]
203    pub const fn gtdlyf2a(
204        &self,
205    ) -> &'static crate::common::Reg<self::Gtdlyfa_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Gtdlyfa_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0x30usize),
209            )
210        }
211    }
212    #[inline(always)]
213    pub const fn gtdlyf3a(
214        &self,
215    ) -> &'static crate::common::Reg<self::Gtdlyfa_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Gtdlyfa_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(0x34usize),
219            )
220        }
221    }
222
223    #[doc = "GTIOC%sB Falling Output Delay Register"]
224    #[inline(always)]
225    pub const fn gtdlyfb(
226        &self,
227    ) -> &'static crate::common::ClusterRegisterArray<
228        crate::common::Reg<self::Gtdlyfb_SPEC, crate::common::RW>,
229        4,
230        0x4,
231    > {
232        unsafe {
233            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2ausize))
234        }
235    }
236    #[inline(always)]
237    pub const fn gtdlyf0b(
238        &self,
239    ) -> &'static crate::common::Reg<self::Gtdlyfb_SPEC, crate::common::RW> {
240        unsafe {
241            crate::common::Reg::<self::Gtdlyfb_SPEC, crate::common::RW>::from_ptr(
242                self._svd2pac_as_ptr().add(0x2ausize),
243            )
244        }
245    }
246    #[inline(always)]
247    pub const fn gtdlyf1b(
248        &self,
249    ) -> &'static crate::common::Reg<self::Gtdlyfb_SPEC, crate::common::RW> {
250        unsafe {
251            crate::common::Reg::<self::Gtdlyfb_SPEC, crate::common::RW>::from_ptr(
252                self._svd2pac_as_ptr().add(0x2eusize),
253            )
254        }
255    }
256    #[inline(always)]
257    pub const fn gtdlyf2b(
258        &self,
259    ) -> &'static crate::common::Reg<self::Gtdlyfb_SPEC, crate::common::RW> {
260        unsafe {
261            crate::common::Reg::<self::Gtdlyfb_SPEC, crate::common::RW>::from_ptr(
262                self._svd2pac_as_ptr().add(0x32usize),
263            )
264        }
265    }
266    #[inline(always)]
267    pub const fn gtdlyf3b(
268        &self,
269    ) -> &'static crate::common::Reg<self::Gtdlyfb_SPEC, crate::common::RW> {
270        unsafe {
271            crate::common::Reg::<self::Gtdlyfb_SPEC, crate::common::RW>::from_ptr(
272                self._svd2pac_as_ptr().add(0x36usize),
273            )
274        }
275    }
276}
277#[doc(hidden)]
278#[derive(Copy, Clone, Eq, PartialEq)]
279pub struct Gtdlycr_SPEC;
280impl crate::sealed::RegSpec for Gtdlycr_SPEC {
281    type DataType = u16;
282}
283
284#[doc = "PWM Output Delay Control Register"]
285pub type Gtdlycr = crate::RegValueT<Gtdlycr_SPEC>;
286
287impl Gtdlycr {
288    #[doc = "PWM Delay Generation Circuit Reset"]
289    #[inline(always)]
290    pub fn dlyrst(
291        self,
292    ) -> crate::common::RegisterField<
293        1,
294        0x1,
295        1,
296        0,
297        gtdlycr::Dlyrst,
298        gtdlycr::Dlyrst,
299        Gtdlycr_SPEC,
300        crate::common::RW,
301    > {
302        crate::common::RegisterField::<
303            1,
304            0x1,
305            1,
306            0,
307            gtdlycr::Dlyrst,
308            gtdlycr::Dlyrst,
309            Gtdlycr_SPEC,
310            crate::common::RW,
311        >::from_register(self, 0)
312    }
313
314    #[doc = "DLL Operation Enable"]
315    #[inline(always)]
316    pub fn dllen(
317        self,
318    ) -> crate::common::RegisterField<
319        0,
320        0x1,
321        1,
322        0,
323        gtdlycr::Dllen,
324        gtdlycr::Dllen,
325        Gtdlycr_SPEC,
326        crate::common::RW,
327    > {
328        crate::common::RegisterField::<
329            0,
330            0x1,
331            1,
332            0,
333            gtdlycr::Dllen,
334            gtdlycr::Dllen,
335            Gtdlycr_SPEC,
336            crate::common::RW,
337        >::from_register(self, 0)
338    }
339}
340impl ::core::default::Default for Gtdlycr {
341    #[inline(always)]
342    fn default() -> Gtdlycr {
343        <crate::RegValueT<Gtdlycr_SPEC> as RegisterValue<_>>::new(0)
344    }
345}
346pub mod gtdlycr {
347
348    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
349    pub struct Dlyrst_SPEC;
350    pub type Dlyrst = crate::EnumBitfieldStruct<u8, Dlyrst_SPEC>;
351    impl Dlyrst {
352        #[doc = "Normal operation"]
353        pub const _0: Self = Self::new(0);
354
355        #[doc = "Reset"]
356        pub const _1: Self = Self::new(1);
357    }
358    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
359    pub struct Dllen_SPEC;
360    pub type Dllen = crate::EnumBitfieldStruct<u8, Dllen_SPEC>;
361    impl Dllen {
362        #[doc = "Disable DLL operation"]
363        pub const _0: Self = Self::new(0);
364
365        #[doc = "Enable DLL operation"]
366        pub const _1: Self = Self::new(1);
367    }
368}
369#[doc(hidden)]
370#[derive(Copy, Clone, Eq, PartialEq)]
371pub struct Gtdlycr2_SPEC;
372impl crate::sealed::RegSpec for Gtdlycr2_SPEC {
373    type DataType = u16;
374}
375
376#[doc = "PWM Output Delay Control Register2"]
377pub type Gtdlycr2 = crate::RegValueT<Gtdlycr2_SPEC>;
378
379impl Gtdlycr2 {
380    #[doc = "PWM Delay Generation Circuit enable for channel 3"]
381    #[inline(always)]
382    pub fn dlyen3(
383        self,
384    ) -> crate::common::RegisterField<
385        11,
386        0x1,
387        1,
388        0,
389        gtdlycr2::Dlyen3,
390        gtdlycr2::Dlyen3,
391        Gtdlycr2_SPEC,
392        crate::common::RW,
393    > {
394        crate::common::RegisterField::<
395            11,
396            0x1,
397            1,
398            0,
399            gtdlycr2::Dlyen3,
400            gtdlycr2::Dlyen3,
401            Gtdlycr2_SPEC,
402            crate::common::RW,
403        >::from_register(self, 0)
404    }
405
406    #[doc = "PWM Delay Generation Circuit enable for channel 2"]
407    #[inline(always)]
408    pub fn dlyen2(
409        self,
410    ) -> crate::common::RegisterField<
411        10,
412        0x1,
413        1,
414        0,
415        gtdlycr2::Dlyen2,
416        gtdlycr2::Dlyen2,
417        Gtdlycr2_SPEC,
418        crate::common::RW,
419    > {
420        crate::common::RegisterField::<
421            10,
422            0x1,
423            1,
424            0,
425            gtdlycr2::Dlyen2,
426            gtdlycr2::Dlyen2,
427            Gtdlycr2_SPEC,
428            crate::common::RW,
429        >::from_register(self, 0)
430    }
431
432    #[doc = "PWM Delay Generation Circuit enable for channel 1"]
433    #[inline(always)]
434    pub fn dlyen1(
435        self,
436    ) -> crate::common::RegisterField<
437        9,
438        0x1,
439        1,
440        0,
441        gtdlycr2::Dlyen1,
442        gtdlycr2::Dlyen1,
443        Gtdlycr2_SPEC,
444        crate::common::RW,
445    > {
446        crate::common::RegisterField::<
447            9,
448            0x1,
449            1,
450            0,
451            gtdlycr2::Dlyen1,
452            gtdlycr2::Dlyen1,
453            Gtdlycr2_SPEC,
454            crate::common::RW,
455        >::from_register(self, 0)
456    }
457
458    #[doc = "PWM Delay Generation Circuit enable for channel 0"]
459    #[inline(always)]
460    pub fn dlyen0(
461        self,
462    ) -> crate::common::RegisterField<
463        8,
464        0x1,
465        1,
466        0,
467        gtdlycr2::Dlyen0,
468        gtdlycr2::Dlyen0,
469        Gtdlycr2_SPEC,
470        crate::common::RW,
471    > {
472        crate::common::RegisterField::<
473            8,
474            0x1,
475            1,
476            0,
477            gtdlycr2::Dlyen0,
478            gtdlycr2::Dlyen0,
479            Gtdlycr2_SPEC,
480            crate::common::RW,
481        >::from_register(self, 0)
482    }
483
484    #[doc = "PWM Delay Generation Circuit bypass for channel 3"]
485    #[inline(always)]
486    pub fn dlybs3(
487        self,
488    ) -> crate::common::RegisterField<
489        3,
490        0x1,
491        1,
492        0,
493        gtdlycr2::Dlybs3,
494        gtdlycr2::Dlybs3,
495        Gtdlycr2_SPEC,
496        crate::common::RW,
497    > {
498        crate::common::RegisterField::<
499            3,
500            0x1,
501            1,
502            0,
503            gtdlycr2::Dlybs3,
504            gtdlycr2::Dlybs3,
505            Gtdlycr2_SPEC,
506            crate::common::RW,
507        >::from_register(self, 0)
508    }
509
510    #[doc = "PWM Delay Generation Circuit bypass for channel 2"]
511    #[inline(always)]
512    pub fn dlybs2(
513        self,
514    ) -> crate::common::RegisterField<
515        2,
516        0x1,
517        1,
518        0,
519        gtdlycr2::Dlybs2,
520        gtdlycr2::Dlybs2,
521        Gtdlycr2_SPEC,
522        crate::common::RW,
523    > {
524        crate::common::RegisterField::<
525            2,
526            0x1,
527            1,
528            0,
529            gtdlycr2::Dlybs2,
530            gtdlycr2::Dlybs2,
531            Gtdlycr2_SPEC,
532            crate::common::RW,
533        >::from_register(self, 0)
534    }
535
536    #[doc = "PWM Delay Generation Circuit bypass for channel 1"]
537    #[inline(always)]
538    pub fn dlybs1(
539        self,
540    ) -> crate::common::RegisterField<
541        1,
542        0x1,
543        1,
544        0,
545        gtdlycr2::Dlybs1,
546        gtdlycr2::Dlybs1,
547        Gtdlycr2_SPEC,
548        crate::common::RW,
549    > {
550        crate::common::RegisterField::<
551            1,
552            0x1,
553            1,
554            0,
555            gtdlycr2::Dlybs1,
556            gtdlycr2::Dlybs1,
557            Gtdlycr2_SPEC,
558            crate::common::RW,
559        >::from_register(self, 0)
560    }
561
562    #[doc = "PWM Delay Generation Circuit bypass for channel 0"]
563    #[inline(always)]
564    pub fn dlybs0(
565        self,
566    ) -> crate::common::RegisterField<
567        0,
568        0x1,
569        1,
570        0,
571        gtdlycr2::Dlybs0,
572        gtdlycr2::Dlybs0,
573        Gtdlycr2_SPEC,
574        crate::common::RW,
575    > {
576        crate::common::RegisterField::<
577            0,
578            0x1,
579            1,
580            0,
581            gtdlycr2::Dlybs0,
582            gtdlycr2::Dlybs0,
583            Gtdlycr2_SPEC,
584            crate::common::RW,
585        >::from_register(self, 0)
586    }
587}
588impl ::core::default::Default for Gtdlycr2 {
589    #[inline(always)]
590    fn default() -> Gtdlycr2 {
591        <crate::RegValueT<Gtdlycr2_SPEC> as RegisterValue<_>>::new(0)
592    }
593}
594pub mod gtdlycr2 {
595
596    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
597    pub struct Dlyen3_SPEC;
598    pub type Dlyen3 = crate::EnumBitfieldStruct<u8, Dlyen3_SPEC>;
599    impl Dlyen3 {
600        #[doc = "Enable delay generation circuit of channel 3"]
601        pub const _0: Self = Self::new(0);
602
603        #[doc = "Disable delay generation circuit of channel 3"]
604        pub const _1: Self = Self::new(1);
605    }
606    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
607    pub struct Dlyen2_SPEC;
608    pub type Dlyen2 = crate::EnumBitfieldStruct<u8, Dlyen2_SPEC>;
609    impl Dlyen2 {
610        #[doc = "Enable delay generation circuit of channel 2"]
611        pub const _0: Self = Self::new(0);
612
613        #[doc = "Disable delay generation circuit of channel 2."]
614        pub const _1: Self = Self::new(1);
615    }
616    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
617    pub struct Dlyen1_SPEC;
618    pub type Dlyen1 = crate::EnumBitfieldStruct<u8, Dlyen1_SPEC>;
619    impl Dlyen1 {
620        #[doc = "Enable delay generation circuit of channel 1"]
621        pub const _0: Self = Self::new(0);
622
623        #[doc = "Disable delay generation circuit of channel 1."]
624        pub const _1: Self = Self::new(1);
625    }
626    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
627    pub struct Dlyen0_SPEC;
628    pub type Dlyen0 = crate::EnumBitfieldStruct<u8, Dlyen0_SPEC>;
629    impl Dlyen0 {
630        #[doc = "Enable delay generation circuit of channel 0"]
631        pub const _0: Self = Self::new(0);
632
633        #[doc = "Disable delay generation circuit of channel 0."]
634        pub const _1: Self = Self::new(1);
635    }
636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
637    pub struct Dlybs3_SPEC;
638    pub type Dlybs3 = crate::EnumBitfieldStruct<u8, Dlybs3_SPEC>;
639    impl Dlybs3 {
640        #[doc = "Bypass delay generation circuit of channel 3"]
641        pub const _0: Self = Self::new(0);
642
643        #[doc = "Do not bypass delay generation circuit of channel 3."]
644        pub const _1: Self = Self::new(1);
645    }
646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
647    pub struct Dlybs2_SPEC;
648    pub type Dlybs2 = crate::EnumBitfieldStruct<u8, Dlybs2_SPEC>;
649    impl Dlybs2 {
650        #[doc = "Bypass delay generation circuit of channel 2"]
651        pub const _0: Self = Self::new(0);
652
653        #[doc = "Do not bypass delay generation circuit of channel 2."]
654        pub const _1: Self = Self::new(1);
655    }
656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
657    pub struct Dlybs1_SPEC;
658    pub type Dlybs1 = crate::EnumBitfieldStruct<u8, Dlybs1_SPEC>;
659    impl Dlybs1 {
660        #[doc = "Bypass delay generation circuit of channel 1"]
661        pub const _0: Self = Self::new(0);
662
663        #[doc = "Do not bypass delay generation circuit of channel 1."]
664        pub const _1: Self = Self::new(1);
665    }
666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
667    pub struct Dlybs0_SPEC;
668    pub type Dlybs0 = crate::EnumBitfieldStruct<u8, Dlybs0_SPEC>;
669    impl Dlybs0 {
670        #[doc = "Bypass delay generation circuit of channel 0"]
671        pub const _0: Self = Self::new(0);
672
673        #[doc = "Do not bypass delay generation circuit of channel 0."]
674        pub const _1: Self = Self::new(1);
675    }
676}
677#[doc(hidden)]
678#[derive(Copy, Clone, Eq, PartialEq)]
679pub struct Gtdlyra_SPEC;
680impl crate::sealed::RegSpec for Gtdlyra_SPEC {
681    type DataType = u16;
682}
683
684#[doc = "GTIOC%sA Rising Output Delay Register"]
685pub type Gtdlyra = crate::RegValueT<Gtdlyra_SPEC>;
686
687impl Gtdlyra {
688    #[doc = "GTIOCnA Output Rising Edge Delay Setting"]
689    #[inline(always)]
690    pub fn dly(
691        self,
692    ) -> crate::common::RegisterField<
693        0,
694        0x1f,
695        1,
696        0,
697        gtdlyra::Dly,
698        gtdlyra::Dly,
699        Gtdlyra_SPEC,
700        crate::common::RW,
701    > {
702        crate::common::RegisterField::<
703            0,
704            0x1f,
705            1,
706            0,
707            gtdlyra::Dly,
708            gtdlyra::Dly,
709            Gtdlyra_SPEC,
710            crate::common::RW,
711        >::from_register(self, 0)
712    }
713}
714impl ::core::default::Default for Gtdlyra {
715    #[inline(always)]
716    fn default() -> Gtdlyra {
717        <crate::RegValueT<Gtdlyra_SPEC> as RegisterValue<_>>::new(0)
718    }
719}
720pub mod gtdlyra {
721
722    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
723    pub struct Dly_SPEC;
724    pub type Dly = crate::EnumBitfieldStruct<u8, Dly_SPEC>;
725    impl Dly {
726        #[doc = "No delay on rising edges"]
727        pub const _00000: Self = Self::new(0);
728    }
729}
730#[doc(hidden)]
731#[derive(Copy, Clone, Eq, PartialEq)]
732pub struct Gtdlyrb_SPEC;
733impl crate::sealed::RegSpec for Gtdlyrb_SPEC {
734    type DataType = u16;
735}
736
737#[doc = "GTIOC%sB Rising Output Delay Register"]
738pub type Gtdlyrb = crate::RegValueT<Gtdlyrb_SPEC>;
739
740impl Gtdlyrb {
741    #[doc = "GTIOCnB Output Rising Edge Delay Setting"]
742    #[inline(always)]
743    pub fn dly(
744        self,
745    ) -> crate::common::RegisterField<
746        0,
747        0x1f,
748        1,
749        0,
750        gtdlyrb::Dly,
751        gtdlyrb::Dly,
752        Gtdlyrb_SPEC,
753        crate::common::RW,
754    > {
755        crate::common::RegisterField::<
756            0,
757            0x1f,
758            1,
759            0,
760            gtdlyrb::Dly,
761            gtdlyrb::Dly,
762            Gtdlyrb_SPEC,
763            crate::common::RW,
764        >::from_register(self, 0)
765    }
766}
767impl ::core::default::Default for Gtdlyrb {
768    #[inline(always)]
769    fn default() -> Gtdlyrb {
770        <crate::RegValueT<Gtdlyrb_SPEC> as RegisterValue<_>>::new(0)
771    }
772}
773pub mod gtdlyrb {
774
775    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
776    pub struct Dly_SPEC;
777    pub type Dly = crate::EnumBitfieldStruct<u8, Dly_SPEC>;
778    impl Dly {
779        #[doc = "No delay on rising edges"]
780        pub const _00000: Self = Self::new(0);
781    }
782}
783#[doc(hidden)]
784#[derive(Copy, Clone, Eq, PartialEq)]
785pub struct Gtdlyfa_SPEC;
786impl crate::sealed::RegSpec for Gtdlyfa_SPEC {
787    type DataType = u16;
788}
789
790#[doc = "GTIOC%sA Falling Output Delay Register"]
791pub type Gtdlyfa = crate::RegValueT<Gtdlyfa_SPEC>;
792
793impl Gtdlyfa {
794    #[doc = "GTIOCnA Output Falling Edge Delay Setting"]
795    #[inline(always)]
796    pub fn dly(
797        self,
798    ) -> crate::common::RegisterField<
799        0,
800        0x1f,
801        1,
802        0,
803        gtdlyfa::Dly,
804        gtdlyfa::Dly,
805        Gtdlyfa_SPEC,
806        crate::common::RW,
807    > {
808        crate::common::RegisterField::<
809            0,
810            0x1f,
811            1,
812            0,
813            gtdlyfa::Dly,
814            gtdlyfa::Dly,
815            Gtdlyfa_SPEC,
816            crate::common::RW,
817        >::from_register(self, 0)
818    }
819}
820impl ::core::default::Default for Gtdlyfa {
821    #[inline(always)]
822    fn default() -> Gtdlyfa {
823        <crate::RegValueT<Gtdlyfa_SPEC> as RegisterValue<_>>::new(0)
824    }
825}
826pub mod gtdlyfa {
827
828    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
829    pub struct Dly_SPEC;
830    pub type Dly = crate::EnumBitfieldStruct<u8, Dly_SPEC>;
831    impl Dly {
832        #[doc = "No delay on rising edges"]
833        pub const _00000: Self = Self::new(0);
834    }
835}
836#[doc(hidden)]
837#[derive(Copy, Clone, Eq, PartialEq)]
838pub struct Gtdlyfb_SPEC;
839impl crate::sealed::RegSpec for Gtdlyfb_SPEC {
840    type DataType = u16;
841}
842
843#[doc = "GTIOC%sB Falling Output Delay Register"]
844pub type Gtdlyfb = crate::RegValueT<Gtdlyfb_SPEC>;
845
846impl Gtdlyfb {
847    #[doc = "GTIOCnB Output Falling Edge Delay Setting"]
848    #[inline(always)]
849    pub fn dly(
850        self,
851    ) -> crate::common::RegisterField<
852        0,
853        0x1f,
854        1,
855        0,
856        gtdlyfb::Dly,
857        gtdlyfb::Dly,
858        Gtdlyfb_SPEC,
859        crate::common::RW,
860    > {
861        crate::common::RegisterField::<
862            0,
863            0x1f,
864            1,
865            0,
866            gtdlyfb::Dly,
867            gtdlyfb::Dly,
868            Gtdlyfb_SPEC,
869            crate::common::RW,
870        >::from_register(self, 0)
871    }
872}
873impl ::core::default::Default for Gtdlyfb {
874    #[inline(always)]
875    fn default() -> Gtdlyfb {
876        <crate::RegValueT<Gtdlyfb_SPEC> as RegisterValue<_>>::new(0)
877    }
878}
879pub mod gtdlyfb {
880
881    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
882    pub struct Dly_SPEC;
883    pub type Dly = crate::EnumBitfieldStruct<u8, Dly_SPEC>;
884    impl Dly {
885        #[doc = "No delay on rising edges"]
886        pub const _00000: Self = Self::new(0);
887    }
888}
ra6m2_pac/gpt_odc.rs

ra6m2_pac/
gpt_odc.rs
