ra6m2_pac/
edmac0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"DMA Controller for the Ethernet Controller Channel 0"]
28unsafe impl ::core::marker::Send for super::Edmac0 {}
29unsafe impl ::core::marker::Sync for super::Edmac0 {}
30impl super::Edmac0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "EDMAC Mode Register"]
38    #[inline(always)]
39    pub const fn edmr(&self) -> &'static crate::common::Reg<self::Edmr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Edmr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "EDMAC Transmit Request Register"]
48    #[inline(always)]
49    pub const fn edtrr(&self) -> &'static crate::common::Reg<self::Edtrr_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Edtrr_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(8usize),
53            )
54        }
55    }
56
57    #[doc = "EDMAC Receive Request Register"]
58    #[inline(always)]
59    pub const fn edrrr(&self) -> &'static crate::common::Reg<self::Edrrr_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Edrrr_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(16usize),
63            )
64        }
65    }
66
67    #[doc = "Transmit Descriptor List Start Address Register"]
68    #[inline(always)]
69    pub const fn tdlar(&self) -> &'static crate::common::Reg<self::Tdlar_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Tdlar_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(24usize),
73            )
74        }
75    }
76
77    #[doc = "Receive Descriptor List Start Address Register"]
78    #[inline(always)]
79    pub const fn rdlar(&self) -> &'static crate::common::Reg<self::Rdlar_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Rdlar_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(32usize),
83            )
84        }
85    }
86
87    #[doc = "ETHERC/EDMAC Status Register"]
88    #[inline(always)]
89    pub const fn eesr(&self) -> &'static crate::common::Reg<self::Eesr_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Eesr_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(40usize),
93            )
94        }
95    }
96
97    #[doc = "ETHERC/EDMAC Status Interrupt Enable Register"]
98    #[inline(always)]
99    pub const fn eesipr(
100        &self,
101    ) -> &'static crate::common::Reg<self::Eesipr_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::Eesipr_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(48usize),
105            )
106        }
107    }
108
109    #[doc = "ETHERC/EDMAC Transmit/Receive Status Copy Enable Register"]
110    #[inline(always)]
111    pub const fn trscer(
112        &self,
113    ) -> &'static crate::common::Reg<self::Trscer_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::Trscer_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(56usize),
117            )
118        }
119    }
120
121    #[doc = "Missed-Frame Counter Register"]
122    #[inline(always)]
123    pub const fn rmfcr(&self) -> &'static crate::common::Reg<self::Rmfcr_SPEC, crate::common::RW> {
124        unsafe {
125            crate::common::Reg::<self::Rmfcr_SPEC, crate::common::RW>::from_ptr(
126                self._svd2pac_as_ptr().add(64usize),
127            )
128        }
129    }
130
131    #[doc = "Transmit FIFO Threshold Register"]
132    #[inline(always)]
133    pub const fn tftr(&self) -> &'static crate::common::Reg<self::Tftr_SPEC, crate::common::RW> {
134        unsafe {
135            crate::common::Reg::<self::Tftr_SPEC, crate::common::RW>::from_ptr(
136                self._svd2pac_as_ptr().add(72usize),
137            )
138        }
139    }
140
141    #[doc = "Transmit FIFO Threshold Register"]
142    #[inline(always)]
143    pub const fn fdr(&self) -> &'static crate::common::Reg<self::Fdr_SPEC, crate::common::RW> {
144        unsafe {
145            crate::common::Reg::<self::Fdr_SPEC, crate::common::RW>::from_ptr(
146                self._svd2pac_as_ptr().add(80usize),
147            )
148        }
149    }
150
151    #[doc = "Receive Method Control Register"]
152    #[inline(always)]
153    pub const fn rmcr(&self) -> &'static crate::common::Reg<self::Rmcr_SPEC, crate::common::RW> {
154        unsafe {
155            crate::common::Reg::<self::Rmcr_SPEC, crate::common::RW>::from_ptr(
156                self._svd2pac_as_ptr().add(88usize),
157            )
158        }
159    }
160
161    #[doc = "Transmit FIFO Underflow Counter"]
162    #[inline(always)]
163    pub const fn tfucr(&self) -> &'static crate::common::Reg<self::Tfucr_SPEC, crate::common::RW> {
164        unsafe {
165            crate::common::Reg::<self::Tfucr_SPEC, crate::common::RW>::from_ptr(
166                self._svd2pac_as_ptr().add(100usize),
167            )
168        }
169    }
170
171    #[doc = "Receive FIFO Overflow Counter"]
172    #[inline(always)]
173    pub const fn rfocr(&self) -> &'static crate::common::Reg<self::Rfocr_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::Rfocr_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(104usize),
177            )
178        }
179    }
180
181    #[doc = "Independent Output Signal Setting Register"]
182    #[inline(always)]
183    pub const fn iosr(&self) -> &'static crate::common::Reg<self::Iosr_SPEC, crate::common::RW> {
184        unsafe {
185            crate::common::Reg::<self::Iosr_SPEC, crate::common::RW>::from_ptr(
186                self._svd2pac_as_ptr().add(108usize),
187            )
188        }
189    }
190
191    #[doc = "Flow Control Start FIFO Threshold Setting Register"]
192    #[inline(always)]
193    pub const fn fcftr(&self) -> &'static crate::common::Reg<self::Fcftr_SPEC, crate::common::RW> {
194        unsafe {
195            crate::common::Reg::<self::Fcftr_SPEC, crate::common::RW>::from_ptr(
196                self._svd2pac_as_ptr().add(112usize),
197            )
198        }
199    }
200
201    #[doc = "Receive Data Padding Insert Register"]
202    #[inline(always)]
203    pub const fn rpadir(
204        &self,
205    ) -> &'static crate::common::Reg<self::Rpadir_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Rpadir_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(120usize),
209            )
210        }
211    }
212
213    #[doc = "Transmit Interrupt Setting Register"]
214    #[inline(always)]
215    pub const fn trimd(&self) -> &'static crate::common::Reg<self::Trimd_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Trimd_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(124usize),
219            )
220        }
221    }
222
223    #[doc = "Receive Buffer Write Address Register"]
224    #[inline(always)]
225    pub const fn rbwar(&self) -> &'static crate::common::Reg<self::Rbwar_SPEC, crate::common::R> {
226        unsafe {
227            crate::common::Reg::<self::Rbwar_SPEC, crate::common::R>::from_ptr(
228                self._svd2pac_as_ptr().add(200usize),
229            )
230        }
231    }
232
233    #[doc = "Receive Descriptor Fetch Address Register"]
234    #[inline(always)]
235    pub const fn rdfar(&self) -> &'static crate::common::Reg<self::Rdfar_SPEC, crate::common::R> {
236        unsafe {
237            crate::common::Reg::<self::Rdfar_SPEC, crate::common::R>::from_ptr(
238                self._svd2pac_as_ptr().add(204usize),
239            )
240        }
241    }
242
243    #[doc = "Transmit Buffer Read Address Register"]
244    #[inline(always)]
245    pub const fn tbrar(&self) -> &'static crate::common::Reg<self::Tbrar_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Tbrar_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(212usize),
249            )
250        }
251    }
252
253    #[doc = "Transmit Descriptor Fetch Address Register"]
254    #[inline(always)]
255    pub const fn tdfar(&self) -> &'static crate::common::Reg<self::Tdfar_SPEC, crate::common::R> {
256        unsafe {
257            crate::common::Reg::<self::Tdfar_SPEC, crate::common::R>::from_ptr(
258                self._svd2pac_as_ptr().add(216usize),
259            )
260        }
261    }
262}
263#[doc(hidden)]
264#[derive(Copy, Clone, Eq, PartialEq)]
265pub struct Edmr_SPEC;
266impl crate::sealed::RegSpec for Edmr_SPEC {
267    type DataType = u32;
268}
269
270#[doc = "EDMAC Mode Register"]
271pub type Edmr = crate::RegValueT<Edmr_SPEC>;
272
273impl Edmr {
274    #[doc = "Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers."]
275    #[inline(always)]
276    pub fn de(
277        self,
278    ) -> crate::common::RegisterField<6, 0x1, 1, 0, edmr::De, edmr::De, Edmr_SPEC, crate::common::RW>
279    {
280        crate::common::RegisterField::<6,0x1,1,0,edmr::De,edmr::De,Edmr_SPEC,crate::common::RW>::from_register(self,0)
281    }
282
283    #[doc = "Transmit/Receive DescriptorLength"]
284    #[inline(always)]
285    pub fn dl(
286        self,
287    ) -> crate::common::RegisterField<4, 0x3, 1, 0, edmr::Dl, edmr::Dl, Edmr_SPEC, crate::common::RW>
288    {
289        crate::common::RegisterField::<4,0x3,1,0,edmr::Dl,edmr::Dl,Edmr_SPEC,crate::common::RW>::from_register(self,0)
290    }
291
292    #[doc = "Software Reset"]
293    #[inline(always)]
294    pub fn swr(
295        self,
296    ) -> crate::common::RegisterField<0, 0x1, 1, 0, edmr::Swr, edmr::Swr, Edmr_SPEC, crate::common::W>
297    {
298        crate::common::RegisterField::<
299            0,
300            0x1,
301            1,
302            0,
303            edmr::Swr,
304            edmr::Swr,
305            Edmr_SPEC,
306            crate::common::W,
307        >::from_register(self, 0)
308    }
309}
310impl ::core::default::Default for Edmr {
311    #[inline(always)]
312    fn default() -> Edmr {
313        <crate::RegValueT<Edmr_SPEC> as RegisterValue<_>>::new(0)
314    }
315}
316pub mod edmr {
317
318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
319    pub struct De_SPEC;
320    pub type De = crate::EnumBitfieldStruct<u8, De_SPEC>;
321    impl De {
322        #[doc = "Big endian mode"]
323        pub const _0: Self = Self::new(0);
324
325        #[doc = "Little endian mode"]
326        pub const _1: Self = Self::new(1);
327    }
328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
329    pub struct Dl_SPEC;
330    pub type Dl = crate::EnumBitfieldStruct<u8, Dl_SPEC>;
331    impl Dl {
332        #[doc = "16 bytes"]
333        pub const _00: Self = Self::new(0);
334
335        #[doc = "32 bytes"]
336        pub const _01: Self = Self::new(1);
337
338        #[doc = "64 bytes"]
339        pub const _10: Self = Self::new(2);
340
341        #[doc = "16 bytes"]
342        pub const _11: Self = Self::new(3);
343    }
344    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
345    pub struct Swr_SPEC;
346    pub type Swr = crate::EnumBitfieldStruct<u8, Swr_SPEC>;
347    impl Swr {
348        #[doc = "no effect."]
349        pub const _0: Self = Self::new(0);
350
351        #[doc = "the corresponding channels of the EDMAC and ETHERC are reset.  Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset."]
352        pub const _1: Self = Self::new(1);
353    }
354}
355#[doc(hidden)]
356#[derive(Copy, Clone, Eq, PartialEq)]
357pub struct Edtrr_SPEC;
358impl crate::sealed::RegSpec for Edtrr_SPEC {
359    type DataType = u32;
360}
361
362#[doc = "EDMAC Transmit Request Register"]
363pub type Edtrr = crate::RegValueT<Edtrr_SPEC>;
364
365impl Edtrr {
366    #[doc = "Transmit Request"]
367    #[inline(always)]
368    pub fn tr(
369        self,
370    ) -> crate::common::RegisterField<
371        0,
372        0x1,
373        1,
374        0,
375        edtrr::Tr,
376        edtrr::Tr,
377        Edtrr_SPEC,
378        crate::common::W,
379    > {
380        crate::common::RegisterField::<
381            0,
382            0x1,
383            1,
384            0,
385            edtrr::Tr,
386            edtrr::Tr,
387            Edtrr_SPEC,
388            crate::common::W,
389        >::from_register(self, 0)
390    }
391}
392impl ::core::default::Default for Edtrr {
393    #[inline(always)]
394    fn default() -> Edtrr {
395        <crate::RegValueT<Edtrr_SPEC> as RegisterValue<_>>::new(0)
396    }
397}
398pub mod edtrr {
399
400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
401    pub struct Tr_SPEC;
402    pub type Tr = crate::EnumBitfieldStruct<u8, Tr_SPEC>;
403    impl Tr {
404        #[doc = "no effect."]
405        pub const _0: Self = Self::new(0);
406
407        #[doc = "When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted."]
408        pub const _1: Self = Self::new(1);
409    }
410}
411#[doc(hidden)]
412#[derive(Copy, Clone, Eq, PartialEq)]
413pub struct Edrrr_SPEC;
414impl crate::sealed::RegSpec for Edrrr_SPEC {
415    type DataType = u32;
416}
417
418#[doc = "EDMAC Receive Request Register"]
419pub type Edrrr = crate::RegValueT<Edrrr_SPEC>;
420
421impl Edrrr {
422    #[doc = "Receive Request"]
423    #[inline(always)]
424    pub fn rr(
425        self,
426    ) -> crate::common::RegisterField<
427        0,
428        0x1,
429        1,
430        0,
431        edrrr::Rr,
432        edrrr::Rr,
433        Edrrr_SPEC,
434        crate::common::RW,
435    > {
436        crate::common::RegisterField::<
437            0,
438            0x1,
439            1,
440            0,
441            edrrr::Rr,
442            edrrr::Rr,
443            Edrrr_SPEC,
444            crate::common::RW,
445        >::from_register(self, 0)
446    }
447}
448impl ::core::default::Default for Edrrr {
449    #[inline(always)]
450    fn default() -> Edrrr {
451        <crate::RegValueT<Edrrr_SPEC> as RegisterValue<_>>::new(0)
452    }
453}
454pub mod edrrr {
455
456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
457    pub struct Rr_SPEC;
458    pub type Rr = crate::EnumBitfieldStruct<u8, Rr_SPEC>;
459    impl Rr {
460        #[doc = "Receive function is disabled."]
461        pub const _0: Self = Self::new(0);
462
463        #[doc = "Receive descriptor is read, and the receive function is enabled."]
464        pub const _1: Self = Self::new(1);
465    }
466}
467#[doc(hidden)]
468#[derive(Copy, Clone, Eq, PartialEq)]
469pub struct Tdlar_SPEC;
470impl crate::sealed::RegSpec for Tdlar_SPEC {
471    type DataType = u32;
472}
473
474#[doc = "Transmit Descriptor List Start Address Register"]
475pub type Tdlar = crate::RegValueT<Tdlar_SPEC>;
476
477impl Tdlar {
478    #[doc = "The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL\\[1:0\\] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b"]
479    #[inline(always)]
480    pub fn tdlar(
481        self,
482    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Tdlar_SPEC, crate::common::RW>
483    {
484        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Tdlar_SPEC,crate::common::RW>::from_register(self,0)
485    }
486}
487impl ::core::default::Default for Tdlar {
488    #[inline(always)]
489    fn default() -> Tdlar {
490        <crate::RegValueT<Tdlar_SPEC> as RegisterValue<_>>::new(0)
491    }
492}
493
494#[doc(hidden)]
495#[derive(Copy, Clone, Eq, PartialEq)]
496pub struct Rdlar_SPEC;
497impl crate::sealed::RegSpec for Rdlar_SPEC {
498    type DataType = u32;
499}
500
501#[doc = "Receive Descriptor List Start Address Register"]
502pub type Rdlar = crate::RegValueT<Rdlar_SPEC>;
503
504impl Rdlar {
505    #[doc = "The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL\\[1:0\\] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b"]
506    #[inline(always)]
507    pub fn rdlar(
508        self,
509    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Rdlar_SPEC, crate::common::RW>
510    {
511        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Rdlar_SPEC,crate::common::RW>::from_register(self,0)
512    }
513}
514impl ::core::default::Default for Rdlar {
515    #[inline(always)]
516    fn default() -> Rdlar {
517        <crate::RegValueT<Rdlar_SPEC> as RegisterValue<_>>::new(0)
518    }
519}
520
521#[doc(hidden)]
522#[derive(Copy, Clone, Eq, PartialEq)]
523pub struct Eesr_SPEC;
524impl crate::sealed::RegSpec for Eesr_SPEC {
525    type DataType = u32;
526}
527
528#[doc = "ETHERC/EDMAC Status Register"]
529pub type Eesr = crate::RegValueT<Eesr_SPEC>;
530
531impl Eesr {
532    #[doc = "Write-Back Complete Flag"]
533    #[inline(always)]
534    pub fn twb(
535        self,
536    ) -> crate::common::RegisterField<
537        30,
538        0x1,
539        1,
540        0,
541        eesr::Twb,
542        eesr::Twb,
543        Eesr_SPEC,
544        crate::common::RW,
545    > {
546        crate::common::RegisterField::<
547            30,
548            0x1,
549            1,
550            0,
551            eesr::Twb,
552            eesr::Twb,
553            Eesr_SPEC,
554            crate::common::RW,
555        >::from_register(self, 0)
556    }
557
558    #[doc = "Transmit Abort Detect Flag"]
559    #[inline(always)]
560    pub fn tabt(
561        self,
562    ) -> crate::common::RegisterField<
563        26,
564        0x1,
565        1,
566        0,
567        eesr::Tabt,
568        eesr::Tabt,
569        Eesr_SPEC,
570        crate::common::RW,
571    > {
572        crate::common::RegisterField::<
573            26,
574            0x1,
575            1,
576            0,
577            eesr::Tabt,
578            eesr::Tabt,
579            Eesr_SPEC,
580            crate::common::RW,
581        >::from_register(self, 0)
582    }
583
584    #[doc = "Receive Abort Detect Flag"]
585    #[inline(always)]
586    pub fn rabt(
587        self,
588    ) -> crate::common::RegisterField<
589        25,
590        0x1,
591        1,
592        0,
593        eesr::Rabt,
594        eesr::Rabt,
595        Eesr_SPEC,
596        crate::common::RW,
597    > {
598        crate::common::RegisterField::<
599            25,
600            0x1,
601            1,
602            0,
603            eesr::Rabt,
604            eesr::Rabt,
605            Eesr_SPEC,
606            crate::common::RW,
607        >::from_register(self, 0)
608    }
609
610    #[doc = "Receive Frame Counter Overflow Flag"]
611    #[inline(always)]
612    pub fn rfcof(
613        self,
614    ) -> crate::common::RegisterField<
615        24,
616        0x1,
617        1,
618        0,
619        eesr::Rfcof,
620        eesr::Rfcof,
621        Eesr_SPEC,
622        crate::common::RW,
623    > {
624        crate::common::RegisterField::<
625            24,
626            0x1,
627            1,
628            0,
629            eesr::Rfcof,
630            eesr::Rfcof,
631            Eesr_SPEC,
632            crate::common::RW,
633        >::from_register(self, 0)
634    }
635
636    #[doc = "Address Error Flag"]
637    #[inline(always)]
638    pub fn ade(
639        self,
640    ) -> crate::common::RegisterField<
641        23,
642        0x1,
643        1,
644        0,
645        eesr::Ade,
646        eesr::Ade,
647        Eesr_SPEC,
648        crate::common::RW,
649    > {
650        crate::common::RegisterField::<
651            23,
652            0x1,
653            1,
654            0,
655            eesr::Ade,
656            eesr::Ade,
657            Eesr_SPEC,
658            crate::common::RW,
659        >::from_register(self, 0)
660    }
661
662    #[doc = "ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared."]
663    #[inline(always)]
664    pub fn eci(
665        self,
666    ) -> crate::common::RegisterField<
667        22,
668        0x1,
669        1,
670        0,
671        eesr::Eci,
672        eesr::Eci,
673        Eesr_SPEC,
674        crate::common::R,
675    > {
676        crate::common::RegisterField::<
677            22,
678            0x1,
679            1,
680            0,
681            eesr::Eci,
682            eesr::Eci,
683            Eesr_SPEC,
684            crate::common::R,
685        >::from_register(self, 0)
686    }
687
688    #[doc = "Frame Transfer Complete Flag"]
689    #[inline(always)]
690    pub fn tc(
691        self,
692    ) -> crate::common::RegisterField<21, 0x1, 1, 0, eesr::Tc, eesr::Tc, Eesr_SPEC, crate::common::RW>
693    {
694        crate::common::RegisterField::<
695            21,
696            0x1,
697            1,
698            0,
699            eesr::Tc,
700            eesr::Tc,
701            Eesr_SPEC,
702            crate::common::RW,
703        >::from_register(self, 0)
704    }
705
706    #[doc = "Transmit Descriptor Empty Flag"]
707    #[inline(always)]
708    pub fn tde(
709        self,
710    ) -> crate::common::RegisterField<
711        20,
712        0x1,
713        1,
714        0,
715        eesr::Tde,
716        eesr::Tde,
717        Eesr_SPEC,
718        crate::common::RW,
719    > {
720        crate::common::RegisterField::<
721            20,
722            0x1,
723            1,
724            0,
725            eesr::Tde,
726            eesr::Tde,
727            Eesr_SPEC,
728            crate::common::RW,
729        >::from_register(self, 0)
730    }
731
732    #[doc = "Transmit FIFO Underflow Flag"]
733    #[inline(always)]
734    pub fn tfuf(
735        self,
736    ) -> crate::common::RegisterField<
737        19,
738        0x1,
739        1,
740        0,
741        eesr::Tfuf,
742        eesr::Tfuf,
743        Eesr_SPEC,
744        crate::common::RW,
745    > {
746        crate::common::RegisterField::<
747            19,
748            0x1,
749            1,
750            0,
751            eesr::Tfuf,
752            eesr::Tfuf,
753            Eesr_SPEC,
754            crate::common::RW,
755        >::from_register(self, 0)
756    }
757
758    #[doc = "Frame Receive Flag"]
759    #[inline(always)]
760    pub fn fr(
761        self,
762    ) -> crate::common::RegisterField<18, 0x1, 1, 0, eesr::Fr, eesr::Fr, Eesr_SPEC, crate::common::RW>
763    {
764        crate::common::RegisterField::<
765            18,
766            0x1,
767            1,
768            0,
769            eesr::Fr,
770            eesr::Fr,
771            Eesr_SPEC,
772            crate::common::RW,
773        >::from_register(self, 0)
774    }
775
776    #[doc = "Receive Descriptor Empty Flag"]
777    #[inline(always)]
778    pub fn rde(
779        self,
780    ) -> crate::common::RegisterField<
781        17,
782        0x1,
783        1,
784        0,
785        eesr::Rde,
786        eesr::Rde,
787        Eesr_SPEC,
788        crate::common::RW,
789    > {
790        crate::common::RegisterField::<
791            17,
792            0x1,
793            1,
794            0,
795            eesr::Rde,
796            eesr::Rde,
797            Eesr_SPEC,
798            crate::common::RW,
799        >::from_register(self, 0)
800    }
801
802    #[doc = "Receive FIFO Overflow Flag"]
803    #[inline(always)]
804    pub fn rfof(
805        self,
806    ) -> crate::common::RegisterField<
807        16,
808        0x1,
809        1,
810        0,
811        eesr::Rfof,
812        eesr::Rfof,
813        Eesr_SPEC,
814        crate::common::RW,
815    > {
816        crate::common::RegisterField::<
817            16,
818            0x1,
819            1,
820            0,
821            eesr::Rfof,
822            eesr::Rfof,
823            Eesr_SPEC,
824            crate::common::RW,
825        >::from_register(self, 0)
826    }
827
828    #[doc = "Carrier Not Detect Flag"]
829    #[inline(always)]
830    pub fn cnd(
831        self,
832    ) -> crate::common::RegisterField<
833        11,
834        0x1,
835        1,
836        0,
837        eesr::Cnd,
838        eesr::Cnd,
839        Eesr_SPEC,
840        crate::common::RW,
841    > {
842        crate::common::RegisterField::<
843            11,
844            0x1,
845            1,
846            0,
847            eesr::Cnd,
848            eesr::Cnd,
849            Eesr_SPEC,
850            crate::common::RW,
851        >::from_register(self, 0)
852    }
853
854    #[doc = "Loss of Carrier Detect Flag"]
855    #[inline(always)]
856    pub fn dlc(
857        self,
858    ) -> crate::common::RegisterField<
859        10,
860        0x1,
861        1,
862        0,
863        eesr::Dlc,
864        eesr::Dlc,
865        Eesr_SPEC,
866        crate::common::RW,
867    > {
868        crate::common::RegisterField::<
869            10,
870            0x1,
871            1,
872            0,
873            eesr::Dlc,
874            eesr::Dlc,
875            Eesr_SPEC,
876            crate::common::RW,
877        >::from_register(self, 0)
878    }
879
880    #[doc = "Late Collision Detect Flag"]
881    #[inline(always)]
882    pub fn cd(
883        self,
884    ) -> crate::common::RegisterField<9, 0x1, 1, 0, eesr::Cd, eesr::Cd, Eesr_SPEC, crate::common::RW>
885    {
886        crate::common::RegisterField::<9,0x1,1,0,eesr::Cd,eesr::Cd,Eesr_SPEC,crate::common::RW>::from_register(self,0)
887    }
888
889    #[doc = "Transmit Retry Over Flag"]
890    #[inline(always)]
891    pub fn tro(
892        self,
893    ) -> crate::common::RegisterField<
894        8,
895        0x1,
896        1,
897        0,
898        eesr::Tro,
899        eesr::Tro,
900        Eesr_SPEC,
901        crate::common::RW,
902    > {
903        crate::common::RegisterField::<
904            8,
905            0x1,
906            1,
907            0,
908            eesr::Tro,
909            eesr::Tro,
910            Eesr_SPEC,
911            crate::common::RW,
912        >::from_register(self, 0)
913    }
914
915    #[doc = "Multicast Address Frame Receive Flag"]
916    #[inline(always)]
917    pub fn rmaf(
918        self,
919    ) -> crate::common::RegisterField<
920        7,
921        0x1,
922        1,
923        0,
924        eesr::Rmaf,
925        eesr::Rmaf,
926        Eesr_SPEC,
927        crate::common::RW,
928    > {
929        crate::common::RegisterField::<
930            7,
931            0x1,
932            1,
933            0,
934            eesr::Rmaf,
935            eesr::Rmaf,
936            Eesr_SPEC,
937            crate::common::RW,
938        >::from_register(self, 0)
939    }
940
941    #[doc = "Alignment Error Flag"]
942    #[inline(always)]
943    pub fn rrf(
944        self,
945    ) -> crate::common::RegisterField<
946        4,
947        0x1,
948        1,
949        0,
950        eesr::Rrf,
951        eesr::Rrf,
952        Eesr_SPEC,
953        crate::common::RW,
954    > {
955        crate::common::RegisterField::<
956            4,
957            0x1,
958            1,
959            0,
960            eesr::Rrf,
961            eesr::Rrf,
962            Eesr_SPEC,
963            crate::common::RW,
964        >::from_register(self, 0)
965    }
966
967    #[doc = "Frame-Too-Long Error Flag"]
968    #[inline(always)]
969    pub fn rtlf(
970        self,
971    ) -> crate::common::RegisterField<
972        3,
973        0x1,
974        1,
975        0,
976        eesr::Rtlf,
977        eesr::Rtlf,
978        Eesr_SPEC,
979        crate::common::RW,
980    > {
981        crate::common::RegisterField::<
982            3,
983            0x1,
984            1,
985            0,
986            eesr::Rtlf,
987            eesr::Rtlf,
988            Eesr_SPEC,
989            crate::common::RW,
990        >::from_register(self, 0)
991    }
992
993    #[doc = "Frame-Too-Short Error Flag"]
994    #[inline(always)]
995    pub fn rtsf(
996        self,
997    ) -> crate::common::RegisterField<
998        2,
999        0x1,
1000        1,
1001        0,
1002        eesr::Rtsf,
1003        eesr::Rtsf,
1004        Eesr_SPEC,
1005        crate::common::RW,
1006    > {
1007        crate::common::RegisterField::<
1008            2,
1009            0x1,
1010            1,
1011            0,
1012            eesr::Rtsf,
1013            eesr::Rtsf,
1014            Eesr_SPEC,
1015            crate::common::RW,
1016        >::from_register(self, 0)
1017    }
1018
1019    #[doc = "PHY-LSI Receive Error Flag"]
1020    #[inline(always)]
1021    pub fn pre(
1022        self,
1023    ) -> crate::common::RegisterField<
1024        1,
1025        0x1,
1026        1,
1027        0,
1028        eesr::Pre,
1029        eesr::Pre,
1030        Eesr_SPEC,
1031        crate::common::RW,
1032    > {
1033        crate::common::RegisterField::<
1034            1,
1035            0x1,
1036            1,
1037            0,
1038            eesr::Pre,
1039            eesr::Pre,
1040            Eesr_SPEC,
1041            crate::common::RW,
1042        >::from_register(self, 0)
1043    }
1044
1045    #[doc = "CRC Error Flag"]
1046    #[inline(always)]
1047    pub fn cerf(
1048        self,
1049    ) -> crate::common::RegisterField<
1050        0,
1051        0x1,
1052        1,
1053        0,
1054        eesr::Cerf,
1055        eesr::Cerf,
1056        Eesr_SPEC,
1057        crate::common::RW,
1058    > {
1059        crate::common::RegisterField::<
1060            0,
1061            0x1,
1062            1,
1063            0,
1064            eesr::Cerf,
1065            eesr::Cerf,
1066            Eesr_SPEC,
1067            crate::common::RW,
1068        >::from_register(self, 0)
1069    }
1070}
1071impl ::core::default::Default for Eesr {
1072    #[inline(always)]
1073    fn default() -> Eesr {
1074        <crate::RegValueT<Eesr_SPEC> as RegisterValue<_>>::new(0)
1075    }
1076}
1077pub mod eesr {
1078
1079    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1080    pub struct Twb_SPEC;
1081    pub type Twb = crate::EnumBitfieldStruct<u8, Twb_SPEC>;
1082    impl Twb {
1083        #[doc = "Write-back has not been completed, or no transmission has been requested."]
1084        pub const _0: Self = Self::new(0);
1085
1086        #[doc = "Write-back to the transmit descriptor has been completed."]
1087        pub const _1: Self = Self::new(1);
1088    }
1089    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1090    pub struct Tabt_SPEC;
1091    pub type Tabt = crate::EnumBitfieldStruct<u8, Tabt_SPEC>;
1092    impl Tabt {
1093        #[doc = "Frame transmission has not been aborted or no transmission has been requested."]
1094        pub const _0: Self = Self::new(0);
1095
1096        #[doc = "Frame transmission has been aborted."]
1097        pub const _1: Self = Self::new(1);
1098    }
1099    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1100    pub struct Rabt_SPEC;
1101    pub type Rabt = crate::EnumBitfieldStruct<u8, Rabt_SPEC>;
1102    impl Rabt {
1103        #[doc = "Frame reception has not been aborted or no reception has been requested."]
1104        pub const _0: Self = Self::new(0);
1105
1106        #[doc = "Frame reception has been aborted."]
1107        pub const _1: Self = Self::new(1);
1108    }
1109    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1110    pub struct Rfcof_SPEC;
1111    pub type Rfcof = crate::EnumBitfieldStruct<u8, Rfcof_SPEC>;
1112    impl Rfcof {
1113        #[doc = "Receive frame counter has not overflowed."]
1114        pub const _0: Self = Self::new(0);
1115
1116        #[doc = "Receive frame counter has overflowed."]
1117        pub const _1: Self = Self::new(1);
1118    }
1119    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1120    pub struct Ade_SPEC;
1121    pub type Ade = crate::EnumBitfieldStruct<u8, Ade_SPEC>;
1122    impl Ade {
1123        #[doc = "Invalid memory address has not been detected (normal operation)."]
1124        pub const _0: Self = Self::new(0);
1125
1126        #[doc = "Invalid memory address has been detected."]
1127        pub const _1: Self = Self::new(1);
1128    }
1129    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1130    pub struct Eci_SPEC;
1131    pub type Eci = crate::EnumBitfieldStruct<u8, Eci_SPEC>;
1132    impl Eci {
1133        #[doc = "ETHERC status interrupt source has not been detected."]
1134        pub const _0: Self = Self::new(0);
1135
1136        #[doc = "ETHERC status interrupt source has been detected."]
1137        pub const _1: Self = Self::new(1);
1138    }
1139    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1140    pub struct Tc_SPEC;
1141    pub type Tc = crate::EnumBitfieldStruct<u8, Tc_SPEC>;
1142    impl Tc {
1143        #[doc = "Transfer have not been completed, or no transfer has been requested."]
1144        pub const _0: Self = Self::new(0);
1145
1146        #[doc = "All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO."]
1147        pub const _1: Self = Self::new(1);
1148    }
1149    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1150    pub struct Tde_SPEC;
1151    pub type Tde = crate::EnumBitfieldStruct<u8, Tde_SPEC>;
1152    impl Tde {
1153        #[doc = "The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1."]
1154        pub const _0: Self = Self::new(0);
1155
1156        #[doc = "The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0."]
1157        pub const _1: Self = Self::new(1);
1158    }
1159    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1160    pub struct Tfuf_SPEC;
1161    pub type Tfuf = crate::EnumBitfieldStruct<u8, Tfuf_SPEC>;
1162    impl Tfuf {
1163        #[doc = "Underflow has not occurred."]
1164        pub const _0: Self = Self::new(0);
1165
1166        #[doc = "Underflow has occurred."]
1167        pub const _1: Self = Self::new(1);
1168    }
1169    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1170    pub struct Fr_SPEC;
1171    pub type Fr = crate::EnumBitfieldStruct<u8, Fr_SPEC>;
1172    impl Fr {
1173        #[doc = "Frame has not been received."]
1174        pub const _0: Self = Self::new(0);
1175
1176        #[doc = "Frame has been received. Update of the receive descriptor is complete."]
1177        pub const _1: Self = Self::new(1);
1178    }
1179    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1180    pub struct Rde_SPEC;
1181    pub type Rde = crate::EnumBitfieldStruct<u8, Rde_SPEC>;
1182    impl Rde {
1183        #[doc = "The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1."]
1184        pub const _0: Self = Self::new(0);
1185
1186        #[doc = "The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0."]
1187        pub const _1: Self = Self::new(1);
1188    }
1189    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1190    pub struct Rfof_SPEC;
1191    pub type Rfof = crate::EnumBitfieldStruct<u8, Rfof_SPEC>;
1192    impl Rfof {
1193        #[doc = "Overflow has not occurred."]
1194        pub const _0: Self = Self::new(0);
1195
1196        #[doc = "Overflow has occurred."]
1197        pub const _1: Self = Self::new(1);
1198    }
1199    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1200    pub struct Cnd_SPEC;
1201    pub type Cnd = crate::EnumBitfieldStruct<u8, Cnd_SPEC>;
1202    impl Cnd {
1203        #[doc = "A carrier has been detected when transmission starts."]
1204        pub const _0: Self = Self::new(0);
1205
1206        #[doc = "A carrier has not been detected during preamble transmission."]
1207        pub const _1: Self = Self::new(1);
1208    }
1209    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1210    pub struct Dlc_SPEC;
1211    pub type Dlc = crate::EnumBitfieldStruct<u8, Dlc_SPEC>;
1212    impl Dlc {
1213        #[doc = "Loss of carrier has not been detected."]
1214        pub const _0: Self = Self::new(0);
1215
1216        #[doc = "Loss of carrier has been detected during frame transmission."]
1217        pub const _1: Self = Self::new(1);
1218    }
1219    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1220    pub struct Cd_SPEC;
1221    pub type Cd = crate::EnumBitfieldStruct<u8, Cd_SPEC>;
1222    impl Cd {
1223        #[doc = "Late collision has not been detected."]
1224        pub const _0: Self = Self::new(0);
1225
1226        #[doc = "Late collision has been detected during frame transmission."]
1227        pub const _1: Self = Self::new(1);
1228    }
1229    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1230    pub struct Tro_SPEC;
1231    pub type Tro = crate::EnumBitfieldStruct<u8, Tro_SPEC>;
1232    impl Tro {
1233        #[doc = "Transmit retry-over condition has not been detected."]
1234        pub const _0: Self = Self::new(0);
1235
1236        #[doc = "Transmit retry-over condition has been detected."]
1237        pub const _1: Self = Self::new(1);
1238    }
1239    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1240    pub struct Rmaf_SPEC;
1241    pub type Rmaf = crate::EnumBitfieldStruct<u8, Rmaf_SPEC>;
1242    impl Rmaf {
1243        #[doc = "Multicast address frame has not been received."]
1244        pub const _0: Self = Self::new(0);
1245
1246        #[doc = "Multicast address frame has been received."]
1247        pub const _1: Self = Self::new(1);
1248    }
1249    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1250    pub struct Rrf_SPEC;
1251    pub type Rrf = crate::EnumBitfieldStruct<u8, Rrf_SPEC>;
1252    impl Rrf {
1253        #[doc = "Alignment error has not been detected."]
1254        pub const _0: Self = Self::new(0);
1255
1256        #[doc = "Alignment error has been detected."]
1257        pub const _1: Self = Self::new(1);
1258    }
1259    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1260    pub struct Rtlf_SPEC;
1261    pub type Rtlf = crate::EnumBitfieldStruct<u8, Rtlf_SPEC>;
1262    impl Rtlf {
1263        #[doc = "Frame-too-long error has not been detected."]
1264        pub const _0: Self = Self::new(0);
1265
1266        #[doc = "Frame-too-long error has been detected."]
1267        pub const _1: Self = Self::new(1);
1268    }
1269    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1270    pub struct Rtsf_SPEC;
1271    pub type Rtsf = crate::EnumBitfieldStruct<u8, Rtsf_SPEC>;
1272    impl Rtsf {
1273        #[doc = "Frame-too-short error has not been detected."]
1274        pub const _0: Self = Self::new(0);
1275
1276        #[doc = "Frame-too-short error has been detected."]
1277        pub const _1: Self = Self::new(1);
1278    }
1279    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1280    pub struct Pre_SPEC;
1281    pub type Pre = crate::EnumBitfieldStruct<u8, Pre_SPEC>;
1282    impl Pre {
1283        #[doc = "PHY-LSI receive error has not been detected."]
1284        pub const _0: Self = Self::new(0);
1285
1286        #[doc = "PHY-LSI receive error has been detected."]
1287        pub const _1: Self = Self::new(1);
1288    }
1289    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1290    pub struct Cerf_SPEC;
1291    pub type Cerf = crate::EnumBitfieldStruct<u8, Cerf_SPEC>;
1292    impl Cerf {
1293        #[doc = "CRC error has not been detected."]
1294        pub const _0: Self = Self::new(0);
1295
1296        #[doc = "CRC error has been detected."]
1297        pub const _1: Self = Self::new(1);
1298    }
1299}
1300#[doc(hidden)]
1301#[derive(Copy, Clone, Eq, PartialEq)]
1302pub struct Eesipr_SPEC;
1303impl crate::sealed::RegSpec for Eesipr_SPEC {
1304    type DataType = u32;
1305}
1306
1307#[doc = "ETHERC/EDMAC Status Interrupt Enable Register"]
1308pub type Eesipr = crate::RegValueT<Eesipr_SPEC>;
1309
1310impl Eesipr {
1311    #[doc = "Write-Back Complete Interrupt Request Enable"]
1312    #[inline(always)]
1313    pub fn twbip(
1314        self,
1315    ) -> crate::common::RegisterField<
1316        30,
1317        0x1,
1318        1,
1319        0,
1320        eesipr::Twbip,
1321        eesipr::Twbip,
1322        Eesipr_SPEC,
1323        crate::common::RW,
1324    > {
1325        crate::common::RegisterField::<
1326            30,
1327            0x1,
1328            1,
1329            0,
1330            eesipr::Twbip,
1331            eesipr::Twbip,
1332            Eesipr_SPEC,
1333            crate::common::RW,
1334        >::from_register(self, 0)
1335    }
1336
1337    #[doc = "Transmit Abort Detect Interrupt Request Enable"]
1338    #[inline(always)]
1339    pub fn tabtip(
1340        self,
1341    ) -> crate::common::RegisterField<
1342        26,
1343        0x1,
1344        1,
1345        0,
1346        eesipr::Tabtip,
1347        eesipr::Tabtip,
1348        Eesipr_SPEC,
1349        crate::common::RW,
1350    > {
1351        crate::common::RegisterField::<
1352            26,
1353            0x1,
1354            1,
1355            0,
1356            eesipr::Tabtip,
1357            eesipr::Tabtip,
1358            Eesipr_SPEC,
1359            crate::common::RW,
1360        >::from_register(self, 0)
1361    }
1362
1363    #[doc = "Receive Abort Detect Interrupt Request Enable"]
1364    #[inline(always)]
1365    pub fn rabtip(
1366        self,
1367    ) -> crate::common::RegisterField<
1368        25,
1369        0x1,
1370        1,
1371        0,
1372        eesipr::Rabtip,
1373        eesipr::Rabtip,
1374        Eesipr_SPEC,
1375        crate::common::RW,
1376    > {
1377        crate::common::RegisterField::<
1378            25,
1379            0x1,
1380            1,
1381            0,
1382            eesipr::Rabtip,
1383            eesipr::Rabtip,
1384            Eesipr_SPEC,
1385            crate::common::RW,
1386        >::from_register(self, 0)
1387    }
1388
1389    #[doc = "Receive Frame Counter Overflow Interrupt Request Enable"]
1390    #[inline(always)]
1391    pub fn rfcofip(
1392        self,
1393    ) -> crate::common::RegisterField<
1394        24,
1395        0x1,
1396        1,
1397        0,
1398        eesipr::Rfcofip,
1399        eesipr::Rfcofip,
1400        Eesipr_SPEC,
1401        crate::common::RW,
1402    > {
1403        crate::common::RegisterField::<
1404            24,
1405            0x1,
1406            1,
1407            0,
1408            eesipr::Rfcofip,
1409            eesipr::Rfcofip,
1410            Eesipr_SPEC,
1411            crate::common::RW,
1412        >::from_register(self, 0)
1413    }
1414
1415    #[doc = "Address Error Interrupt Request Enable"]
1416    #[inline(always)]
1417    pub fn adeip(
1418        self,
1419    ) -> crate::common::RegisterField<
1420        23,
1421        0x1,
1422        1,
1423        0,
1424        eesipr::Adeip,
1425        eesipr::Adeip,
1426        Eesipr_SPEC,
1427        crate::common::RW,
1428    > {
1429        crate::common::RegisterField::<
1430            23,
1431            0x1,
1432            1,
1433            0,
1434            eesipr::Adeip,
1435            eesipr::Adeip,
1436            Eesipr_SPEC,
1437            crate::common::RW,
1438        >::from_register(self, 0)
1439    }
1440
1441    #[doc = "ETHERC Status Register Source Interrupt Request Enable"]
1442    #[inline(always)]
1443    pub fn eciip(
1444        self,
1445    ) -> crate::common::RegisterField<
1446        22,
1447        0x1,
1448        1,
1449        0,
1450        eesipr::Eciip,
1451        eesipr::Eciip,
1452        Eesipr_SPEC,
1453        crate::common::RW,
1454    > {
1455        crate::common::RegisterField::<
1456            22,
1457            0x1,
1458            1,
1459            0,
1460            eesipr::Eciip,
1461            eesipr::Eciip,
1462            Eesipr_SPEC,
1463            crate::common::RW,
1464        >::from_register(self, 0)
1465    }
1466
1467    #[doc = "Frame Transfer Complete Interrupt Request Enable"]
1468    #[inline(always)]
1469    pub fn tcip(
1470        self,
1471    ) -> crate::common::RegisterField<
1472        21,
1473        0x1,
1474        1,
1475        0,
1476        eesipr::Tcip,
1477        eesipr::Tcip,
1478        Eesipr_SPEC,
1479        crate::common::RW,
1480    > {
1481        crate::common::RegisterField::<
1482            21,
1483            0x1,
1484            1,
1485            0,
1486            eesipr::Tcip,
1487            eesipr::Tcip,
1488            Eesipr_SPEC,
1489            crate::common::RW,
1490        >::from_register(self, 0)
1491    }
1492
1493    #[doc = "Transmit Descriptor Empty Interrupt Request Enable"]
1494    #[inline(always)]
1495    pub fn tdeip(
1496        self,
1497    ) -> crate::common::RegisterField<
1498        20,
1499        0x1,
1500        1,
1501        0,
1502        eesipr::Tdeip,
1503        eesipr::Tdeip,
1504        Eesipr_SPEC,
1505        crate::common::RW,
1506    > {
1507        crate::common::RegisterField::<
1508            20,
1509            0x1,
1510            1,
1511            0,
1512            eesipr::Tdeip,
1513            eesipr::Tdeip,
1514            Eesipr_SPEC,
1515            crate::common::RW,
1516        >::from_register(self, 0)
1517    }
1518
1519    #[doc = "Transmit FIFO Underflow Interrupt Request Enable"]
1520    #[inline(always)]
1521    pub fn tfufip(
1522        self,
1523    ) -> crate::common::RegisterField<
1524        19,
1525        0x1,
1526        1,
1527        0,
1528        eesipr::Tfufip,
1529        eesipr::Tfufip,
1530        Eesipr_SPEC,
1531        crate::common::RW,
1532    > {
1533        crate::common::RegisterField::<
1534            19,
1535            0x1,
1536            1,
1537            0,
1538            eesipr::Tfufip,
1539            eesipr::Tfufip,
1540            Eesipr_SPEC,
1541            crate::common::RW,
1542        >::from_register(self, 0)
1543    }
1544
1545    #[doc = "Frame Receive Interrupt Request Enable"]
1546    #[inline(always)]
1547    pub fn frip(
1548        self,
1549    ) -> crate::common::RegisterField<
1550        18,
1551        0x1,
1552        1,
1553        0,
1554        eesipr::Frip,
1555        eesipr::Frip,
1556        Eesipr_SPEC,
1557        crate::common::RW,
1558    > {
1559        crate::common::RegisterField::<
1560            18,
1561            0x1,
1562            1,
1563            0,
1564            eesipr::Frip,
1565            eesipr::Frip,
1566            Eesipr_SPEC,
1567            crate::common::RW,
1568        >::from_register(self, 0)
1569    }
1570
1571    #[doc = "Receive Descriptor Empty Interrupt Request Enable"]
1572    #[inline(always)]
1573    pub fn rdeip(
1574        self,
1575    ) -> crate::common::RegisterField<
1576        17,
1577        0x1,
1578        1,
1579        0,
1580        eesipr::Rdeip,
1581        eesipr::Rdeip,
1582        Eesipr_SPEC,
1583        crate::common::RW,
1584    > {
1585        crate::common::RegisterField::<
1586            17,
1587            0x1,
1588            1,
1589            0,
1590            eesipr::Rdeip,
1591            eesipr::Rdeip,
1592            Eesipr_SPEC,
1593            crate::common::RW,
1594        >::from_register(self, 0)
1595    }
1596
1597    #[doc = "Receive FIFO Overflow Interrupt Request Enable"]
1598    #[inline(always)]
1599    pub fn rfofip(
1600        self,
1601    ) -> crate::common::RegisterField<
1602        16,
1603        0x1,
1604        1,
1605        0,
1606        eesipr::Rfofip,
1607        eesipr::Rfofip,
1608        Eesipr_SPEC,
1609        crate::common::RW,
1610    > {
1611        crate::common::RegisterField::<
1612            16,
1613            0x1,
1614            1,
1615            0,
1616            eesipr::Rfofip,
1617            eesipr::Rfofip,
1618            Eesipr_SPEC,
1619            crate::common::RW,
1620        >::from_register(self, 0)
1621    }
1622
1623    #[doc = "Carrier Not Detect Interrupt Request Enable"]
1624    #[inline(always)]
1625    pub fn cndip(
1626        self,
1627    ) -> crate::common::RegisterField<
1628        11,
1629        0x1,
1630        1,
1631        0,
1632        eesipr::Cndip,
1633        eesipr::Cndip,
1634        Eesipr_SPEC,
1635        crate::common::RW,
1636    > {
1637        crate::common::RegisterField::<
1638            11,
1639            0x1,
1640            1,
1641            0,
1642            eesipr::Cndip,
1643            eesipr::Cndip,
1644            Eesipr_SPEC,
1645            crate::common::RW,
1646        >::from_register(self, 0)
1647    }
1648
1649    #[doc = "Loss of Carrier Detect Interrupt Request Enable"]
1650    #[inline(always)]
1651    pub fn dlcip(
1652        self,
1653    ) -> crate::common::RegisterField<
1654        10,
1655        0x1,
1656        1,
1657        0,
1658        eesipr::Dlcip,
1659        eesipr::Dlcip,
1660        Eesipr_SPEC,
1661        crate::common::RW,
1662    > {
1663        crate::common::RegisterField::<
1664            10,
1665            0x1,
1666            1,
1667            0,
1668            eesipr::Dlcip,
1669            eesipr::Dlcip,
1670            Eesipr_SPEC,
1671            crate::common::RW,
1672        >::from_register(self, 0)
1673    }
1674
1675    #[doc = "Late Collision Detect Interrupt Request Enable"]
1676    #[inline(always)]
1677    pub fn cdip(
1678        self,
1679    ) -> crate::common::RegisterField<
1680        9,
1681        0x1,
1682        1,
1683        0,
1684        eesipr::Cdip,
1685        eesipr::Cdip,
1686        Eesipr_SPEC,
1687        crate::common::RW,
1688    > {
1689        crate::common::RegisterField::<
1690            9,
1691            0x1,
1692            1,
1693            0,
1694            eesipr::Cdip,
1695            eesipr::Cdip,
1696            Eesipr_SPEC,
1697            crate::common::RW,
1698        >::from_register(self, 0)
1699    }
1700
1701    #[doc = "Transmit Retry Over Interrupt Request Enable"]
1702    #[inline(always)]
1703    pub fn troip(
1704        self,
1705    ) -> crate::common::RegisterField<
1706        8,
1707        0x1,
1708        1,
1709        0,
1710        eesipr::Troip,
1711        eesipr::Troip,
1712        Eesipr_SPEC,
1713        crate::common::RW,
1714    > {
1715        crate::common::RegisterField::<
1716            8,
1717            0x1,
1718            1,
1719            0,
1720            eesipr::Troip,
1721            eesipr::Troip,
1722            Eesipr_SPEC,
1723            crate::common::RW,
1724        >::from_register(self, 0)
1725    }
1726
1727    #[doc = "Multicast Address Frame Receive Interrupt Request Enable"]
1728    #[inline(always)]
1729    pub fn rmafip(
1730        self,
1731    ) -> crate::common::RegisterField<
1732        7,
1733        0x1,
1734        1,
1735        0,
1736        eesipr::Rmafip,
1737        eesipr::Rmafip,
1738        Eesipr_SPEC,
1739        crate::common::RW,
1740    > {
1741        crate::common::RegisterField::<
1742            7,
1743            0x1,
1744            1,
1745            0,
1746            eesipr::Rmafip,
1747            eesipr::Rmafip,
1748            Eesipr_SPEC,
1749            crate::common::RW,
1750        >::from_register(self, 0)
1751    }
1752
1753    #[doc = "Alignment Error Interrupt Request Enable"]
1754    #[inline(always)]
1755    pub fn rrfip(
1756        self,
1757    ) -> crate::common::RegisterField<
1758        4,
1759        0x1,
1760        1,
1761        0,
1762        eesipr::Rrfip,
1763        eesipr::Rrfip,
1764        Eesipr_SPEC,
1765        crate::common::RW,
1766    > {
1767        crate::common::RegisterField::<
1768            4,
1769            0x1,
1770            1,
1771            0,
1772            eesipr::Rrfip,
1773            eesipr::Rrfip,
1774            Eesipr_SPEC,
1775            crate::common::RW,
1776        >::from_register(self, 0)
1777    }
1778
1779    #[doc = "Frame-Too-Long Error Interrupt Request Enable"]
1780    #[inline(always)]
1781    pub fn rtlfip(
1782        self,
1783    ) -> crate::common::RegisterField<
1784        3,
1785        0x1,
1786        1,
1787        0,
1788        eesipr::Rtlfip,
1789        eesipr::Rtlfip,
1790        Eesipr_SPEC,
1791        crate::common::RW,
1792    > {
1793        crate::common::RegisterField::<
1794            3,
1795            0x1,
1796            1,
1797            0,
1798            eesipr::Rtlfip,
1799            eesipr::Rtlfip,
1800            Eesipr_SPEC,
1801            crate::common::RW,
1802        >::from_register(self, 0)
1803    }
1804
1805    #[doc = "Frame-Too-Short Error Interrupt Request Enable"]
1806    #[inline(always)]
1807    pub fn rtsfip(
1808        self,
1809    ) -> crate::common::RegisterField<
1810        2,
1811        0x1,
1812        1,
1813        0,
1814        eesipr::Rtsfip,
1815        eesipr::Rtsfip,
1816        Eesipr_SPEC,
1817        crate::common::RW,
1818    > {
1819        crate::common::RegisterField::<
1820            2,
1821            0x1,
1822            1,
1823            0,
1824            eesipr::Rtsfip,
1825            eesipr::Rtsfip,
1826            Eesipr_SPEC,
1827            crate::common::RW,
1828        >::from_register(self, 0)
1829    }
1830
1831    #[doc = "PHY-LSI Receive Error Interrupt Request Enable"]
1832    #[inline(always)]
1833    pub fn preip(
1834        self,
1835    ) -> crate::common::RegisterField<
1836        1,
1837        0x1,
1838        1,
1839        0,
1840        eesipr::Preip,
1841        eesipr::Preip,
1842        Eesipr_SPEC,
1843        crate::common::RW,
1844    > {
1845        crate::common::RegisterField::<
1846            1,
1847            0x1,
1848            1,
1849            0,
1850            eesipr::Preip,
1851            eesipr::Preip,
1852            Eesipr_SPEC,
1853            crate::common::RW,
1854        >::from_register(self, 0)
1855    }
1856
1857    #[doc = "CRC Error Interrupt Request Enable"]
1858    #[inline(always)]
1859    pub fn cerfip(
1860        self,
1861    ) -> crate::common::RegisterField<
1862        0,
1863        0x1,
1864        1,
1865        0,
1866        eesipr::Cerfip,
1867        eesipr::Cerfip,
1868        Eesipr_SPEC,
1869        crate::common::RW,
1870    > {
1871        crate::common::RegisterField::<
1872            0,
1873            0x1,
1874            1,
1875            0,
1876            eesipr::Cerfip,
1877            eesipr::Cerfip,
1878            Eesipr_SPEC,
1879            crate::common::RW,
1880        >::from_register(self, 0)
1881    }
1882}
1883impl ::core::default::Default for Eesipr {
1884    #[inline(always)]
1885    fn default() -> Eesipr {
1886        <crate::RegValueT<Eesipr_SPEC> as RegisterValue<_>>::new(0)
1887    }
1888}
1889pub mod eesipr {
1890
1891    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1892    pub struct Twbip_SPEC;
1893    pub type Twbip = crate::EnumBitfieldStruct<u8, Twbip_SPEC>;
1894    impl Twbip {
1895        #[doc = "Write-back complete interrupt request is disabled."]
1896        pub const _0: Self = Self::new(0);
1897
1898        #[doc = "Write-back complete interrupt request is enabled."]
1899        pub const _1: Self = Self::new(1);
1900    }
1901    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1902    pub struct Tabtip_SPEC;
1903    pub type Tabtip = crate::EnumBitfieldStruct<u8, Tabtip_SPEC>;
1904    impl Tabtip {
1905        #[doc = "Transmit abort detect interrupt request is disabled."]
1906        pub const _0: Self = Self::new(0);
1907
1908        #[doc = "Transmit abort detect interrupt request is enabled."]
1909        pub const _1: Self = Self::new(1);
1910    }
1911    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1912    pub struct Rabtip_SPEC;
1913    pub type Rabtip = crate::EnumBitfieldStruct<u8, Rabtip_SPEC>;
1914    impl Rabtip {
1915        #[doc = "Receive abort detect interrupt request is disabled."]
1916        pub const _0: Self = Self::new(0);
1917
1918        #[doc = "Receive abort detect interrupt request is enabled."]
1919        pub const _1: Self = Self::new(1);
1920    }
1921    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1922    pub struct Rfcofip_SPEC;
1923    pub type Rfcofip = crate::EnumBitfieldStruct<u8, Rfcofip_SPEC>;
1924    impl Rfcofip {
1925        #[doc = "Receive frame counter overflow interrupt request is disabled."]
1926        pub const _0: Self = Self::new(0);
1927
1928        #[doc = "Receive frame counter overflow interrupt request is enabled."]
1929        pub const _1: Self = Self::new(1);
1930    }
1931    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1932    pub struct Adeip_SPEC;
1933    pub type Adeip = crate::EnumBitfieldStruct<u8, Adeip_SPEC>;
1934    impl Adeip {
1935        #[doc = "Address error interrupt request is disabled."]
1936        pub const _0: Self = Self::new(0);
1937
1938        #[doc = "Address error interrupt request is enabled."]
1939        pub const _1: Self = Self::new(1);
1940    }
1941    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1942    pub struct Eciip_SPEC;
1943    pub type Eciip = crate::EnumBitfieldStruct<u8, Eciip_SPEC>;
1944    impl Eciip {
1945        #[doc = "ETHERC status interrupt request is disabled."]
1946        pub const _0: Self = Self::new(0);
1947
1948        #[doc = "ETHERC status interrupt request is enabled."]
1949        pub const _1: Self = Self::new(1);
1950    }
1951    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1952    pub struct Tcip_SPEC;
1953    pub type Tcip = crate::EnumBitfieldStruct<u8, Tcip_SPEC>;
1954    impl Tcip {
1955        #[doc = "Frame transmission complete interrupt request is disabled."]
1956        pub const _0: Self = Self::new(0);
1957
1958        #[doc = "Frame transmission complete interrupt request is enabled."]
1959        pub const _1: Self = Self::new(1);
1960    }
1961    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1962    pub struct Tdeip_SPEC;
1963    pub type Tdeip = crate::EnumBitfieldStruct<u8, Tdeip_SPEC>;
1964    impl Tdeip {
1965        #[doc = "Transmit descriptor empty interrupt request is disabled."]
1966        pub const _0: Self = Self::new(0);
1967
1968        #[doc = "Transmit descriptor empty interrupt request is enabled."]
1969        pub const _1: Self = Self::new(1);
1970    }
1971    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1972    pub struct Tfufip_SPEC;
1973    pub type Tfufip = crate::EnumBitfieldStruct<u8, Tfufip_SPEC>;
1974    impl Tfufip {
1975        #[doc = "Underflow interrupt request is disabled."]
1976        pub const _0: Self = Self::new(0);
1977
1978        #[doc = "Underflow interrupt request is enabled."]
1979        pub const _1: Self = Self::new(1);
1980    }
1981    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1982    pub struct Frip_SPEC;
1983    pub type Frip = crate::EnumBitfieldStruct<u8, Frip_SPEC>;
1984    impl Frip {
1985        #[doc = "Frame reception interrupt request is disabled."]
1986        pub const _0: Self = Self::new(0);
1987
1988        #[doc = "Frame reception interrupt request is enabled."]
1989        pub const _1: Self = Self::new(1);
1990    }
1991    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1992    pub struct Rdeip_SPEC;
1993    pub type Rdeip = crate::EnumBitfieldStruct<u8, Rdeip_SPEC>;
1994    impl Rdeip {
1995        #[doc = "Receive descriptor empty interrupt request is disabled."]
1996        pub const _0: Self = Self::new(0);
1997
1998        #[doc = "Receive descriptor empty interrupt request is enabled."]
1999        pub const _1: Self = Self::new(1);
2000    }
2001    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2002    pub struct Rfofip_SPEC;
2003    pub type Rfofip = crate::EnumBitfieldStruct<u8, Rfofip_SPEC>;
2004    impl Rfofip {
2005        #[doc = "Overflow interrupt request is disabled."]
2006        pub const _0: Self = Self::new(0);
2007
2008        #[doc = "Overflow interrupt request is enabled."]
2009        pub const _1: Self = Self::new(1);
2010    }
2011    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2012    pub struct Cndip_SPEC;
2013    pub type Cndip = crate::EnumBitfieldStruct<u8, Cndip_SPEC>;
2014    impl Cndip {
2015        #[doc = "Carrier not detect interrupt request is disabled."]
2016        pub const _0: Self = Self::new(0);
2017
2018        #[doc = "Carrier not detect interrupt request is enabled."]
2019        pub const _1: Self = Self::new(1);
2020    }
2021    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2022    pub struct Dlcip_SPEC;
2023    pub type Dlcip = crate::EnumBitfieldStruct<u8, Dlcip_SPEC>;
2024    impl Dlcip {
2025        #[doc = "Loss of carrier detect interrupt request is disabled."]
2026        pub const _0: Self = Self::new(0);
2027
2028        #[doc = "Loss of carrier detect interrupt request is enabled."]
2029        pub const _1: Self = Self::new(1);
2030    }
2031    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2032    pub struct Cdip_SPEC;
2033    pub type Cdip = crate::EnumBitfieldStruct<u8, Cdip_SPEC>;
2034    impl Cdip {
2035        #[doc = "Late collision detect interrupt request is disabled."]
2036        pub const _0: Self = Self::new(0);
2037
2038        #[doc = "Late collision detect interrupt request is enabled."]
2039        pub const _1: Self = Self::new(1);
2040    }
2041    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2042    pub struct Troip_SPEC;
2043    pub type Troip = crate::EnumBitfieldStruct<u8, Troip_SPEC>;
2044    impl Troip {
2045        #[doc = "Transmit retry over interrupt request is disabled."]
2046        pub const _0: Self = Self::new(0);
2047
2048        #[doc = "Transmit retry over interrupt request is enabled."]
2049        pub const _1: Self = Self::new(1);
2050    }
2051    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2052    pub struct Rmafip_SPEC;
2053    pub type Rmafip = crate::EnumBitfieldStruct<u8, Rmafip_SPEC>;
2054    impl Rmafip {
2055        #[doc = "Multicast address frame receive interrupt request is disabled."]
2056        pub const _0: Self = Self::new(0);
2057
2058        #[doc = "Multicast address frame receive interrupt request is enabled."]
2059        pub const _1: Self = Self::new(1);
2060    }
2061    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2062    pub struct Rrfip_SPEC;
2063    pub type Rrfip = crate::EnumBitfieldStruct<u8, Rrfip_SPEC>;
2064    impl Rrfip {
2065        #[doc = "Alignment error interrupt request is disabled."]
2066        pub const _0: Self = Self::new(0);
2067
2068        #[doc = "Alignment error interrupt request is enabled."]
2069        pub const _1: Self = Self::new(1);
2070    }
2071    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2072    pub struct Rtlfip_SPEC;
2073    pub type Rtlfip = crate::EnumBitfieldStruct<u8, Rtlfip_SPEC>;
2074    impl Rtlfip {
2075        #[doc = "Frame-too-long error interrupt request is disabled."]
2076        pub const _0: Self = Self::new(0);
2077
2078        #[doc = "Frame-too-long error interrupt request is enabled."]
2079        pub const _1: Self = Self::new(1);
2080    }
2081    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2082    pub struct Rtsfip_SPEC;
2083    pub type Rtsfip = crate::EnumBitfieldStruct<u8, Rtsfip_SPEC>;
2084    impl Rtsfip {
2085        #[doc = "Frame-too-short error interrupt request is disabled."]
2086        pub const _0: Self = Self::new(0);
2087
2088        #[doc = "Frame-too-short error interrupt request is enabled."]
2089        pub const _1: Self = Self::new(1);
2090    }
2091    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2092    pub struct Preip_SPEC;
2093    pub type Preip = crate::EnumBitfieldStruct<u8, Preip_SPEC>;
2094    impl Preip {
2095        #[doc = "PHY-LSI receive error interrupt request is disabled."]
2096        pub const _0: Self = Self::new(0);
2097
2098        #[doc = "PHY-LSI receive error interrupt request is enabled."]
2099        pub const _1: Self = Self::new(1);
2100    }
2101    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2102    pub struct Cerfip_SPEC;
2103    pub type Cerfip = crate::EnumBitfieldStruct<u8, Cerfip_SPEC>;
2104    impl Cerfip {
2105        #[doc = "CRC error interrupt request is disabled."]
2106        pub const _0: Self = Self::new(0);
2107
2108        #[doc = "CRC error interrupt request is enabled."]
2109        pub const _1: Self = Self::new(1);
2110    }
2111}
2112#[doc(hidden)]
2113#[derive(Copy, Clone, Eq, PartialEq)]
2114pub struct Trscer_SPEC;
2115impl crate::sealed::RegSpec for Trscer_SPEC {
2116    type DataType = u32;
2117}
2118
2119#[doc = "ETHERC/EDMAC Transmit/Receive Status Copy Enable Register"]
2120pub type Trscer = crate::RegValueT<Trscer_SPEC>;
2121
2122impl Trscer {
2123    #[doc = "RMAF Flag Copy Enable"]
2124    #[inline(always)]
2125    pub fn rmafce(
2126        self,
2127    ) -> crate::common::RegisterField<
2128        7,
2129        0x1,
2130        1,
2131        0,
2132        trscer::Rmafce,
2133        trscer::Rmafce,
2134        Trscer_SPEC,
2135        crate::common::RW,
2136    > {
2137        crate::common::RegisterField::<
2138            7,
2139            0x1,
2140            1,
2141            0,
2142            trscer::Rmafce,
2143            trscer::Rmafce,
2144            Trscer_SPEC,
2145            crate::common::RW,
2146        >::from_register(self, 0)
2147    }
2148
2149    #[doc = "RRF Flag Copy Enable"]
2150    #[inline(always)]
2151    pub fn rrfce(
2152        self,
2153    ) -> crate::common::RegisterField<
2154        4,
2155        0x1,
2156        1,
2157        0,
2158        trscer::Rrfce,
2159        trscer::Rrfce,
2160        Trscer_SPEC,
2161        crate::common::RW,
2162    > {
2163        crate::common::RegisterField::<
2164            4,
2165            0x1,
2166            1,
2167            0,
2168            trscer::Rrfce,
2169            trscer::Rrfce,
2170            Trscer_SPEC,
2171            crate::common::RW,
2172        >::from_register(self, 0)
2173    }
2174}
2175impl ::core::default::Default for Trscer {
2176    #[inline(always)]
2177    fn default() -> Trscer {
2178        <crate::RegValueT<Trscer_SPEC> as RegisterValue<_>>::new(0)
2179    }
2180}
2181pub mod trscer {
2182
2183    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2184    pub struct Rmafce_SPEC;
2185    pub type Rmafce = crate::EnumBitfieldStruct<u8, Rmafce_SPEC>;
2186    impl Rmafce {
2187        #[doc = "The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor."]
2188        pub const _0: Self = Self::new(0);
2189
2190        #[doc = "The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor."]
2191        pub const _1: Self = Self::new(1);
2192    }
2193    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2194    pub struct Rrfce_SPEC;
2195    pub type Rrfce = crate::EnumBitfieldStruct<u8, Rrfce_SPEC>;
2196    impl Rrfce {
2197        #[doc = "The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor."]
2198        pub const _0: Self = Self::new(0);
2199
2200        #[doc = "The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor."]
2201        pub const _1: Self = Self::new(1);
2202    }
2203}
2204#[doc(hidden)]
2205#[derive(Copy, Clone, Eq, PartialEq)]
2206pub struct Rmfcr_SPEC;
2207impl crate::sealed::RegSpec for Rmfcr_SPEC {
2208    type DataType = u32;
2209}
2210
2211#[doc = "Missed-Frame Counter Register"]
2212pub type Rmfcr = crate::RegValueT<Rmfcr_SPEC>;
2213
2214impl Rmfcr {
2215    #[doc = "Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception."]
2216    #[inline(always)]
2217    pub fn mfc(
2218        self,
2219    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Rmfcr_SPEC, crate::common::RW>
2220    {
2221        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Rmfcr_SPEC,crate::common::RW>::from_register(self,0)
2222    }
2223}
2224impl ::core::default::Default for Rmfcr {
2225    #[inline(always)]
2226    fn default() -> Rmfcr {
2227        <crate::RegValueT<Rmfcr_SPEC> as RegisterValue<_>>::new(0)
2228    }
2229}
2230
2231#[doc(hidden)]
2232#[derive(Copy, Clone, Eq, PartialEq)]
2233pub struct Tftr_SPEC;
2234impl crate::sealed::RegSpec for Tftr_SPEC {
2235    type DataType = u32;
2236}
2237
2238#[doc = "Transmit FIFO Threshold Register"]
2239pub type Tftr = crate::RegValueT<Tftr_SPEC>;
2240
2241impl Tftr {
2242    #[doc = "Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4.  Example:     00Dh: 52 bytes     040h: 256 bytes     100h: 1024 bytes     200h: 2048 bytes"]
2243    #[inline(always)]
2244    pub fn tft(
2245        self,
2246    ) -> crate::common::RegisterField<
2247        0,
2248        0x7ff,
2249        1,
2250        0,
2251        tftr::Tft,
2252        tftr::Tft,
2253        Tftr_SPEC,
2254        crate::common::RW,
2255    > {
2256        crate::common::RegisterField::<
2257            0,
2258            0x7ff,
2259            1,
2260            0,
2261            tftr::Tft,
2262            tftr::Tft,
2263            Tftr_SPEC,
2264            crate::common::RW,
2265        >::from_register(self, 0)
2266    }
2267}
2268impl ::core::default::Default for Tftr {
2269    #[inline(always)]
2270    fn default() -> Tftr {
2271        <crate::RegValueT<Tftr_SPEC> as RegisterValue<_>>::new(0)
2272    }
2273}
2274pub mod tftr {
2275
2276    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2277    pub struct Tft_SPEC;
2278    pub type Tft = crate::EnumBitfieldStruct<u8, Tft_SPEC>;
2279    impl Tft {
2280        #[doc = "Store and forward mode"]
2281        pub const _0_X_000: Self = Self::new(0);
2282    }
2283}
2284#[doc(hidden)]
2285#[derive(Copy, Clone, Eq, PartialEq)]
2286pub struct Fdr_SPEC;
2287impl crate::sealed::RegSpec for Fdr_SPEC {
2288    type DataType = u32;
2289}
2290
2291#[doc = "Transmit FIFO Threshold Register"]
2292pub type Fdr = crate::RegValueT<Fdr_SPEC>;
2293
2294impl Fdr {
2295    #[doc = "Receive FIFO Depth"]
2296    #[inline(always)]
2297    pub fn tfd(
2298        self,
2299    ) -> crate::common::RegisterField<8, 0x1f, 1, 0, fdr::Tfd, fdr::Tfd, Fdr_SPEC, crate::common::RW>
2300    {
2301        crate::common::RegisterField::<8,0x1f,1,0,fdr::Tfd,fdr::Tfd,Fdr_SPEC,crate::common::RW>::from_register(self,0)
2302    }
2303
2304    #[doc = "Transmit FIFO Depth"]
2305    #[inline(always)]
2306    pub fn rfd(
2307        self,
2308    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, fdr::Rfd, fdr::Rfd, Fdr_SPEC, crate::common::RW>
2309    {
2310        crate::common::RegisterField::<0,0x1f,1,0,fdr::Rfd,fdr::Rfd,Fdr_SPEC,crate::common::RW>::from_register(self,0)
2311    }
2312}
2313impl ::core::default::Default for Fdr {
2314    #[inline(always)]
2315    fn default() -> Fdr {
2316        <crate::RegValueT<Fdr_SPEC> as RegisterValue<_>>::new(0)
2317    }
2318}
2319pub mod fdr {
2320
2321    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2322    pub struct Tfd_SPEC;
2323    pub type Tfd = crate::EnumBitfieldStruct<u8, Tfd_SPEC>;
2324    impl Tfd {
2325        #[doc = "4096 bytes"]
2326        pub const _01111: Self = Self::new(15);
2327    }
2328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2329    pub struct Rfd_SPEC;
2330    pub type Rfd = crate::EnumBitfieldStruct<u8, Rfd_SPEC>;
2331    impl Rfd {
2332        #[doc = "2048 bytes"]
2333        pub const _00111: Self = Self::new(7);
2334    }
2335}
2336#[doc(hidden)]
2337#[derive(Copy, Clone, Eq, PartialEq)]
2338pub struct Rmcr_SPEC;
2339impl crate::sealed::RegSpec for Rmcr_SPEC {
2340    type DataType = u32;
2341}
2342
2343#[doc = "Receive Method Control Register"]
2344pub type Rmcr = crate::RegValueT<Rmcr_SPEC>;
2345
2346impl Rmcr {
2347    #[doc = "Receive Request Reset"]
2348    #[inline(always)]
2349    pub fn rnr(
2350        self,
2351    ) -> crate::common::RegisterField<
2352        0,
2353        0x1,
2354        1,
2355        0,
2356        rmcr::Rnr,
2357        rmcr::Rnr,
2358        Rmcr_SPEC,
2359        crate::common::RW,
2360    > {
2361        crate::common::RegisterField::<
2362            0,
2363            0x1,
2364            1,
2365            0,
2366            rmcr::Rnr,
2367            rmcr::Rnr,
2368            Rmcr_SPEC,
2369            crate::common::RW,
2370        >::from_register(self, 0)
2371    }
2372}
2373impl ::core::default::Default for Rmcr {
2374    #[inline(always)]
2375    fn default() -> Rmcr {
2376        <crate::RegValueT<Rmcr_SPEC> as RegisterValue<_>>::new(0)
2377    }
2378}
2379pub mod rmcr {
2380
2381    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2382    pub struct Rnr_SPEC;
2383    pub type Rnr = crate::EnumBitfieldStruct<u8, Rnr_SPEC>;
2384    impl Rnr {
2385        #[doc = "EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received."]
2386        pub const _0: Self = Self::new(0);
2387
2388        #[doc = "EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received."]
2389        pub const _1: Self = Self::new(1);
2390    }
2391}
2392#[doc(hidden)]
2393#[derive(Copy, Clone, Eq, PartialEq)]
2394pub struct Tfucr_SPEC;
2395impl crate::sealed::RegSpec for Tfucr_SPEC {
2396    type DataType = u32;
2397}
2398
2399#[doc = "Transmit FIFO Underflow Counter"]
2400pub type Tfucr = crate::RegValueT<Tfucr_SPEC>;
2401
2402impl Tfucr {
2403    #[doc = "Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh."]
2404    #[inline(always)]
2405    pub fn under(
2406        self,
2407    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Tfucr_SPEC, crate::common::RW>
2408    {
2409        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Tfucr_SPEC,crate::common::RW>::from_register(self,0)
2410    }
2411}
2412impl ::core::default::Default for Tfucr {
2413    #[inline(always)]
2414    fn default() -> Tfucr {
2415        <crate::RegValueT<Tfucr_SPEC> as RegisterValue<_>>::new(0)
2416    }
2417}
2418
2419#[doc(hidden)]
2420#[derive(Copy, Clone, Eq, PartialEq)]
2421pub struct Rfocr_SPEC;
2422impl crate::sealed::RegSpec for Rfocr_SPEC {
2423    type DataType = u32;
2424}
2425
2426#[doc = "Receive FIFO Overflow Counter"]
2427pub type Rfocr = crate::RegValueT<Rfocr_SPEC>;
2428
2429impl Rfocr {
2430    #[doc = "Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh."]
2431    #[inline(always)]
2432    pub fn over(
2433        self,
2434    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Rfocr_SPEC, crate::common::RW>
2435    {
2436        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Rfocr_SPEC,crate::common::RW>::from_register(self,0)
2437    }
2438}
2439impl ::core::default::Default for Rfocr {
2440    #[inline(always)]
2441    fn default() -> Rfocr {
2442        <crate::RegValueT<Rfocr_SPEC> as RegisterValue<_>>::new(0)
2443    }
2444}
2445
2446#[doc(hidden)]
2447#[derive(Copy, Clone, Eq, PartialEq)]
2448pub struct Iosr_SPEC;
2449impl crate::sealed::RegSpec for Iosr_SPEC {
2450    type DataType = u32;
2451}
2452
2453#[doc = "Independent Output Signal Setting Register"]
2454pub type Iosr = crate::RegValueT<Iosr_SPEC>;
2455
2456impl Iosr {
2457    #[doc = "External Loopback Mode"]
2458    #[inline(always)]
2459    pub fn elb(
2460        self,
2461    ) -> crate::common::RegisterField<
2462        0,
2463        0x1,
2464        1,
2465        0,
2466        iosr::Elb,
2467        iosr::Elb,
2468        Iosr_SPEC,
2469        crate::common::RW,
2470    > {
2471        crate::common::RegisterField::<
2472            0,
2473            0x1,
2474            1,
2475            0,
2476            iosr::Elb,
2477            iosr::Elb,
2478            Iosr_SPEC,
2479            crate::common::RW,
2480        >::from_register(self, 0)
2481    }
2482}
2483impl ::core::default::Default for Iosr {
2484    #[inline(always)]
2485    fn default() -> Iosr {
2486        <crate::RegValueT<Iosr_SPEC> as RegisterValue<_>>::new(0)
2487    }
2488}
2489pub mod iosr {
2490
2491    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2492    pub struct Elb_SPEC;
2493    pub type Elb = crate::EnumBitfieldStruct<u8, Elb_SPEC>;
2494    impl Elb {
2495        #[doc = "The ETn_EXOUT pin outputs low."]
2496        pub const _0: Self = Self::new(0);
2497
2498        #[doc = "The ETn_EXOUT pin outputs high."]
2499        pub const _1: Self = Self::new(1);
2500    }
2501}
2502#[doc(hidden)]
2503#[derive(Copy, Clone, Eq, PartialEq)]
2504pub struct Fcftr_SPEC;
2505impl crate::sealed::RegSpec for Fcftr_SPEC {
2506    type DataType = u32;
2507}
2508
2509#[doc = "Flow Control Start FIFO Threshold Setting Register"]
2510pub type Fcftr = crate::RegValueT<Fcftr_SPEC>;
2511
2512impl Fcftr {
2513    #[doc = "Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.)"]
2514    #[inline(always)]
2515    pub fn rffo(
2516        self,
2517    ) -> crate::common::RegisterField<
2518        16,
2519        0x7,
2520        1,
2521        0,
2522        fcftr::Rffo,
2523        fcftr::Rffo,
2524        Fcftr_SPEC,
2525        crate::common::RW,
2526    > {
2527        crate::common::RegisterField::<
2528            16,
2529            0x7,
2530            1,
2531            0,
2532            fcftr::Rffo,
2533            fcftr::Rffo,
2534            Fcftr_SPEC,
2535            crate::common::RW,
2536        >::from_register(self, 0)
2537    }
2538
2539    #[doc = "Receive FIFO Data PAUSE Output Threshold(When  (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.)"]
2540    #[inline(always)]
2541    pub fn rfdo(
2542        self,
2543    ) -> crate::common::RegisterField<
2544        0,
2545        0x7,
2546        1,
2547        0,
2548        fcftr::Rfdo,
2549        fcftr::Rfdo,
2550        Fcftr_SPEC,
2551        crate::common::RW,
2552    > {
2553        crate::common::RegisterField::<
2554            0,
2555            0x7,
2556            1,
2557            0,
2558            fcftr::Rfdo,
2559            fcftr::Rfdo,
2560            Fcftr_SPEC,
2561            crate::common::RW,
2562        >::from_register(self, 0)
2563    }
2564}
2565impl ::core::default::Default for Fcftr {
2566    #[inline(always)]
2567    fn default() -> Fcftr {
2568        <crate::RegValueT<Fcftr_SPEC> as RegisterValue<_>>::new(458759)
2569    }
2570}
2571pub mod fcftr {
2572
2573    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2574    pub struct Rffo_SPEC;
2575    pub type Rffo = crate::EnumBitfieldStruct<u8, Rffo_SPEC>;
2576    impl Rffo {
2577        #[doc = "When 2 receive frames have been stored in the receive FIFO."]
2578        pub const _000: Self = Self::new(0);
2579
2580        #[doc = "When 4 receive frames have been stored in the receive FIFO."]
2581        pub const _001: Self = Self::new(1);
2582
2583        #[doc = "When 6 receive frames have been stored in the receive FIFO."]
2584        pub const _010: Self = Self::new(2);
2585
2586        #[doc = "When 8 receive frames have been stored in the receive FIFO."]
2587        pub const _011: Self = Self::new(3);
2588
2589        #[doc = "When 10 receive frames have been stored in the receive FIFO."]
2590        pub const _100: Self = Self::new(4);
2591
2592        #[doc = "When 12 receive frames have been stored in the receive FIFO."]
2593        pub const _101: Self = Self::new(5);
2594
2595        #[doc = "When 14 receive frames have been stored in the receive FIFO."]
2596        pub const _110: Self = Self::new(6);
2597
2598        #[doc = "When 16 receive frames have been stored in the receive FIFO."]
2599        pub const _111: Self = Self::new(7);
2600    }
2601    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2602    pub struct Rfdo_SPEC;
2603    pub type Rfdo = crate::EnumBitfieldStruct<u8, Rfdo_SPEC>;
2604    impl Rfdo {
2605        #[doc = "When  224 ( 256 - 32) bytes of data is stored in the receive FIFO."]
2606        pub const _000: Self = Self::new(0);
2607
2608        #[doc = "When  480 ( 512 - 32) bytes of data is stored in the receive FIFO."]
2609        pub const _001: Self = Self::new(1);
2610
2611        #[doc = "When  736 ( 768 - 32) bytes of data is stored in the receive FIFO."]
2612        pub const _010: Self = Self::new(2);
2613
2614        #[doc = "When  992 (1024 - 32) bytes of data is stored in the receive FIFO."]
2615        pub const _011: Self = Self::new(3);
2616
2617        #[doc = "When 1248 (1280 - 32) bytes of data is stored in the receive FIFO."]
2618        pub const _100: Self = Self::new(4);
2619
2620        #[doc = "When 1504 (1536 - 32) bytes of data is stored in the receive FIFO."]
2621        pub const _101: Self = Self::new(5);
2622
2623        #[doc = "When 1760 (1792 - 32) bytes of data is stored in the receive FIFO."]
2624        pub const _110: Self = Self::new(6);
2625
2626        #[doc = "When 2016 (2048 - 32) bytes of data is stored in the receive FIFO."]
2627        pub const _111: Self = Self::new(7);
2628    }
2629}
2630#[doc(hidden)]
2631#[derive(Copy, Clone, Eq, PartialEq)]
2632pub struct Rpadir_SPEC;
2633impl crate::sealed::RegSpec for Rpadir_SPEC {
2634    type DataType = u32;
2635}
2636
2637#[doc = "Receive Data Padding Insert Register"]
2638pub type Rpadir = crate::RegValueT<Rpadir_SPEC>;
2639
2640impl Rpadir {
2641    #[doc = "Padding Size"]
2642    #[inline(always)]
2643    pub fn pads(
2644        self,
2645    ) -> crate::common::RegisterField<
2646        16,
2647        0x3,
2648        1,
2649        0,
2650        rpadir::Pads,
2651        rpadir::Pads,
2652        Rpadir_SPEC,
2653        crate::common::RW,
2654    > {
2655        crate::common::RegisterField::<
2656            16,
2657            0x3,
2658            1,
2659            0,
2660            rpadir::Pads,
2661            rpadir::Pads,
2662            Rpadir_SPEC,
2663            crate::common::RW,
2664        >::from_register(self, 0)
2665    }
2666
2667    #[doc = "Padding Slot"]
2668    #[inline(always)]
2669    pub fn padr(
2670        self,
2671    ) -> crate::common::RegisterField<
2672        0,
2673        0x3f,
2674        1,
2675        0,
2676        rpadir::Padr,
2677        rpadir::Padr,
2678        Rpadir_SPEC,
2679        crate::common::RW,
2680    > {
2681        crate::common::RegisterField::<
2682            0,
2683            0x3f,
2684            1,
2685            0,
2686            rpadir::Padr,
2687            rpadir::Padr,
2688            Rpadir_SPEC,
2689            crate::common::RW,
2690        >::from_register(self, 0)
2691    }
2692}
2693impl ::core::default::Default for Rpadir {
2694    #[inline(always)]
2695    fn default() -> Rpadir {
2696        <crate::RegValueT<Rpadir_SPEC> as RegisterValue<_>>::new(0)
2697    }
2698}
2699pub mod rpadir {
2700
2701    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2702    pub struct Pads_SPEC;
2703    pub type Pads = crate::EnumBitfieldStruct<u8, Pads_SPEC>;
2704    impl Pads {
2705        #[doc = "No padding is inserted."]
2706        pub const _00: Self = Self::new(0);
2707
2708        #[doc = "1 byte is inserted."]
2709        pub const _01: Self = Self::new(1);
2710
2711        #[doc = "2 bytes are inserted."]
2712        pub const _10: Self = Self::new(2);
2713
2714        #[doc = "3 bytes are inserted."]
2715        pub const _11: Self = Self::new(3);
2716    }
2717    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2718    pub struct Padr_SPEC;
2719    pub type Padr = crate::EnumBitfieldStruct<u8, Padr_SPEC>;
2720    impl Padr {
2721        #[doc = "Padding is inserted at the head of received data."]
2722        pub const _00_H: Self = Self::new(0);
2723    }
2724}
2725#[doc(hidden)]
2726#[derive(Copy, Clone, Eq, PartialEq)]
2727pub struct Trimd_SPEC;
2728impl crate::sealed::RegSpec for Trimd_SPEC {
2729    type DataType = u32;
2730}
2731
2732#[doc = "Transmit Interrupt Setting Register"]
2733pub type Trimd = crate::RegValueT<Trimd_SPEC>;
2734
2735impl Trimd {
2736    #[doc = "Transmit Interrupt Mode"]
2737    #[inline(always)]
2738    pub fn tim(
2739        self,
2740    ) -> crate::common::RegisterField<
2741        4,
2742        0x1,
2743        1,
2744        0,
2745        trimd::Tim,
2746        trimd::Tim,
2747        Trimd_SPEC,
2748        crate::common::RW,
2749    > {
2750        crate::common::RegisterField::<
2751            4,
2752            0x1,
2753            1,
2754            0,
2755            trimd::Tim,
2756            trimd::Tim,
2757            Trimd_SPEC,
2758            crate::common::RW,
2759        >::from_register(self, 0)
2760    }
2761
2762    #[doc = "Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt."]
2763    #[inline(always)]
2764    pub fn tis(
2765        self,
2766    ) -> crate::common::RegisterField<
2767        0,
2768        0x1,
2769        1,
2770        0,
2771        trimd::Tis,
2772        trimd::Tis,
2773        Trimd_SPEC,
2774        crate::common::RW,
2775    > {
2776        crate::common::RegisterField::<
2777            0,
2778            0x1,
2779            1,
2780            0,
2781            trimd::Tis,
2782            trimd::Tis,
2783            Trimd_SPEC,
2784            crate::common::RW,
2785        >::from_register(self, 0)
2786    }
2787}
2788impl ::core::default::Default for Trimd {
2789    #[inline(always)]
2790    fn default() -> Trimd {
2791        <crate::RegValueT<Trimd_SPEC> as RegisterValue<_>>::new(0)
2792    }
2793}
2794pub mod trimd {
2795
2796    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2797    pub struct Tim_SPEC;
2798    pub type Tim = crate::EnumBitfieldStruct<u8, Tim_SPEC>;
2799    impl Tim {
2800        #[doc = "Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted."]
2801        pub const _0: Self = Self::new(0);
2802
2803        #[doc = "Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed."]
2804        pub const _1: Self = Self::new(1);
2805    }
2806    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2807    pub struct Tis_SPEC;
2808    pub type Tis = crate::EnumBitfieldStruct<u8, Tis_SPEC>;
2809    impl Tis {
2810        #[doc = "Transmit Interrupt is disabled."]
2811        pub const _0: Self = Self::new(0);
2812
2813        #[doc = "Transmit Interrupt is enabled."]
2814        pub const _1: Self = Self::new(1);
2815    }
2816}
2817#[doc(hidden)]
2818#[derive(Copy, Clone, Eq, PartialEq)]
2819pub struct Rbwar_SPEC;
2820impl crate::sealed::RegSpec for Rbwar_SPEC {
2821    type DataType = u32;
2822}
2823
2824#[doc = "Receive Buffer Write Address Register"]
2825pub type Rbwar = crate::RegValueT<Rbwar_SPEC>;
2826
2827impl Rbwar {
2828    #[doc = "Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception."]
2829    #[inline(always)]
2830    pub fn rbwar(
2831        self,
2832    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Rbwar_SPEC, crate::common::R>
2833    {
2834        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Rbwar_SPEC,crate::common::R>::from_register(self,0)
2835    }
2836}
2837impl ::core::default::Default for Rbwar {
2838    #[inline(always)]
2839    fn default() -> Rbwar {
2840        <crate::RegValueT<Rbwar_SPEC> as RegisterValue<_>>::new(0)
2841    }
2842}
2843
2844#[doc(hidden)]
2845#[derive(Copy, Clone, Eq, PartialEq)]
2846pub struct Rdfar_SPEC;
2847impl crate::sealed::RegSpec for Rdfar_SPEC {
2848    type DataType = u32;
2849}
2850
2851#[doc = "Receive Descriptor Fetch Address Register"]
2852pub type Rdfar = crate::RegValueT<Rdfar_SPEC>;
2853
2854impl Rdfar {
2855    #[doc = "Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception."]
2856    #[inline(always)]
2857    pub fn rdfar(
2858        self,
2859    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Rdfar_SPEC, crate::common::R>
2860    {
2861        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Rdfar_SPEC,crate::common::R>::from_register(self,0)
2862    }
2863}
2864impl ::core::default::Default for Rdfar {
2865    #[inline(always)]
2866    fn default() -> Rdfar {
2867        <crate::RegValueT<Rdfar_SPEC> as RegisterValue<_>>::new(0)
2868    }
2869}
2870
2871#[doc(hidden)]
2872#[derive(Copy, Clone, Eq, PartialEq)]
2873pub struct Tbrar_SPEC;
2874impl crate::sealed::RegSpec for Tbrar_SPEC {
2875    type DataType = u32;
2876}
2877
2878#[doc = "Transmit Buffer Read Address Register"]
2879pub type Tbrar = crate::RegValueT<Tbrar_SPEC>;
2880
2881impl Tbrar {
2882    #[doc = "Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register."]
2883    #[inline(always)]
2884    pub fn tbrar(
2885        self,
2886    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Tbrar_SPEC, crate::common::R>
2887    {
2888        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Tbrar_SPEC,crate::common::R>::from_register(self,0)
2889    }
2890}
2891impl ::core::default::Default for Tbrar {
2892    #[inline(always)]
2893    fn default() -> Tbrar {
2894        <crate::RegValueT<Tbrar_SPEC> as RegisterValue<_>>::new(0)
2895    }
2896}
2897
2898#[doc(hidden)]
2899#[derive(Copy, Clone, Eq, PartialEq)]
2900pub struct Tdfar_SPEC;
2901impl crate::sealed::RegSpec for Tdfar_SPEC {
2902    type DataType = u32;
2903}
2904
2905#[doc = "Transmit Descriptor Fetch Address Register"]
2906pub type Tdfar = crate::RegValueT<Tdfar_SPEC>;
2907
2908impl Tdfar {
2909    #[doc = "Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register."]
2910    #[inline(always)]
2911    pub fn tdfar(
2912        self,
2913    ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Tdfar_SPEC, crate::common::R>
2914    {
2915        crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Tdfar_SPEC,crate::common::R>::from_register(self,0)
2916    }
2917}
2918impl ::core::default::Default for Tdfar {
2919    #[inline(always)]
2920    fn default() -> Tdfar {
2921        <crate::RegValueT<Tdfar_SPEC> as RegisterValue<_>>::new(0)
2922    }
2923}
ra6m2_pac/edmac0.rs

ra6m2_pac/
edmac0.rs
